WO2020199437A1

WO2020199437A1 - Gate driving circuit and array substrate

Info

Publication number: WO2020199437A1
Application number: PCT/CN2019/098478
Authority: WO
Inventors: 陈帅
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2019-04-01
Filing date: 2019-07-31
Publication date: 2020-10-08
Also published as: CN110047450A

Abstract

Provided are a gate driving circuit and an array substrate. The gate driving circuit comprises a plurality of shift registers (10), each of the shift registers (10) comprising a pull-up control unit (1), a pull-up unit (2), a signal download unit (3), a first pull-down unit (4), a second pull-down unit (4') and a pull-down maintaining unit (5). The first pull-down unit (4) is electrically connected to a second gate signal output port (G(N+2)), the second pull-down unit (4') is electrically connected to a third gate signal output port (G(N+3)), and a signal of the third gate signal output port G(N+3) is later than a signal of the second gate signal output port (G(N+2)).

Description

Gate drive circuit and array substrate

Technical field

The present disclosure relates to the field of display technology, in particular to a gate driving circuit and an array substrate.

Background technique

The basic concept of GOA (Gate Driver on Array) is to integrate the gate drive circuit of TFT LCD on the glass substrate to form a scanning drive for the liquid crystal panel. Compared with the traditional drive technology using COF, GOA can not only greatly save manufacturing costs, but also eliminates the COF bonding process on the gate side, which is also extremely beneficial to productivity improvement. Therefore, GOA is the key technology for the development of LCD panels in the future.

The GOA production process will inevitably encounter the problem of poor process uniformity. Therefore, if a shift register has uneven impedance and capacitance compared to other shift registers, it may cause the group of GOA circuits The grade transmission is abnormal, which affects the stability of the entire GOA circuit.

Therefore, there is a need to provide a gate driving circuit and an array substrate to solve the problems in the prior art.

technical problem

In the existing GOA, if a certain shift register has an uneven impedance and an uneven capacitance compared to the circuit corresponding to other shift registers, it may cause an abnormality in the stage transmission of the group of GOA circuits, thereby affecting the stability of the entire GOA circuit.

Technical solutions

To solve the above technical problems, the present disclosure provides a gate driving circuit including a plurality of shift registers, wherein each of the shift registers includes: a pull-up control unit, a pull-up unit, a signal download unit, A first pull-down unit, a second pull-down unit, and a pull-down maintenance unit. The pull-up unit is electrically connected to a first gate signal output port. The first pull-down unit is electrically connected to a second gate signal output port. The second pull-down unit is electrically connected to a third gate signal output port. The signal of the third gate signal output port is delayed from the signal of the second gate signal output port.

In the gate drive circuit described in one of the embodiments of the present disclosure, the pull-up control unit is electrically connected to the pull-up unit, the signal download unit, the first pull-down unit, and the The second pull-down unit and the pull-down maintenance unit. The first pull-down unit and the second pull-down unit are electrically connected to the gate signal output port.

In the gate driving circuit described in an embodiment of the present disclosure, the pull-up control unit includes a first transistor, a drain of the first transistor is electrically connected to the pull-up unit, and A gate of the first transistor is electrically connected to a first signal source, and a source of the first transistor is electrically connected to a second gate signal output port.

In one of the embodiments of the present disclosure, the gate driving circuit further includes a bootstrap capacitor, which is electrically connected to the pull-up control unit, the pull-up unit, the signal download unit, and the pull-down sustain unit.

In the gate driving circuit described in an embodiment of the present disclosure, the pull-down sustain unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a An eighth transistor, wherein a source of the third transistor and a source and a gate of the fourth transistor are electrically connected to a high-level voltage source, and a gate of the third transistor is electrically connected To a drain of the fourth transistor and a source of the sixth transistor, a drain of the third transistor is electrically connected to a gate of the seventh transistor and a source of the eighth transistor A gate and a source of the fifth transistor, a source of the seventh transistor is electrically connected to the drain of the first transistor, and a source of the eighth transistor is electrically connected to the A gate signal output port, a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the drain of the first transistor, a drain of the fifth transistor, a A drain of the sixth transistor, a drain of the seventh transistor, and a drain of the eighth transistor are all electrically connected to a low-level voltage source.

In the gate driving circuit described in one of the embodiments of the present disclosure, the pull-up unit includes a ninth transistor, and a gate of the ninth transistor is electrically connected to the drain of the first transistor. A source of the ninth transistor is electrically connected to a first clock signal source, and a drain of the ninth transistor is electrically connected to the gate signal output port.

In the gate drive circuit described in one of the embodiments of the present disclosure, the signal download unit includes a tenth transistor, and a source of the tenth transistor is electrically connected to the first clock signal source, A gate of the tenth transistor is electrically connected to the drain of the first transistor, and a drain of the tenth transistor is electrically connected to a clock signal output port.

In the gate drive circuit described in one of the embodiments of the present disclosure, the first pull-down unit includes an eleventh transistor and a twelfth transistor, and a source of the eleventh transistor is electrically connected To the gate signal output port, a source of the twelfth transistor is electrically connected to the drain of the first transistor, a gate of the eleventh transistor and the twelfth transistor A gate of the transistor is electrically connected to the second gate signal output port, a drain of the eleventh transistor and a drain of the twelfth transistor are electrically connected to a low-level voltage source.

In the gate drive circuit described in an embodiment of the present disclosure, the second pull-down unit includes a thirteenth transistor and a fourteenth transistor, and a source of the thirteenth transistor is electrically connected to For the gate signal output port, a source of the fourteenth transistor is electrically connected to the drain of the first transistor, a gate of the thirteenth transistor and a gate of the fourteenth transistor A gate is electrically connected to the third gate signal output port, and a drain of the thirteenth transistor and a drain of the fourteenth transistor are electrically connected to a low-level voltage source.

The present disclosure also provides an array substrate including: a substrate, a pixel array, a gate driving circuit, and a clock signal generator. The pixel array, the gate driving circuit, and the clock signal generator are arranged on the substrate. The clock signal generator is used to provide a clock signal to the gate driving circuit. The gate driving circuit is used to drive the pixel array. Wherein, the gate driving circuit includes a plurality of shift registers. Each of the shift registers includes: a pull-up control unit, a pull-up unit, a signal download unit, a first pull-down unit, a second pull-down unit, and a pull-down maintenance unit. The pull-up unit is electrically connected to a first gate signal output port. The first pull-down unit is electrically connected to a second gate signal output port. The second pull-down unit is electrically connected to a third gate signal output port. The signal of the third gate signal output port is delayed from the signal of the second gate signal output port.

Beneficial effect

Compared with the prior art, in order to solve the above technical problems, in the gate driving circuit and the array substrate provided by the present disclosure, the signal of the third gate signal output port is delayed compared to the signal of the second gate signal output port. Therefore, if the first pull-down unit is abnormal, the second pull-down unit can still turn off the shift register, pull down the potential of the first gate signal output port, and solve the problem of the distortion of the potential waveform causing the pixel Abnormal charging, etc.

Description of the drawings

FIG. 1 shows a block diagram of the structure of a shift register according to an embodiment of the present disclosure;

2 shows a schematic block diagram of the structure of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 3 shows a schematic diagram of a structural circuit of a shift register according to an embodiment of the present disclosure;

4 shows a schematic block diagram of the structure of an array substrate according to an embodiment of the present disclosure; and

FIG. 5 shows a schematic diagram of circuit waveforms of a shift register according to an embodiment of the present disclosure.

The best mode of the invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that the present disclosure can be implemented.

In order to make the above and other objectives, features, and advantages of the present disclosure more comprehensible, preferred embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Furthermore, the directional terms mentioned in the present disclosure, such as up, down, top, bottom, front, back, left, right, inside, outside, side layer, surrounding, center, horizontal, horizontal, vertical, vertical, axial , Radial, uppermost or lowermost layers, etc., are only the direction of reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present disclosure, rather than to limit the present disclosure.

In the figure, units with similar structures are indicated by the same reference numerals.

1, 2 and 5, the present disclosure provides a gate driving circuit 100 including a plurality of shift registers 10, wherein each of the shift registers 10 includes: a pull-up control unit 1, a pull-up Unit 2, a signal download unit 3, a first pull-down unit 4, a second pull-down unit 4', and a pull-down maintenance unit 5. The pull-up unit 2 is electrically connected to a first gate signal output port G(N). The first pull-down unit 4 is electrically connected to a second gate signal output port G(N+2). The second pull-down unit 4'is electrically connected to a third gate signal output port G(N+3). The signal G(N+3) of the third gate signal output port is delayed from the signal of the second gate signal output port G(N+2).

Specifically, each disclosure of this application takes a 4-clock stage transfer shift register as an example, but this application does not limit the number of stages of transfer, and those skilled in the art can follow the teachings of this application and do not violate this application. Under the spirit of the invention, the 4-clock-level transmission shift register is modified into a 6-clock-level transmission shift register or an 8-clock-level transmission shift register.

In the gate driving circuit 100 described in one of the embodiments of the present disclosure, the pull-up control unit 1 is electrically connected to the pull-up unit 2, the signal download unit 2, the first pull-down unit Unit 4, the second pull-down unit 4', and the pull-down maintenance unit 5. The first pull-down unit 4 and the second pull-down unit 4'are electrically connected to the gate signal output port G(N).

In the gate driving circuit 100 described in an embodiment of the present disclosure, the pull-up control unit 1 includes a first transistor T1. A drain of the first transistor T1 is electrically connected to the pull-up unit 2. A gate of the first transistor T1 is electrically connected to a first signal source ST(N-2). A source of the first transistor T1 is electrically connected to a second gate signal output port G(N-2).

In one of the embodiments of the present disclosure, the gate driving circuit 100 further includes a bootstrap capacitor 6, which is electrically connected to the pull-up control unit 1, the pull-up unit 2, and the signal download unit 3. And the pull-down maintaining unit 5.

1 and 3, in the gate driving circuit 100 described in an embodiment of the present disclosure, the pull-down sustain unit 5 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, A sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, wherein a source of the third transistor T3 and a source and a gate of the fourth transistor T4 are electrically connected to a high Level voltage source LC, a gate of the third transistor T3 is electrically connected to a drain of the fourth transistor T4 and a source of the sixth transistor T6, and a drain of the third transistor T3 The electrode is electrically connected to a gate of the seventh transistor T7, a gate of the eighth transistor T8 and a source of the fifth transistor T5, and a source of the seventh transistor T7 is electrically connected to The drain of the first transistor T1, a source of the eighth transistor T8 are electrically connected to the gate signal output port G(N), a gate of the fifth transistor T5 and the A gate of the sixth transistor T6 is electrically connected to the drain of the first transistor T1, a drain of the fifth transistor T5, a drain of the sixth transistor T6, and the seventh transistor A drain of T7 and a drain of the eighth transistor T8 are both electrically connected to a low-level voltage source VSS.

1 and 3, in the gate driving circuit 100 described in an embodiment of the present disclosure, wherein the pull-up unit 2 includes a ninth transistor T9, and a gate of the ninth transistor T9 is electrically connected To the drain of the first transistor T1, a source of the ninth transistor T9 is electrically connected to a first clock signal source CK1, and a drain of the ninth transistor T9 is electrically connected to the gate Polar signal output port G(N).

1 and 3, in the gate driving circuit 100 described in one of the embodiments of the present disclosure, the signal downloading unit 3 includes a tenth transistor T10, and a source electrode of the tenth transistor T10 Connected to the first clock signal source CK1, a gate of the tenth transistor T10 is electrically connected to the drain of the first transistor T1, and a drain of the tenth transistor T10 is electrically connected to a Clock signal output port ST(N).

1 and 3, in the gate driving circuit 100 described in an embodiment of the present disclosure, wherein the first pull-down unit 4 includes an eleventh transistor T11 and a twelfth transistor T12, the A source of the eleventh transistor T11 is electrically connected to the gate signal output port G(N), a source of the twelfth transistor T12 is electrically connected to the drain of the first transistor T1, A gate of the eleventh transistor T11 and a gate of the twelfth transistor T12 are electrically connected to the second gate signal output port G(N+2), and the eleventh transistor T11 A drain and a drain of the twelfth transistor T12 are electrically connected to a low-level voltage source VSS.

1 and 3, in the gate driving circuit 100 described in an embodiment of the present disclosure, the second pull-down unit 4'includes a thirteenth transistor T13 and a fourteenth transistor T14, the A source of the thirteenth transistor T13 is electrically connected to the gate signal output port G(N), a source of the fourteenth transistor T14 is electrically connected to the drain of the first transistor T1, A gate of the thirteenth transistor T13 and a gate of the fourteenth transistor T14 are electrically connected to the third gate signal output port G(N+3), and the gate of the thirteenth transistor T13 A drain and a drain of the fourteenth transistor T14 are electrically connected to a low-level voltage source VSS.

Due to the gate driving circuit and the array substrate of the embodiment of the present disclosure, the signal of the third gate signal output port is delayed from the signal of the second gate signal output port. Therefore, if the first pull-down unit is abnormal, the second pull-down unit can still turn off the shift register, pull down the potential of the first gate signal output port, and solve the problem of the distortion of the potential waveform causing the pixel Abnormal charging, etc.

Specifically, referring to FIGS. 3 and 5, assuming that the GOA circuit level transmission is abnormal due to process tolerances or unevenness, the second gate signal output port G(N+2) cannot be charged to a sufficiently high potential, so the The eleventh transistor T11 and the twelfth transistor T12 cannot be effectively turned on, and the gate signal output port G(N) cannot be pulled down to a low potential. However, the third gate signal output port G(N+3) can still be charged to a sufficiently high potential, so the thirteenth transistor T13 and the fourteenth transistor T14 can be effectively turned on and the gate signal The output port G(N) is pulled down to a low level to avoid abnormal pulses.

1 to 4, the present disclosure also provides an array substrate 1000 including: a substrate 400, a pixel array 300, a gate driving circuit 100, and a clock signal generator 200. The pixel array 300, the gate driving circuit 100, and the clock signal generator 200 are disposed on the substrate 400. The clock signal generator 200 is used to provide a clock signal to the gate driving circuit 100. The gate driving circuit 100 is used to drive the pixel array 300. Wherein, the gate driving circuit 100 includes: a plurality of shift registers 10. Each of the shift registers 10 includes: a pull-up control unit 1, a pull-up unit 2, a signal download unit 3, a first pull-down unit 4, a second pull-down unit 4', and a pull-down maintenance unit 5. The pull-up unit 2 is electrically connected to a first gate signal output port G(N). The first pull-down unit 4 is electrically connected to a second gate signal output port G(N+2). The second pull-down unit 4'is electrically connected to a third gate signal output port G(N+3). The signal of the third gate signal output port G (N+3) is delayed from the signal of the second gate signal output port G (N+2).

Although the present disclosure has been shown and described with respect to one or more implementation manners, those skilled in the art will think of equivalent variations and modifications based on the reading and understanding of the specification and the drawings. The present disclosure includes all such modifications and variations, and is limited only by the scope of the appended claims. Especially with regard to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (for example, it is functionally equivalent) , Even if the structure is not equivalent to the disclosed structure that performs the functions in the exemplary implementation of the present specification shown herein. In addition, although a specific feature of this specification has been disclosed with respect to only one of several implementations, this feature can be combined with one or more of other implementations that may be desirable and advantageous for a given or specific application. Other feature combinations. Moreover, as far as the terms "including", "having", "containing" or their variations are used in specific embodiments or claims, such terms are intended to be included in a similar manner to the term "comprising".

The above are only the preferred embodiments of the present disclosure. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present disclosure, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the present disclosure. protected range.

Claims

A gate drive circuit includes: a plurality of shift registers, wherein each of the shift registers includes: A pull-up control unit, a pull-up unit, a signal download unit, a first pull-down unit, a second pull-down unit, and a pull-down maintenance unit, wherein the pull-up unit is electrically connected to a first gate signal Output port, the first pull-down unit is electrically connected to a second gate signal output port, the second pull-down unit is electrically connected to a third gate signal output port, wherein the third gate signal output port The signal of is delayed from the signal of the second gate signal output port.
8. The gate driving circuit of claim 1, wherein the pull-up control unit is electrically connected to the pull-up unit, the signal download unit, the first pull-down unit, and the second pull-down unit And the pull-down maintaining unit, the first pull-down unit and the second pull-down unit are electrically connected to the gate signal output port.
3. The gate driving circuit of claim 2, wherein the pull-up control unit comprises a first transistor, a drain of the first transistor is electrically connected to the pull-up unit, and the first transistor A gate is electrically connected to a first signal source, and a source of the first transistor is electrically connected to a second gate signal output port.
3. The gate driving circuit of claim 3, further comprising a bootstrap capacitor electrically connected to the pull-up control unit, the pull-up unit, the signal download unit, and the pull-down sustain unit.
3. The gate driving circuit of claim 3, wherein the pull-down sustain unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, Wherein, a source of the third transistor and a source and a gate of the fourth transistor are electrically connected to a high-level voltage source, and a gate of the third transistor is electrically connected to the first A drain of the fourth transistor and a source of the sixth transistor, a drain of the third transistor is electrically connected to a gate of the seventh transistor, a gate of the eighth transistor and all A source of the fifth transistor, a source of the seventh transistor is electrically connected to the drain of the first transistor, and a source of the eighth transistor is electrically connected to the gate signal output Port, a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the drain of the first transistor, a drain of the fifth transistor, the sixth transistor A drain of the seventh transistor, and a drain of the eighth transistor are all electrically connected to a low-level voltage source.
5. The gate driving circuit of claim 3, wherein the pull-up unit comprises a ninth transistor, a gate of the ninth transistor is electrically connected to the drain of the first transistor, and A source of the ninth transistor is electrically connected to a first clock signal source, and a drain of the ninth transistor is electrically connected to the gate signal output port.
7. The gate driving circuit of claim 6, wherein the signal download unit comprises a tenth transistor, a source of the tenth transistor is electrically connected to the first clock signal source, and the tenth transistor A gate of the transistor is electrically connected to the drain of the first transistor, and a drain of the tenth transistor is electrically connected to a clock signal output port.
7. The gate driving circuit of claim 3, wherein the first pull-down unit includes an eleventh transistor and a twelfth transistor, and a source of the eleventh transistor is electrically connected to the gate A signal output port, a source of the twelfth transistor is electrically connected to the drain of the first transistor, a gate of the eleventh transistor and a gate of the twelfth transistor Electrically connected to the second gate signal output port, a drain of the eleventh transistor and a drain of the twelfth transistor are electrically connected to a low-level voltage source.
5. The gate driving circuit of claim 3, wherein the second pull-down unit includes a thirteenth transistor and a fourteenth transistor, and a source of the thirteenth transistor is electrically connected to the gate A signal output port, a source of the fourteenth transistor is electrically connected to the drain of the first transistor, a gate of the thirteenth transistor and a gate of the fourteenth transistor are electrically connected Connected to the third gate signal output port, a drain of the thirteenth transistor and a drain of the fourteenth transistor are electrically connected to a low-level voltage source.
An array substrate, comprising: a substrate, a pixel array, a gate drive circuit, and a clock signal generator, wherein the pixel array, the gate drive circuit, and the clock signal generator are arranged at On the substrate, the clock signal generator is used to provide a clock signal to the gate drive circuit, and the gate drive circuit is used to drive the pixel array, wherein the gate drive circuit includes: a plurality of shifters Bit register, wherein each of the shift registers includes: a pull-up control unit, a pull-up unit, a signal download unit, a first pull-down unit, a second pull-down unit, and a pull-down maintenance unit, wherein The pull-up unit is electrically connected to a first gate signal output port, the first pull-down unit is electrically connected to a second gate signal output port, and the second pull-down unit is electrically connected to a third gate A signal output port, wherein the signal of the third gate signal output port is delayed than the signal of the second gate signal output port.
10. The array substrate of claim 10, wherein the pull-up control unit is electrically connected to the pull-up unit, the signal download unit, the first pull-down unit, the second pull-down unit, and the The pull-down maintaining unit, the first pull-down unit and the second pull-down unit are electrically connected to the gate signal output port.
11. The array substrate of claim 11, wherein the pull-up control unit comprises a first transistor, a drain of the first transistor is electrically connected to the pull-up unit, and a gate of the first transistor The electrode is electrically connected to a first signal source, and a source of the first transistor is electrically connected to a second gate signal output port.
11. The array substrate of claim 12, further comprising a bootstrap capacitor electrically connected to the pull-up control unit, the pull-up unit, the signal download unit, and the pull-down maintenance unit.
11. The array substrate of claim 12, wherein the pull-down sustain unit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein, A source of the third transistor and a source and a gate of the fourth transistor are electrically connected to a high-level voltage source, and a gate of the third transistor is electrically connected to the fourth transistor A drain of the sixth transistor and a source of the sixth transistor, a drain of the third transistor is electrically connected to a gate of the seventh transistor, a gate of the eighth transistor and the first A source of five transistors, a source of the seventh transistor is electrically connected to the drain of the first transistor, and a source of the eighth transistor is electrically connected to the gate signal output port, A gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the drain of the first transistor, a drain of the fifth transistor, a drain of the sixth transistor The drain, a drain of the seventh transistor, and a drain of the eighth transistor are all electrically connected to a low-level voltage source.
11. The array substrate of claim 12, wherein the pull-up unit comprises a ninth transistor, a gate of the ninth transistor is electrically connected to the drain of the first transistor, and the ninth transistor A source of the transistor is electrically connected to a first clock signal source, and a drain of the ninth transistor is electrically connected to the gate signal output port.
15. The array substrate of claim 15, wherein the signal download unit comprises a tenth transistor, a source of the tenth transistor is electrically connected to the first clock signal source, and the A gate is electrically connected to the drain of the first transistor, and a drain of the tenth transistor is electrically connected to a clock signal output port.
11. The array substrate of claim 12, wherein the first pull-down unit comprises an eleventh transistor and a twelfth transistor, and a source of the eleventh transistor is electrically connected to the gate signal An output port, a source of the twelfth transistor is electrically connected to the drain of the first transistor, a gate of the eleventh transistor and a gate of the twelfth transistor are electrically connected To the second gate signal output port, a drain of the eleventh transistor and a drain of the twelfth transistor are electrically connected to a low-level voltage source.
12. The array substrate of claim 12, wherein the second pull-down unit comprises a thirteenth transistor and a fourteenth transistor, and a source of the thirteenth transistor is electrically connected to the gate signal output Port, a source of the fourteenth transistor is electrically connected to the drain of the first transistor, a gate of the thirteenth transistor and a gate of the fourteenth transistor are electrically connected to The third gate signal output port, a drain of the thirteenth transistor and a drain of the fourteenth transistor are electrically connected to a low-level voltage source.