CN110047450A - Gate driving circuit and array substrate - Google Patents
Gate driving circuit and array substrate Download PDFInfo
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- CN110047450A CN110047450A CN201910256967.9A CN201910256967A CN110047450A CN 110047450 A CN110047450 A CN 110047450A CN 201910256967 A CN201910256967 A CN 201910256967A CN 110047450 A CN110047450 A CN 110047450A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
This announcement provides gate driving circuit and array substrate.The gate driving circuit includes a plurality of shift registers.Each described shift register includes leaflet member under a pull-up control unit, a pull-up unit, a signal, one first drop-down unit, one second drop-down unit and a drop-down maintenance unit.First drop-down unit is electrically connected to a second grid signal output end mouth.Second drop-down unit is electrically connected to a third grid signal output port.Wherein signal delay of the signal of the third grid signal output port than the second grid signal output end mouth.
Description
[technical field]
This announcement is related to field of display technology, in particular to a kind of gate driving circuit and array substrate.
[background technique]
The basic conception of GOA (Gate Driver on Array) is that the gate driving circuit of TFT LCD is integrated in glass
On glass substrate, the turntable driving to liquid crystal display panel is formed.GOA not only can be substantially compared to traditional actuation techniques using COF
Degree saves manufacturing cost, and eliminates the bonding processing procedure of the side gate COF, and it is also extremely advantageous for being promoted to production capacity.Cause
This, GOA is the focus technology of the following liquid crystal display panel development.
The bad problem of process uniformity can be inevitably encountered in GOA production process, therefore, if a certain shift register phase
Circuit more corresponding than other shift registers, which is in the presence of that impedance is uneven, capacitor is uneven, then may cause this group of GOA circuit-level
Outflow is existing abnormal, to influence the stability of entire GOA circuit.
Therefore it is in need a kind of gate driving circuit and array substrate be provided, it is of the existing technology to solve the problems, such as.
[summary of the invention]
In order to solve the above technical problems, the one of this announcement is designed to provide gate driving circuit and array substrate, can solve
Situations such as certainly processing procedure tolerance or unevenness cause the outflow of GOA circuit-level existing abnormal.
To reach above-mentioned purpose, it includes a plurality of shift registers that this announcement, which provides a kind of gate driving circuit, wherein every
One shift register includes: leaflet member under a pull-up control unit, a pull-up unit, a signal, one first drop-down list
Member, one second drop-down unit and a drop-down maintenance unit.The pull-up unit is electrically connected to a first grid signal output end mouth.
First drop-down unit is electrically connected to a second grid signal output end mouth.Second drop-down unit is electrically connected to a third
Grid signal output port.Wherein the signal of the third grid signal output port is than the second grid signal output end mouth
Signal delay.
In the gate driving circuit as described in the examples of this announcement therein one, wherein the pull-up control unit is electrically connected
Leaflet member, first drop-down unit, second drop-down unit and drop-down dimension under to the pull-up unit, the signal
Hold unit.First drop-down unit and second drop-down unit are electrically connected to the grid signal output port.
In the gate driving circuit as described in the examples of this announcement therein one, wherein the pull-up control unit includes one
The first transistor, a drain electrode of the first transistor are electrically connected to the pull-up unit, a grid of the first transistor
It is electrically connected to one first signal source, a source electrode of the first transistor is electrically connected to a second grid signal output end mouth.
A bootstrap capacitor is further included in the gate driving circuit as described in the examples of this announcement therein one, is electrically connected to institute
State leaflet member and the drop-down maintenance unit under pull-up control unit, the pull-up unit, the signal.
In the gate driving circuit as described in the examples of this announcement therein one, wherein the drop-down maintenance unit includes one
Third transistor, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor and one the 8th transistor,
Wherein, a source electrode and a grid for a source electrode of the third transistor and the 4th transistor is electrically connected to high levle electricity
Potential source, a grid of the third transistor be electrically connected to the 4th transistor one drain electrode and the 6th transistor one
Source electrode, a drain electrode of the third transistor be electrically connected to a grid of the 7th transistor, the 8th transistor one
One source electrode of one source electrode of grid and the 5th transistor, the 7th transistor is electrically connected to the institute of the first transistor
State drain electrode, a source electrode of the 8th transistor is electrically connected to the grid signal output port, and the one of the 5th transistor
One grid of grid and the 6th transistor is electrically connected to the drain electrode of the first transistor, the 5th transistor
One drain electrode, a drain electrode of the 6th transistor, a drain electrode of the 7th transistor and a drain electrode of the 8th transistor
It is electrically connected to a low level voltage source.
In the gate driving circuit as described in the examples of this announcement therein one, wherein the pull-up unit includes one the 9th
Transistor, a grid of the 9th transistor are electrically connected to the drain electrode of the first transistor, the 9th transistor
A source electrode be electrically connected to one first signal source of clock, it is defeated that a drain electrode of the 9th transistor is electrically connected to the grid signal
Exit port.
In the gate driving circuit as described in the examples of this announcement therein one, wherein leaflet member includes one under the signal
Tenth transistor, a source electrode of the tenth transistor are electrically connected to first signal source of clock, the tenth transistor
One grid is electrically connected to the drain electrode of the first transistor, and a drain electrode of the tenth transistor is electrically connected to clock news
Number output port.
In the gate driving circuit as described in the examples of this announcement therein one, wherein first drop-down unit includes one
11st transistor and 1 the tenth two-transistor, a source electrode of the 11st transistor are electrically connected to the grid signal output
Port, a source electrode of the tenth two-transistor are electrically connected to the drain electrode of the first transistor, the 11st crystal
One grid of one grid of pipe and the tenth two-transistor is electrically connected to the second grid signal output end mouth, and the described tenth
A drain electrode and a drain electrode of the tenth two-transistor for one transistor is electrically connected to a low level voltage source.
In the gate driving circuit as described in the examples of this announcement therein one, wherein second drop-down unit includes one
13rd transistor and 1 the 14th transistor, a source electrode of the 13rd transistor are electrically connected to the grid signal output
Port, a source electrode of the 14th transistor are electrically connected to the drain electrode of the first transistor, the 13rd crystal
One grid of one grid of pipe and the 14th transistor is electrically connected to the third grid signal output port, and the described tenth
A drain electrode and a drain electrode of the 14th transistor for three transistors is electrically connected to a low level voltage source.
It includes: a substrate, a pixel array, a gate driving circuit and for the moment that this announcement, which also provides a kind of array substrate,
Clock signal generator.The pixel array, the gate driving circuit and the clock signal generator are set to the substrate
On.The clock signal generator is to provide clock signal to the gate driving circuit.The gate driving circuit to
Drive the pixel array.Wherein, the gate driving circuit includes: a plurality of shift registers.Each described displacement is posted
Storage includes: leaflet member under a pull-up control unit, a pull-up unit, a signal, one first drop-down unit, one second drop-down list
Member and a drop-down maintenance unit.The pull-up unit is electrically connected to a first grid signal output end mouth.First drop-down is single
Member is electrically connected to a second grid signal output end mouth.Second drop-down unit is electrically connected to a third grid signal output end
Mouthful.Wherein signal delay of the signal of the third grid signal output port than the second grid signal output end mouth.
Due to the gate driving circuit and array substrate of this revealed embodiment, the third grid signal output port
Signal delay of the signal than the second grid signal output end mouth.Therefore, if first drop-down unit occurs abnormal, institute
The shift register can still be closed by stating the second drop-down unit, pull down the current potential of the first grid signal output end mouth, be solved
Potential waveform occurs distorting so that situations such as pixel charging is abnormal.
For the above content of this announcement can be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate institute's accompanying drawings, makees
Detailed description are as follows:
[Detailed description of the invention]
Fig. 1 shows the structure block schematic diagram of the shift register of the embodiment according to this announcement；
Fig. 2 shows the structure block schematic diagram of the gate driving circuit of the embodiment according to this announcement；
Fig. 3 shows the structural circuit schematic diagram of the shift register of the embodiment according to this announcement；
Fig. 4 shows the structure block schematic diagram of the array substrate of the embodiment according to this announcement；And
Fig. 5 shows the circuit waveform schematic diagram of the shift register of the embodiment according to this announcement.
[specific embodiment]
In order to which the above-mentioned and other purposes of this announcement, feature, advantage can be clearer and more comprehensible, it is excellent that spy is hereafter lifted into this announcement
Embodiment is selected, and cooperates institute's accompanying drawings, is described in detail below.Furthermore the direction term that this announcement is previously mentioned, such as above and below,
Top, bottom, front, rear, left and right, inside and outside, side layer, around, center, it is horizontal, laterally, vertically, longitudinally, axial direction, radial direction, top layer or
Lowest level etc. is only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand this announcement, and
It is non-to limit this announcement.
The similar unit of structure is to be given the same reference numerals in the figure.
Referring to Fig.1, Fig. 2 and Fig. 5, it includes a plurality of shift registers 10 that this announcement, which provides a kind of gate driving circuit 100,
Wherein, each described shift register 10 include: leaflet member 3 under a pull-up control unit 1, a pull-up unit 2, a signal,
One first drop-down unit 4, one second drop-down unit 4 ' and a drop-down maintenance unit 5.The pull-up unit 2 is electrically connected to one first
Grid signal output port G (N).First drop-down unit 4 is electrically connected to a second grid signal output end mouth G (N+2).Institute
It states the second drop-down unit 4 ' and is electrically connected to a third grid signal output port G (N+3).The wherein third grid signal output
Signal delay of the signal G (N+3) of port than the second grid signal output end mouth G (N+2).
Specifically, each announcement of the application is by taking 4 clock grades pass shift register as an example, but the application not limiter stage
The order of biography, the teaching of general skill personnel Ke Yi the application of this field, in the case where not violating present invention spirit, by 4
Clock grade passes shift register and is modified as 6 clock grades biography shift register or 8 clock grades biography shift register etc..
In the gate driving circuit 100 as described in the examples of this announcement therein one, wherein 1 electricity of the pull-up control unit
Be connected to leaflet member 2 under the pull-up unit 2, the signal, first drop-down unit 4, second drop-down unit 4 ' and
The drop-down maintenance unit 5.It is defeated that first drop-down unit 4 and second drop-down unit 4 ' are electrically connected to the grid signal
Exit port G (N).
In the gate driving circuit 100 as described in the examples of this announcement therein one, wherein the pull-up control unit 1 is wrapped
Include a first transistor T1.A drain electrode of the first transistor T1 is electrically connected to the pull-up unit 2.The first transistor
A grid of T1 is electrically connected to one first signal source ST (N-2).A source electrode of the first transistor T1 is electrically connected to one second
Grid signal output port G (N-2).
A bootstrap capacitor 6 is further included in the gate driving circuit 100 as described in the examples of this announcement therein one, is electrically connected
Leaflet member 3 and the drop-down maintenance unit 5 under the pull-up control unit 1, the pull-up unit 2, the signal.
Referring to Fig.1 and 3, in the gate driving circuit 100 as described in the examples of this announcement therein one, wherein the drop-down
Maintenance unit 5 includes a third transistor T3, one the 4th transistor T4, one the 5th transistor T5, one the 6th transistor T6, one the
Seven transistor T7 and one the 8th transistor T8 a, wherein source electrode of the third transistor T3 is with the 4th transistor T4's
One source electrode and a grid are electrically connected to a high levle voltage source LC, and a grid of the third transistor T3 is electrically connected to described
A drain electrode of four transistor T4 and a source electrode of the 6th transistor T6, a drain electrode of the third transistor T3 are electrically connected to
A grid, a grid of the 8th transistor T8 and a source electrode of the 5th transistor T5 of the 7th transistor T7,
A source electrode of the 7th transistor T7 is electrically connected to the drain electrode of the first transistor T1, the 8th transistor T8's
One source electrode is electrically connected to the grid signal output port G (N), a grid and the 6th crystal of the 5th transistor T5
A grid of pipe T6 is electrically connected to the drain electrode of the first transistor T1, and the one of the 5th transistor T5 drains, is described
A drain electrode of 6th transistor T6, a drain electrode of the 7th transistor T7 and a drain electrode of the 8th transistor T8 are electrically connected
It is connected to a low level voltage source VSS.
Referring to Fig.1 and 3, in the gate driving circuit 100 as described in the examples of this announcement therein one, wherein the pull-up
Unit 2 includes one the 9th transistor T9, and a grid of the 9th transistor T9 is electrically connected to the institute of the first transistor T1
Drain electrode is stated, a source electrode of the 9th transistor T9 is electrically connected to one first signal source of clock CK1, the 9th transistor T9's
One drain electrode is electrically connected to the grid signal output port G (N).
Referring to Fig.1 and 3, in the gate driving circuit 100 as described in the examples of this announcement therein one, wherein the signal
Lower leaflet member 3 includes 1 the tenth transistor T10, and a source electrode of the tenth transistor T10 is electrically connected to the first clock letter
Number source CK1, a grid of the tenth transistor T10 are electrically connected to the drain electrode of the first transistor T1, and the described tenth
A drain electrode of transistor T10 is electrically connected to a clock signal output end mouth ST (N).
Referring to Fig.1 and 3, in the gate driving circuit 100 as described in the examples of this announcement therein one, wherein described first
Drop-down unit 4 includes 1 the 11st transistor T11 and 1 the tenth two-transistor T12, a source electrode of the 11st transistor T11
It is electrically connected to the grid signal output port G (N), a source electrode of the tenth two-transistor T12 is electrically connected to described first
The drain electrode of transistor T1, a grid of the 11st transistor T11 and the grid electricity of the tenth two-transistor T12
It is connected to the second grid signal output end mouth G (N+2), a drain electrode of the 11st transistor T11 and the described 12nd
A drain electrode of transistor T12 is electrically connected to a low level voltage source VSS.
Referring to Fig.1 and 3, in the gate driving circuit 100 as described in the examples of this announcement therein one, wherein described second
Drop-down unit 4 ' includes 1 the 13rd transistor T13 and 1 the 14th transistor T14, a source of the 13rd transistor T13
Pole is electrically connected to the grid signal output port G (N), and a source electrode of the 14th transistor T14 is electrically connected to described
The drain electrode of one transistor T1, a grid of the 13rd transistor T13 and a grid of the 14th transistor T14
It is electrically connected to the third grid signal output port G (N+3), a drain electrode of the 13rd transistor T13 and the described tenth
A drain electrode of four transistor T14 is electrically connected to a low level voltage source VSS.
Due to the gate driving circuit and array substrate of this revealed embodiment, the third grid signal output port
Signal delay of the signal than the second grid signal output end mouth.Therefore, if first drop-down unit occurs abnormal, institute
The shift register can still be closed by stating the second drop-down unit, pull down the current potential of the first grid signal output end mouth, be solved
Potential waveform occurs distorting so that situations such as pixel charging is abnormal.
Specifically, referring to Fig. 3 and 5, it is assumed that described because processing procedure tolerance or unevenness cause the outflow of GOA circuit-level existing abnormal
Second grid signal output end mouth G (N+2) can not be charged to enough high potentials, therefore the 11st transistor T11 and institute
Stating the tenth two-transistor T12 can not effectively open, and the grid signal output port G (N) can not be pulled down to low potential.But institute
Enough high potentials, therefore the 13rd transistor T13 can be still charged to by stating third grid signal output port G (N+3)
And the 14th transistor T14 can be opened effectively the grid signal output port G (N) being pulled down to low potential, be avoided
The generation of abnormal pulsers.
Referring to figs. 1 to 4, this announcement also provide a kind of array substrate 1000 include: a substrate 400, a pixel array 300,
One gate driving circuit 100 and a clock signal generator 200.The pixel array 300, the gate driving circuit 100,
And the clock signal generator 200 is set on the substrate 400.The clock signal generator 200 is to provide clock
Signal gives the gate driving circuit 100.The gate driving circuit 100 is to drive the pixel array 300.Wherein, institute
Stating gate driving circuit 100 includes: a plurality of shift registers 10.Each described shift register 10 includes: a pull-up control
Leaflet member 3, one first drop-down unit 4, one second drop-down unit 4 ' and a drop-down under unit 1 processed, a pull-up unit 2, a signal
Maintenance unit 5.The pull-up unit 2 is electrically connected to a first grid signal output end mouth G (N).First drop-down unit, 4 electricity
It is connected to a second grid signal output end mouth G (N+2).It is defeated that second drop-down unit 4 ' is electrically connected to a third grid signal
Exit port G (N+3).Wherein the signal of the third grid signal output port G (N+3) is than the second grid signal output end
The signal delay of mouth G (N+2).
Due to the gate driving circuit and array substrate of this revealed embodiment, the third grid signal output port
Signal delay of the signal than the second grid signal output end mouth.Therefore, if first drop-down unit occurs abnormal, institute
The shift register can still be closed by stating the second drop-down unit, pull down the current potential of the first grid signal output end mouth, be solved
Potential waveform occurs distorting so that situations such as pixel charging is abnormal.
Specifically, referring to Fig. 3 and 5, it is assumed that described because processing procedure tolerance or unevenness cause the outflow of GOA circuit-level existing abnormal
Second grid signal output end mouth G (N+2) can not be charged to enough high potentials, therefore the 11st transistor T11 and institute
Stating the tenth two-transistor T12 can not effectively open, and the grid signal output port G (N) can not be pulled down to low potential.But institute
Enough high potentials, therefore the 13rd transistor T13 can be still charged to by stating third grid signal output port G (N+3)
And the 14th transistor T14 can be opened effectively the grid signal output port G (N) being pulled down to low potential, be avoided
The generation of abnormal pulsers.
Although this announcement, those skilled in the art have shown and described relative to one or more implementations
It will be appreciated that equivalent variations and modification based on the reading and understanding to the specification and drawings.This announcement includes all such repairs
Change and modification, and is limited only by the scope of the following claims.In particular, to various functions executed by the above components, use
It is intended to correspond in the term for describing such component and executes the specified function of the component (such as it is functionally of equal value
) random component (unless otherwise instructed), even if in structure with execute the exemplary of this specification shown in this article and realize
The open structure of function in mode is not equivalent.In addition, although the special characteristic of this specification is relative to several realization sides
Only one in formula is disclosed, but this feature can with such as can be for a given or particular application expectation and it is advantageous
One or more other features combinations of other implementations.Moreover, with regard to term " includes ", " having ", " containing " or its deformation
For being used in specific embodiments or claims, such term is intended to wrap in a manner similar to the term " comprising "
It includes.
The above is only the preferred embodiments of this announcement, it is noted that for those of ordinary skill in the art, is not departing from
Under the premise of this announcement principle, several improvements and modifications can also be made, these improvements and modifications also should be regarded as the guarantor of this announcement
Protect range.
Claims (10)
1. a kind of gate driving circuit characterized by comprising a plurality of shift registers, wherein each described displacement is posted
Storage includes: leaflet member under a pull-up control unit, a pull-up unit, a signal, one first drop-down unit, one second drop-down list
Member and a drop-down maintenance unit, wherein the pull-up unit is electrically connected to a first grid signal output end mouth, under described first
Unit is drawn to be electrically connected to a second grid signal output end mouth, it is defeated that second drop-down unit is electrically connected to a third grid signal
Exit port, wherein the signal of the third grid signal output port prolongs than the signal of the second grid signal output end mouth
Late.
2. gate driving circuit as described in claim 1, which is characterized in that the pull-up control unit is electrically connected on described
Leaflet member, first drop-down unit, second drop-down unit and the drop-down maintenance unit under unit, the signal are drawn,
First drop-down unit and second drop-down unit are electrically connected to the grid signal output port.
3. gate driving circuit as claimed in claim 2, which is characterized in that the pull-up control unit includes a first crystal
Pipe, a drain electrode of the first transistor are electrically connected to the pull-up unit, and a grid of the first transistor is electrically connected to
One first signal source, a source electrode of the first transistor are electrically connected to a second grid signal output end mouth.
4. gate driving circuit as claimed in claim 3, which is characterized in that further include a bootstrap capacitor, be electrically connected to described
Leaflet member and the drop-down maintenance unit under pull-up control unit, the pull-up unit, the signal.
5. gate driving circuit as claimed in claim 3, which is characterized in that the drop-down maintenance unit includes a third crystal
Pipe, one the 4th transistor, one the 5th transistor, one the 6th transistor, one the 7th transistor and one the 8th transistor, wherein institute
It states a source electrode of third transistor and a source electrode of the 4th transistor and a grid is electrically connected to a high levle voltage source, institute
The grid for stating third transistor is electrically connected to a drain electrode and a source electrode of the 6th transistor for the 4th transistor, institute
The drain electrode for stating third transistor is electrically connected to a grid of the 7th transistor, a grid of the 8th transistor and institute
A source electrode of the 5th transistor is stated, a source electrode of the 7th transistor is electrically connected to the drain electrode of the first transistor,
One source electrode of the 8th transistor is electrically connected to the grid signal output port, a grid of the 5th transistor and institute
The grid for stating the 6th transistor is electrically connected to the drain electrode of the first transistor, a drain electrode of the 5th transistor,
One drain electrode of the 6th transistor, a drain electrode of the 7th transistor and a drain electrode of the 8th transistor are electrically connected
To a low level voltage source.
6. gate driving circuit as claimed in claim 3, which is characterized in that the pull-up unit includes one the 9th transistor,
One grid of the 9th transistor is electrically connected to the drain electrode of the first transistor, a source electrode of the 9th transistor
It is electrically connected to one first signal source of clock, a drain electrode of the 9th transistor is electrically connected to the grid signal output port.
7. gate driving circuit as claimed in claim 6, which is characterized in that leaflet member includes 1 the tenth crystal under the signal
Pipe, a source electrode of the tenth transistor are electrically connected to first signal source of clock, the grid electricity of the tenth transistor
It is connected to the drain electrode of the first transistor, a drain electrode of the tenth transistor is electrically connected to a clock signal output end
Mouthful.
8. gate driving circuit as claimed in claim 3, which is characterized in that first drop-down unit includes 1 the 11st brilliant
Body pipe and 1 the tenth two-transistor, a source electrode of the 11st transistor are electrically connected to the grid signal output port, institute
The source electrode for stating the tenth two-transistor is electrically connected to the drain electrode of the first transistor, a grid of the 11st transistor
One grid of pole and the tenth two-transistor is electrically connected to the second grid signal output end mouth, the 11st transistor
A drain electrode and a drain electrode of the tenth two-transistor be electrically connected to a low level voltage source.
9. gate driving circuit as claimed in claim 3, which is characterized in that second drop-down unit includes 1 the 13rd brilliant
Body pipe and 1 the 14th transistor, a source electrode of the 13rd transistor are electrically connected to the grid signal output port, institute
The source electrode for stating the 14th transistor is electrically connected to the drain electrode of the first transistor, a grid of the 13rd transistor
One grid of pole and the 14th transistor is electrically connected to the third grid signal output port, the 13rd transistor
A drain electrode and a drain electrode of the 14th transistor be electrically connected to a low level voltage source.
10. a kind of array substrate characterized by comprising a substrate, a pixel array, a gate driving circuit and a clock
Signal generator, wherein the pixel array, the gate driving circuit and the clock signal generator are set to described
On substrate, the clock signal generator is to provide clock signal to the gate driving circuit, the gate driving circuit
To drive the pixel array, wherein the gate driving circuit includes: a plurality of shift registers, wherein each institute
Stating shift register includes: leaflet member under a pull-up control unit, a pull-up unit, a signal, one first drop-down unit, one
Two drop-down units and a drop-down maintenance unit, wherein the pull-up unit is electrically connected to a first grid signal output end mouth, institute
It states the first drop-down unit and is electrically connected to a second grid signal output end mouth, second drop-down unit is electrically connected to a third grid
Pole signal output end mouth, wherein the signal of the third grid signal output port is than the second grid signal output end mouth
Signal delay.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910256967.9A CN110047450A (en) | 2019-04-01 | 2019-04-01 | Gate driving circuit and array substrate |
| PCT/CN2019/098478 WO2020199437A1 (en) | 2019-04-01 | 2019-07-31 | Gate driving circuit and array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910256967.9A CN110047450A (en) | 2019-04-01 | 2019-04-01 | Gate driving circuit and array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110047450A true CN110047450A (en) | 2019-07-23 |
Family
ID=67275757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910256967.9A Pending CN110047450A (en) | 2019-04-01 | 2019-04-01 | Gate driving circuit and array substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110047450A (en) |
| WO (1) | WO2020199437A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110599898A (en) * | 2019-08-20 | 2019-12-20 | 深圳市华星光电技术有限公司 | Grid driving array type display panel |
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| WO2020199437A1 (en) * | 2019-04-01 | 2020-10-08 | 深圳市华星光电技术有限公司 | Gate driving circuit and array substrate |
| CN110599898A (en) * | 2019-08-20 | 2019-12-20 | 深圳市华星光电技术有限公司 | Grid driving array type display panel |
| US11308834B2 (en) | 2019-08-20 | 2022-04-19 | Tcl China Star Optoelectronics Technology Co., Ltd. | GOA display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020199437A1 (en) | 2020-10-08 |
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