WO2020199164A1 - Écran d'affichage et dispositif d'affichage - Google Patents

Écran d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2020199164A1
WO2020199164A1 PCT/CN2019/081277 CN2019081277W WO2020199164A1 WO 2020199164 A1 WO2020199164 A1 WO 2020199164A1 CN 2019081277 W CN2019081277 W CN 2019081277W WO 2020199164 A1 WO2020199164 A1 WO 2020199164A1
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WO
WIPO (PCT)
Prior art keywords
layer
signal shielding
electrode
display panel
signal
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Application number
PCT/CN2019/081277
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English (en)
Chinese (zh)
Inventor
尹翔
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深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201980079793.1A priority Critical patent/CN113348407A/zh
Priority to PCT/CN2019/081277 priority patent/WO2020199164A1/fr
Publication of WO2020199164A1 publication Critical patent/WO2020199164A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular to a display panel and a display device.
  • the overlap capacitance between the metal trace and the cathode in the existing display panel is relatively large, which is prone to signal crosstalk.
  • the voltage of the cathode is easily affected and fluctuates, thereby affecting the display effect of the display panel.
  • the embodiments of the present application provide a display panel and a display device, which can improve the display effect of the display panel.
  • a display panel including:
  • the driving layer is provided with electrode line components
  • the pixel unit includes a pixel electrode layer, and the pixel electrode layer is laminated on the driving layer;
  • the signal shielding layer is laminated between the driving layer and the pixel unit, and is used to shield the interference of the signal flowing through the electrode line assembly to the pixel electrode layer.
  • the plane where the driving layer is located be a projection plane
  • the orthographic projection of the signal shielding layer on the projection plane at least partially covers the electrode wire assembly.
  • the electrode wire assembly includes:
  • a plurality of first electrode lines are sequentially arranged on the driving layer
  • a plurality of second electrode lines are arranged on the driving layer in sequence;
  • the orthographic projection of the signal shielding layer on the projection plane covers at least part of the plurality of first electrode lines and/or the plurality of second electrode lines.
  • the signal shielding layer includes:
  • a first signal shielding layer, the orthographic projection of the first signal shielding layer on the projection plane covers all of the plurality of first electrode lines;
  • a second signal shielding layer, the orthographic projection of the second signal shielding layer on the projection plane covers all of the plurality of second electrode lines.
  • the first signal shielding layer includes a plurality of first signal shielding portions, and the orthographic projection of each of the first signal shielding portions on the projection plane covers a corresponding one of the first electrode lines, and each One ends of the first signal shielding portion are all connected to the same preset potential.
  • the second signal shielding layer includes a plurality of second signal shielding portions, and the orthographic projection of each second signal shielding portion on the projection plane covers a corresponding one of the second electrode lines, and each One ends of the second signal shielding portion are all connected to the same preset potential.
  • any two first electrode lines in the plurality of first electrode lines are parallel to each other, any two second electrode lines in the plurality of second electrode lines are parallel to each other, and the plurality of second electrode lines Any one of the second electrode lines intersects any one of the plurality of first electrode lines;
  • any one of the second signal shielding parts and any one of the first signal shielding parts have overlapping parts.
  • one end of each of the first signal shielding portions extends out of the display area of the display panel
  • each second signal shielding portion extends out of the display area of the display panel.
  • the first electrode line is a data line
  • the second electrode line is a scan line
  • the first electrode line is a scan line
  • the second electrode line is a data line
  • the signal shielding layer is connected to a preset potential.
  • the preset potential is a ground potential.
  • the pixel electrode layer is a cathode.
  • the driving layer includes:
  • the switch array layer is provided with the electrode wire assembly
  • the pixel defining layer is laminated on the substrate and away from the passivation layer, and the pixel electrode layer is laminated on the pixel defining layer and away from the substrate.
  • the substrate is patterned to form the signal shielding layer.
  • the driving layer further includes a first insulating layer, the first insulating layer is laminated between the switch array layer and the passivation layer, and the signal shielding layer is laminated on the first insulating layer And the passivation layer.
  • the driving layer further includes a second insulating layer, the second insulating layer is laminated between the substrate and the pixel defining layer, and the signal shielding layer is laminated on the second insulating layer and The pixels define between layers.
  • a thin film transistor substrate includes the thin film transistor.
  • a display device includes the display panel as described above.
  • the driving layer is provided with an electrode line assembly
  • the pixel unit includes a pixel electrode layer
  • the pixel electrode layer is laminated on the driving layer
  • the signal shielding layer is laminated on the driving layer and Between the pixel units, the signal shielding layer is used to shield the interference of the signal flowing through the electrode line assembly on the pixel electrode layer. Therefore, it can reduce the influence of the signal on the voltage or current in the pixel electrode layer, thereby improving the signal crosstalk of the display panel Phenomenon, thereby improving the display effect of the display panel.
  • FIG. 1a is a schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • FIG. 1b is a schematic diagram of the layout between the electrode line assembly, the pixel electrode layer, and the signal shielding layer in a display panel provided by an embodiment of the present application;
  • FIG. 1c is a schematic diagram of orthographic projection of the signal shielding layer onto the projection plane with the plane where the driving layer is located as the projection plane provided by an embodiment of the present application;
  • FIG. 2 is a schematic diagram of the layout between the electrode line assembly, the pixel electrode layer and the signal shielding layer in a display panel provided by another embodiment of the present application;
  • 3a is a schematic cross-sectional view of the display panel cut along the AA" direction at the overlapping portion of the signal shielding layer, the first wiring layer, and the second wiring layer according to an embodiment of the present application;
  • 3b is a schematic cross-sectional view of the display panel along the AA′′ direction at the overlapping portion of the signal shielding layer, the first wiring layer, and the second wiring layer according to another embodiment of the present application;
  • 3c is a schematic cross-sectional view of the display panel along the AA′′ direction at the overlapped portion of the signal shielding layer, the first wiring layer, and the second wiring layer provided by still another embodiment of the present application.
  • sputtering electroplating, molding, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), evaporation, hybrid physical-chemical vapor deposition (Hybrid Physical-Chemical Vapor Deposition, HPCVD) , Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), etc.
  • CVD chemical Vapor Deposition
  • PVD physical vapor deposition
  • evaporation hybrid physical-chemical vapor deposition
  • HPCVD Hybrid Physical-Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the structural shape of the thin film transistor provided by the embodiments of the present application can be square, rectangular, ring or diamond, etc. It is understood that the "ring" herein includes an approximate ring, as long as those skilled in the art, according to the content described herein, Other replacements or improvements are made to the structure and shape of the thin film transistor, and all thin film transistors with a certain structure and shape should fall within the protection scope of the embodiments of the present application.
  • a display panel 10 provided by an embodiment of the present application includes a driving layer 20, a pixel unit 30 and a signal shielding layer 40.
  • the display panel 10 provided in this embodiment may be a TFT screen (Thin Film Transistor, TFT film field effect transistor) or a TFD screen (Thin Film Diode, TFD film diode), UFB screen (Ultra Fine Bright, UFB), STN screen (Super Twisted Nematic, STN), OLED screen (Organic Light-Emitting Diode, OLED organic light-emitting diode), AMOLED screen (Active Matrix/Organic Light Emitting Diode) , AMOLED active matrix organic light-emitting diode panel) and so on.
  • TFT screen Thi Film Transistor, TFT film field effect transistor
  • TFD screen Thi Film Diode, TFD film diode
  • UFB screen Ultra Fine Bright, UFB
  • STN screen Super Twisted Nematic, STN
  • OLED screen Organic Light-Emitting Diode, OLED organic light-emitting diode
  • AMOLED screen Active Matrix/Organic Light Emitting Diode
  • the display panel 10 includes a display area 11, and the display area 11 is used to display images generated under the action of a plurality of pixel units 30.
  • the driving layer 20 is used to drive the pixel unit 30 to display images.
  • the driving layer 20 can adopt any suitable driving structure.
  • the driving layer 20 can adopt a thin film transistor array substrate composed of bottom gate thin film transistors, or a top gate
  • the thin film transistor array substrate composed of thin film transistors can even be a thin film transistor array substrate composed of double gate thin film transistors mixed with bottom gate and top gate.
  • the driving layer 20 is provided with an electrode line assembly 50, which is used to transmit scan signals and/or data signals. For example, when the electrode line assembly 50 is applied with a scan signal to gate the corresponding thin film transistors in the driving layer 20, the data The signal can then be output to the corresponding pixel unit 30.
  • the layout of the electrode wire assembly 50 on the driving layer 20 can be defined by itself according to actual business requirements.
  • the pixel unit 30 is used to display an image.
  • the pixel unit 30 here can be an LCD pixel unit or an OLED pixel unit.
  • the pixel unit 30 includes an anode, an organic functional layer, etc. , Cathode, polarizer, touch module, etc.
  • the organic functional layer may be composed of the following structural layers in sequence: a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, and an electron injection layer.
  • the pixel unit 30 includes a pixel electrode layer 31, and the pixel electrode layer 31 is laminated on the driving layer 20.
  • the pixel electrode layer 31 serves as an electrode for being applied with a voltage.
  • the pixel electrode layer 31 is an anode.
  • the pixel electrode layer 13 is a cathode.
  • the signal shielding layer 40 is laminated between the driving layer 20 and the pixel unit 30.
  • the signal shielding layer 40 is used to shield the interference of the signal flowing through the electrode line assembly 50 to the pixel electrode layer 31.
  • the signal is a high-frequency signal or an enable If the signal lacks the shielding effect of the signal shielding layer 40, the high-frequency signal or the enable signal will greatly affect the stability and reliability of the voltage or current in the pixel electrode layer 31. Through the shielding effect of the signal shielding layer 40, the voltage or current in the pixel electrode layer 31 is relatively stable and reliable, so as to display reliable and high-quality images.
  • the signal shielding layer 40 is made of metal materials or metal oxides.
  • the signal shielding layer 40 can shield the interference of the signal flowing through the electrode line assembly 50 on the pixel electrode layer, thereby reducing the influence of high-frequency signals on the voltage or current in the pixel electrode layer 31, thereby improving the signal of the display panel 10.
  • the crosstalk phenomenon further improves the display effect of the display panel 10.
  • the pixel electrode layer 31 is used as an anode or a cathode, an overlap capacitance is formed between the pixel electrode layer 31 and the pixel electrode layer 31. Therefore, when a high frequency signal flows through the electrode line assembly 50, the high frequency signal will affect The voltage or current to the pixel electrode layer 31 is stable.
  • the plane where the driving layer 20 is located is the projection plane 20a, and the orthographic projection 20b of the signal shielding layer 40 on the projection plane covers the electrode wire assembly 50.
  • the signal shielding layer 40 is provided directly above the electrode line assembly 50, that is, the signal shielding layer 40 is interposed between the electrode line assembly 50 and the pixel electrode layer 31.
  • the signal shielding layer 40 can shield the influence of high-frequency signals on the voltage or current in the pixel electrode layer 31.
  • the width of the orthographic projection is greater than the width of the electrode wire assembly 50, it is understandable that in some embodiments, the shape or width of the orthographic projection can be better adapted to the shape or width of the electrode wire assembly 50.
  • the orthographic projection of the signal shielding layer 40 on the projection plane is to completely cover the electrode wire assembly 50.
  • the orthographic projection of the signal shielding layer 40 on the projection plane may also partially cover the electrode wire assembly 50.
  • the signal shielding layer 40 is connected to a preset potential, where the preset potential is any suitable constant potential, for example, the preset potential is a ground potential. Since the signal shielding layer 40 is connected to the same preset potential, it can ensure that when the signal shielding layer 40 shields high-frequency signals, the signal shielding layer 40 has a uniform reference potential to avoid local currents or harmful magnetic fields caused by high-frequency signals. Interference, thereby reliably improving the signal shielding layer 40 to shield the interference of high frequency signals on the pixel electrode layer 31.
  • the metal layer wiring design scheme of most display panels is as follows: the scan line is wired on the thin film transistor substrate, the data line is wired on the scan line, the cathode is laid out on the data line, and the anode is laid out on the cathode.
  • the cathode is the closest to the data line, and the overlap capacitance between the cathode and the data line is relatively large, and high-frequency signals are easier to couple to the voltage or current of the cathode, thereby causing signal crosstalk.
  • the shielding effect of the signal shielding layer 40 can make the display effect of the display panel provided by this embodiment better than most existing display panels.
  • the electrode wire assembly 50 includes a plurality of first electrode wires 501 and a plurality of second electrode wires 502.
  • a plurality of first electrode lines 501 are sequentially arranged on the driving layer 20, and a plurality of second electrode lines 502 are sequentially arranged on the driving layer 20.
  • the second electrode lines 502 Is the scan line.
  • the first electrode line 501 is a scan line
  • the second electrode line 502 is a data line.
  • the orthographic projection of the signal shielding layer 40 on the projection plane covers at least part of the first electrode lines 501 and/or the second electrode lines 502, that is, it is understandable that the signal shielding layer 40 is
  • the orthographic projection of the projection plane can cover one or more of a large number of first electrode lines 501, can also cover one or more of a large number of second electrode lines 502, or can simultaneously cover a large number of first electrode lines 501
  • One or more of and one or more of the plurality of second electrode lines 502 may also cover the entire number of first electrode lines 501 and/or the entire number of second electrode lines 502.
  • the first electrode line 501 is a scan line
  • the second electrode line 502 is a data line.
  • the orthographic projection of the signal shielding layer 40 on the projection plane covers a portion of the first electrode lines 501 or the first electrode lines 501
  • the two-electrode line 502 can shield the high frequency signal from the data line or the scan line.
  • the orthographic projection of the signal shielding layer 40 on the projection plane covers a portion of a number of first electrode lines 501 and a number of second electrode lines 502, it can simultaneously shield high-frequency signals from data lines and scan lines, thereby extremely The display effect of the display panel 10 is greatly improved.
  • the signal shielding layer 40 includes: a first signal shielding layer 41 and a second signal shielding layer 42.
  • the orthographic projection of the first signal shielding layer 41 on the projection plane covers all several first electrode lines 501, and the orthographic projection of the second signal shielding layer 42 on the projection plane covers all several second electrode lines 502.
  • Adopting a layered shielding structure which can adaptively follow the routing structure of the first electrode line 501 and the second electrode line 502 to provide the first signal shielding layer 41 and the second signal shielding layer 42 respectively. Therefore, it can be better Ground shields the interference of the pixel electrode layer 31 from high-frequency signals from various types and electrode lines.
  • the first signal shielding layer 41 includes a plurality of first signal shielding portions 411, and the orthographic projection of each first signal shielding portion 411 on the projection plane covers a corresponding first electrode line 501 One end of each first signal shielding portion 411 extends out of the display area 11 of the display panel 10, and one end of each first signal shielding portion 411 is connected to the same preset potential.
  • the second signal shielding layer 42 includes a plurality of second signal shielding portions 421.
  • the orthographic projection of each second signal shielding portion 421 on the projection plane covers a corresponding second electrode line 502, and one end of each second signal shielding portion 421 extends The display area 11 of the display panel 10 is shown, and one end of each second signal shielding portion 421 is connected to the same preset potential.
  • each first electrode line 501 or second electrode line 502 corresponds to its own signal shielding part, it can better shield the pixel electrodes from high-frequency signals from various and various electrode lines. Layer 31 interference.
  • the first electrode line 501 and the second electrode line 502 are routed in a "well" shape, that is, any two first electrode lines 501 among the plurality of first electrode lines 501 are parallel to each other, and several Any two of the second electrode wires 502 are parallel to each other, and any one of the plurality of second electrode wires 502 is connected to any one of the plurality of first electrode wires 501. Intersect, for example, the second electrode line 502 is perpendicular to the first electrode line 501.
  • any second signal shielding portion 421 and any first signal shielding portion 411 have overlapping portions 43. That is, the first signal shielding portion 411 and the second signal shielding portion 421 can be masked on the same layer structure, so that any second signal shielding portion 421 and any first signal shielding portion 411 have overlapping portions 43 .
  • the driving layer 20 includes a switch array layer 21, a passivation layer 22, a substrate 23, and a pixel defining layer 24.
  • the switch array layer 21 is used to receive scan signals or data signals to drive the pixel unit 30 to display images.
  • the switch array layer 21 is provided with an electrode line assembly 21.
  • the switch array layer 21 includes a thin film transistor substrate 211, a first wiring layer 212, and an interlayer dielectric layer stacked in sequence. 213 and the second wiring layer 214, wherein the first wiring layer 212 is provided with a first electrode line 501, the second wiring layer 214 is provided with a second electrode line 502, the first electrode line 501 can be used as a scan line, The two-electrode line 502 can be used as a data line.
  • the thin film transistor substrate 211 may use a flexible substrate or a rigid substrate.
  • the flexible substrate includes flexible materials such as thin glass, metal foil, or plastic substrate.
  • the plastic substrate includes a flexible structure coated on both sides of the base film.
  • the base film includes such as polyimide (PI), polycarbonate (PC), polyethylene glycol terephthalate (PET), polyethersulfone (PES), polyethylene film (PEN), fiber reinforced plastic ( FRP) and other resins.
  • the rigid substrate can be, but is not limited to, a glass substrate, a metal substrate, or a ceramic substrate.
  • the interlayer dielectric layer 213 can protect the thin film transistor from moving particles or other undesirable impurity charges, and it can attract the impurity charges from the electrode terminals to prevent the thin film transistor from being affected by the impurity charges and the like.
  • the passivation layer 22 is laminated on the switch array layer 21, and the passivation layer 22 contributes to the improvement of the electrical characteristics of the thin film transistor.
  • the passivation layer 22 can be a silicon nitride insulating layer, which has excellent photoelectric properties, mechanical properties, and strong barriers to impurity particle diffusion and water vapor penetration.
  • the thinner silicon nitride insulating layer is not easy to block the diffusion phenomenon, and as the thickness of the passivation layer 22 increases, the contaminant concentration at the interface of the active layer decreases. However, when the thickness exceeds a critical value, the contaminant concentration will decrease.
  • the thickness of the passivation layer 22 is set to be 100-400 nm without being greatly reduced and reaching a minimum value.
  • the passivation layer 22 may also adopt a single-layer silicon dioxide (SiO2) or double-layer silicon dioxide/silicon nitride (SiO2/SiNx) structure or an organic film layer structure.
  • the substrate 23 is laminated on the passivation layer 22 and away from the switch array layer 21.
  • the substrate 23 is a transparent glass substrate.
  • the substrate 23 includes indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). , Indium Tin Zinc Oxide (ITZO), etc.
  • the pixel defining layer 24 is stacked on the substrate 23 and away from the passivation layer 22, and the pixel electrode layer 31 is stacked on the pixel defining layer 24 and away from the substrate 23.
  • the pixel defining layer 24 defines the position of the pixel unit 30, wherein the shape of the pixel defining layer 24 can be any suitable shape, such as trapezoid, inverted trapezoid, rectangle, square and so on.
  • the signal shielding layer 40 is provided in the substrate 23 by a mask, that is, the substrate 23 is patterned to form the aforementioned signal shielding layer 40.
  • the user can avoid the original substrate pattern on the substrate 23 and add a pattern of the signal shielding layer 40.
  • the user can also recreate the mask, which re-lays out the substrate pattern and the signal shielding layer 40 pattern.
  • the signal shielding layer 40 is connected in series and connected to the ground potential.
  • the signal shielding layer 40 is designed. Since the signal shielding layer 40 is patterned in the substrate 23, no additional layer structure is required. Therefore, the thickness of the driving layer 20 can be reduced.
  • the difference from the above-mentioned embodiments is that the signal shielding layer 40 can be separately provided as a layer structure at a corresponding position.
  • the driving layer 20 further includes a first insulating layer 25, the first insulating layer 25 is laminated between the switch array layer 21 and the passivation layer 22, and the signal shielding layer 40 is laminated on the first insulating layer 25 and the passivation layer. ⁇ 22 Among them.
  • the signal shielding layer 40 is connected in series and connected to the ground potential.
  • the first insulating layer 25 may adopt a single-layer silicon dioxide (SiO2) or a double-layer silicon dioxide/silicon nitride (SiO2/SiNx) structure or an organic film layer structure.
  • the remaining metal portion in the signal shielding layer 40 can form a pixel capacitor with the first wiring layer 21 or the second wiring layer 214.
  • the signal shielding layer 40 is designed in this way. On the one hand, it can shield the interference of high-frequency signals. On the other hand, it can increase the pixel capacitance and improve the display effect.
  • the difference from the foregoing embodiments is that the signal shielding layer 40 can be separately provided as a layer structure at another corresponding position.
  • the driving layer 20 further includes a second insulating layer 26, the second insulating layer 26 is laminated between the substrate 23 and the pixel defining layer 24, and the signal shielding layer 40 is laminated on the second insulating layer 26 and the pixel defining layer. Between layers 24. In this embodiment, the signal shielding layer 40 is connected in series and connected to the ground potential.
  • the second insulating layer 26 may adopt a single-layer silicon dioxide (SiO2) or double-layer silicon dioxide/silicon nitride (SiO2/SiNx) structure or an organic film layer structure.
  • the signal shielding layer 40 and the second wiring layer 214 are sequentially separated from the passivation layer 22, the substrate 23 and the second insulating layer 26, relatively speaking, the signal shielding layer 40 and the second wiring layer The distance between the 214 is relatively long, which can reduce the interference of the electrons in the signal shielding layer 40 on the second electrode line 502 carrying high-frequency signals.
  • the signal shielding layer 40 having a distance can reduce the impedance of the second electrode line 502.
  • the embodiments of the present application provide a display device.
  • the display device can select the display panels described in the above embodiments.
  • the signal shielding layer in the display panel can shield the high-frequency signal in the electrode line assembly, the influence of the high-frequency signal on the voltage in the pixel electrode layer is reduced, thereby improving the signal crosstalk phenomenon of the display device and further improving the display effect of the display device.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un écran d'affichage (10) et un dispositif d'affichage. L'écran d'affichage (10) comprend une couche de commande 20), une unité de pixel (30) et une couche de blindage de signal (40). La couche de commande (20) est pourvue d'un composant de fil d'électrode (50). L'unité de pixel (30) comprend une couche d'électrode de pixel (31) empilée sur la couche de commande (20). La couche de blindage de signal (40) est empilée entre la couche de commande (20) et l'unité de pixel (30), et est utilisée pour protéger la couche d'électrode de pixel (31) contre une interférence à partir de signaux transmis dans le composant de fil d'électrode (50). Ainsi, l'invention peut réduire l'impact de signaux transmis dans le composant de fil d'électrode (50) sur des tensions ou des courants dans la couche d'électrode de pixel (31), réduisant ainsi la diaphonie de signal de l'écran d'affichage (10), et améliorant les performances d'affichage de l'écran d'affichage (10).
PCT/CN2019/081277 2019-04-03 2019-04-03 Écran d'affichage et dispositif d'affichage WO2020199164A1 (fr)

Priority Applications (2)

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CN201980079793.1A CN113348407A (zh) 2019-04-03 2019-04-03 显示面板及显示装置
PCT/CN2019/081277 WO2020199164A1 (fr) 2019-04-03 2019-04-03 Écran d'affichage et dispositif d'affichage

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CN104597643A (zh) * 2015-01-30 2015-05-06 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN109154758A (zh) * 2016-05-31 2019-01-04 伊英克公司 用于电光显示器的背板
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