WO2020199059A1

WO2020199059A1 - Multi-channel multi-carrier transceiver

Info

Publication number: WO2020199059A1
Application number: PCT/CN2019/080695
Authority: WO
Inventors: 毛懿鸿; 高鹏
Original assignee: 华为技术有限公司
Priority date: 2019-03-30
Filing date: 2019-03-30
Publication date: 2020-10-08
Also published as: CN113508529A

Abstract

Provided is a multi-channel multi-carrier transceiver, comprising: a first channel for transmitting a first carrier; a second channel for transmitting a second carrier; a first ADPLL coupled to the first channel and used for providing a local oscillator signal for the first channel; a second ADPLL coupled to the second channel and used for providing a local oscillator signal for the second channel; and a configuration circuit coupled to the first ADPLL and the second ADPLL respectively and used for configuring the first ADPLL or the second ADPLL according to combination information of the first carrier and the second carrier. A phase-locked loop is configured according to combination information of a plurality of carriers, so that the phase-locked loop can eliminate spurs caused by frequency pulling of the plurality of carriers, and the reliability of multi-channel multi-carrier communication is improved; a plurality of phase-locked loops can be arranged side by side in parallel on a layout and are not limited to the loop bandwidth of the phase-locked loop; and area overheads can be economized, and the area cost introduced itself is small.

Description

Multi-channel multi-carrier transceiver

Technical field

This application relates to the field of electronic technology, and in particular to a multi-channel multi-carrier transceiver.

Background technique

In the radio frequency chip, a phase-locked loop is used to provide a stable local oscillator (LO) signal to the transmitter and receiver. Among them, as shown in Figure 1 is a schematic diagram of the structure of an all digital phase-locked loop (ADPLL) in the radio frequency transceiver. Compared with the traditional phase-locked loop, the area of the ADPLL can be more flexibly adjusted with the process size The decline in the decrease, so it is more and more widely used. ADPLL generally includes a time-digital converter (TDC), a digital filter, a digital-controlled oscillator (DCO), and a feedback divider (Ndivider). The principle of the phase-locked loop is to use a high-precision clock as a reference source to generate a high-frequency signal of several multiples of its frequency. The actual required LO signal is generated through a frequency divider (LO Div in Figure 1). The frequency conversion mixer (as shown in Figure 1 up-converter) and power amplifier (power amplifier, PA) then transmit the baseband signal, or the low-noise amplifier (low noise amplifier) is passed through the down-conversion mixer (mixer) in the receiver. The received radio frequency signal is converted into a baseband signal.

When there are multiple phase-locked loops working at the same time on the chip, such as in the scenario of discontinuous carrier aggregation, there are spurs or interference caused by frequency pulling between multiple DCOs. These spurs all make the output signal of the phase-locked loop exceed the spectrum mask defined by the transmitting system at the corresponding frequency deviation, deteriorate the noise figure of the blocking scene defined by the receiving system, or directly deteriorate the noise of the phase-locked loop. Due to the coexistence of multiple local oscillator frequencies and clocks in the system and many interference paths, spurs have become the most critical indicator in the engineering design of the phase-locked loop.

An existing method for reducing spurious or interference is mainly to use the low-pass characteristic of the filter in the phase-locked loop to filter the spurious. For low-order modulation systems with low noise requirements, reducing the loop bandwidth can effectively suppress out-of-band spurs. As shown in Figure 2, the bandwidth to spur suppression schematic diagram, after the loop bandwidth is reduced from 150kHz to about 70kHz, the spur is reduced by about 12dB.

However, as the system has higher and higher requirements for the integrated phase noise of the phase-locked loop, the use of a small bandwidth cannot meet the noise requirements of the system. When the bandwidth is increased, the loop's ability to suppress spurs deteriorates, even when the spurs fall into the ring The back loop within the channel bandwidth has no ability to suppress spurs. In this case, it is no longer possible to optimize the bandwidth to meet the requirements of low noise and low spurious at the same time. In addition, because the smallest raster in 5G applications is 15kHz, it can theoretically generate spurs of 15kHz and its harmonics, and the typical bandwidth of a phase-locked loop is much greater than 15kHz, so spurs cannot be suppressed by reducing the bandwidth.

In addition to optimizing bandwidth, another way to reduce spurious or interference is to use the schematic diagram of the interference source and the interfered source isolation scheme as shown in Figure 3. Through careful layout and routing, improve the interference sources (such as DCO/ The isolation between PA/power supply, etc. and the interfered source (clock trace/DCO/power supply, etc.) can also improve better spurious performance. For example, the distance between the inductances of two DCOs is 100um, and the spur caused by pulling is -40dBc. If it is stretched farther to 200um, the spur can be reduced to -50dBc, which reduces the influence of integrated phase noise. Or the distance between the clock trace and the DCO inductor is 100um, resulting in the decimal spur on the output spectrum being -60dBc, which cannot meet the spectral mask requirements of the transmitter. If the distance is 200um and the spur is reduced to -70dBc, the requirement is met.

However, the method to increase the isolation between the interference source and the interfered source is often to extend the interference source and the interfered source, or use a protection ring/protection band, or use different power supplies for modules with different operating frequencies to obtain sufficient These methods will increase the chip area. In addition, as communication systems become more and more complex, there are more and more on-chip subsystems, and interference sources and interference channels have also increased. It has become more and more difficult to improve spurious performance by increasing isolation, and the cost has also increased. Bigger.

Summary of the invention

The embodiment of the present application provides a multi-channel multi-carrier transceiver to improve the reliability of multi-channel multi-carrier communication.

In a first aspect, a multi-channel multi-carrier transceiver is provided, including: a first channel, used to transmit a first carrier; a second channel, used to transmit a second carrier; a first all-digital phase-locked loop ADPLL, coupled to The first channel is used to provide the local oscillator signal for the first channel; the second ADPLL is coupled to the second channel and is used to provide the local oscillator signal for the second channel; and the configuration circuit is respectively coupled The first ADPLL and the second ADPLL are used to configure the first ADPLL or the second ADPLL according to the combination information of the first carrier and the second carrier. In this aspect, by configuring the phase-locked loop according to the combined information of multiple carriers, the phase-locked loop can eliminate the spurs caused by the frequency pulling of multiple carriers and improve the reliability of multi-channel multi-carrier communication.

In one implementation, the first ADPLL or the second ADPLL further includes a signal generation circuit, the signal generation circuit is coupled to the configuration circuit, and the signal generation circuit is configured to configure the stray signal according to the configuration circuit. Frequency to eliminate the spurs. In this implementation, the signal generation circuit can accurately eliminate the spurs caused by the frequency pulling of multiple carriers according to the stray frequency configured by the configuration circuit.

In another implementation, the configuration circuit is specifically configured to configure the frequency of the stray as the absolute value of the difference between the first frequency and the second frequency, where the first frequency is the frequency of the first carrier. , The second frequency is the frequency of the second carrier. In this implementation, the frequency of the configuration stray is the absolute value of the difference between the frequency of the first carrier and the frequency of the second carrier, and the frequency of the stray can be accurately determined.

In another implementation, the configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B), where Flo_A is the frequency of the first carrier, and Div_A is connected to the first ADPLL The division rate of the local oscillator, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the Mentioned second frequency. In this implementation, the frequency of the spurious is related to the frequency of each carrier and the division rate of the local oscillator.

In another implementation, the signal generation circuit includes a single-tone complex signal generation circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generation circuit, and a spurious cancellation circuit that are connected to each other; the single-tone complex signal generation circuit The circuit is coupled to the configuration circuit; the single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious The frequency of the dispersion is the same; the adaptive algorithm circuit is used for adaptively converging the spurs according to the single-tone complex signal to obtain a converged signal; the loop phase compensation circuit is used for the single-tone complex signal Phase compensation is performed on the audio complex signal and the converged signal to obtain a compensated signal; the cancellation signal generating circuit is used for generating the spurious cancellation based on the converged signal and the compensated signal Signal; and the stray cancellation circuit is configured to use the stray cancellation signal to cancel the spurs in the signal. In this implementation, the frequency of the stray cancellation signal generated by the signal generating circuit is the same as the frequency of the spur, and the amplitude and phase of the stray cancellation signal are converged through an adaptive algorithm, so that the spur amplitude in the DCO signal is reduced to meet the system It is required that the all-digital method can eliminate the spurs caused by frequency pulling between multiple DCOs.

In yet another implementation, the configuration circuit is used to configure a plurality of spurious frequencies, and the configuration circuit is connected to a plurality of the signal generation circuits in parallel; the plurality of signal generation circuits connected in parallel is used to configure each signal The single-tone complex signal generated by the single-tone complex signal generation circuit in each signal generation circuit can eliminate multiple spurs at the same time. In this implementation, the configuration circuit can configure multiple signal generating circuits with multiple spurious frequency rates at the same time, so that multiple signal generating circuits can eliminate multiple spurs and improve configuration efficiency.

In another implementation, the configuration circuit is used to configure a plurality of spurious frequencies, and the configuration circuit is connected in series with a plurality of the signal generating circuits; the plurality of serially connected signal generating circuits are used to configure according to The single-tone complex signal generated by the single-tone complex signal generation circuit in each signal generation circuit sequentially eliminates the multiple spurs. In this implementation, the configuration circuit can sequentially configure the multiple signal generating circuits with multiple spurious frequencies, so that the multiple signal generating circuits can eliminate multiple spurs.

In a second aspect, a multi-channel multi-carrier transceiver is provided, including: a first channel, used to transmit a first carrier; a second channel, used to transmit a second carrier; a first all-digital phase-locked loop ADPLL, coupled to The first channel is used to provide a local oscillator signal for the first channel; a second ADPLL, coupled to the second channel, is used to provide a local oscillator signal for the second channel; the first ADPLL and The second ADPLL is placed side by side in parallel on the layout. In this aspect, multiple phase-locked loops can be placed side by side in parallel on the layout, not limited to the loop bandwidth of the phase-locked loop, and can save the area overhead caused by isolation limitations or power distribution, and the area introduced by itself The price is small.

In one implementation, the inductance of the first ADPLL is adjacent to the inductance of the second ADPLL.

In yet another implementation, the transceiver further includes a configuration circuit, which is respectively coupled to the first ADPLL and the second ADPLL, and is configured to perform an adjustment based on the combination information of the first carrier and the second carrier. The first ADPLL or the second ADPLL is configured.

In yet another implementation, the first ADPLL or the second ADPLL further includes a signal generation circuit, the signal generation circuit is coupled to the configuration circuit, and the signal generation circuit is configured to perform according to the configuration of the configuration circuit The frequency of the spur, eliminate the spur.

In another implementation, the configuration circuit is specifically configured to configure the frequency of the stray as the absolute value of the difference between the first frequency and the second frequency, where the first frequency is the frequency of the first carrier. , The second frequency is the frequency of the second carrier.

In another implementation, the configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B), where Flo_A is the frequency of the first carrier, and Div_A is connected to the first ADPLL The division rate of the local oscillator, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the Mentioned second frequency.

In another implementation, the signal generation circuit includes a single-tone complex signal generation circuit, an adaptive algorithm circuit, a loop phase compensation circuit, a cancellation signal generation circuit, and a spurious cancellation circuit that are connected to each other; the single-tone complex signal generation circuit The circuit is coupled to the configuration circuit; the single-tone complex signal generating circuit is used to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious The frequency of the dispersion is the same; the adaptive algorithm circuit is used for adaptively converging the spurs according to the single-tone complex signal to obtain a converged signal; the loop phase compensation circuit is used for the single-tone complex signal Phase compensation is performed on the audio complex signal and the converged signal to obtain a compensated signal; the cancellation signal generating circuit is used for generating the spurious cancellation based on the converged signal and the compensated signal Signal; The stray cancellation circuit is used to use the stray cancellation signal to cancel the spurs in the signal.

Description of the drawings

Figure 1 is a schematic diagram of the structure of an all-digital phase-locked loop in a radio frequency transceiver;

Figure 2 is a schematic diagram of bandwidth suppression to spurs;

Figure 3 is a schematic diagram of the isolation scheme between the interference source and the interfered source;

Fig. 4 is a schematic structural diagram of an exemplary multi-channel multi-carrier transceiver;

5 is a schematic structural diagram of a multi-channel multi-carrier transceiver provided by an embodiment of the application;

FIG. 6a is a schematic diagram of the internal structure of a phase locked loop provided by an embodiment of the application;

6b is a schematic diagram of the internal structure of another phase-locked loop provided by an embodiment of the application;

FIG. 7a is a detailed structural diagram of the signal generating circuit 25a in the embodiment shown in FIG. 6a;

FIG. 7b is a detailed structural diagram of the signal generating circuit 25b in the embodiment shown in FIG. 6b;

FIG. 8 is a schematic structural diagram of parallel spurious cancellation provided by an embodiment of the application;

Figure 9 is a schematic diagram of the layout of two phase-locked loops.

detailed description

The technical solution of the present application will be described below in conjunction with the above-mentioned drawings.

Please refer to FIG. 4, which is a schematic structural diagram of an exemplary multi-channel multi-carrier transceiver. FIG 4 is a fifth-generation (5 ^th generation, 5G) receives a mobile communication system applications carrier aggregation (carrier aggregation, CA) and the combination Band28 Band79 is a schematic, two carrier frequency carriers are: Fsig1 = 800MHz, Fsig2 = 4800.2MHz ; The local oscillator frequencies of the two receiving channels are: Flo1=800MHz, Flo2=4800.2MHz; the division ratios of LO1 and LO2 are respectively selected as 12 and 2, then the DCO frequencies of the two synthesizer outputs are Fdco1=9600MHz, Fdco2=9600.4 MHz, two DCOs pulling each other will produce a spur of Fspur=0.4MHz, which is called a frequency pulling spur (pulling). If the isolation between the two DCOs is insufficient, the generated spur will seriously deteriorate the integrated noise of the phase-locked loop.

Related scenarios also include inter-band carrier aggregation (inter-band CA) and intra-band non-contiguous carrier aggregation (intra-band non-contiguous carrier aggregation, intra-band NC-CA) of the transmitting system or receiving system , Dual-carrier dual-standby (dual carrier dual standby, DSDS) and other situations where multiple DCOs work at the same time. Since there are many CA combinations in 5G applications, there are many scenarios where DCO frequencies are similar.

In view of this, this application provides a multi-channel multi-carrier transceiver. By configuring the phase-locked loop according to the combined information of multiple carriers, the phase-locked loop can eliminate the spurs caused by the frequency pulling of multiple carriers. Improved the reliability of multi-channel and multi-carrier communication; multiple phase-locked loops can be placed side by side on the layout, not limited to the loop bandwidth of the phase-locked loop, and can save area overhead, and the area cost introduced by itself is small .

Please refer to FIG. 5. FIG. 5 is a schematic structural diagram of a multi-channel multi-carrier transceiver according to an embodiment of the application. The transceiver includes a first channel (not shown in the figure) for transmitting the first carrier; Channel (not shown in the figure), used to transmit the second carrier; the first ADPLL11, coupled to the first channel, used to provide the local oscillator signal for the first channel; the second ADPLL12, coupled to the first channel Two channels, used to provide local oscillator signals for the second channel; and a configuration circuit 13, coupled to the first ADPLL 11 and the second ADPLL 12, respectively, and used to perform according to the first carrier and the second carrier To configure the first ADPLL11 or the second ADPLL12.

Specifically, the configuration circuit is used to configure the spurious frequency. This spur is caused by the frequency pulling of the two carriers, specifically the frequency pulling of the DCO of the two phase-locked loops.

Specifically, the configuration circuit is used to configure the frequency of the stray as the absolute value of the difference between the first frequency and the second frequency, wherein the first frequency is the frequency of the first carrier, and the second The frequency is the frequency of the second carrier.

As shown in Table 1, assuming that the phase-locked loop 1 works in frequency band A and the phase-locked loop 2 works in frequency band B, the frequency of the traction spur is configured as Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B). Wherein, Flo_A is the frequency of the first carrier, that is, the frequency of the phase-locked loop 1 working, Div_A is the division rate of the local oscillator connected to the first ADPLL, and Flo_A*Div_A is the first frequency , Which is the DCO frequency of PLL 1. Flo_B is the frequency of the second carrier, that is, the frequency of the phase-locked loop 2 working, Div_B is the division rate of the local oscillator connected to the second ADPLL, and Flo_B*Div_B is the second frequency, namely DCO frequency of PLL 2.

Assuming that the phase-locked loop 1 works in frequency band C, and the phase-locked loop 2 works in frequency band D, the frequency of the traction spurious is configured as Fspur_C_D=Abs(Flo_C*Div_C-Flo_D*Div_D). Wherein, Flo_C is the frequency of the first carrier, Div_C is the division rate of the local oscillator connected to the first ADPLL, and Flo_C*Div_C is the first frequency, that is, the DCO frequency of the phase-locked loop 1. Flo_D is the frequency of the second carrier, Div_D is the division rate of the local oscillator connected to the second ADPLL, and Flo_D*Div_D is the second frequency, that is, the DCO frequency of the phase locked loop 2.

Of course, the phase-locked loop 1 working in the frequency band A or the frequency band C here, and the phase-locked loop 2 working in the frequency band B or the frequency band D is only an example, which is not limited in this application.

The parameters in Table 1 can be pre-configured. When the frequency bands in which the first ADPLL and the second ADPLL work are determined, the spurious frequency to be configured can be determined.

Table 1

As shown in Table 2, examples of the specific frequency band, frequency point, LO division rate, and DCO frequency of the phase-locked loop are given. The values of the above parameters can be substituted into the above-mentioned traction spurious frequency configuration formula to calculate the specific The frequency value of traction spurs. For example, assuming that the phase-locked loop 1 works in the frequency band B3 and the phase-locked loop 2 works in the frequency band B8, then Fspur=Abs(1875*4-937.6*8)=Abs(7500-7500.8)=0.8.

Table 2

As shown in Table 3, assuming that the LO division rate is fixed, it is also possible to configure only the frequency points in advance. The traction spurious frequency can also be obtained according to the frequency band where the phase-locked loop is located, the fixed LO division rate and the pre-configured frequency point.

table 3

As shown in Table 4, an example of the specific frequency band and frequency point of the phase-locked loop is given. Assuming that the LO division rate corresponding to PLL 1 is 4, and the LO division rate corresponding to PLL 2 is 8, then Substituting the values of the aforementioned parameters into the formula of the aforementioned traction spurious frequency configuration, the specific frequency value of the traction spurious is calculated. For example, assuming that the phase-locked loop 1 works in the frequency band B3 and the phase-locked loop 2 works in the frequency band B8, then Fspur=Abs(1875*4-937.6*8)=Abs(7500-7500.8)=0.8.

Table 4

The configuration method (configured phase-locked loop, working frequency band, working frequency point) needs to be listed in the user manual, as shown in Table 1 to Table 4. Among them, Form 1 is only for designers, and there is no need to write into the user manual, just provide the information in Form 3.

Further, as shown in Fig. 6a and Fig. 6b of the internal structure diagram of the phase-locked loop, an ADPLL (including the first ADPLL11 and the second ADPLL12) includes a time-to-digital converter 21, a digital filter 22, a digital The oscillator 23 and the feedback frequency divider 24 are controlled. In this embodiment, the ADPLL may also include a signal generating circuit. In FIG. 6a, the signal generating circuit 25 is connected between TDC21 and DCO23; in FIG. 6b, the signal generating circuit 25 is connected between TDC21 and digital filter 22. And the signal generating circuit is also coupled to the configuration circuit. The signal generating circuit is used to eliminate the spurs according to the frequency of the spurs configured by the configuration circuit.

Among them, the output TDC_OUT of TDC21 includes a spurious signal with amplitude A _spur , frequency f _spur , and phase φ _spur . The signal generating circuit 25 is used to generate a single-tone complex signal with the same frequency as the spurious frequency, and generate a spurious cancellation signal according to the amplitude and phase of the spurious signal in the output of the TDC, and use an adaptive algorithm to cancel the spurious The amplitude of the signal is converged, and the phase of the stray cancellation signal is compensated, so that the stray amplitude in the signal output by the TDC is reduced to meet the system requirements, thereby ultimately reducing the stray energy of the phase-locked loop output signal.

Specifically, please refer to FIG. 7a, which is a detailed structural diagram of the signal generating circuit 25 shown in FIG. 6a. As shown in FIG. 7a, the signal generation circuit 25 may include a single-tone complex signal generation circuit 251, an adaptive algorithm circuit 252, a loop phase compensation circuit 253, a cancellation signal generation circuit 254, and a stray cancellation circuit 255 that are coupled to each other. The signal generating circuit 25 is coupled to the configuration circuit 13, and the configuration circuit 13 is connected to the single tone complex signal generating circuit 251. The TDC21 output includes a signal and a pulling spur, where the pulling spur is a time-varying signal. The signal output by TDC21 and the pulling spur are passed through the digital filter 22, and the digital filter 22 outputs the filtered signal (called "signal_filtering") and the filtered pulling spur (called "pulling spur_filtering") , Where the pulling spurious_filtering is also a time-varying signal. The signal generating circuit 25 uses the generated traction spur cancellation signal to cancel the traction spur_filtering outputted by the digital filter 22 to obtain a filtered signal.

Fig. 7b is a detailed structural diagram of the signal generating circuit 25 shown in Fig. 6b. The internal structure of the signal generating circuit 25 is the same as that of the signal generating circuit 25 shown in Fig. 7a, except that the signal generating circuit 25 is connected between TDC21 and digital filter 22.

Different from the open-loop calibration method of fractional spurs, traction spur elimination is a closed-loop calibration of real-time monitoring, calculation and elimination. Therefore, traction spurs are a time-varying signal. In this embodiment, the single-tone complex signal generating circuit 251 generates a frequency f _spur complex tone signal ^e j2πFspur ^{* t,} the same frequency spurious tones complex signal frequency f _spur.

ADPLL cannot directly obtain the frequency information of the traction spurious, and the software responsible for configuring the working frequency of the ADPLL can know the frequency information of the traction spurious according to the working scenario, that is, the CA combination information. Therefore, the frequency of the spur can be determined by the above configuration circuit 13 Configured. When the frequencies of the interference source DCO (Aggressor) and the interfered source DCO (victim) are known, the configuration circuit 13 can obtain the spurious frequency. Specifically, the configuration circuit 13 configures the frequency of the stray as the absolute value of the difference between the first frequency and the second frequency, the first frequency is the frequency of the signal output by the DCO of the interference source, and the second frequency is the interfered The frequency of the signal output by the source's DCO. For example, as shown in Figure 4, subsystem 1 is locked at f _dco1 , and after opening subsystem 2 that will work at f _dco2 , the spurious frequency to be eliminated can be configured as f _spur =|f _dco1- f _dco2 |.

Frequency pulling between multiple DCOs will generate spurs. The output of TDC21 includes this spur. The adaptive algorithm circuit 252 detects the amplitude A _cl and phase φ _cl of the traction spurious corresponding to the frequency in the output of the TDC251 according to the frequency of the single-tone complex signal, and performs adaptive convergence to obtain the converged signal

Since both the adaptive algorithm circuit 252 and the cancellation signal generation circuit 254 need to use the above-mentioned single-tone complex signal, the adaptive algorithm circuit 252 and the cancellation signal generation circuit 254 have a phase shift due to the phase-locked loop to the traction spurs, so the loop The phase compensation circuit 253 performs phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal

The cancellation signal generation circuit 254 combines the converged signal output by the adaptive algorithm circuit 252 and the compensated signal output by the loop phase compensation circuit 253 to generate a spurious cancellation signal A _cl *sin(2πf _spur *t+φ _comp + φ _cl ).

Since the frequency of the spurious cancellation signal is the same as the frequency of the spurious, the amplitude and phase of the spurious cancellation signal have been converged by the adaptive algorithm, and the spurious amplitude in the signal output by the digital filter is reduced to meet the system requirements. Therefore, the signal The spurs are basically eliminated.

The interference source DCO (aggressor) directly interferes with the interfered DCO (victim), and there are frequency pulling spurs on the interfered DCO, and the frequency is fspur=|fdco_victim-fdco_aggressor|. Since the output signal of the TDC can directly reflect the spurs modulated on the DCO, the TDC output includes signal and pulling spurs. Inject a traction spurious cancellation signal with a frequency of fspur, an amplitude of Acal, and a phase of φcal into the input or output of the digital filter, where the amplitude Acal and phase φcal are detected by the TDC output and calculated by an adaptive algorithm, where Acal and φcal is a time-varying signal during the convergence process of the adaptive algorithm. When the adaptive algorithm converges, ideally the traction spurious component of the frequency fspur in the TDC output signal disappears, so the output of the spur cancellation circuit only leaves the signal and the traction spurious cancellation signal. In actual implementation, due to the limited accuracy of the cancellation signal, the traction spurious component will not disappear completely, but it can still be reduced to the acceptable range of the system.

In the above-mentioned embodiment, further, in an implementation, a plurality of signal generating circuits are connected between the TDC and the digital filter as an example (the solution of the TDC and DCO connecting the signal generating circuit can also adopt this implementation), If the output of the TDC includes spurs of multiple frequencies, the parallel spur elimination structure is shown in Figure 8. The configuration circuit can be connected in parallel with multiple signal generating circuits, and the configuration circuit can be used to configure multiple spurs. Frequency of. The multiple signal generating circuits connected in parallel are used to eliminate multiple spurs at the same time according to the single tone complex signal generated by the single tone complex signal generating circuit in each signal generating circuit. Specifically, the output of TDC is a signal

Then multiple signal generating circuits can be connected in parallel in the TDC and the digital filter: spurious 1 signal generating circuit, spurious 2 signal generating circuit, ... spurious k signal generating circuit. Among them, the spurious 1 signal generating circuit generates a spurious cancellation signal

To cancel spur_1; similarly, the spurious 2 signal generating circuit generates a spurious cancellation signal

To cancel spur_2, the spurious k signal generating circuit generates a spurious cancellation signal

To offset spur_k. Among them, these multiple signal generating circuits can work simultaneously. Thus, these multiple parallel signal generating circuits can finally eliminate all spurs in the output of the TDC. Specifically, the parallel operation of the signal generating circuits means that the aforementioned circuits included in each signal generating circuit are connected in parallel as a whole.

In another implementation, if the output of the TDC includes spurs of multiple frequencies, the configuration circuit is used to configure the frequencies of multiple strays, and the configuration circuit is serially connected to a plurality of the signal generating circuits; The two serially connected signal generating circuits are used for sequentially eliminating the multiple spurs according to the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit. Specifically, the adaptive algorithm circuits in the multiple signal generating circuits are connected in series to extract the spurious amplitude and phase of each frequency, and the other circuits of the signal generating circuit are connected in parallel to the corresponding adaptive algorithm as a whole. Circuit.

According to a multi-channel multi-carrier transceiver provided by an embodiment of the present application, the phase-locked loop is configured according to the combined information of multiple carriers, so that the phase-locked loop can eliminate the spurious caused by the frequency pulling of multiple carriers and improve Improve the reliability of multi-channel multi-carrier communication.

An embodiment of the application also provides a multi-channel multi-carrier transceiver, including: a first channel, used to transmit a first carrier; a second channel, used to transmit a second carrier; a first ADPLL, coupled to the first channel , Used to provide the local oscillator signal for the first channel; the second ADPLL, coupled to the second channel, used to provide the local oscillator signal for the second channel; the first ADPLL and the second ADPLL in the layout Place the top side by side in parallel. Optionally, the inductance of the first ADPLL is adjacent to the inductance of the second ADPLL.

The layout schematic diagram of two phase-locked loops shown in FIG. 9 illustrates the layout of N phase-locked loops, and each phase-locked loop is placed side by side on the layout in parallel. And the inductance of each phase locked loop is adjacent.

Multiple phase-locked loops can be placed side by side in parallel on the layout, are not limited to the loop bandwidth of the phase-locked loop, and can save area overhead, and the area cost introduced by itself is small.

Further, the transceiver further includes a configuration circuit, which is respectively coupled to the first ADPLL and the second ADPLL, and is configured to perform the calculation on the first carrier and the second carrier according to the combination information of the first carrier and the second carrier. An ADPLL or the second ADPLL is configured. For the configuration of the spurious frequency, refer to the above-mentioned embodiment.

Further, the first ADPLL or the second ADPLL further includes a signal generation circuit, the signal generation circuit is coupled to the configuration circuit, and the signal generation circuit is configured to generate spurious signals according to the configuration of the configuration circuit. Frequency to eliminate the spurs. Regarding how the signal generating circuit performs spurious elimination, reference may be made to the foregoing embodiment.

After applying the above-mentioned signal generation circuit, the on-chip DCOs can be placed side by side and the spacing can be less than 1mm, or other circuits are prioritized during layout and routing on the top of the chip, without being limited by the stray traction between the DCOs, making the top of the chip The layout is more flexible.

This application provides a multi-channel multi-carrier transceiver. Multiple phase-locked loops can be placed side by side in parallel on the layout, which is not limited to the loop bandwidth of the phase-locked loop, and can save area overhead, and the area cost introduced by itself Very small.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the division of the unit is only a logical function division. In actual implementation, there can be other divisions. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not. carried out. The displayed or discussed mutual coupling, or direct coupling, or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be sent from one website, computer, server, or data center to another via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) A website, computer, server or data center for transmission. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media. The usable medium can be read-only memory (ROM), random access memory (RAM), or magnetic medium, such as floppy disk, hard disk, magnetic tape, magnetic disk, or optical medium, for example, Digital versatile disc (DVD) or semiconductor media, for example, solid state disk (SSD), etc.

Claims

A multi-channel multi-carrier transceiver, characterized in that it comprises:

The first channel is used to transmit the first carrier;

The second channel is used to transmit the second carrier;

The first all-digital phase-locked loop ADPLL, coupled to the first channel, is used to provide a local oscillator signal for the first channel;

A second ADPLL, coupled to the second channel, for providing a local oscillator signal for the second channel;

A configuration circuit, respectively coupled to the first ADPLL and the second ADPLL, and configured to configure the first ADPLL or the second ADPLL according to the combination information of the first carrier and the second carrier .
The multi-channel multi-carrier transceiver according to claim 1, wherein the first ADPLL or the second ADPLL further comprises a signal generation circuit, the signal generation circuit is coupled to the configuration circuit, and the signal The generating circuit is used to eliminate the spurs according to the frequency of the spurs configured by the configuration circuit.
The multi-channel multi-carrier transceiver according to claim 2, wherein the configuration circuit is specifically configured to configure the frequency of the spurious as the absolute value of the difference between the first frequency and the second frequency, wherein The first frequency is the frequency of the first carrier, and the second frequency is the frequency of the second carrier.
The multi-channel multi-carrier transceiver according to claim 3, wherein the configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B), wherein Flo_A is the frequency of the first carrier Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, and Div_B is the frequency of the second carrier The division rate of the local oscillator, Flo_B*Div_B is the second frequency.
The multi-channel multi-carrier transceiver according to any one of claims 2 to 4, wherein the signal generating circuit comprises a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, A cancellation signal generating circuit and a stray cancellation circuit; the single-tone complex signal generating circuit is coupled to the configuration circuit;

The single-tone complex signal generating circuit is configured to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious;

The adaptive algorithm circuit is configured to perform adaptive convergence on the spurs according to the single-tone complex signal to obtain a converged signal;

The loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal;

The cancellation signal generating circuit is used to generate the spurious cancellation signal according to the converged signal and the compensated signal;

The stray cancellation circuit is used for using the stray cancellation signal to cancel spurs in the signal.
The multi-channel multi-carrier transceiver according to claim 5, wherein the configuration circuit is used to configure a plurality of spurious frequencies, and the configuration circuit is connected to a plurality of the signal generating circuits in parallel;

The multiple signal generating circuits connected in parallel are used to simultaneously eliminate multiple spurs according to the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit.
The multi-channel multi-carrier transceiver according to any one of claims 2 to 5, wherein the configuration circuit is used to configure a plurality of spurious frequencies, and the configuration circuit is serially connected with a plurality of the signal generating circuits connection;

The multiple serially connected signal generating circuits are used for sequentially eliminating the multiple spurs according to the single-tone complex signal generated by the single-tone complex signal generating circuit in each signal generating circuit.
A multi-channel multi-carrier transceiver, characterized in that it comprises:

The first channel is used to transmit the first carrier;

The second channel is used to transmit the second carrier;

The first all-digital phase-locked loop ADPLL, coupled to the first channel, is used to provide a local oscillator signal for the first channel;

A second ADPLL, coupled to the second channel, for providing a local oscillator signal for the second channel;

The first ADPLL and the second ADPLL are placed side by side in parallel on the layout.
The multi-channel multi-carrier transceiver according to claim 8, wherein the inductance of the first ADPLL is adjacent to the inductance of the second ADPLL.
The multi-channel multi-carrier transceiver according to claim 8 or 9, wherein the transceiver further comprises a configuration circuit, which is respectively coupled to the first ADPLL and the second ADPLL, and is configured to perform according to the The combination information of the first carrier and the second carrier configures the first ADPLL or the second ADPLL.
The multi-channel multi-carrier transceiver of claim 10, wherein the first ADPLL or the second ADPLL further comprises a signal generating circuit, the signal generating circuit is coupled to the configuration circuit, and The signal generation circuit is used to eliminate the spurs according to the frequency of the configuration of the configuration circuit.
The multi-channel multi-carrier transceiver according to claim 11, wherein the configuration circuit is specifically configured to configure the frequency of the spurious as the absolute value of the difference between the first frequency and the second frequency, wherein The first frequency is the frequency of the first carrier, and the second frequency is the frequency of the second carrier.
The multi-channel multi-carrier transceiver according to claim 12, wherein the configured spurious frequency Fspur_A_B=Abs(Flo_A*Div_A-Flo_B*Div_B), wherein Flo_A is the frequency of the first carrier Div_A is the division rate of the local oscillator connected to the first ADPLL, Flo_A*Div_A is the first frequency, Flo_B is the frequency of the second carrier, and Div_B is the frequency of the second carrier The division rate of the local oscillator, Flo_B*Div_B is the second frequency.
The multi-channel multi-carrier transceiver according to any one of claims 11 to 13, wherein the signal generating circuit comprises a single-tone complex signal generating circuit, an adaptive algorithm circuit, a loop phase compensation circuit, A cancellation signal generating circuit and a stray cancellation circuit; the single-tone complex signal generating circuit is coupled to the configuration circuit;

The single-tone complex signal generating circuit is configured to generate a single-tone complex signal according to the frequency of the spurious configured by the configuration circuit, and the frequency of the single-tone complex signal is the same as the frequency of the spurious;

The adaptive algorithm circuit is configured to perform adaptive convergence on the spurs according to the single-tone complex signal to obtain a converged signal;

The loop phase compensation circuit is used to perform phase compensation on the single-tone complex signal and the converged signal to obtain a compensated signal;

The cancellation signal generating circuit is used to generate the spurious cancellation signal according to the converged signal and the compensated signal;

The stray cancellation circuit is used for using the stray cancellation signal to cancel spurs in the signal.