WO2020189300A1 - Rectifier and non-contact power-feeding system - Google Patents

Abstract

This rectifier comprises a power feeder for supplying alternating current, a first switching element in which a switch is made between a conduction state and a non-conduction state with respect to the alternating current, a detection circuit which is connected in series to the first switching element and to which an AC voltage that corresponds to the alternating current is applied, and a control circuit for switching between the conduction state and the non-conduction state of the first switching element on the basis of the AC voltage. Chattering occurring in a switching element is thereby suppressed while an increase in power consumption is limited.

Description

Rectifier and non-contact power supply system

One aspect of the present disclosure relates to a rectifier and a non-contact power supply system. This application claims the priority of Japanese Patent Application No. 2019-052085 filed in Japan on March 20, 2019, the contents of which are incorporated herein by reference.

In the full-wave rectifier circuit described in Patent Document 1, a sub synchronous rectifier transistor, which is a sub low-side switch, is connected in parallel to a main synchronous rectifier transistor which is a main low-side switch. Then, the sub synchronous rectification transistor is controlled so as to be switched on and off at a timing different from that of the main synchronous rectification transistor. According to Patent Document 1, this makes it possible to prevent chattering that occurs when the main synchronous rectification transistor is turned off.

JP-A-2017-169268

According to the full-wave rectifier circuit described in Patent Document 1, the number of transistors increases because a sub synchronous rectifier transistor is required. Therefore, the power consumption for turning on and off the increased number of transistors also increases. One aspect of the present disclosure is to suppress chattering generated in a switching element while suppressing an increase in power consumption.

The rectifying device according to one aspect of the present disclosure is connected in series with a feeding unit that supplies an alternating current, a first switching element that switches between a conductive state and a non-conducting state with respect to the alternating current, and the first switching element. A detection circuit to which an AC voltage corresponding to the AC current is applied, and a control circuit for switching between the conductive state and the non-conducting state of the first switching element based on the AC voltage.

According to one aspect of the present disclosure, chattering generated in the switching element can be suppressed while suppressing an increase in power consumption.

It is a figure which shows an example of the structure of the non-contact power supply system which concerns on Embodiment 1. FIG. An example of the time change of the drive state of the voltage detection element, the first switching element, and the second switching element in the rectifier shown in FIG. 1 is shown, and in particular, the time change of the AC voltage applied to the voltage detection element. It is a figure which shows the state. An example of the time change of the drive state of the voltage detection element, the first switching element, and the second switching element in the rectifier shown in FIG. 1 is shown, and in particular, the alternating current flowing through the first switching element and the gate drive are shown. It is a figure which shows the state of the time change of a voltage. An example of the time change of the drive state of the voltage detection element, the first switching element, and the second switching element in the rectifier shown in FIG. 1 is shown, and in particular, the alternating current flowing through the second switching element and the gate drive are shown. It is a figure which shows the state of the time change of a voltage. FIG. 5 is a diagram showing an example of an alternating current flow in a state where the first switching element is on and the second switching element is off in the rectifier device shown in FIG. 1. FIG. 5 is a diagram showing an example of an alternating current flow in a state where the first switching element is off and the second switching element is on in the rectifier device shown in FIG. 1. It is a figure which shows the example of the operation of the control circuit in the rectifier apparatus shown in FIG. It is a figure which shows an example of the structure of the rectifying apparatus which concerns on Embodiment 2. It is a figure which shows the example of the flow of the alternating current in the state which the 1st switching element and the 4th switching element are on in the rectifying apparatus which concerns on Embodiment 3. It is a figure which shows the example of the flow of the alternating current in the state which the 2nd switching element and the 3rd switching element are on in the rectifying apparatus which concerns on Embodiment 3.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or equivalent elements are designated by the same reference numerals, and duplicate description will be omitted.

[Embodiment 1]
(Configuration of non-contact power supply system 1)
FIG. 1 is a diagram showing an example of the configuration of the non-contact power supply system 1 according to the first embodiment. As shown in FIG. 1, the non-contact power supply system 1 includes a power transmission device 2 and a rectifier device 5. The non-contact power supply system 1 is an example of a system that wirelessly supplies electric power from the power transmission device 2 to the rectifier device 5. As a method of supplying electric power from the power transmission device 2 to the rectifier device 5, various methods such as an electromagnetic induction method and a magnetic resonance method can be adopted. The rectifying device 5 may be used for mobile devices such as smartphones and drones, and may be used for various electronic devices other than mobile devices. The circuit configurations of the power transmission device 2 and the rectifier device 5 shown in FIG. 1 are examples, and the circuit configurations other than those shown in FIG. 1 may be used.

The power transmission device 2 wirelessly supplies electric power to the rectifier device 5, for example. The power transmission device 2 includes, for example, a drive power supply 3, a power transmission coil L2, and a resonance capacitor C4. The drive power supply 3 outputs an AC voltage. The drive power supply 3 is realized by, for example, an inverter circuit. The frequency of the drive power supply 3 is, for example, 150 kHz to 200 kHz in the case of the electromagnetic induction method and the ISM band band (for example, 6.78 MHz) in the case of the magnetic resonance method. The resonance capacitor C4 is a capacitor for resonating with the power transmission coil L2. The power transmission coil L2 transmits electric power to the rectifier 5 based on the AC voltage supplied from the drive power source 3.

In the example shown in FIG. 1, one terminal of the resonance capacitor C4 is connected to the drive power supply 3, and the other terminal is connected to the power transmission coil L2. The terminal of the power transmission coil L2 opposite to the terminal connected to the resonance capacitor C4 is connected to the drive power supply 3. For example, in the power transmission device 2, a closed circuit is formed by connecting a drive power supply 3, a resonance capacitor C4, and a power transmission coil L2 in series in order. As a result, when an AC voltage is supplied from the drive power supply 3 to the resonance capacitor C4 and the power transmission coil L2, the resonance capacitor C4 and the power transmission coil L2 resonate with each other. Then, the power transmission coil L2 supplies electric power to the rectifier 5 arranged close to the power transmission coil L2.

The rectifier 5 includes a half-wave rectifier circuit. The rectifier 5 includes, for example, a power receiving coil (feeding unit) L1, a detection circuit 7, a first switching element M1, a second switching element M2, a storage capacitor (third storage unit) C3, and a control circuit 10. Has. The detection circuit 7 includes a first resonance capacitor (first storage unit) C1, a second resonance capacitor (second storage unit) C2, and a voltage detection element R1. The ground GND1 to GND4, which will be described later, are reference potential points.

The power receiving coil L1 generates an alternating current by magnetically coupling with the power transmission coil L2 when the power transmission coil L2 of the power transmission device 2 is brought close to the power receiving coil L1. For example, the power receiving coil L1 is an element that wirelessly receives power from the power transmitting coil L2. In other words, the power receiving coil L1 is an element that supplies an alternating current to the circuit in the rectifier device 5. When the rectifying device 5 is not configured as a wireless power receiving device, it may be provided with an AC power supply that outputs an AC voltage or an AC current instead of the power receiving coil L1. In this case, the power transmission device 2 is unnecessary.

The detection circuit 7 is a circuit for detecting a voltage for turning off the first switching element M1 as described later, based on the alternating current generated in the power receiving coil L1. The detection circuit 7 is interposed between the power receiving coil L1 and the first switching element M1 and is connected in series with each of them.

The first resonance capacitor C1 is a capacitor for resonating with the power receiving coil L1 by being connected in series with the power receiving coil L1. The first resonance capacitor C1 is interposed between the power receiving coil L1 and the first switching element M1 and is connected in series with each of them. That is, one terminal of the first resonant capacitor C1 is connected to the power receiving coil L1, and the other terminal is connected to the connection point P1 between the source terminal M1s of the first switching element M1 and the ground GND1 which will be described later. Has been done.

The second resonance capacitor C2 is connected in parallel with the first resonance capacitor C1 and the capacitance is adjusted between the second resonance capacitor C2 and the first resonance capacitor C1 to adjust the amount of alternating current flowing through the voltage detection element R1. By connecting the voltage detection element R1 in series with the second resonance capacitor C2 and the first switching element M1, an AC voltage corresponding to the AC current flowing through the voltage detection element R1 is applied. In other words, the voltage detection element R1 causes the first switching element M1 to detect a change in the AC voltage value according to a change in the AC current value inflow or outflow.

In this way, in the detection circuit 7, for example, by connecting the first resonance capacitor C1 and the second resonance capacitor C2 in parallel, the alternating current flowing in or out of the first switching element M1 is diverted to cause a voltage detection element. It can be sent to R1. Therefore, a minute AC current that has been split can be passed through the voltage detection element R1, and power consumption can be reduced. The detection circuit 7 may have a configuration in which the second resonance capacitor C2 is omitted and the voltage detection element R1 is provided between the first resonance capacitor C1 and the source terminal M1s of the first switching element M1. Further, the voltage detection element R1 is, for example, a resistor, but is not limited to the resistor, and may be a component capable of detecting or detecting an AC voltage based on an AC current.

The second resonance capacitor C2 and the voltage detection element R1 are connected in series. The series circuit in which the second resonance capacitor C2 and the voltage detection element R1 are connected is connected in parallel with the first resonance capacitor C1. In the voltage detection element R1, one terminal is connected to the connection point P2 between the connection point P1 and one terminal of the first resonance capacitor C1, and the other terminal is one terminal of the second resonance capacitor C2. Is connected to. Of the second resonance capacitor C2, the terminal on the opposite side to the terminal connected to the voltage detection element R1 is connected to the connection point P3 between the power receiving coil L1 and the first resonance capacitor C1. The connection point where the voltage detection element R1 and the second resonance capacitor C2 are connected is referred to as a connection point P4.

The first switching element M1 is, for example, a transistor such as a MOSFET (metal-oxide-semiconductor field-effect transistor). The first switching element M1 has a source terminal M1s, a drain terminal M1d, and a gate terminal M1g. The first switching element M1 is turned on between the source terminal M1s and the drain terminal M1d with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal M1g by the control circuit 10. It switches between conductive state) and off (non-conducting state).

The source terminal M1s is connected to the ground GND1 and is also connected to the first resonance capacitor C1 and the voltage detection element R1 via the connection points P1 and P2. The drain terminal M1d is connected to the source terminal M2s of the second switching element M2, and is also connected to the power receiving coil L1 via the connection point P5 between the drain terminal M1d and the source terminal M2s. The gate terminal M1g is connected to the output terminal of the RS flip-flop circuit 11 via a buffer BUF1 provided in the control circuit 10 described later.

The second switching element M2 is connected in series with each of the first switching element M1 and the power receiving coil L1. The second switching element M2 is, for example, a transistor such as a MOSFET. The second switching element M2 has a source terminal M2s, a drain terminal M2d, and a gate terminal M2g. The second switching element M2 is turned on between the source terminal M2s and the drain terminal M2d with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal M2g by the control circuit 10. It switches between conductive state) and off (non-conducting state).

As described above, the source terminal M2s is connected to the drain terminal M1d of the first switching element M1 via the connection point P5, and is also connected to the power receiving coil L1. The drain terminal M2d is connected to the connection point P6 and branches in two directions at the connection point P6. While branching in two directions at the connection point P6, one path is connected to the storage capacitor C3, and the other path is connected to the negative input terminal of the comparator CMP3 described later. As will be described later, the gate terminal M2g is connected to the output terminal of the RS flip-flop circuit 12 via the buffer BUF2 included in the control circuit 10.

The storage capacitor C3 is, for example, a rechargeable power source for operating an electronic device equipped with a rectifier device 5. The power storage capacitor C3 is connected to the power receiving coil L1 and the first switching element M1 via the second switching element M2. For example, in the storage capacitor C3, as described above, one terminal is connected to the drain terminal M2d of the second switching element M2 and the negative input terminal of the comparator CMP3 via the connection point P6, and the other terminal is connected. The terminal is connected to the ground GND4.

The control circuit 10 switches between on (conducting state) and off (non-conducting state) of the first switching element M1 based on the AC voltage applied to the voltage detection element R1, and turns on (non-conducting state) of the second switching element M2. It switches between conductive state) and off (non-conducting state). The control circuit 10 controls each of the first switching element M1 and the second switching element M2 so that on and off are reversed. The control circuit 10 includes, for example, comparators CMP1 to CMP3, RS flip- flop circuits 11 and 12, a level shift circuit 13, an inverter INV1, and buffers BUF1 and BUF2.

The comparator CMP1 monitors the AC voltage applied to the voltage detection element R1. The comparator CMP11 controls the reset input of the RS flip- flop circuits 11 and 12 based on the comparison result between the AC voltage applied to the voltage detection element R1 and the threshold voltage Vth1 (first threshold voltage). In the comparator CMP1, the negative side input terminal is connected to the connection point P4 between the second resonance capacitor C2 and the voltage detection element R1, and the positive side input terminal is via the voltage source VTH1 that outputs the threshold voltage Vth1. Is connected to the ground GND2. The output terminal of the comparator CMP1 branches in two directions at the connection point P7, one path is connected to the reset input terminal of the RS flip-flop circuit 11, and the other path is the inverter INV1 and the level shift connected in order. It is connected to the reset input terminal of the RS flip-flop circuit 12 via the circuit 13.

The comparator CMP2 controls the set input of the RS flip-flop circuit 11 based on the comparison result between the voltage between the drain terminal M1d and the source terminal M1s of the first switching element M1 and the threshold voltage Vth2. The comparator CMP2 detects the timing at which the first switching element M1 turns on. In the comparator CMP2, the negative side input terminal is connected to the connection point P8 between the connection point P5 and the drain terminal M1d of the first switching element M1, and the positive side input terminal is a voltage that outputs the threshold voltage Vth2. It is connected to the ground GND3 via the source VTH2. The output terminal of the comparator CMP2 is connected to the set input terminal of the RS flip-flop circuit 11.

The comparator CMP3 controls the set input of the RS flip-flop circuit 12 based on the comparison result between the voltage between the drain terminal M2d and the source terminal M2s of the second switching element M2 and the threshold voltage Vth3. In the comparator CMP3, the positive side input terminal is connected to the connection point P5 via the voltage source VTH3 that outputs the threshold voltage Vth3, and the negative side input terminal is connected to the connection point P6. The output terminal of the comparator CMP3 is connected to the set input terminal of the RS flip-flop circuit 12.

The RS flip-flop circuit 11 controls the gate drive voltage of the first switching element M1 based on the outputs of the comparator CMP1 and the comparator CMP2, respectively. In the RS flip-flop circuit 11, the set input terminal is connected to the output terminal of the comparator CMP2, the reset input terminal is connected to the output terminal of the comparator CMP1 via the connection point P7, and the output terminal is the first via the buffer BUF1. It is connected to the gate terminal M1g of the switching element M1.

The RS flip-flop circuit 12 controls the gate drive voltage of the second switching element M2 based on the outputs of the comparator CMP2 and the comparator CMP3, respectively. In the RS flip-flop circuit 12, the set input terminal is connected to the output terminal of the comparator CMP3, the reset input terminal is connected to the output terminal of the comparator CMP1 via the level shift circuit 13 and the inverter INV1, and the output terminal is the buffer BUF2. It is connected to the gate terminal M2g of the second switching element M2 via.

The level shift circuit 13 and the inverter INV1 are connected between the output terminal of the comparator CMP1 and the reset input terminal of the RS flip-flop circuit 12. The level shift circuit 13 matches the ground potentials of the first switching element M1 and the second switching element M2.

The circuit configuration of the control circuit 10 described with reference to FIG. 1 is an example, and the control circuit 10 has the first switching element M1 and the second switching element based on the AC voltage applied to the voltage detection element R1. Any circuit configuration may be used as long as it can be controlled so as to invert the on and off of each of the M2. By using a transistor such as the first switching element M1 and the second switching element M2 as an element for rectifying an alternating current, it is possible to reduce power consumption as compared with the case where a diode is used. In the rectifier 5, for example, the second switching element M2 may be formed of a diode instead of a transistor.

(Alternating current path through the rectifier 5)
2A to 2C are diagrams showing an example of the time change of the drive state of the voltage detection element R1, the first switching element M1, and the second switching element M2 in the rectifier device 5 shown in FIG. .. In particular, FIG. 2A shows a state of time change of the AC voltage applied to the voltage detection element R1, FIG. 2B shows a state of time change of the AC current flowing through the first switching element M1 and the gate drive voltage, and FIG. 2C shows the state of time change. , The state of the time change of the alternating current flowing through the second switching element M2 and the gate drive voltage is shown.

FIG. 3 is a diagram showing an example of an alternating current flow in a rectifier 5 shown in FIG. 1 in a state where the first switching element M1 is on and the second switching element M2 is off. FIG. 4 is a diagram showing an example of an alternating current flow in a rectifier 5 shown in FIG. 1 in a state where the first switching element M1 is off and the second switching element M2 is on. Hereinafter, the path of the alternating current when the first switching element M1 is on and the path of the alternating current when the first switching element M1 is off will be described in order.

<< Path of alternating current I1 when the first switching element M1 is on >>
First, the path of the alternating current I1 flowing through the rectifier 5 when the first switching element M1 is on and the second switching element M2 is off will be described with reference to FIGS. 2A to 2C and FIG. FIG. 3 shows the flow of alternating current during the period from time t0 to t1 and the period from time t2 to t3 in FIGS. 2A to 2C. Since the period from time t2 to t3 is the same as the period from time t0 to t1, the description thereof will be omitted. During the period from time t0 to t1, the control circuit 10 turns on the first switching element M1 and turns off the second switching element M2.

Then, as shown in the period from time t0 to t1 in FIG. 2A and FIG. 3, when the power receiving coil L1 receives power from the power transmission coil L2 (see FIG. 1), an alternating current flows through the voltage detection element R1, that is, the voltage. The AC voltage V_R1 applied to the detection element R1 rises and becomes equal to or higher than the threshold voltage Vth1. Further, since the first switching element M1 is on during the period from time t0 to t1 in FIG. 2B and as shown in FIG. 3, the drain terminal M1d and the source are used in the first switching element M1 with reference to the ground GND1. The drain source voltage M1_Vds, which is the voltage between the terminals M1s, has a low level (negative level), and the source / drain current M1_Isd flows from the source terminal M1s to the drain terminal M1d. Further, since the second switching element M2 is off during the period from time t0 to t1 in FIG. 2C and as shown in FIG. 3, the drain terminal M2d and the drain terminal M2d in the second switching element M2 are based on the connection point P5. The drain source voltage M2_Vds, which is the voltage between the source terminals M2s, has a high level (positive level), and no current (source / drain current M2_Isd) flows from the source terminal M2s to the drain terminal M2d.

As described above, assuming that the alternating current flowing through the power receiving coil L1 is the alternating current I1 during the period from time t0 to t1, the alternating current I1 flows from the source terminal M1s of the first switching element M1 to the drain terminal M1d and reaches the connection point P5. Therefore, it does not flow in the direction of the second switching element M2, but flows from the connection point P5 through the power receiving coil L1, and at the connection point P3, branches in the direction of flowing to the first resonance capacitor C1 and the direction of flow to the second resonance capacitor C2. The shunt current of the alternating current I1 flowing through the second resonance capacitor C2 further flows through the voltage detection element R1 and merges with the shunt current of the alternating current I1 flowing through the first resonance capacitor C1 at the connection point P2. Then, the alternating current I1 flows into the source terminal M1s of the first switching element M1 via the connection point P1.

As described above, since the control circuit 10 turns off the second switching element M2 when the first switching element M1 is turned on, the alternating current I1 does not flow to the storage capacitor C3, and the storage capacitor C3 Will not be charged.

<< Path of AC current I2 when the second switching element M2 is on >>
Next, the path of the alternating current I2 flowing through the rectifier 5 when the first switching element M1 is off and the second switching element M2 is on will be described with reference to FIGS. 2A to 2C and FIG. FIG. 4 shows the flow of alternating current during the period from time t1 to t2 in FIGS. 2A to 2C.

During the period from time t1 to t2, the control circuit 10 turns off the first switching element M1 and turns on the second switching element M2. Then, the power receiving coil L1 receives power from the power transmission coil L2 (see FIG. 1) and the like.

Then, as shown in the period from time t1 to t2 in FIG. 2A and FIG. 4, the polarity of the AC current flowing through the voltage detection element R1 changes, that is, the AC voltage applied to the voltage detection element R1 decreases, and the threshold value The voltage becomes less than Vth1. Further, since the first switching element M1 is off as shown in the period from time t1 to t2 in FIG. 2B and FIG. 4, the drain source voltage M1_Vds is set in the first switching element M1 with reference to the ground GND1. It is a high level (positive level), and no current (source / drain current M1_Isd) flows from the source terminal M1s to the drain terminal M1d. Further, as shown in FIGS. 2C and 4, since the second switching element M2 is on, the drain source voltage M2_Vds is low level (negative level) in the second switching element M2 with reference to the connection point P5. The source / drain current M2_Isd flows from the source terminal M2s to the drain terminal M2d.

As described above, assuming that the alternating current flowing through the power receiving coil L1 is the alternating current I2 during the period from time t1 to t2, the alternating current I2 does not flow from the connection point P1 toward the source terminal M1s of the first switching element M1 and is connected. At the point P2, the current branches into the direction of flow to the first resonance capacitor C1 and the direction of flow to the voltage detection element R1 and the second resonance capacitor C2. Then, the shunt currents flowing through the first resonance capacitor C1 and the voltage detection element R1 and the second resonance capacitor C2 merge at the connection point P3, pass through the power receiving coil L1 and the connection point P5, and then switch to the second. It flows through the source terminal M2s and the drain terminal M2d of the element M2 (as described above, the alternating current I2 flowing between the source terminal M2s and the drain terminal M2d is also referred to as a source drain current M2_Isd). Then, the alternating current I2 output from the drain terminal M2d is supplied to the storage capacitor C3 via the connection point P6.

As described above, the rectifier 5 includes the second switching element M2 connected in series with the first switching element M1. Further, the rectifier 5 includes a power storage capacitor C3 which is connected to the power receiving coil L1 and the first switching element M1 via the second switching element M2 and stores electricity based on the alternating current I2. Then, the control circuit 10 switches the on and off of the second switching element M2 so as to be inverted with the on and off of the first switching element M1. As a result, when the first switching element M1 is turned off and the second switching element M2 is turned on, the storage capacitor C3 can be charged based on the alternating current I2 passing through the second switching element M2.

(Operation of control circuit 10)
FIG. 5 is a diagram showing an example of the operation of the control circuit 10 in the rectifier device 5 shown in FIG. Using FIGS. 2A to 5, the operation of the control circuit 10 when turning on the first switching element M1 from off to on, and the control circuit when turning off the first switching element M1 from on to off. The 10 operations will be described in order.

<< Operation of the control circuit 10 when turning on the first switching element M1 >>
The operation of the control circuit 10 when the first switching element M1 is turned on will be described with reference to FIGS. 2A to 2C, FIGS. 3 and 5. In FIGS. 2A to 2C and 5, the times when the control circuit 10 turns on the first switching element M1 and turns off the second switching element M2 are at time t0 and at time t2. Here, the time t2 will be described as an example.

As shown at time t2 and FIG. 3 in FIG. 2A, the AC voltage V_R1 of the voltage detection element R1 becomes equal to or higher than the threshold voltage Vth1 supplied by the voltage source VTH1. Then, as shown at time t2 in FIGS. 3 and 5, the comparator CMP1 detects that the AC voltage V_R1 of the voltage detection element R1 becomes equal to or higher than the threshold voltage Vth1 and outputs a low-level output signal CP1. As a result, the comparator CMP1 inputs the low-level output signal CP1 to the reset input terminal of the RS flip-flop circuit 11, and level-shifts the high-level output signal CP1 inverted signal in which the output signal CP1 is inverted by the inverter INV1. Input is made to the reset input terminal of the RS flip-flop circuit 12 via the circuit 13. In this way, the comparator CMP1 monitors whether or not the AC voltage of the voltage detecting element R1 connected in series with the first switching element M1 becomes less than the threshold voltage Vth1. Since the level shift circuit 13 is provided between the output terminal of the comparator CMP1 and the reset input terminal of the RS flip-flop circuit 12, the ground potentials of the first switching element M1 and the second switching element M2 are matched. be able to.

Further, as shown at time t2 and FIG. 3 in FIG. 2B, the drain source voltage M1_Vds between the drain terminal M1d and the source terminal M1s of the first switching element M1 falls and the voltage source VTH2 supplies the voltage source VTH2 with reference to the ground GND1. The threshold voltage is less than Vth2. Then, as shown at time t2 in FIGS. 3 and 5, the comparator CMP2 detects that the drain source voltage M1_Vds of the first switching element M1 has become less than the threshold voltage Vth2, and outputs a high-level output signal CP2. To do. As a result, the comparator CMP2 inputs the high-level output signal CP2 to the set input terminal of the RS flip-flop circuit 11. In this way, the comparator CMP2 monitors whether or not the drain source voltage M1_Vds between the drain terminal M1d and the source terminal M1s of the first switching element M1 becomes less than the threshold voltage Vth2.

Then, as shown at time t2 in FIGS. 3 and 5, in the RS flip flop circuit 11, the low level output signal CP1 is input to the reset input terminal by the comparator CMP1, and the high level output signal CP2 is set by the comparator CMP2. Since it has been input to the input terminal, a high-level output signal Q1 is output, and a high-level gate drive voltage M1_Vg is applied to the gate terminal M1g of the first switching element M1 via the buffer BUF1. As a result, the first switching element M1 is turned on. Then, as shown in FIGS. 2B and 3, the source / drain current M1_Isd begins to flow between the source terminal M1s and the drain terminal M1d of the first switching element M1. In this way, the first switching element M1 controls the rise of the gate drive voltage based on the change in the drain source voltage M1_Vds of the switching element M1 monitored by the comparator CMP2.

Further, as shown at time t2 and FIG. 3 in FIG. 2C, the drain source voltage M2_Vds between the drain terminal M2d and the source terminal M2s of the second switching element M2 rises with reference to the connection point P5, and the voltage source VTH3 is supplied. The threshold voltage is Vth3 or higher. Then, as shown in t = 2 in FIGS. 3 and 5, the comparator CMP3 detects that the drain source voltage M2_Vds of the second switching element M2 becomes equal to or higher than the threshold voltage Vth3, and outputs a low-level output signal CP3. Output.

As a result, the comparator CMP3 inputs the low-level output signal CP3 to the set input terminal of the RS flip-flop circuit 12. In this way, the comparator CMP3 monitors whether or not the drain source voltage M2_Vds between the drain terminal M2d and the source terminal M2s of the second switching element M2 becomes less than the threshold voltage Vth3.

Then, as shown at time t2 in FIGS. 3 and 5, in the RS flip flop circuit 12, a high level output signal CP1 inverting signal is input to the reset input terminal by the comparator CMP1 and the inverter INV1, and the low level is input by the comparator CMP3. Since the output signal CP3 is input to the set input terminal, the low-level output signal Q2 is output, and the low-level gate drive voltage M2_Vg is applied to the gate terminal M2g of the second switching element M2 via the buffer BUF2. As a result, the second switching element M2 is turned off. Then, as shown in FIGS. 2C and 3, the source / drain current M2_Isd does not flow between the source terminal M2s and the drain terminal M2d of the second switching element M2.

As described above, the comparator CMP1 and the RS flipflop circuit 12 are applied to the voltage detection element R1 connected in series to the source terminal M2s and the drain terminal M2d of the second switching element M2 via the first switching element M1. The second switching element M2 is turned off based on the AC voltage V_R1. Further, since the inverter INV1 is provided between the output terminal of the comparator CMP1 and the reset input terminal of the RS flip-flop circuit 12, the first switching element M1 is turned on and off based on the output signal from the comparator CMP1. , The on and off of the second switching element M2 can be inverted.

Here, when the switching element is turned off based on the AC voltage applied to the voltage detection element connected in parallel to the source terminal and the drain terminal of the switching element, a current is generated between the source terminal and the drain terminal immediately before the switching element is turned off. Due to the influence of the voltage change between the source terminal and the drain terminal generated by turning off the switching element where the switching element was flowing, chattering occurs in which the gate drive voltage of the switching element repeatedly rises and falls in a short period of time.

On the other hand, according to the rectifier 5, the voltage detection element R1 is not parallel to the source terminal M2s and the drain terminal M2d of the second switching element M2, but is connected in series via the first switching element M1. Then, the comparator CMP1 and the RS flipflop circuit 12 are based on the alternating current input or output to the source terminal M2s and the drain terminal M2d of the second switching element M2 (that is, the alternating current flowing through the voltage detection element R1). Turn off the switching element M2. Therefore, immediately before the second switching element M2 is turned off, the second switching element M2 is turned off where the current was flowing between the source terminal M2s and the drain terminal M2d, so that the voltage between the source terminal M2s and the drain terminal M2d is increased. Even if a change occurs, the second switching element M2 can be turned off without being affected by the voltage change. As a result, the comparator CMP1 and the RS flip-flop circuit 12 can suppress the occurrence of chattering and turn off the second switching element M2.

<< Operation of the control circuit 10 when turning off the first switching element M1 >>
The operation of the control circuit 10 when the first switching element M1 is turned off will be described with reference to FIGS. 2A to 2C, FIGS. 4 and 5. In FIGS. 2A to 2C and 5, the time when the control circuit 10 turns off the first switching element M1 and turns on the second switching element M2 is at time t1 and at time t3. Here, the time t1 will be described as an example.

As shown at time t1 and FIG. 4 in FIG. 2A, the AC voltage V_R1 of the voltage detection element R1 becomes less than the threshold voltage Vth1 supplied by the voltage source VTH1. Then, as shown at time t1 in FIGS. 4 and 5, the comparator CMP1 detects that the AC voltage V_R1 of the voltage detection element R1 has become less than the threshold voltage Vth1, and outputs a high-level output signal CP1. As a result, the comparator CMP1 inputs the high-level output signal CP1 to the reset input terminal of the RS flip-flop circuit 11, and level-shifts the low-level output signal CP1 inverted signal in which the output signal CP1 is inverted by the inverter INV1. Input is made to the reset input terminal of the RS flip-flop circuit 12 via the circuit 13. In this way, the comparator CMP1 monitors whether or not the AC voltage of the voltage detecting element R1 connected in series with the first switching element M1 becomes less than the threshold voltage Vth1.

Further, as shown at time t1 and FIG. 4 in FIG. 2B, the drain source voltage M1_Vds between the drain terminal M1d and the source terminal M1s of the first switching element M1 rises and is supplied by the voltage source VTH2 with reference to the ground GND1. The threshold voltage is Vth2 or higher. Then, as shown at time t1 in FIGS. 4 and 5, the comparator CMP2 detects that the drain source voltage M1_Vds of the first switching element M1 becomes equal to or higher than the threshold voltage Vth2, and outputs a low-level output signal CP2. To do. As a result, the comparator CMP2 inputs the low-level output signal CP2 to the set input terminal of the RS flip-flop circuit 11. In this way, the comparator CMP2 monitors whether or not the drain source voltage M1_Vds between the drain terminal M1d and the source terminal M1s of the first switching element M1 becomes less than the threshold voltage Vth2.

Then, as shown at time t1 in FIGS. 4 and 5, in the RS flip flop circuit 11, the high level output signal CP1 is input to the reset input terminal by the comparator CMP1, and the low level output signal CP2 is set by the comparator CMP2. Since it is input to the input terminal, the low-level output signal Q1 is output, and the low-level gate drive voltage M1_Vg is applied to the gate terminal M1g of the first switching element M1 via the buffer BUF1. As a result, the first switching element M1 is turned off. Then, as shown in FIGS. 2B and 4, the source / drain current M1_Isd does not flow between the source terminal M1s and the drain terminal M1d of the first switching element M1.

In this way, the comparator CMP1 and the RS flip-flop circuit 11 turn off the first switching element M1 based on the AC voltage V_R1 applied to the voltage detection element R1 connected in series with the source terminal M1s and the drain terminal M1d. ..

Here, as described above, when the switching element is turned off based on the AC voltage applied to the voltage detection element connected in parallel to the source terminal and the drain terminal of the switching element, the source terminal and the source terminal and the drain terminal immediately before the switching element is turned off Chattering occurs due to the influence of the voltage change between the source terminal and the drain terminal that occurs when the switching element is turned off where the current is flowing between the drain terminals.

On the other hand, according to the rectifier 5, the voltage detection element R1 is connected in series with the source terminal M1s and the drain terminal M1d of the first switching element M1 instead of in parallel. Then, the comparator CMP1 and the RS flipflop circuit 11 are first based on the alternating current input or output to the source terminal M1s and the drain terminal M1d of the first switching element M1 (that is, the alternating current flowing through the voltage detection element R1). Turn off the switching element M1. Therefore, immediately before the first switching element M1 is turned off, the voltage changes between the source terminal M1s and the drain terminal M1d by turning off the first switching element M1 where the current was flowing between the source terminal M1s and the drain terminal M1d. Even if the above occurs, the first switching element M1 can be turned off without being affected by the voltage change. Therefore, the comparator CMP1 and the RS flip-flop circuit 11 can suppress the occurrence of chattering and turn off the first switching element M1.

Further, as shown at time t1 and FIG. 4 in FIG. 2C, the drain source voltage M2_Vds between the drain terminal M2d and the source terminal M2s of the second switching element M2 falls with reference to the connection point P5, and the voltage source VTH3 becomes The supplied threshold voltage is less than Vth3. Then, as shown at time t1 in FIGS. 4 and 5, the comparator CMP3 detects that the drain source voltage M2_Vds of the second switching element M2 has become less than the threshold voltage Vth3, and outputs a high-level output signal CP3. To do. As a result, the comparator CMP3 inputs the high-level output signal CP3 to the set input terminal of the RS flip-flop circuit 12. In this way, the comparator CMP3 monitors whether or not the drain source voltage M2_Vds between the drain terminal M2d and the source terminal M2s of the second switching element M2 becomes less than the threshold voltage Vth3.

Then, as shown at time t1 in FIGS. 4 and 5, in the RS flip flop circuit 12, the low level output signal CP1 inverting signal is input to the reset input terminal by the comparator CMP1 and the inverter INV1, and the high level is input by the comparator CMP3. Since the output signal CP3 is input to the set input terminal, the high level output signal Q2 is output, and the high level gate drive voltage M2_Vg is applied to the gate terminal M2g of the second switching element M2 via the buffer BUF2. As a result, the second switching element M2 is turned on. Then, as shown at time t1 and FIG. 4 in FIG. 2C, the source / drain current M2_Isd begins to flow between the source terminal M2s and the drain terminal M2d of the second switching element M2. As a result, the storage capacitor C3 can be charged through the second switching element M2.

Here, it is desirable that the first switching element M1 and the second switching element M2 are turned on during a period in which the capacitive charging energy between the terminals is discharged and the parasitic diode formed inside is conducting. Therefore, considering an ideal state in which there is no signal delay in the control circuit 10, the threshold voltage Vth1 = 0V, the threshold voltage Vth2 = 0V, and the threshold voltage Vth3 = 0V may be used.

However, in reality, a delay occurs in the signal between each element in the control circuit 10. Therefore, the threshold voltage Vth1 is preferably a potential at which the first switching element M1 turns off before the AC voltage V_R1 becomes zero (positive state). Further, the threshold voltage Vth3 and the threshold voltage Vth2 are preferably negative potentials.

That is, for example, it is preferable that the threshold voltage Vth1> 0, the threshold voltage Vth2 <0, and the threshold voltage Vth3 <0. Thereby, for example, at time t1, the inversion timing of the output signal of the comparator CMP1 can be more reliably and earlier than the inversion timing of the output signals of the comparator CMP2 and the comparator CMP3. That is, the rectifier 5 can be operated more reliably so that the comparators CMP2 and CMP3 invert the output signal after the comparator CMP1 inverts the output signal. In this way, since the comparators CMP2 and CMP3 operate after the comparator CMP1 operates, even if the signal delay in the control circuit 10 is taken into consideration, the malfunction of the control circuit 10 can be prevented more reliably. The on and off timings of the first switching element M1 and the second switching element M2 can be controlled based on the change in the AC voltage of the voltage detecting element R1.

The values of the threshold voltage Vth1, the threshold voltage Vth2, and the threshold voltage Vth3 may be determined based on the characteristics of the comparators CMP1, CMP2, and CMP3, and the characteristics of the first switching element M1 and the second switching element M2. By adjusting each of the threshold voltages Vth1 to Vth3 in this way, it is possible to control the inversion timing of the output signals of the comparators CMP1 to CMP3. As an example, the threshold voltage Vth1 can be set to about several mV to several tens of mV, the threshold voltage Vth2 can be set to about −50 mV to −300 mV, and the threshold voltage Vth3 can be set to about −50 mV to −300 mV.

(Main advantage)
As shown in FIGS. 2A to 2C, FIGS. 3 and 4, and the like, in the rectifying device 5, the voltage detection element R1 to which the AC voltage V_R1 as a reference for turning off the first switching element M1 is applied is the first switching. It is connected to the drain terminal M1d and the source terminal M1s of the element M1 in series instead of in parallel. Therefore, when the first switching element M1 turns off, it is possible to suppress the occurrence of chattering due to a voltage change between the drain terminal M1d and the source terminal M1s of the first switching element M1.

Further, the voltage detection element R1 is also connected to the drain terminal M2d and the source terminal M2s of the second switching element M2 in series via the first switching element M1 instead of in parallel. Therefore, it is possible to suppress the occurrence of chattering due to the voltage change between the drain terminal M2d and the source terminal M2s of the second switching element M2 when the second switching element M2 turns off.

Then, according to the rectifier 5, unlike the full-wave rectifier circuit described in Patent Document 1, a sub synchronous rectifier transistor for preventing chattering is provided for each of the first switching element M1 and the second switching element M2. It is not necessary to install them in parallel. Therefore, according to the rectifier 5, a half-wave rectifier circuit that is driven with lower power consumption and suppresses the occurrence of chattering in a smaller circuit area than the full-wave rectifier circuit described in Patent Document 1 is provided. Can be configured. As a result, by mounting the rectifier 5 on various electronic devices, it is possible to obtain a miniaturized electronic device with low power consumption. In particular, by mounting the rectifier 5 on a mobile device, it is possible to obtain a mobile device with low power consumption and miniaturization.

[Embodiment 2]
The second embodiment of the present disclosure will be described below. For convenience of explanation, the same reference numerals will be added to the members having the same functions as the members described in the first embodiment, and the description will not be repeated. FIG. 6 is a diagram showing an example of the configuration of the rectifying device 5A according to the second embodiment. The non-contact power feeding system 1 shown in FIG. 1 or the like may include the rectifying device 5A shown in FIG. 6 instead of the rectifying device 5. The rectifying device 5A includes a control circuit 10A in place of the control circuit 10 provided in the rectifying device 5 (FIG. 1 and the like). The control circuit 10A includes a comparator CMP4 instead of the inverter INV1 provided in the control circuit 10 (FIG. 1 and the like).

In the present embodiment, the output terminal of the comparator CMP1 is connected to the reset input terminal of the RS flip-flop circuit 11 without branching in two directions, and is not connected to the reset input terminal of the RS flip-flop circuit 12. .. In the comparator CMP4, the positive input terminal is connected to the connection point P8 between the negative input terminal of the comparator CMP1 and the connection point P4, and the negative input terminal has a threshold voltage Vth4 (second threshold voltage). It is connected to the ground GND5 via the output voltage source VTH4. The output terminal of the comparator CMP4 is connected to the reset input terminal of the RS flip-flop circuit 12 via the level shift circuit 13. The other configuration of the rectifier 5A is the same as that of the rectifier 5 (FIG. 1 and the like).

In the rectifier 5A, the comparator CMP1 controls the reset input of the RS flip-flop circuit 11 based on the comparison result between the AC voltage of the voltage detection element R1 and the threshold voltage Vth1. Specifically, when the AC voltage of the voltage detection element R1 becomes less than the threshold voltage Vth1, the comparator CMP1 inputs a high level output signal to the reset input terminal of the RS flip flop circuit 11, and the AC voltage of the voltage detection element R1. When the threshold voltage Vth1 or higher is reached, a low-level output signal is input to the reset input terminal of the RS flip-flop circuit 11.

Further, the comparator CMP4 controls the reset input of the RS flip-flop circuit 12 based on the comparison result between the AC voltage of the voltage detection element R1 and the threshold voltage Vth4. Specifically, when the AC voltage of the voltage detection element R1 becomes less than the threshold voltage Vth4, the comparator CMP4 inputs a high level output signal to the reset input terminal of the RS flip flop circuit 12, and the AC voltage of the voltage detection element R1. When the threshold voltage Vth4 or higher is reached, a low-level output signal is input to the reset input terminal of the RS flip-flop circuit 11.

As described above, according to the rectifier 5A, the reset input timing of the RS flip-flop circuit 11 and the reset input timing of the RS flip-flop circuit 12 can be individually adjusted by the separate threshold voltages Vth1 and Vth4. it can. That is, according to the rectifier 5A, the turn-off timing of the first switching element M1 and the turn-off timing of the second switching element M2 can be adjusted by different threshold voltages Vth1 and Vth4.

As a result, the turn-off timing of the first switching element M1 and the turn-off timing of the second switching element M2 can be more accurately matched. As a result, it is possible to obtain a rectifier 5A that can be charged efficiently.

Here, for example, the output terminal of the comparator CMP1 is directly connected to the reset input terminal of the RS flip-flop circuit 11, while the output terminal of the comparator CMP4 resets the RS flip-flop circuit 12 via the level shift circuit 13. It is connected to the input terminal. Therefore, the reset input of the RS flip-flop circuit 12 is more likely to be delayed than the reset input of the RS flip-flop circuit 11. In other words, the turn-off timing of the second switching element M2 is more likely to be delayed than the turn-off timing of the first switching element M1.

Therefore, for example, the threshold voltage Vth2 of the comparator CMP2 is set to be smaller than the threshold voltage Vth4 of the comparator CMP4 by about several tens of mV to several hundreds of mV. In other words, the threshold voltage Vth4 is made larger than the threshold voltage Vth1. As a result, the comparator CMP4 can output an inverted signal from the output terminal before the comparator CMP2. As a result, the turn-off timing of the second switching element M2 can be matched with the turn-off timing of the first switching element M1.

[Embodiment 3]
Embodiment 3 of the present disclosure will be described below. For convenience of explanation, the same reference numerals are added to the members having the same functions as the members described in the first and second embodiments, and the description is not repeated. FIG. 7 is a diagram showing an example of an alternating current flow in a state where the first switching element M1 and the fourth switching element M4 are on in the rectifier device 5B according to the third embodiment. FIG. 8 is a diagram showing an example of an alternating current flow in a state where the second switching element M2 and the third switching element M3 are on in the rectifier device 5B according to the third embodiment. The non-contact power feeding system 1 shown in FIG. 1 and the like may include the rectifying device 5B shown in FIGS. 7 and 8 in place of the rectifying device 5.

First, an example of the configuration of the rectifying device 5B according to the third embodiment will be described with reference to FIG. 7. The rectifier 5B is a full-wave rectifier circuit. The rectifying device 5B includes a control circuit 10B in place of the control circuit 10 provided in the rectifying device 5 (FIG. 1 and the like), and further includes a third switching element M3 and a fourth switching element M4. The control circuit 10B includes, for example, the level shift circuits 13B1, 13B2, 13B3 and the inverter INV1B in place of the level shift circuit 13 and the inverter INV1 provided in the control circuit 10 (FIG. 1 and the like). The connection relationship between the power receiving coil L1, the first resonance capacitor C1, the second resonance capacitor C2, and the voltage detection element R1 is the same as that of the control circuit 10 (FIG. 1 and the like).

In the first switching element M1, the source terminal M1s is connected to the ground GND1. The drain terminal M1d is branched in three directions via the connection point P11, and the first path is connected from the connection point P11 to the voltage detection element R1 and the first resonance capacitor C1 via the connection point P2, respectively. The second path is connected from the connection point P11 to the source terminal M2s of the second switching element M2, and the third path is connected from the connection point P11 to the negative input terminal of the comparator CMP2. The gate terminal M1g is connected to the connection point P12 via the buffer BUF1, branches in two directions from the connection point P12, and the first path is connected to the output terminal of the RS flip-flop circuit 11 from the connection point P12. The second path is connected to the level shift circuit 13B2 from the connection point P12.

In the second switching element M2, the source terminal M2s is connected to each of the voltage detection element R1 and the first resonance capacitor C1 via the connection point P11, and is also connected to the drain terminal M1d of the first switching element M1. There is. The drain terminal M2d is connected to one terminal of the storage capacitor C3 via the connection point P13. The gate terminal M2g is connected to the output terminal of the RS flip-flop circuit 12 via the buffer BUF4, the level shift circuit 13B3, and the connection point P14.

The third switching element M3 is a transistor such as a MOSFET. The third switching element M3 has a source terminal M3s, a drain terminal M3d, and a gate terminal M3g. The third switching element M3 is turned on between the source terminal M3s and the drain terminal M3d with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal M3g by the control circuit 10B. It switches between conductive state) and off (non-conducting state).

In the third switching element M3, the source terminal M3s is connected to the ground GND6 which is a reference potential point. The drain terminal M3d is connected to the source terminal M4s of the fourth switching element M4 via the connection point P15, and is also connected to one terminal of the power receiving coil L1. The gate terminal M3g is connected to the output terminal of the RS flip-flop circuit 12 via the buffer BUF3 and the connection point P14.

The fourth switching element M4 is, for example, a transistor such as a MOSFET. The fourth switching element M4 has a source terminal M4s, a drain terminal M4d, and a gate terminal M4g. The fourth switching element M4 is turned on between the source terminal M4s and the drain terminal M4d with respect to the alternating current flowing through the power receiving coil L1 by controlling the gate drive voltage supplied to the gate terminal M4g by the control circuit 10B. It switches between conductive state) and off (non-conducting state).

In the fourth switching element M4, the source terminal M4s is connected to the drain terminal M3d of the third switching element M3 via the connection point P15, and is also connected to one terminal of the power receiving coil L1. The drain terminal M4d is connected to one terminal of the storage capacitor C3 via the connection point P13. The gate terminal M4g is connected to the output terminal of the RS flip-flop circuit 11 via the buffer BUF2, the level shift circuit 13B2, and the connection point P12.

The comparator CMP1 is connected to the connection point P16 between the connection point P2 and the connection point P11 via the voltage source VTH1 whose negative input terminal outputs the threshold voltage Vth1. The positive input terminal of the comparator CMP1 is connected to the connection point P4. The output terminal of the comparator CMP1 is connected to the connection point P17 via the level shift circuit 13B1 and branches in two directions from the connection point P17. The first path is connected to the reset input terminal of the RS flip-flop circuit from the connection point P17, and the second path is connected to the reset input terminal of the RS flip-flop circuit 12 from the connection point P17 via the inverter INV1B. ..

The comparator CMP2 is connected to the ground GND3 via the voltage source VTH2 whose positive input terminal outputs the threshold voltage Vth2. The negative input terminal of the comparator CMP2 is connected to the connection point P11. The output terminal of the comparator CMP2 is connected to the set input terminal of the RS flip-flop circuit 11.

The comparator CMP3 is connected to the ground GND7, which is the reference potential point, via the voltage source VTH3 whose positive input terminal outputs the threshold voltage Vth3. The negative input terminal of the comparator CMP3 is connected to the connection point P18 between the connection point P15 and the drain terminal M3d of the third switching element M3. The output terminal of the comparator CMP3 is connected to the set input terminal of the RS flip-flop circuit 12.

Of the RS flip-flop circuit 11, the set input terminal is connected to the output terminal of the comparator CMP2, and the reset input terminal is connected to the output terminal of the comparator CMP1 via the connection point P17 and the level shift circuit 13B1. The output terminal of the RS flip-flop circuit 11 branches in two directions via the connection point P12, the first path is connected to the gate terminal M1g of the first switching element M1 via the buffer BUF1, and the second path is a level shift circuit. It is connected to the gate terminal M4g of the fourth switching element M4 via 13B2 and the buffer BUF2.

In the RS flip-flop circuit 12, the set input terminal is connected to the output terminal of the comparator CMP3, and the reset input terminal is connected to the output terminal of the comparator CMP1 via the inverter INV1B, the connection point P17 and the level shift circuit 13B1. .. The output terminal of the RS flip-flop circuit 12 branches in two directions via the connection point P14, the first path is connected to the gate terminal M3g of the third switching element M3 via the buffer BUF3, and the second path is level-shifted. It is connected to the gate terminal M4g of the fourth switching element M4 via the circuit 13B3 and the buffer BUF4.

Next, with reference to FIG. 7, the operation of the control circuit 10B when the first switching element M1 and the fourth switching element M4 of the rectifying device 5 turn on and the flow of the alternating current I1B flowing through the rectifying device 5 will be described.

When the drain-source voltage of the first switching element M1 becomes low level and becomes less than the threshold voltage Vth2, the comparator CMP2 outputs a high level output signal to the set input terminal of the RS flip-flop circuit 11. At this time, the AC voltage applied to the voltage detection element R1 becomes less than the threshold voltage Vth1, and the comparator CMP1 outputs a low-level output signal to the level shift circuit 13B1. Then, the low level output signal output from the level shift circuit 13B1 is input to the reset input terminal of the RS flip-flop circuit 11, and the inverted signal inverted to the high level by the inverter INV1B through the connection point P17 is transmitted. It is input to the reset input terminal of the RS flip-flop circuit 12.

The RS flip-flop circuit 11 outputs a high-level output signal because the low-level output signal is input to the reset input terminal by the comparator CMP1 and the high-level output signal is input to the set input terminal by the comparator CMP2. Then, the RS flip-flop circuit 11 applies a high-level gate drive voltage to the gate terminal M1g of the first switching element M1 via the buffer BUF1, and applies a high-level gate drive voltage via the level shift circuit 13B2 and the buffer BUF2 to the fourth switching element M4. A high level gate drive voltage is applied to the gate terminal M4g of the above. As a result, the RS flip-flop circuit 11 turns on the first switching element M1 and the fourth switching element M4.

At this time, since the voltage between the drain sources of the third switching element M3 becomes high level and becomes the threshold voltage Vth3 or more, the comparator CMP3 outputs a low level output signal to the set input terminal of the RS flip-flop circuit 12.

Then, the RS flip-flop circuit 12 outputs a low-level output signal because the high-level inverted signal is input to the reset input terminal by the comparator CMP1 and the low-level output signal is input to the set input terminal by the comparator CMP3. .. Then, the RS flip-flop circuit 12 applies a low-level gate drive voltage to the gate terminal M3g of the third switching element M3 via the buffer BUF3, and applies a low-level gate drive voltage via the level shift circuit 13B3 and the buffer BUF4 to the second switching element M2. A low-level gate drive voltage is applied to the gate terminal M2g of the above. As a result, the S flip-flop circuit 12 turns off the second switching element M2 and the third switching element M3.

In this way, when the first switching element M1 and the fourth switching element M4 are turned on and the second switching element M2 and the third switching element M3 are turned off, the alternating current I1B becomes the source terminal M1s of the first switching element M1. Flows from the drain terminal M1d, does not flow from the connection point P11 toward the second switching element M2, and flows into the connection point P2. Then, the alternating current I1B branches from the connection point P2, flows through the first resonance capacitor C1 in one path, flows through the voltage detection element R1 and the second resonance capacitor C2 in the other path, and merges at the connection point P3. To do. Then, the alternating current I1B merged at the connection point P3 flows through the power receiving coil L1 and the connection point P15, flows from the source terminal M4s of the fourth switching element M4 to the drain terminal M4d, passes through the connection point P13, and reaches the storage capacitor C3. Be supplied. As a result, the storage capacitor C3 is charged.

Next, with reference to FIG. 8, the operation of the control circuit 10B when the second switching element M2 and the third switching element M3 of the rectifying device 5 turn on and the flow of the alternating current I2B flowing through the rectifying device 5 will be described.

When the AC voltage applied to the voltage detection element R1 becomes the threshold voltage Vth1 or higher, the comparator CMP1 outputs a high-level output signal to the level shift circuit 13B1. Then, the high-level output signal output from the level shift circuit 13B1 is input to the reset input terminal of the RS flip-flop circuit 11, and the inverted signal inverted to the low level by the inverter INV1B through the connection point P17 is transmitted. It is input to the reset input terminal of the RS flip-flop circuit 12. At this time, since the voltage between the drain sources of the first switching element M1 becomes high level and becomes the threshold voltage Vth2 or more, the comparator CMP2 outputs a low level output signal to the set input terminal of the RS flip-flop circuit 11.

Then, the RS flip-flop circuit 11 outputs the low-level output signal because the high-level output signal is input to the reset input terminal by the comparator CMP1 and the low-level output signal is input to the set input terminal by the comparator CMP2. .. Then, the RS flip-flop circuit 11 applies a low-level gate drive voltage to the gate terminal M1g of the first switching element M1 via the buffer BUF1, and applies a low-level gate drive voltage via the level shift circuit 13B2 and the buffer BUF2 to the fourth switching element M4. A low-level gate drive voltage is applied to the gate terminal M4g of the above. As a result, the RS flip-flop circuit 11 turns off the first switching element M1 and the fourth switching element M4.

Further, when the voltage between the drain sources of the third switching element M3 becomes low level and becomes less than the threshold voltage Vth3, the comparator CMP3 outputs a high level output signal to the set input terminal of the RS flip-flop circuit 12.

At this time, the RS flip-flop circuit 12 outputs a high-level output signal because the low-level inverted signal is input to the reset input terminal by the comparator CMP1 and the high-level output signal is input to the set input terminal by the comparator CMP3. To do. Then, the RS flip-flop circuit 12 applies a high-level gate drive voltage to the gate terminal M3g of the third switching element M3 via the buffer BUF3, and applies a high-level gate drive voltage via the level shift circuit 13B3 and the buffer BUF4 to the second switching element M2. A high level gate drive voltage is applied to the gate terminal M2g of the above. As a result, the RS flip-flop circuit 12 turns on the second switching element M2 and the third switching element M3.

In this way, when the first switching element M1 and the fourth switching element M4 are turned off and the second switching element M2 and the third switching element M3 are turned on, the alternating current I2B becomes the source terminal M3s of the third switching element M3. Flows from the drain terminal M3d, does not flow from the connection point P15 in the direction of the fourth switching element M4, and flows into the connection point P3 via the power receiving coil L1. Then, the alternating current I2B branches from the connection point P3, flows through the first resonance capacitor C1 in one path, flows through the second resonance capacitor C2 and the voltage detection element R1 in the other path, and merges at the connection point P2. To do. Then, the alternating current I2B merged at the connection point P2 flows into the connection point P11. Then, the alternating current I2B does not flow from the connection point P11 in the direction of the first switching element M1, but flows from the source terminal M4s of the fourth switching element M4 to the drain terminal M4d, and is supplied to the storage capacitor C3 via the connection point P13. Will be done. As a result, the storage capacitor C3 is charged.

In this way, the control circuit 10B is operated so as to invert the on and off of the first switching element M1 and the fourth switching element M4 and the second switching element M2 and the third switching element M3. Since the reference potential (potential of the connection point P4) detected by the comparator CMP1 based on the voltage detection element R1 is different from the reference potential of each of the first switching element M1 and the third switching element M3, the comparator CMP1 is the level shift circuit 13B1. The output signal is input to each of the RS flip- flop circuits 11 and 12 via. Further, since the fourth switching element M4 has a different reference potential from the first switching element M1, the RS flip-flop circuit 11 operates the fourth switching element M4 via the level shift circuit 13B1. Further, since the second switching element M2 has a different reference potential from the third switching element M3, the RS flip-flop circuit 12 operates the second switching element M2 via the level shift circuit 13B3.

As described above, in the rectifier 5B, the first switching element M1 is connected in series with the voltage detection element R1. Further, the second switching element M2 is connected in series with the voltage detection element R1. Then, the comparator CMP1 and the RS flip-flop circuit 11 turn off the first switching element M1 and the fourth switching element M4 based on the change in the AC voltage applied to the voltage detection element R1. Therefore, the first switching element M1 and the fourth switching element M4 can be turned off while suppressing chattering.

Further, the third switching element M3 is connected in series to the voltage detection element R1 via the power receiving coil L1 and the second resonance capacitor C2. Further, the fourth switching element M4 is connected in series via a power receiving coil L1 and a second resonance capacitor C2. Then, the comparator CMP1 and the RS flip-flop circuit 12 turn off the second switching element M2 and the third switching element M3 based on the change in the AC voltage applied to the voltage detection element R1. Therefore, the second switching element M2 and the third switching element M3 can be turned off while suppressing chattering.

The present disclosure is not limited to the above-described embodiment, and is substantially the same as the configuration shown in the above-described embodiment, a configuration that exhibits the same action and effect, or a configuration that can achieve the same purpose. May be replaced with.

1 Non-contact power supply system 2 Power transmission device 3 Drive power supply 5, 5A, 5B Rectifier 7 Detection circuit 10, 10A, 10B Control circuit 11, 12 Flip-flop circuit 13, 13B1 to 13B3 Level shift circuit BUF1 to BUF4 Buffer C1 1st Resonant capacitor (first power storage unit)
C2 2nd resonant capacitor (2nd storage unit)
C3 power storage capacitor (third power storage unit)
C4 Resonant capacitor CMP1 to CMP4 Comparator INV1, INV1B Inverter L1 Power receiving coil (feeding unit)
L2 Power transmission coil M1 1st switching element M2 2nd switching element M3 3rd switching element M4 4th switching element R1 Voltage detection element

Claims (9)

1. A power supply unit that supplies alternating current and
   A first switching element that switches between a conductive state and a non-conducting state with respect to the alternating current,
   A detection circuit connected in series to the first switching element and to which an alternating voltage corresponding to the alternating current is applied.
   A rectifier device including a control circuit for switching between the conductive state and the non-conducting state of the first switching element based on the AC voltage.
2. A second switching element that switches between a conductive state and a non-conducting state with respect to the alternating current and is connected in series with the first switching element.
   The rectifier according to claim 1, wherein the control circuit switches between the conductive state and the non-conducting state of the second switching element so as to reverse the conductive state and the non-conducting state of the first switching element.
3. The rectifying device according to claim 2, further comprising a third power storage unit that is connected to the power supply unit and the first switching element via the second switching element and stores electricity based on the alternating current.
4. The rectifier according to claim 2 or 3, wherein the front power feeding unit has a power receiving coil that wirelessly receives power and supplies the alternating current.
5. When the AC voltage becomes less than a predetermined first threshold voltage, the control circuit switches the first switching element to the non-conducting state and switches the second switching element to the conducting state.
   The rectifier according to any one of claims 2 to 4, wherein the first threshold voltage is positive.
6. The rectification according to claim 5, wherein the control circuit switches between a conductive state and a non-conducting state of the second switching element when the AC voltage becomes a predetermined second threshold voltage different from the first threshold voltage. apparatus.
7. A third switching element and a fourth switching element that switch between a conductive state and a non-conducting state with respect to the alternating current are provided.
   The third switching element is connected in series with the detection circuit.
   The third power storage unit is connected to the power feeding unit and the third switching element via the fourth switching element.
   The control circuit switches the conduction state and non-conduction state of the first switching element and the fourth switching element so as to be inverted with the conduction state and non-conduction state of the second switching element and the third switching element. The rectifying device according to claim 3.
8. The detection circuit
   A first power storage unit interposed between the power feeding unit and the first switching element and connected in series with the first switching element.
   A second power storage unit connected in parallel with the first power storage unit,
   The rectifying device according to any one of claims 1 to 7, further comprising a voltage detecting element connected in parallel with the first power storage unit and connected in series with the second power storage unit.
9. The rectifying device according to claim 4 and
   A non-contact power feeding system having a power transmission coil that wirelessly transmits power to the power receiving coil.

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