WO2020184145A1

WO2020184145A1 - Image encoding device, image encoding method, image decoding device, and image decoding method

Info

Publication number: WO2020184145A1
Application number: PCT/JP2020/006993
Authority: WO
Inventors: 健治近藤
Original assignee: ソニー株式会社
Priority date: 2019-03-08
Filing date: 2020-02-21
Publication date: 2020-09-17
Also published as: JP2022068378A

Abstract

The present disclosure relates to an image encoding device, an image encoding method, an image decoding device, and an image decoding method which enhance image quality and encoding efficiency while avoiding a reduction in processing speed. According to the present invention, an orthogonal transform unit obtains, in transform units of a block size ２×２, transform coefficients by performing orthogonal transform on a prediction residual, which is obtained in a block size ４×４ that is a processing unit to be encoded when an image is encoded. In addition, a quantization unit quantizes the transform coefficients in processing units of the block size ４×４, and obtains quantized transform coefficients. The encoding unit encodes the quantized transform coefficients in processing units of the block size ４×４, and outputs a bitstream. The present technology can be applied to, for example, an encoding device which performs encoding by using intra prediction.

Description

Image coding device, image coding method, image decoding device, and image decoding method

The present disclosure relates to an image encoding device, an image coding method, an image decoding device, and an image decoding method, and in particular, an image in which image quality and coding efficiency can be improved while avoiding a decrease in processing speed. The present invention relates to a coding device, an image coding method, an image decoding device, and an image decoding method.

In ITU-T (International Telecommunication Union Telecommunication Standardization Sector), JVET (Joint Video Exploration Team), which is developing next-generation video coding, provides various video coding as disclosed in Non-Patent Document 1. is suggesting.

By the way, conventionally, when an input image contains an impulse signal, the influence of the impulse signal spreads over the entire processing unit to be processed for coding, which not only reduces the reproducibility of the image but also deteriorates the reproducibility of the image. There is a concern that the coding efficiency will decrease. On the other hand, when the processing unit to be processed for coding is reduced, it is considered that the spread of the influence of the impulse signal can be suppressed, the deterioration of the image quality can be suppressed, and the coding efficiency can be improved. .. However, in this case, the processing speed at the time of encoding and decoding is reduced.

This disclosure has been made in view of such a situation, and is intended to enable improvement of image quality and coding efficiency while avoiding a decrease in processing speed.

The coding apparatus of one aspect of the present disclosure converts the predicted residual obtained in the processing unit to be encoded by orthogonal conversion in a conversion unit smaller than the processing unit when encoding the image, and has a conversion coefficient. The orthogonal conversion unit for obtaining the above, the quantization unit for obtaining the quantization conversion coefficient by quantizing the conversion coefficient in the processing unit, and the code for encoding the quantization conversion coefficient in the processing unit and outputting a bit stream. It is equipped with a conversion unit.

In the coding method of one aspect of the present disclosure, when the coding apparatus encodes an image, the predicted residuals obtained in the processing unit to be encoded are orthogonal to each other in a conversion unit smaller than the processing unit. The conversion coefficient is obtained by conversion, the conversion coefficient is quantized in the processing unit to obtain the quantization conversion coefficient, and the quantization conversion coefficient is encoded in the processing unit to output a bit stream. Including that.

In one aspect of the present disclosure, when encoding an image, the predicted residual obtained in the processing unit to be encoded is orthogonally converted in a conversion unit smaller than the processing unit to obtain a conversion coefficient. , The conversion coefficient is quantized in the processing unit to obtain the quantization conversion coefficient, and the quantization conversion coefficient is encoded in the processing unit to output a bit stream.

The decoding device of one aspect of the present disclosure includes a decoding unit that decodes a bit stream encoded in a processing unit to be encoded in the processing unit to obtain a quantization conversion coefficient, and the quantization conversion coefficient. Is provided with an inverse quantization unit for obtaining a conversion coefficient by decoding in the processing unit, and an inverse orthogonal conversion unit for obtaining a predicted residual by inversely converting the conversion coefficient in a conversion unit smaller than the processing unit. ..

The decoding method of one aspect of the present disclosure is that the decoding apparatus decodes a bit stream encoded in a processing unit to be encoded in the processing unit to obtain a quantization conversion coefficient, and the quantum The conversion coefficient is decoded in the processing unit to obtain the conversion coefficient, and the conversion coefficient is inversely orthogonalized in a conversion unit smaller than the processing unit to obtain the predicted residual.

In one aspect of the present disclosure, a bit stream encoded in a processing unit to be encoded is decoded in the processing unit to obtain a quantization conversion coefficient, and the quantization conversion coefficient is reversed in the processing unit. The conversion coefficient is obtained by quantization, and the conversion coefficient is inversely orthogonalized in a conversion unit smaller than the processing unit to obtain the predicted residual.

It is a figure which shows the relationship between the processing unit of a block size 4 × 4 and a reference pixel. It is a figure explaining the coding which performs orthogonal conversion in the conversion unit of block size 4 × 4. It is a figure explaining the coding which performs orthogonal conversion in the conversion unit of block size 2 × 2. It is a figure explaining the coding which performs orthogonal conversion in the conversion unit of block size 4 × 2. It is a block diagram which shows the 1st configuration example of a coding apparatus. It is a figure explaining the flow of data. It is a block diagram which shows the 1st configuration example of a decoding apparatus. It is a flowchart explaining the 1st processing example of a coding process. It is a flowchart explaining the 1st process example of a decoding process. It is a block diagram which shows the 2nd structural example of a coding apparatus. It is a block diagram which shows the 2nd configuration example of a decoding apparatus. It is a flowchart explaining the 2nd processing example of the coding processing. It is a flowchart explaining the 2nd processing example of the decoding processing. It is a block diagram which shows the 3rd structural example of a coding apparatus. It is a flowchart explaining the 3rd processing example of the coding processing. It is a flowchart explaining the cost calculation process in a normal orthogonal conversion mode. It is a flowchart explaining the cost calculation process in a 2 × 2 orthogonal conversion mode. It is a flowchart explaining the 3rd processing example of the decoding processing. It is a flowchart explaining the 4th processing example of a coding process. It is a flowchart explaining the 4th processing example of the decoding processing. It is a figure explaining an example of the improvement method of the scan of the quantization conversion coefficient. It is a figure explaining another example of the improvement method of the scan of the quantization conversion coefficient. It is a block diagram which shows the structural example of one Embodiment of the computer to which this technique is applied.

Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

<Relationship between block size and image quality and coding efficiency>
The relationship between the block size, the image quality, and the coding efficiency will be described with reference to FIGS. 1 to 5.

For example, in the intra prediction, the pixels of the decoded image that has already been reconstructed are referred to. Then, the pixel of the processing unit that is the target of coding at the present time may also be referred to in the intra prediction when the coding is performed for the subsequent processing unit.

That is, as shown in FIG. 1, when intra-prediction is performed in a processing unit having a block size of 4 × 4, the pixels of the already reconstructed decoded image on the left and upper sides of the processing unit are used as reference pixels. .. Then, the pixels of the decoded image reconstructed with the block size of 4 × 4 may also be referred to in the intra prediction performed thereafter.

Also, conventionally, orthogonal conversion is performed with the same block size as the coding processing unit when performing intra prediction. Therefore, for example, when the coding is performed in the processing unit of the block size 4 × 4, the orthogonal conversion is performed in the conversion unit of the block size 4 × 4.

With reference to FIG. 2, coding for performing orthogonal conversion in a conversion unit having a block size of 4 × 4 will be described.

For example, of the pixels of the processing unit having a block size of 4 × 4 of the input image to be encoded, only one pixel (the pixel hatched in the input image shown in FIG. 2) has an extremely large value. Suppose there is an input called a signal.

Therefore, in the prediction residual, which is the difference between the input image and the intra prediction image, the value of one pixel becomes high in the form of an impulse because it is difficult to predict the impulse signal in the intra prediction. It ends up.

And, conventionally, orthogonal conversion is performed for such a predicted residual in a conversion unit of a block size of 4 × 4. For example, discrete cosine transform (DCT: Discrete Cosine Transform) and discrete sine transform (DST: Discrete Sine Transform) are mainly used as orthogonal transforms.

Here, when the predicted residual containing a high value in the impulse shape is orthogonally transformed by using the discrete cosine transform or the discrete sine transform, the influence of the impulse signal spreads over a wide range in the conversion coefficient obtained by the orthogonal transform. It is known. In the example shown in FIG. 2, as a case where the influence of the impulse signal spreads most widely, a state in which the influence of the impulse signal spreads over the entire processing unit having a block size of 4 × 4 is shown. Normally, the orthogonal conversion is performed for the purpose of concentrating the signal at a specific position such as the upper left after the orthogonal conversion, and the impulse signal affects a wide range over the entire processing unit of the block size 4 × 4. Is not preferable.

After that, in the quantization conversion coefficient obtained by performing quantization on the conversion coefficient, a quantization error occurs by quantizing each pixel, so that the quantization error occurs in the entire processing unit having a block size of 4 × 4. Will spread. At this time, if the signals are concentrated at a specific position such as the upper left after orthogonal conversion, it can be expected that other signals can be reduced, so that the quantization error can be reduced after quantization, whereas the block size is 4 × 4. When the quantization error spreads over the entire processing unit, the advantage of reducing the quantization error cannot be obtained.

Then, in the coding for the quantization conversion coefficient, the quantization conversion coefficient is generally scanned in a scan order called a zigzag scan indicated by an arrow as shown in the figure. At this time, since the quantization error spreads over the entire processing unit having a block size of 4 × 4, many hatched quantization conversion coefficients are encoded. Therefore, for the purpose of compressing the moving image, the amount of code is large here, resulting in inefficient signal transmission. On the other hand, for example, in a state where the signal is concentrated at a specific position such as the upper left after orthogonal conversion as described above, many coefficients become 0 and the code amount of 0 is small, so that the coding is efficient. Can be done.

In addition, the inverse quantization of the quantized predicted residual is performed, and the inverse quantized conversion coefficient is obtained.

Furthermore, by performing inverse orthogonal transformation on the inverse quantized conversion coefficient, the predicted residual that has been inversely orthogonally transformed can be obtained. At this time, in the predicted residual that has been inversely orthogonally converted, the quantization error is widened so that the surrounding values gradually increase around the pixel containing the impulse signal.

Then, the input image is decoded by adding the inverse orthogonally converted predicted residual and the intra-predicted image, and the reconstructed decoded image is acquired. Therefore, in the reconstructed decoded image, the impulse signal included in the input image is gradually spread around the pixel as the center, and the reproducibility of the image is deteriorated.

That is, when the orthogonal conversion is performed in the conversion unit of the block size 4 × 4, the influence of the impulse signal included in the input image spreads over the entire processing unit of the block size 4 × 4, and the image quality of the decoded image is improved. It will get worse. For example, a signal quality index called Peak signal-to-noise ratio (PSNR) has also been shown to deteriorate the signal quality.

In this way, for example, when the input image contains an impulse signal, the effect of energy concentration expected for orthogonal conversion cannot be obtained, and conversely, the energy is diffused. Therefore, not only the image quality is deteriorated as described above, but also the amount of information of the level signal that must be input to the bit stream is increased, so that there is a concern that the coding efficiency is lowered.

Therefore, as described with reference to FIGS. 3 and 4, by making the conversion unit for performing orthogonal conversion smaller than the processing unit for encoding, for example, the spread of the influence of the impulse signal is suppressed, and the image quality and image quality are improved. It is expected that the decrease in coding efficiency can be suppressed.

With reference to FIG. 3, coding for performing orthogonal conversion in a conversion unit having a block size of 2 × 2 will be described.

Similar to the example shown in FIG. 2, the block size 4 × 4 is used as a coding processing unit, and the value of one pixel is converted into an impulse from an input image containing an impulse signal having an extremely large value in only one pixel. A higher predicted residual is obtained.

Then, for such a predicted residual, the processing unit for encoding the block size 4 × 4 is divided, and the orthogonal conversion is performed in the conversion unit having the block size 2 × 2. In this case, the influence of the impulse signal only spreads within the conversion unit of the lower right block size 2 × 2 including the impulse signal. As described above, the diffusion of the influence of the impulse signal on the predicted residual is suppressed to a narrow range as compared with the example of FIG.

After that, the conversion coefficient is quantized in processing units of block size 4 × 4, and even in the quantization conversion coefficient obtained by this quantization, the quantization error is the block size 2 × 2 at the lower right. It will occur within the range.

Then, in the coding for the quantization conversion coefficient, the quantization conversion coefficient is scanned in the same scan order as the example shown in FIG. At this time, since there are quantization conversion coefficients only in the four block sizes 2 × 2 at the lower right, there are cases where all of the block sizes 4 × 4 have quantization conversion coefficients as shown in the example shown in FIG. By comparison, the amount of code that must be transmitted can be reduced. That is, since the code amount can be small, high efficiency can be achieved for the purpose of compressing the moving image.

Furthermore, by performing inverse orthogonal transformation on the inverse quantized conversion coefficient, the predicted residual that has been inversely orthogonally transformed can be obtained. At this time, since the orthogonal conversion is performed in the conversion unit of the block size 2 × 2, the quantization error is suppressed to the range of the block size 2 × 2 at the lower right in the predicted residual obtained by the inverse orthogonal conversion. ..

Then, by adding the predicted residuals that have been inversely orthogonally converted and the intra-predicted image, the input image is decoded and the reconstructed decoded image is acquired. Therefore, in the reconstructed decoded image, the influence of the impulse signal included in the input image is limited to the block size 2 × 2 in the lower right, and the decoded image is compared with the example of FIG. The image quality can be improved. For example, a signal quality index called Peak signal-to-noise ratio (PSNR) has also been shown to improve signal quality.

With reference to FIG. 4, coding for performing orthogonal conversion in a conversion unit having a block size of 4 × 2 will be described.

As shown in FIG. 4, even when the orthogonal conversion is performed in the conversion unit of the block size 4 × 2, the block size is the same as the case where the orthogonal conversion is performed in the conversion unit of the block size 2 × 2 (see FIG. 3). Compared with the case where orthogonal conversion (see FIG. 2) is performed in 4 × 4 conversion units, it is possible to suppress the spread of the influence of the impulse signal included in the input image. That is, by performing orthogonal conversion in conversion units having a block size of 4 × 2, it is possible to suppress deterioration in image quality and coding efficiency.

As described with reference to FIGS. 3 and 4, when encoding is performed in a processing unit having a block size of 4 × 4, it is orthogonal to a conversion unit having a smaller block size of 2 × 2 or a block size of 4 × 2. By performing the conversion, it is possible to suppress the spread of the influence of the impulse signal included in the input image.

Therefore, in the coding and decoding of the present embodiment, the input image including the impulse signal is subjected to orthogonal conversion by performing orthogonal conversion in a conversion unit having a block size smaller than the processing unit to be processed for coding and decoding. However, deterioration of image quality and coding efficiency is avoided. At this time, in the coding and decoding of the present embodiment, as described later, a decrease in processing speed is avoided as compared with a method in which the processing unit itself to be processed for coding and decoding is made into a small block size. can do.

<First Configuration Example of Encoding Device and Decoding Device>
FIG. 5 is a block diagram showing a configuration example of a first embodiment of a coding apparatus to which the present technology is applied.

As shown in FIG. 5, the coding apparatus 11 includes a calculation unit 21, an orthogonal conversion unit 22, a quantization unit 23, an inverse quantization unit 24, an inverse orthogonal conversion unit 25, a calculation unit 26, a frame memory 27, and a prediction unit 28. , And a coding unit 29.

The calculation unit 21 sequentially targets the pictures that are the moving images of the input frame unit as the coding target, and acquires the pixels according to the coding processing unit from the coding target picture as the input image of the coding target. For example, in the first embodiment, the calculation unit 21 acquires pixels of a processing unit having a block size of 4 × 4 as an input image to be encoded. Then, the calculation unit 21 supplies the orthogonal conversion unit 22 with the prediction residual obtained by subtracting the intra prediction image supplied from the prediction unit 28 from the input image.

The orthogonal conversion unit 22 performs orthogonal conversion processing on the predicted residual supplied from the calculation unit 21, derives the conversion coefficient, and supplies it to the quantization unit 23. At this time, as described above with reference to FIG. 3, the orthogonal conversion unit 22 divides the processing unit of the block size 4 × 4 into four, and performs the orthogonal conversion four times in the conversion unit of the block size 2 × 2. .. Alternatively, as described above with reference to FIG. 4, the orthogonal conversion unit 22 divides the processing unit of the block size 4 × 4 into two, and performs the orthogonal conversion twice in the conversion unit of the block size 4 × 2.

The quantization unit 23 performs quantization with respect to the conversion coefficient supplied from the orthogonal conversion unit 22, derives the quantization conversion coefficient in a processing unit of block size 4 × 4, and causes the inverse quantization unit 24 and the coding unit 29 to derive the quantization conversion coefficient. Supply.

The inverse quantization unit 24 performs inverse quantization with respect to the quantization conversion coefficient supplied from the quantization unit 23, that is, reverses the quantization by the quantization unit 23, and in a processing unit of block size 4 × 4. The inverse quantized conversion coefficient is derived and supplied to the inverse orthogonal conversion unit 25.

The inverse orthogonal conversion unit 25 performs inverse orthogonal conversion on the inverse quantized conversion coefficient supplied from the inverse quantization unit 24, that is, reverses the orthogonal conversion process by the orthogonal conversion unit 22, and performs inverse orthogonal conversion. The prediction error is derived and supplied to the calculation unit 26. At this time, the inverse orthogonal conversion unit 25 divides the processing unit of the block size 4 × 4 into four, and performs the inverse orthogonal conversion four times in the conversion unit of the block size 2 × 2, similarly to the orthogonal conversion unit 22. Alternatively, the inverse orthogonal conversion unit 25 divides the processing unit of the block size 4 × 4 into two, and performs the inverse orthogonal conversion twice in the conversion unit of the block size 4 × 2, similarly to the orthogonal conversion unit 22.

The calculation unit 26 decodes a processing unit having a block size of 4 × 4 by adding the inverse orthogonally converted prediction error supplied from the inverse orthogonal conversion unit 25 and the intra prediction image supplied from the prediction unit 28. The image is reconstructed and supplied to the frame memory 27.

The frame memory 27 stores the decoded image of the processing unit of the block size 4 × 4 supplied from the calculation unit 26 in the buffer. Then, the frame memory 27 reads the pixel designated by the prediction unit 28 from the buffer and supplies it to the prediction unit 28 as a reference pixel.

The prediction unit 28 acquires reference pixels (see FIG. 1) referred to in the intra prediction when encoding the input image to be encoded from the frame memory 27, and uses those reference pixels to block size 4 Intra-prediction is performed in x4 processing units. As a result, the prediction unit 28 generates an intra prediction image and supplies it to the calculation unit 21 and the calculation unit 26.

The coding unit 29 encodes the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the quantization unit 23 according to a predetermined coding method, and outputs a bit stream obtained by the coding.

The coding device 11 is configured in this way, and the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25 perform orthogonal conversion and inverse orthogonal conversion in a conversion unit having a block size smaller than the coding processing unit. As a result, as described above with reference to FIGS. 3 and 4, the coding apparatus 11 can suppress the spread of the influence of the impulse signal even if it is included in the input image, and the image quality and coding can be suppressed. The decrease in efficiency can be suppressed.

Here, in the coding apparatus 11, when performing coding using intra-prediction, as shown by the arrow of the broken line in FIG. 5, it is necessary to perform processing such that data loops for each coding processing unit. .. That is, the coding device 11 starts from the previous block in the order of the calculation unit 21, the orthogonal conversion unit 22, the quantization unit 23, the inverse quantization unit 24, the inverse orthogonal conversion unit 25, the calculation unit 26, and the prediction unit 28. It is configured to use the output data to make the next intra-prediction.

Therefore, in the coding apparatus 11, if the coding processing unit itself is reduced, the processing speed for performing the coding processing will decrease. That is, when the coding processing unit is a block size of 2 × 2, the processing speed is simply reduced to 1/4 as compared with the case where the coding processing unit is a block size of 4 × 4. Is assumed. Therefore, it is considered to set the block size to 4 × 4 as the minimum size of the coding processing unit.

Therefore, in the coding apparatus 11, the coding processing unit is a block size of 4 × 4, and the conversion unit of the orthogonal conversion and the inverse orthogonal conversion is a block size of 2 × 2, thereby avoiding such a decrease in processing speed. can do.

That is, as shown in A of FIG. 6, conventionally, orthogonal conversion and inverse orthogonal conversion have been performed with a block size of 4 × 4, which is a coding processing unit. On the other hand, in the coding apparatus 11, as shown in B of FIG. 6, the coding processing unit remains the block size 4 × 4, and the orthogonal conversion and the inverse orthogonal conversion are performed with a smaller block size of 2 × 2. I do. Alternatively, as shown in C of FIG. 6, the coding apparatus 11 performs orthogonal conversion and inverse orthogonal conversion with a block size of 4 × 2, which is smaller than the block size of 4 × 4, while the coding processing unit remains the same. ..

Therefore, the coding apparatus 11 aims to improve the image quality and coding efficiency while avoiding a decrease in processing speed as compared with the case where orthogonal conversion and inverse orthogonal conversion are performed with a block size of 4 × 4, which is a coding processing unit. be able to.

FIG. 7 is a block diagram showing a configuration example of the first embodiment of the decoding device to which the present technology is applied.

As shown in FIG. 7, the decoding device 12 includes a decoding unit 41, an inverse quantization unit 42, an inverse orthogonal conversion unit 43, a calculation unit 44, a frame memory 45, and a prediction unit 46.

The decoding unit 41 acquires the bit stream output from the coding device 11 and performs decoding according to the decoding method corresponding to the coding method used by the coding unit 29, thereby following the decoding processing unit. The quantization conversion coefficient is acquired and supplied to the inverse quantization unit 42. For example, in the first embodiment, the decoding unit 41 acquires the quantization conversion coefficient of the processing unit having a block size of 4 × 4 and supplies it to the inverse quantization unit 42.

The inverse quantization unit 42 performs inverse quantization on the quantization conversion coefficient supplied from the decoding unit 41, derives the inverse quantization conversion coefficient in the processing unit of the block size 4 × 4, and the inverse orthogonal conversion unit 43. Supply to. That is, the dequantization unit 42 performs the same processing as the dequantization unit 24 of FIG.

The inverse orthogonal conversion unit 43 performs inverse orthogonal conversion on the inverse quantized conversion coefficient supplied from the inverse quantization unit 42, derives the inverse orthogonal conversion prediction error, and supplies it to the calculation unit 44. That is, the inverse orthogonal conversion unit 43 performs the same processing as the inverse orthogonal conversion unit 25 of FIG. Therefore, the inverse orthogonal conversion unit 43 divides the processing unit of the block size 4 × 4 into four, and performs the inverse orthogonal conversion four times in the conversion unit of the block size 2 × 2. Alternatively, the inverse orthogonal conversion unit 43 divides the processing unit of the block size 4 × 4 into two, and performs the inverse orthogonal conversion twice in the conversion unit of the block size 4 × 2.

The calculation unit 44 adds the inverse orthogonally converted prediction error supplied from the inverse orthogonality conversion unit 43 and the intra-orthogonal prediction image supplied from the prediction unit 46 to obtain a decoded image of a processing unit having a block size of 4 × 4. Is calculated. Then, the calculation unit 44 outputs the calculated decoded image as an output image output from the decoding device 12 and supplies it to the frame memory 27.

The frame memory 45 stores the decoded image of the processing unit of the block size 4 × 4 supplied from the arithmetic unit 44 in the buffer. Then, the frame memory 45 reads the pixel designated by the prediction unit 46 from the buffer and supplies it to the prediction unit 46 as a reference pixel.

The prediction unit 46 acquires reference pixels (see FIG. 1) referred to in the intra prediction when decoding a processing unit having a block size of 4 × 4 to be decoded from the frame memory 45, and uses those reference pixels. Intra-prediction is performed in processing units with a block size of 4 × 4. That is, the prediction unit 46 performs the same processing as the prediction unit 28 in FIG. 5, generates an intra prediction image, and supplies it to the calculation unit 44.

The decoding device 12 is configured in this way, and the inverse orthogonal conversion unit 43 performs inverse orthogonal conversion in a conversion unit having a block size smaller than the decoding processing unit.

Then, in the decoding device 12, similarly to the coding device 11, when decoding using the intra prediction, the data loops for each decoding processing unit as shown by the broken line arrow in FIG. 7. Processing is required. At that time, the decoding device 12 can avoid a decrease in processing speed as compared with the case where the inverse orthogonal conversion is performed with a block size of 4 × 4, which is a decoding processing unit.

<First processing example of coding processing and decoding processing>
A first processing example of the coding processing performed in the coding apparatus 11 will be described with reference to the flowchart shown in FIG.

In step S11, the prediction unit 28 acquires reference pixels referenced in a processing unit having a block size of 4 × 4 to be encoded from the frame memory 27, and performs intra prediction using those reference pixels. As a result, the prediction unit 28 generates an intra prediction image of a processing unit having a block size of 4 × 4 and supplies it to the calculation unit 21 and the calculation unit 26.

In step S12, the calculation unit 21 acquires pixels of a processing unit having a block size of 4 × 4 as an input image to be encoded. Then, the calculation unit 21 subtracts the intra prediction image supplied from the prediction unit 28 in step S11 from the input image, and obtains the prediction residual of the processing unit of the block size 4 × 4 obtained by the calculation unit 21 in the orthogonal conversion unit 22. Supply to.

In step S13, the orthogonal conversion unit 22 divides the predicted residual of the processing unit of the block size 4 × 4 supplied from the calculation unit 21 in step S12 into the conversion unit of the block size 2 × 2. Then, the orthogonal conversion unit 22 performs orthogonal conversion for each conversion unit having a block size of 2 × 2 to derive a conversion coefficient. At this time, the orthogonal conversion unit 22 acquires the conversion coefficient of the processing unit of the block size 4 × 4 by performing the orthogonal conversion for each conversion unit of the block size 2 × 2 four times, and supplies the conversion coefficient to the quantization unit 23. ..

In step S14, the quantization unit 23 performs quantization with respect to the conversion coefficient of the processing unit of the block size 4 × 4 supplied from the orthogonal conversion unit 22 in step S13, derives the quantization conversion coefficient, and dequantizes the inverse quantization unit. It is supplied to 24 and the coding unit 29.

In step S15, the inverse quantization unit 24 performs inverse quantization with respect to the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the quantization unit 23 in step S14, and the inverse quantization conversion coefficient is obtained. It is derived and supplied to the inverse orthogonal conversion unit 25.

In step S16, the inverse orthogonal conversion unit 25 divides the conversion coefficient of the processing unit of the block size 4 × 4 supplied from the inverse quantization unit 24 in step S15 into the conversion unit of the block size 2 × 2. Then, the inverse orthogonal conversion unit 25 performs inverse orthogonal conversion for each conversion unit having a block size of 2 × 2 to derive a prediction error. At this time, the inverse orthogonal conversion unit 25 acquires the inverse orthogonal conversion prediction error of the processing unit of the block size 4 × 4 by performing the inverse orthogonal conversion for each conversion unit of the block size 2 × 2 four times. It is supplied to the calculation unit 26.

In step S17, the calculation unit 26 includes the inverse orthogonal conversion prediction error of the processing unit of the block size 4 × 4 supplied from the inverse orthogonal conversion unit 25 in step S16 and the block supplied from the prediction unit 28 in step S11. Add the intra-predicted image of the processing unit of size 4 × 4. As a result, the calculation unit 26 reconstructs the decoded image of the processing unit having a block size of 4 × 4 and supplies it to the frame memory 27.

In step S18, the frame memory 27 stores and stores the decoded image of the processing unit of the block size 4 × 4 supplied from the calculation unit 26 in step S17 in the buffer.

In step S19, the coding unit 29 encodes the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the quantization unit 23 in step S14 according to a predetermined coding method. Then, the processing is terminated after the coding unit 29 outputs the bit stream obtained by the coding, and the same processing is subsequently performed with the next input image as the coding target.

A first processing example of the decoding process performed in the decoding device 12 will be described with reference to the flowchart shown in FIG.

In step S21, the decoding unit 41 acquires the bit stream output from the encoding device 11. Then, the decoding unit 41 performs decoding according to the decoding method corresponding to the coding method used by the coding unit 29 in step S19 of FIG. 8, thereby performing the quantization conversion coefficient of the processing unit of the block size 4 × 4. Is obtained and supplied to the inverse quantization unit 42.

In step S22, the inverse quantization unit 42 performs inverse quantization with respect to the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the decoding unit 41 in step S21, and derives the inverse quantization conversion coefficient. Then, it is supplied to the inverse orthogonal conversion unit 43.

In step S23, the inverse orthogonal conversion unit 43 divides the conversion coefficient of the processing unit of the block size 4 × 4 supplied from the inverse quantization unit 42 in step S22 into the conversion unit of the block size 2 × 2. Then, the inverse orthogonal conversion unit 43 performs inverse orthogonal conversion for each conversion unit having a block size of 2 × 2 to derive a prediction error. At this time, the inverse orthogonal conversion unit 43 acquires the inverse orthogonal conversion prediction error of the processing unit of the block size 4 × 4 by performing the inverse orthogonal conversion for each conversion unit of the block size 2 × 2 four times. It is supplied to the calculation unit 44.

In step S24, the prediction unit 46 acquires reference pixels (see FIG. 1) referred to in the intra prediction when decoding a processing unit having a block size of 4 × 4 to be decoded from the frame memory 45, and obtains them. Intra-prediction is performed in processing units of block size 4 × 4 using reference pixels. Then, the prediction unit 46 generates an intra prediction image of a processing unit having a block size of 4 × 4 and supplies it to the calculation unit 44.

In step S25, the calculation unit 44 includes the inverse orthogonal conversion prediction error of the processing unit of the block size 4 × 4 supplied from the inverse orthogonal conversion unit 43 in step S23 and the intra-orthogonal conversion supplied from the prediction unit 46 in step S24. Add with the predicted image. As a result, the calculation unit 44 reconstructs the decoded image of the processing unit having a block size of 4 × 4, outputs the decoded image as an output image output from the decoding device 12, and supplies the decoded image to the frame memory 27.

In step S26, the frame memory 45 stores and stores the decoded image of the processing unit of the block size 4 × 4 supplied from the calculation unit 44 in step S25 in the buffer. After that, the processing is terminated, then the bit stream to be coded is acquired, and the same processing is performed thereafter.

As described above, when the coding device 11 and the decoding device 12 perform coding and decoding in a processing unit having a block size of 4 × 4, they are opposite to the orthogonal conversion in a conversion unit having a block size of 2 × 2 which is smaller than that. By performing the orthogonal conversion, it is possible to improve the image quality and the coding efficiency while avoiding the decrease in the processing speed.

<Second configuration example of encoding device and decoding device>
FIG. 10 is a block diagram showing a configuration example of a second embodiment of a coding apparatus to which the present technology is applied. The detailed description of the configuration common to the coding device 11 of FIG. 5 in the coding device 11A shown in FIG. 10 will be omitted.

That is, as shown in FIG. 10, the coding device 11A includes a calculation unit 21, an orthogonal conversion unit 22, a quantization unit 23, an inverse quantization unit 24, an inverse orthogonal conversion unit 25, a calculation unit 26, a frame memory 27, and a prediction. It has the same configuration as the coding device 11 of FIG. 5 in that it includes a unit 28 and a coding unit 29. The coding device 11A has a configuration different from that of the coding device 11 of FIG. 5 in that it includes a control unit 30. In FIG. 10, the arrow indicating the control from the control unit 30 to the blocks other than the orthogonal conversion unit 22 is not shown.

The control unit 30 determines whether or not the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, and if it is determined that the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, the orthogonal conversion unit 22 and the inverse orthogonal conversion are performed. A conversion unit having a block size of 2 × 2 is set for the unit 25. Further, in this case, the control unit 30 controls all the blocks of the coding device 11A so as to execute the coding in the 2 × 2 orthogonal conversion mode. That is, in this case, the same processing as the flowchart of FIG. 8 described above is performed, and the mode in which such processing is performed is hereinafter referred to as a 2 × 2 orthogonal conversion mode.

For example, the conditions for performing the 2x2 orthogonal conversion mode are that the coding processing unit is a block size of 4x4, intra-prediction is used, and a specific intra-prediction mode (for example, DC prediction or planar prediction). Etc.) is set. Therefore, the control unit 30 performs a 2 × 2 orthogonal conversion mode when the coding processing unit is a block size of 4 × 4, an intra prediction is used, or a specific intra prediction mode is used. It can be determined that the conditions are satisfied.

Alternatively, these conditions may be used in combination. For example, assuming that the coding processing unit is a block size of 4 × 4, intra-prediction is used, and a specific intra-prediction mode is satisfied, the condition for performing the 2 × 2 orthogonal conversion mode is satisfied. May be good.

When the control unit 30 determines that the condition for performing the 2 × 2 orthogonal conversion mode is not satisfied, the control unit 30 sets the same conversion unit as the coding processing unit for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25. To do. That is, in this case, a mode in which coding by orthogonal conversion similar to the conventional one is performed and such processing is performed is usually referred to as an orthogonal conversion mode.

FIG. 11 is a block diagram showing a configuration example of a second embodiment of the decoding device to which the present technology is applied. The details of the configuration of the decoding device 12A shown in FIG. 11 that is common to the decoding device 12 of FIG. 7 will be omitted.

That is, as shown in FIG. 11, the decoding device 12A includes a decoding unit 41, an inverse quantization unit 42, an inverse orthogonal conversion unit 43, a calculation unit 44, a frame memory 45, and a prediction unit 46. It has the same configuration as the decoding device 12. The decoding device 12A has a configuration different from that of the decoding device 12 of FIG. 7 in that it includes a control unit 47.

The control unit 47 determines whether or not the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, as in the control unit 30 of FIG. Then, when the control unit 47 determines that the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, the control unit 47 sets a conversion unit having a block size of 2 × 2 for the inverse orthogonal conversion unit 43, and 2 × 2 Control is performed on all blocks of the decoding device 12A so that decoding is performed in the orthogonal conversion mode. On the other hand, when the control unit 47 determines that the condition for performing the 2 × 2 orthogonal conversion mode is not satisfied, the control unit 47 sets the same conversion unit as the decoding processing unit for the inverse orthogonal conversion unit 43, and is normally orthogonal. Control is performed on all blocks of the decoding device 12A so that decoding is executed in the conversion mode.

As described above, the coding device 11A and the decoding device 12A are configured, and the 2 × 2 orthogonal conversion mode and the normal orthogonal conversion mode can be switched and used according to the conditions for performing the 2 × 2 orthogonal conversion mode. As a result, for example, it becomes possible to meet the processing in which it is desirable to perform the orthogonal conversion in the processing unit of the block size 4 × 4.

<Second processing example of coding processing and decoding processing>
A second processing example of the coding processing performed in the coding apparatus 11A will be described with reference to the flowchart shown in FIG.

In step S31, the control unit 30 determines whether or not the condition for performing the 2 × 2 orthogonal conversion mode as described above is satisfied.

If the control unit 30 determines in step S31 that the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, the process proceeds to step S32. In step S32, the control unit 30 sets a conversion unit having a block size of 2 × 2 for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes the unit so as to execute coding in the 2 × 2 orthogonal conversion mode. Controls all blocks of device 11A. As a result, the same processing as the flowchart of FIG. 8 is performed, and then the processing is terminated.

On the other hand, if the control unit 30 determines in step S31 that the condition for performing the 2 × 2 orthogonal conversion mode is not satisfied, the process proceeds to step S33. In step S33, the control unit 30 sets the same conversion unit as the coding processing unit for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes so as to execute the coding in the normal orthogonal conversion mode. Control is performed for all blocks of the device 11A. As a result, in steps S13 and S16 of the flowchart of FIG. 8, coding is performed in which the orthogonal conversion and the inverse orthogonal conversion are performed once in the same conversion unit as the processing unit, and then the processing is terminated.

A second processing example of the decoding process performed in the decoding device 12A will be described with reference to the flowchart shown in FIG.

In step S41, the control unit 47 determines whether or not the condition for performing the 2 × 2 orthogonal conversion mode as described above is satisfied.

If the control unit 47 determines in step S41 that the condition for performing the 2 × 2 orthogonal conversion mode is satisfied, the process proceeds to step S42. In step S42, the control unit 47 sets a conversion unit having a block size of 2 × 2 for the inverse orthogonal conversion unit 43, and performs decoding for all the blocks of the decoding device 12A so as to execute decoding in the 2 × 2 orthogonal conversion mode. Take control. As a result, the same processing as the flowchart of FIG. 9 is performed, and then the processing is terminated.

On the other hand, if the control unit 47 determines in step S41 that the condition for performing the 2 × 2 orthogonal conversion mode is not satisfied, the process proceeds to step S43. In step S43, the control unit 47 sets the same conversion unit as the decoding processing unit for the inverse orthogonal conversion unit 43, and controls all the blocks of the decoding device 12A so as to execute the decoding in the normal orthogonal conversion mode. I do. As a result, in step S23 of the flowchart of FIG. 9, decoding is executed in which the inverse orthogonal conversion is performed once in the same conversion unit as the processing unit, and then the processing is terminated.

As described above, the coding device 11A and the decoding device 12A can be used by switching between the 2 × 2 orthogonal conversion mode and the normal orthogonal conversion mode according to the conditions for performing the 2 × 2 orthogonal conversion mode. Note that, for example, the coding device 11A may put a 2 × 2 orthogonal conversion flag indicating the result of determination according to the condition of performing the 2 × 2 orthogonal conversion mode into the bit stream and transmit the result. In this case, the decoding device 12A can switch between the 2 × 2 orthogonal conversion mode and the normal orthogonal conversion mode based on the 2 × 2 orthogonal conversion flag.

<Third configuration example of encoding device and decoding device>
FIG. 14 is a block diagram showing a configuration example of a third embodiment of a coding device to which the present technology is applied. The detailed description of the configuration common to the coding device 11 of FIG. 5 in the coding device 11B shown in FIG. 14 will be omitted. In FIG. 14, the arrow indicating the control from the control unit 30 to the blocks other than the orthogonal conversion unit 22 is not shown.

That is, as shown in FIG. 14, the coding device 11B includes a calculation unit 21, an orthogonal conversion unit 22, a quantization unit 23, an inverse quantization unit 24, an inverse orthogonal conversion unit 25, a calculation unit 26, a frame memory 27, and a prediction. It has the same configuration as the coding device 11 of FIG. 5 in that it includes a unit 28 and a coding unit 29. The coding device 11B has a configuration different from that of the coding device 11 of FIG. 5 in that it includes a control unit 30 and a work amount calculation unit 31.

The control unit 30 determines the magnitude relationship between the two types of costs (RD cost J1 and RD cost J2, which will be described later) supplied from the work amount calculation unit 31, and is out of the 2 × 2 orthogonal conversion mode and the normal orthogonal conversion mode. Control is performed so that the one with the lower cost is selected.

Then, when the 2x2 orthogonal conversion mode is selected, the control unit 30 sets a 2x2 orthogonal conversion flag (tu_2x2_flag = 1) indicating that the 2x2 orthogonal conversion is performed, and puts the control unit 30 into the bit stream. Control is performed on the coding unit 29 so as to transmit. Further, the control unit 30 sets a conversion unit having a block size of 2 × 2 for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and the coding device 11B so as to execute coding in the 2 × 2 orthogonal conversion mode. Controls all blocks of. For example, this 2 × 2 orthogonal conversion flag (tu_2x2_flag) is described in the fourth line from the bottom of “7.3.4.6 Coding unit syntax” of Non-Patent Document 1 described above, “transform_tree (x0, y0, cbWidth, cbHeight) , TreeType) ”, it is preferable to place it immediately before.

On the other hand, when the normal orthogonal conversion mode is selected, the control unit 30 sets a 2x2 orthogonal conversion flag (tu_2x2_flag = 0) indicating that the 2x2 orthogonal conversion is not performed, puts it in a bit stream, and transmits it. The coding unit 29 is controlled so as to be performed. Further, the control unit 30 sets the same conversion unit as the coding processing unit for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and the coding device 11B so as to execute the coding in the normal orthogonal conversion mode. Controls all blocks of.

The work amount calculation unit 31 calculates the RD cost J1 normally required when the orthogonal conversion mode is performed and the RD cost J2 required when the 2 × 2 orthogonal conversion mode is performed, and the control unit 30 Supply to. The process of calculating the RD cost J1 by the work amount calculation unit 31 will be described later with reference to the flowchart of FIG. 16, and the process of calculating the RD cost J2 will be described later with reference to the flowchart of FIG. ..

On the other hand, the coding side has the same configuration as the decoding device 12A shown in FIG. That is, in the decoding device 12A, the decoding unit 41 acquires the 2 × 2 orthogonal conversion flag from the bit stream and supplies it to the control unit 47. Then, the control unit 47 performs control such as selecting either the 2 × 2 orthogonal conversion mode or the normal orthogonal conversion mode according to the 2 × 2 orthogonal conversion flag.

As described above, in the coding device 11B, when the control unit 30 determines that the RD cost J2 is smaller than the RD cost J1 (J2 <J1), the 2 × 2 orthogonal conversion mode is selected, and the RD cost J2 is set. When it is determined that the RD cost is J1 or more (J2 ≧ J1), the orthogonal conversion mode is usually selected.

Therefore, the coding device 11B can perform coding by orthogonal conversion so as to reduce the cost. Then, the coding device 11B can transmit the selection to the decoding device 12A by the 2 × 2 orthogonal conversion flag, and the decoding device 12A can also perform the decoding by the orthogonal conversion so as to reduce the cost. it can.

<Third processing example of coding processing and decoding processing>
A third processing example of the coding processing performed in the coding apparatus 11B will be described with reference to the flowchart shown in FIG.

In step S51, the work amount calculation unit 31 performs cost calculation processing in the normal orthogonal conversion mode (see the flowchart of FIG. 16) to calculate and control the RD cost J1 required when the normal orthogonal conversion mode is performed. Notify department 30.

In step S52, the work amount calculation unit 31 performs the cost calculation process in the 2 × 2 orthogonal conversion mode (see the flowchart of FIG. 17), and determines the RD cost J2 required when the 2 × 2 orthogonal conversion mode is performed. Calculate and notify the control unit 30.

In step S53, the control unit 30 compares the RD cost J1 in the normal orthogonal conversion mode with the RD cost J2 in the 2 × 2 orthogonal conversion mode, and determines whether the RD cost J2 is smaller than the RD cost J1.

If the control unit 30 determines in step S53 that the RD cost J2 is smaller than the RD cost J1 (J2 <J1), the process proceeds to step S54.

In step S54, the control unit 30 sets a 2 × 2 orthogonal conversion flag (tu_2x2_flag = 1) indicating that the 2 × 2 orthogonal conversion is performed, and controls the coding unit 29 so as to put it in the bit stream and transmit it. Do. In response to this, the encoding unit 29 puts a 2 × 2 orthogonal conversion flag indicating that the 2 × 2 orthogonal conversion is performed into the bit stream and transmits the bit stream.

In step S55, the control unit 30 sets a conversion unit having a block size of 2 × 2 for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes the unit so as to execute coding in the 2 × 2 orthogonal conversion mode. Controls all blocks of device 11B. As a result, the same processing as the flowchart of FIG. 8 is performed, and then the processing is terminated.

On the other hand, in step S53, when the control unit 30 determines that the RD cost J2 is not smaller than the RD cost J1, that is, when the RD cost J2 is determined to be RD cost J1 or more (J2 ≧ J1), the processing is performed. The process proceeds to step S56.

In step S56, the control unit 30 sets a 2 × 2 quadrature conversion flag (tu_2x2_flag = 0) indicating that the 2 × 2 quadrature conversion is not performed, and controls the coding unit 29 so as to put it in the bit stream and transmit it. I do. In response to this, the encoding unit 29 puts a 2 × 2 orthogonal conversion flag indicating that the 2 × 2 orthogonal conversion is not performed into the bit stream and transmits the bit stream.

In step S57, the control unit 30 sets the same conversion unit as the coding processing unit for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes so as to execute the coding in the normal orthogonal conversion mode. Controls all blocks of device 11B. As a result, in steps S13 and S16 of the flowchart of FIG. 8, coding is performed in which the orthogonal conversion and the inverse orthogonal conversion are performed once in the same conversion unit as the processing unit, and then the processing is terminated.

FIG. 16 is a flowchart illustrating the cost calculation process in the normal orthogonal conversion mode performed in step S51 of FIG.

In steps S61 to S64, the same processing as in steps S11 to S14 of FIG. 8 is performed. In step S63, orthogonal conversion is performed in processing units having a block size of 4 × 4. Then, in step S65, the coding unit 29 encodes the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the quantization unit 23 in step S64 according to a predetermined coding method to calculate the workload. It is supplied to the unit 31, and the work amount calculation unit 31 calculates the code amount R1.

In steps S66 to S68, the same processing as in steps S15 to S17 of FIG. 8 is performed, and the decoded image of the processing unit of the block size 4 × 4 calculated by the calculation unit 26 in step S68 is supplied to the work amount calculation unit 31. To. In step S67, inverse orthogonal conversion is performed in processing units having a block size of 4 × 4. Then, in step S69, the work amount calculation unit 31 calculates the square error D1 from the decoded image of the processing unit of the block size 4 × 4 supplied in step S68.

In step S70, the work amount calculation unit 31 calculates and obtains the RD cost J1 in the normal orthogonal conversion mode based on the code amount R1 calculated in step S65 and the square error D1 calculated in step S69, and then obtains the result. The process is terminated.

FIG. 17 is a flowchart illustrating the cost calculation process in the 2 × 2 orthogonal conversion mode performed in step S52 of FIG.

In steps S81 to S84, the same processing as in steps S11 to S14 of FIG. 8 is performed. Then, in step S85, the coding unit 29 encodes the quantization conversion coefficient of the processing unit of the block size 4 × 4 supplied from the quantization unit 23 in step S84 according to a predetermined coding method to calculate the workload. It is supplied to the unit 31, and the work amount calculation unit 31 calculates the code amount R2.

In steps S86 to S88, the same processing as in steps S15 to S17 of FIG. 8 is performed, and the decoded image of the processing unit of the block size 4 × 4 calculated by the calculation unit 26 in step S88 is supplied to the work amount calculation unit 31. To. Then, in step S89, the work amount calculation unit 31 calculates the square error D2 from the decoded image of the processing unit of the block size 4 × 4 supplied in step S88.

In step S90, the work amount calculation unit 31 calculates and obtains the RD cost J2 in the 2 × 2 orthogonal conversion mode based on the code amount R2 calculated in step S85 and the squared error D2 calculated in step S89. After that, the process is finished.

A third processing example of the decoding process performed in the decoding device 12A will be described with reference to the flowchart shown in FIG.

In step S101, the decoding unit 41 acquires a 2 × 2 orthogonal conversion flag from the bit stream output from the coding device 11B in step S55 or S57 of FIG. 15 and supplies it to the control unit 47.

In step S102, the control unit 47 determines whether or not the 2 × 2 orthogonal conversion flag supplied from the decoding unit 41 in step S101 indicates that the 2 × 2 orthogonal conversion is performed.

If the control unit 47 determines in step S102 that the 2 × 2 orthogonal conversion flag performs 2 × 2 orthogonal conversion (tu_2x2_flag = 1), the process proceeds to step S103. In step S103, the control unit 47 sets a conversion unit having a block size of 2 × 2 for the inverse orthogonal conversion unit 43, and all blocks of the decoding device 12A so as to execute coding in the 2 × 2 orthogonal conversion mode. Control against. As a result, the same processing as the flowchart of FIG. 9 is performed, and then the processing is terminated.

On the other hand, if the control unit 47 determines in step S102 that the 2 × 2 orthogonal conversion flag does not indicate that 2 × 2 orthogonal conversion is performed (tu_2x2_flag = 0), the process proceeds to step S104. In step S104, the control unit 47 sets the same conversion unit as the decoding processing unit for the inverse orthogonal conversion unit 43, and for all the blocks of the coding device 11A so as to execute the decoding in the normal orthogonal conversion mode. Take control. As a result, in step S23 of the flowchart of FIG. 9, decoding is executed in which the inverse orthogonal conversion is performed once in the same conversion unit as the processing unit, and then the processing is terminated.

As described above, the coding device 11B and the decoding device 12A can be used by switching between the 2 × 2 orthogonal conversion mode and the normal orthogonal conversion mode so as to reduce the cost.

<Fourth processing example of coding processing and decoding processing>
A fourth processing example of the coding processing performed in the coding apparatus 11B will be described with reference to the flowchart shown in FIG.

In steps S111 and S112, the same processing as in steps S51 and S52 of FIG. 15 is performed, and the RD cost J1 in the normal orthogonal conversion mode and the RD cost J2 in the 2 × 2 orthogonal conversion mode are notified to the control unit 30.

In step S113, the work amount calculation unit 31 performs the cost calculation process in the 4 × 2 orthogonal conversion mode, calculates the RD cost J3 required when the 4 × 2 orthogonal conversion mode is performed, and causes the control unit 30 to calculate the RD cost J3. Notice. In the cost calculation process in the 4 × 2 orthogonal conversion mode, the processes of steps S83 and S87 in the cost calculation process in the 2 × 2 orthogonal conversion mode described with reference to the flowchart of FIG. 17 are in the processing unit of the block size 4 × 2. Will be done. Then, the control unit 30 is notified of the RD cost J3 in the 4 × 2 orthogonal conversion mode obtained based on the code amount R3 and the square error D3.

In step S114, the control unit 30 compares the RD cost J1 in the normal orthogonal conversion mode, the RD cost J2 in the 2 × 2 orthogonal conversion mode, and the RD cost J3 in the 4 × 2 orthogonal conversion mode, and selects the mode with the lowest cost. judge.

If the control unit 30 determines in step S114 that the mode with the lowest cost is the RD cost J2 in the 2 × 2 orthogonal conversion mode, the process proceeds to step S115.

In step S115, the control unit 30 sets an orthogonal conversion mode flag (tu_index_2) indicating that 2 × 2 orthogonal conversion is performed, and controls the coding unit 29 so as to put it in a bit stream and transmit it. In response to this, the encoding unit 29 puts an orthogonal conversion mode flag indicating that the 2 × 2 orthogonal conversion is performed into the bit stream and transmits it.

In step S116, the control unit 30 sets a conversion unit having a block size of 2 × 2 for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes so as to execute coding in the 2 × 2 orthogonal conversion mode. Controls all blocks of device 11B. As a result, the same processing as the flowchart of FIG. 8 is performed, and then the processing is terminated.

On the other hand, if the control unit 30 determines in step S114 that the mode with the lowest cost is the RD cost J3 in the 4 × 2 orthogonal conversion mode, the process proceeds to step S117.

In step S117, the control unit 30 sets an orthogonal conversion mode flag (tu_index_1) indicating that 4 × 2 orthogonal conversion is performed, and controls the coding unit 29 so as to put it in a bit stream and transmit it. In response to this, the encoding unit 29 puts an orthogonal conversion mode flag indicating that the 4 × 2 orthogonal conversion is performed into the bit stream and transmits it.

In step S118, the control unit 30 sets a conversion unit having a block size of 4 × 2 for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes so as to execute coding in the 4 × 2 orthogonal conversion mode. Controls all blocks of device 11B. As a result, in steps S13 and S16 of the flowchart of FIG. 8, coding is performed in which orthogonal conversion and inverse orthogonal conversion are performed twice in each processing unit having a block size of 4 × 2, and then the processing is terminated.

On the other hand, if the control unit 30 determines in step S114 that the mode with the lowest cost is the RD cost J1 in the normal orthogonal conversion mode, the process proceeds to step S119.

In step S119, the control unit 30 sets an orthogonal conversion mode flag (tu_index_0) indicating that normal orthogonal conversion is performed, and controls the coding unit 29 so as to put it in a bit stream and transmit it. In response to this, the encoding unit 29 puts the orthogonal conversion mode flag indicating that the normal orthogonal conversion is performed into the bit stream and transmits it.

In step S120, the control unit 30 sets the same conversion unit as the coding processing unit for the orthogonal conversion unit 22 and the inverse orthogonal conversion unit 25, and encodes so as to execute the coding in the normal orthogonal conversion mode. Controls all blocks of device 11B. As a result, in steps S13 and S16 of the flowchart of FIG. 8, coding is performed in which the orthogonal conversion and the inverse orthogonal conversion are performed once in the same conversion unit as the processing unit, and then the processing is terminated.

A fourth processing example of the coding processing performed in the decoding device 12A will be described with reference to the flowchart shown in FIG.

In step S131, the decoding unit 41 acquires the orthogonal conversion mode flag from the bit stream output from the coding device 11B in steps S116, S118, or S120 of FIG. 19 and supplies it to the control unit 47.

In step S132, the control unit 47 performs any of 2 × 2 orthogonal conversion, 4 × 2 orthogonal conversion, and normal orthogonal conversion with the orthogonal conversion mode flag supplied from the decoding unit 41 in step S131. Is determined.

If the control unit 47 determines in step S132 that the orthogonal conversion mode flag indicates that 2 × 2 orthogonal conversion is performed (tu_index_2), the process proceeds to step S133. In step S133, the control unit 47 sets a conversion unit having a block size of 2 × 2 for the inverse orthogonal conversion unit 43, and performs decoding for all the blocks of the decoding device 12B so as to execute decoding in the 2 × 2 orthogonal conversion mode. Take control. As a result, the same processing as the flowchart of FIG. 9 is performed, and then the processing is terminated.

On the other hand, if the control unit 47 determines in step S132 that the orthogonal conversion mode flag indicates that 4 × 2 orthogonal conversion is performed (tu_index_1), the process proceeds to step S134. In step S134, the control unit 47 sets a conversion unit having a block size of 4 × 2 for the inverse orthogonal conversion unit 43, and performs decoding for all blocks of the decoding device 12B so as to execute decoding in the 4 × 2 orthogonal conversion mode. Take control. As a result, in step S23 of the flowchart of FIG. 9, decoding is executed in which the inverse orthogonal conversion is performed twice in the conversion unit of the block size 4 × 2, and then the processing is terminated.

On the other hand, if the control unit 47 determines in step S132 that the orthogonal conversion mode flag indicates that normal orthogonal conversion is performed (tu_index_0), the process proceeds to step S135. In step S135, the control unit 47 sets the same conversion unit as the decoding processing unit for the inverse orthogonal conversion unit 43, and for all the blocks of the coding device 11B so as to execute the decoding in the normal orthogonal conversion mode. Take control. As a result, in step S23 of the flowchart of FIG. 9, decoding is executed in which the inverse orthogonal conversion is performed once in the same conversion unit as the processing unit, and then the processing is terminated.

As described above, the coding device 11B and the decoding device 12A can be used by switching between the 2 × 2 orthogonal conversion mode, the 4 × 2 orthogonal conversion mode, and the normal orthogonal conversion mode so as to reduce the cost.

<How to improve the scan of quantization conversion coefficient>
A method for improving the scan of the quantization conversion coefficient will be described with reference to FIGS. 21 and 22.

For example, as shown in the upper part of FIG. 21, when orthogonal conversion is conventionally performed in a processing unit of block size 4 × 4, low frequency components are gathered in the upper left of block size 4 × 4, and lower right of block size 4 × 4. High frequency components will be collected in. Therefore, if the orthogonal transformation is performed properly, the signal will be concentrated in the upper left.

Then, as described above, in the present embodiment, the orthogonal conversion is performed in the conversion unit of the block size 2 × 2. Here, the following equation (1) shows the orthogonal transformation performed in the processing unit of the block size 2 × 2.

This equation (1) is called a two-point Hadamard transform, the upper equation of the equation (1) shows a forward orthogonal transform, and the lower equation of the equation (1) is. It shows the orthogonal transform in the opposite direction. Then, according to the equation (1), the predicted residual (x ₀ , x ₁ ), which is the value to be orthogonally converted, is converted into the conversion coefficient (X ₀ , X ₁ ), which is the value after the orthogonal conversion. ..

For example, when a processing unit having a block size of 4 × 4 is divided into four and an orthogonal conversion is performed in a conversion unit having a block size of 2 × 2, first, two rows of two points are orthogonally converted in the horizontal direction. , The converted value is subjected to orthogonal conversion of two points in two columns in the vertical direction.

The middle part of FIG. 21 shows a state in which orthogonal conversion is performed in conversion units of block size 2 × 2, and the upper left pixel of block size 2 × 2, that is, pixel 00, pixel 02, and pixel 20 respectively. , And low frequency components are concentrated in the pixel 22. Therefore, it is preferable to change the scanning order of the quantization conversion coefficient as shown in the lower part of FIG. 21 by utilizing the characteristic that signals are gathered in the upper left of each of the block sizes 2 × 2.

For example, as described in the coding in FIG. 2 above, conventionally, in the entire processing unit having a block size of 4 × 4, a zigzag (Z-shaped straight line bends left and right many times from the lower right to the upper left). The quantization conversion coefficient was scanned in the scan order of (shape). On the other hand, for four block size 2 × 2 conversion units, scanning the quantization conversion coefficients in a zigzag order from the lower right to the upper left of each conversion unit is performed by quantizing the corresponding positions. For each conversion coefficient, the quantization conversion coefficient is changed so that it is scanned in a scanning order that repeats in a zigzag order from the lower right to the upper left of the conversion unit.

That is, first, the quantization conversion coefficient at the lower right of each conversion unit is scanned in a zigzag manner from the lower right to the upper left for each conversion unit, and then the quantization conversion coefficient at the upper right of each conversion unit is displayed. Scan in a zigzag manner from the lower right to the upper left for each conversion unit. Then, the lower left quantization conversion coefficient of each conversion unit is scanned in a zigzag manner from the lower right to the upper left for each conversion unit, and finally, the upper left quantization conversion coefficient of each conversion unit is converted. Scan from the lower right to the upper left in a zigzag manner.

As a result, the scan order is such that the pixels with a high possibility of having a small quantization conversion coefficient come first, and the pixels with a high possibility of having a large quantization conversion coefficient come after with the conventional scan order. Specifically, pixel 33, pixel 13, pixel 31, pixel 11, pixel 23, pixel 03, pixel 21, pixel 01, pixel 32, pixel 12, pixel 30, pixel 10, pixel 22, pixel 02, pixel 20, And the scanning order of pixel 00.

As a result, for example, those having a quantization conversion coefficient of 0 are collected first, and efficient coding is achieved.

Next, with reference to FIG. 22, another example of an improvement method for scanning the quantization conversion coefficient will be described.

For example, due to the nature of intra-prediction, there is a characteristic that the residual signals on the left and upper sides near the reference pixel become smaller. Therefore, using this characteristic, after orthogonal conversion is performed in the conversion unit of the block size 2 × 2 as shown in the upper part of FIG. 22, the block size 2 × 2 in the upper left is performed as shown in the middle part of FIG. After exchanging the conversion unit of the above and the conversion unit of the lower right block size 2 × 2, scanning is performed in the scanning order described with reference to FIG. That is, the conversion unit on the lower right side and the conversion unit on the upper left side are made symmetrical with respect to the diagonal line connecting the upper right and the lower left, and the arrangement of the quantization conversion coefficient in the conversion unit can be changed for each conversion unit. After the replacement (without), scan the quantization conversion coefficient. As a result, specifically, pixel 11, pixel 13, pixel 31, pixel 33, pixel 01, pixel 03, pixel 21, pixel 23, pixel 10, pixel 12, pixel 30, pixel 32, pixel 00, pixel 02, The scanning order of the pixel 20 and the pixel 22 is set.

That is, due to the above-mentioned characteristics, the conversion coefficient after orthogonal conversion is expected to be smaller in the upper left block size 2 × 2 and larger in the lower right block size 2 × 2. Therefore, the upper left block size 2x2 and the lower right block size 2x2 are exchanged, and the lower right block size 2x2, which is expected to have a relatively large residual signal, is placed later in the scanning order. By setting, more efficient coding is achieved.

Therefore, for example, the coding unit 29 scans the quantization conversion coefficient in such a scanning order, so that the coding device 11 can further improve the coding efficiency.

<Computer configuration example>
Next, the series of processes (information processing method) described above can be performed by hardware or software. When a series of processes is performed by software, the programs constituting the software are installed on a general-purpose computer or the like.

FIG. 23 is a block diagram showing a configuration example of an embodiment of a computer in which a program for executing the above-mentioned series of processes is installed.

The program can be recorded in advance on the hard disk 105 or ROM 103 as a recording medium built in the computer.

Alternatively, the program can be stored (recorded) in the removable recording medium 111 driven by the drive 109. Such a removable recording medium 111 can be provided as so-called package software. Here, examples of the removable recording medium 111 include a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory.

In addition to installing the program on the computer from the removable recording medium 111 as described above, the program can be downloaded to the computer via a communication network or a broadcasting network and installed on the built-in hard disk 105. That is, for example, the program transfers wirelessly from a download site to a computer via an artificial satellite for digital satellite broadcasting, or transfers to a computer by wire via a network such as LAN (Local Area Network) or the Internet. be able to.

The computer includes a CPU (Central Processing Unit) 102, and an input/output interface 110 is connected to the CPU 102 via a bus 101.

When a command is input by the user by operating the input unit 107 or the like via the input / output interface 110, the CPU 102 executes a program stored in the ROM (Read Only Memory) 103 accordingly. .. Alternatively, the CPU 102 loads the program stored in the hard disk 105 into the RAM (Random Access Memory) 104 and executes it.

As a result, the CPU 102 performs processing according to the above-mentioned flowchart or processing performed according to the above-mentioned block diagram configuration. Then, the CPU 102 outputs the processing result from the output unit 106, transmits it from the communication unit 108, or records it on the hard disk 105, if necessary, via the input / output interface 110, for example.

The input unit 107 is composed of a keyboard, a mouse, a microphone, and the like. Further, the output unit 106 is composed of an LCD (Liquid Crystal Display), a speaker, or the like.

Here, in the present specification, the processing performed by the computer according to the program does not necessarily have to be performed in chronological order in the order described as the flowchart. That is, the processing performed by the computer according to the program also includes processing executed in parallel or individually (for example, parallel processing or processing by an object).

Further, the program may be processed by one computer (processor) or may be distributed by a plurality of computers. Further, the program may be transferred to a distant computer and executed.

Furthermore, in the present specification, the system means a set of a plurality of constituent elements (devices, modules (parts), etc.), and it does not matter whether or not all constituent elements are in the same housing. Therefore, a plurality of devices housed in separate housings and connected via a network, and a device in which a plurality of modules are housed in one housing are both systems. ..

Further, for example, the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units). On the contrary, the configurations described above as a plurality of devices (or processing units) may be collectively configured as one device (or processing unit). Further, of course, a configuration other than the above may be added to the configuration of each device (or each processing unit). Further, if the configuration and operation of the entire system are substantially the same, a part of the configuration of one device (or processing unit) may be included in the configuration of another device (or other processing unit). ..

Further, for example, this technology can have a cloud computing configuration in which one function is shared by a plurality of devices via a network and jointly processed.

Further, for example, the above-mentioned program can be executed in any device. In that case, the device may have necessary functions (functional blocks, etc.) so that necessary information can be obtained.

Further, for example, each step described in the above flowchart can be executed by one device or can be shared and executed by a plurality of devices. Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by one device or shared by a plurality of devices. In other words, a plurality of processes included in one step can be executed as processes of a plurality of steps. On the contrary, the processes described as a plurality of steps can be collectively executed as one step.

In the program executed by the computer, the processing of the steps for describing the program may be executed in chronological order according to the order described in this specification, or may be called in parallel or called. It may be executed individually at a necessary timing such as time. That is, as long as there is no contradiction, the processing of each step may be executed in an order different from the above-mentioned order. Further, the processing of the step for writing this program may be executed in parallel with the processing of another program, or may be executed in combination with the processing of another program.

It should be noted that the present techniques described in the present specification can be independently implemented independently as long as there is no contradiction. Of course, any plurality of the present technologies can be used in combination. For example, some or all of the techniques described in any of the embodiments may be combined with some or all of the techniques described in other embodiments. It is also possible to carry out a part or all of any of the above-mentioned techniques in combination with other techniques not described above.

<Example of configuration combination>
The present technology can also have the following configurations.
(1)
When encoding an image, an orthogonal conversion unit that obtains the conversion coefficient by orthogonally converting the predicted residual obtained in the processing unit to be encoded in a conversion unit smaller than the processing unit.
A quantization unit that quantizes the conversion coefficient in the processing unit to obtain the quantization conversion coefficient,
A coding device including a coding unit that encodes the quantization conversion coefficient in the processing unit and outputs a bit stream.
(2)
The quantization unit and the coding unit perform processing in a processing unit having a block size of 4 × 4.
The coding device according to (1) above, wherein the orthogonal conversion unit performs orthogonal conversion in conversion units having a block size of 2 × 2 or a block size of 4 × 2.
(3)
The coding according to (1) or (2) above, further comprising a control unit for determining whether or not the orthogonal conversion unit performs orthogonal conversion in a conversion unit smaller than the processing unit of the coding according to a predetermined condition. apparatus.
(4)
As the predetermined condition, one of the block size 4 × 4, the intra prediction, and the specific intra prediction mode is used as the processing unit of the coding according to the above (3). Encoding device.
(5)
The first cost required when the orthogonal conversion unit performs orthogonal conversion in the coding processing unit, and the orthogonal conversion unit performs orthogonal conversion in a conversion unit smaller than the coding processing unit. It also has a work amount calculation unit that calculates the second cost required in some cases.
The control unit compares the first cost with the second cost, determines that the orthogonal conversion is performed in the conversion unit when the second cost is small, and sets a flag indicating the determination result. The encoding device according to (3) above, which is put into the bit stream and transmitted.
(6)
The work amount calculation unit has a first cost required when performing orthogonal conversion with a block size of 4 × 4, a second cost required when performing orthogonal conversion with a block size of 2 × 2, and Calculate the third cost required when orthogonal conversion is performed with a block size of 4 × 2.
The control unit determines that the orthogonal conversion is performed in the conversion unit of the block size, which is the smallest of the first cost, the second cost, and the third cost, and determines the determination result. The encoding device according to (5) above, wherein the indicated flag is put into the bit stream and transmitted.
(7)
The coding unit scans the quantization conversion coefficient in a zigzag order from the lower right to the upper left of each conversion unit, and the conversion is performed for each of the quantization conversion coefficients at the corresponding positions. The coding apparatus according to any one of (1) to (6) above, wherein coding is performed in a scanning order that repeats in a zigzag order from the lower right to the upper left of the unit.
(8)
The coding unit replaces the conversion unit on the lower right side and the conversion unit on the upper left side with the diagonal line connecting the upper right and the lower left symmetrical, and then replaces each conversion unit, and then the scan order. The coding apparatus according to (7) above.
(9)
The encoding device
When encoding an image, the predicted residuals obtained in the processing unit to be encoded are orthogonally converted in conversion units smaller than the processing unit to obtain the conversion coefficient.
Quantizing the conversion coefficient in the processing unit to obtain the quantization conversion coefficient,
A coding method including encoding the quantization conversion coefficient in the processing unit and outputting a bit stream.
(10)
A decoding unit that decodes a bit stream encoded in a processing unit to be encoded in the processing unit to obtain a quantization conversion coefficient.
An inverse quantization unit that obtains the conversion coefficient by dequantizing the quantization conversion coefficient in the processing unit,
A decoding device including an inverse orthogonal conversion unit for obtaining a predicted residual by inversely orthogonally converting the conversion coefficient in a conversion unit smaller than the processing unit.
(11)
The decoding unit and the inverse quantization unit perform processing in processing units having a block size of 4 × 4.
The decoding device according to (10) above, wherein the inverse orthogonal conversion unit performs inverse orthogonal conversion in conversion units having a block size of 2 × 2 or a block size of 4 × 2.
(12)
(10) or (11) above, further comprising a control unit for determining whether or not the inverse orthogonal conversion unit performs inverse orthogonal conversion in a conversion unit smaller than the coding processing unit according to a predetermined condition. Decryptor.
(13)
As the predetermined condition, one of the block size 4 × 4, the intra-prediction, and the specific intra-prediction mode is used as the processing unit of the coding according to the above (12). Decryptor.
(14)
The control unit is a flag included in the bit stream, and according to a flag indicating a determination result indicating whether or not orthogonal conversion is performed in a conversion unit smaller than the processing unit of the coding on the coding side. The decoding device according to (12) above, which determines whether or not the inverse orthogonal conversion unit performs inverse orthogonal conversion in a conversion unit smaller than the coding processing unit.
(15)
The control unit is a flag included in the bit stream, and either performs orthogonal conversion with a block size of 4 × 4 on the coding side, performs orthogonal conversion with a block size of 2 × 2, or performs orthogonal conversion with a block size of 4 × 2. The decoding device according to (12) above, wherein the inverse orthogonal conversion unit selects a conversion unit for performing inverse orthogonal conversion according to a flag indicating a determination result of determining whether to perform orthogonal conversion.
(16)
Decryptor
Obtaining the quantization conversion coefficient by decoding the bitstream encoded in the processing unit to be encoded in the processing unit.
The conversion coefficient is obtained by inversely quantizing the quantization conversion coefficient in the processing unit.
A decoding method including obtaining a predicted residual by inversely orthogonally converting the conversion coefficient in a conversion unit smaller than the processing unit.

Note that the present embodiment is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present disclosure. Further, the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

11 Encoding device, 12 Decoding device, 21 Arithmetic unit, 22 Orthogonal conversion unit, 23 Quantization unit, 24 Inverse quantization unit, 25 Inverse orthogonal conversion unit, 26 Arithmetic unit, 27 Frame memory, 28 Prediction unit, 29 Coding Unit, 30 control unit, 31 workload calculation unit, 41 decoding unit, 42 inverse quantization unit, 43 inverse orthogonal conversion unit, 44 calculation unit, 45 frame memory, 46 prediction unit, 47 control unit

Claims

When encoding an image, an orthogonal conversion unit that obtains the conversion coefficient by orthogonally converting the predicted residual obtained in the processing unit to be encoded in a conversion unit smaller than the processing unit.
A quantization unit that quantizes the conversion coefficient in the processing unit to obtain the quantization conversion coefficient,
A coding device including a coding unit that encodes the quantization conversion coefficient in the processing unit and outputs a bit stream.
The quantization unit and the coding unit perform processing in a processing unit having a block size of 4 × 4.
The coding device according to claim 1, wherein the orthogonal conversion unit performs orthogonal conversion in conversion units having a block size of 2 × 2 or a block size of 4 × 2.
The coding apparatus according to claim 1, further comprising a control unit for determining whether or not the orthogonal conversion unit performs orthogonal conversion in a conversion unit smaller than the coding processing unit according to a predetermined condition.
The third aspect of claim 3, wherein the coding processing unit is block size 4 × 4, intra-prediction, or a specific intra-prediction mode is used as the predetermined condition. Encoding device.
The first cost required when the orthogonal conversion unit performs orthogonal conversion in the coding processing unit, and the orthogonal conversion unit performs orthogonal conversion in a conversion unit smaller than the coding processing unit. It also has a work amount calculation unit that calculates the second cost required in some cases.
The control unit compares the first cost with the second cost, determines that the orthogonal conversion is performed in the conversion unit when the second cost is small, and sets a flag indicating the determination result. The encoding device according to claim 3, wherein the bit stream is put into the bit stream and transmitted.
The work amount calculation unit has a first cost required when performing orthogonal conversion with a block size of 4 × 4, a second cost required when performing orthogonal conversion with a block size of 2 × 2, and Calculate the third cost required when orthogonal conversion is performed with a block size of 4 × 2.
The control unit determines that the orthogonal conversion is performed in the conversion unit of the block size, which is the smallest of the first cost, the second cost, and the third cost, and determines the determination result. The encoding device according to claim 5, wherein the indicated flag is put into the bit stream and transmitted.
The coding unit scans the quantization conversion coefficient in a zigzag order from the lower right to the upper left of each conversion unit, and the conversion is performed for each of the quantization conversion coefficients at the corresponding positions. The coding apparatus according to claim 1, wherein coding is performed in a scanning order that repeats in a zigzag order from the lower right to the upper left of the unit.
The coding unit replaces the conversion unit on the lower right side and the conversion unit on the upper left side with the diagonal line connecting the upper right and the lower left symmetrical, and then replaces each conversion unit, and then the scan order. The coding apparatus according to claim 7, wherein the coding device is performed according to claim 7.
The encoding device
When encoding an image, the predicted residuals obtained in the processing unit to be encoded are orthogonally converted in conversion units smaller than the processing unit to obtain the conversion coefficient.
Quantizing the conversion coefficient in the processing unit to obtain the quantization conversion coefficient,
A coding method including encoding the quantization conversion coefficient in the processing unit and outputting a bit stream.
A decoding unit that decodes a bit stream encoded in a processing unit to be encoded in the processing unit to obtain a quantization conversion coefficient.
An inverse quantization unit that obtains the conversion coefficient by dequantizing the quantization conversion coefficient in the processing unit,
A decoding device including an inverse orthogonal conversion unit for obtaining a predicted residual by inversely orthogonally converting the conversion coefficient in a conversion unit smaller than the processing unit.
The decoding unit and the inverse quantization unit perform processing in processing units having a block size of 4 × 4.
The decoding device according to claim 10, wherein the inverse orthogonal conversion unit performs inverse orthogonal conversion in conversion units having a block size of 2 × 2 or a block size of 4 × 2.
The decoding device according to claim 10, further comprising a control unit for determining whether or not the inverse orthogonal conversion unit performs inverse orthogonal conversion in a conversion unit smaller than the coding processing unit according to a predetermined condition.
The twelfth claim, wherein the coding processing unit is a block size of 4 × 4, an intra-prediction, or a specific intra-prediction mode is used as the predetermined condition. Decryptor.
The control unit is a flag included in the bit stream, and according to a flag indicating a determination result indicating whether or not orthogonal conversion is performed in a conversion unit smaller than the processing unit of the coding on the coding side. The decoding device according to claim 12, wherein the inverse orthogonal conversion unit determines whether or not the inverse orthogonal conversion is performed in a conversion unit smaller than the coding processing unit.
The control unit is a flag included in the bit stream, and either performs orthogonal conversion with a block size of 4 × 4 on the coding side, performs orthogonal conversion with a block size of 2 × 2, or performs orthogonal conversion with a block size of 4 × 2. The decoding device according to claim 12, wherein the inverse orthogonal conversion unit selects a conversion unit for performing inverse orthogonal conversion according to a flag indicating a determination result of determining whether to perform orthogonal conversion.
Decryptor
Obtaining the quantization conversion coefficient by decoding the bitstream encoded in the processing unit to be encoded in the processing unit.
The conversion coefficient is obtained by inversely quantizing the quantization conversion coefficient in the processing unit.
A decoding method including obtaining a predicted residual by inversely orthogonally converting the conversion coefficient in a conversion unit smaller than the processing unit.