WO2020176123A1 - Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals - Google Patents

Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals Download PDF

Info

Publication number
WO2020176123A1
WO2020176123A1 PCT/US2019/038390 US2019038390W WO2020176123A1 WO 2020176123 A1 WO2020176123 A1 WO 2020176123A1 US 2019038390 W US2019038390 W US 2019038390W WO 2020176123 A1 WO2020176123 A1 WO 2020176123A1
Authority
WO
WIPO (PCT)
Prior art keywords
address
memory
register
data
latch
Prior art date
Application number
PCT/US2019/038390
Other languages
French (fr)
Inventor
Keith Edwin Curtis
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Priority to CN201980092913.1A priority Critical patent/CN113474761B/en
Priority to DE112019006932.2T priority patent/DE112019006932T5/en
Publication of WO2020176123A1 publication Critical patent/WO2020176123A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Definitions

  • the present disclosure relates to direct memory access (DMA) control and, more particularly, a programmable arbitrary sequence DMA controller for configuring multiple core independent peripherals (CIPs).
  • DMA direct memory access
  • CIPs core independent peripherals
  • a core independent peripheral is considered to be a peripheral that does not need to be controlled by the CPU to perform its function.
  • a conventional analog-to-digital converter must be controlled by the CPU to sample each value and the CPU must store the result once it is obtained.
  • a core independent version of such an analog-to-digital converter may be still configured by the CPU but once it has been configured, it may operate independently from the CPU and for example may be independently triggered and store results in specific locations.
  • Other core independent peripherals may be implemented which allows to free the CPU from control tasks and, thus, enhance processing power of a microcontroller.
  • One of the main advantages to core independent peripherals (CIPs) is that they can be reconfigured on-the-fly to change the performance or operation of the CIP, a pseudo peripheral. Unfortunately, the CIP configuration registers may be scattered across multiple memory mapped special function register (SFR) address banks. Using program firmware to do a CIP reconfiguration is also relatively slow and incurs a latency time in response to an external signal.
  • SFR special function
  • One method that can be used is configuring together two DMA peripherals, one which accesses the SFR address list from memory, and then programs the second DMA peripheral with these SFR addresses which then makes the actual CIP reconfiguration data transfers to the CIP SFRs. This is very inefficient in that multiple registers are duplicated, and the writing speed is slower. It also requires the two DMA peripherals be cross-connected in such a way as to trigger each other. If either DMA peripheral hits an error or a fault the DMA operation fails.
  • DMA direct memory access
  • a programmable arbitrary sequence direct memory access (DMA) controller may comprise: a first address pointer register; a second address pointer register; a data latch coupled to a first data bus; an address latch coupled to a second data bus; a multiplexer having a first input coupled to the first address pointer register, a second input coupled to the address latch, a third input coupled to the second address pointer register, and an output coupled to an address bus; and control logic coupled to and controlling the first and second address pointer registers, the address latch, the multiplexer and the data latch.
  • DMA direct memory access
  • the control logic may communicate with bus arbitration logic.
  • the data latch may write to and read from the first data bus.
  • the first data bus may be coupled to a data memory.
  • the second data bus may be coupled to a program memory.
  • the program memory may be a non volatile memory.
  • the non-volatile memory may be a flash programmable memory.
  • the data memory may be a random-access memory (RAM).
  • the first and second data buses may be coupled to a memory.
  • first and second byte counters may communicate with the control logic and may count a number of data bytes transferred.
  • a method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller may comprise the steps of: reading a register address stored at a memory address specified by a first address pointer register; storing the register address in an address latch; reading configuration data stored at another memory address specified by a second address pointer register; storing the configuration data in a data latch; and writing the configuration data stored in the data latch to a register at the register address stored in the address latch.
  • DMA direct memory access
  • the method may comprise the step of coupling the data latch to a first data bus and data memory.
  • the method may comprise the step of coupling the address latch to a second data bus and program memory.
  • the register may be a peripheral register.
  • peripheral register may be a special function register.
  • the special function register may be associated with a core independent peripheral (CIP).
  • a method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller comprise the steps of: reading a register address stored at a memory address specified by a first address pointer register; storing the register address in an address latch; reading configuration data stored in a peripheral register having a memory address specified by the register address in the address latch; storing the configuration data in a data latch; and writing the configuration data to a memory at an address specified by a second address pointer register.
  • DMA direct memory access
  • the method may comprise the step of coupling the data latch to a first data bus and data memory.
  • the method may comprise the step of coupling the address latch to a second data bus and program memory.
  • the register may be a peripheral register.
  • the peripheral register may be a special function register.
  • the special function register may be associated with a core independent peripheral (CIP).
  • FIG. 1 illustrates a prior art schematic block diagram of a direct memory access (DMA) controller
  • Figure 2 illustrates a schematic block diagram of a programmable arbitrary sequence DMA controller, according to specific example embodiments of this disclosure
  • Figure 3 illustrates a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 loading new configuration data into an arbitrary sequence memory location, according to specific example embodiments of this disclosure
  • Figure 4 illustrates a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 reading existing configuration data from an arbitrary sequence memory location, according to specific example embodiments of this disclosure.
  • Figure 5 illustrates a schematic block diagram of sequential and non-sequential memory locations.
  • Embodiments of the present disclosure may comprise a programmable arbitrary sequence DMA controller.
  • One side of a memory system address (source or destination) is accessed normally (sequentially) using source/destination address registers and a counter.
  • the second side of the memory system (destination or source) is accessed indirectly.
  • An address register holds an address of a memory location.
  • the memory location holds the actual location to be accessed.
  • SFRs special function registers are generally registers for configuring and controlling functionality of various peripherals. For easy access to these registers, they are memory mapped to the data memory space.
  • the programmable arbitrary sequence DMA controller can copy the contents of multiple peripherals to memory, or from memory to the peripheral SFRs, without the requirement that the addresses of the SFRs be in sequential order. It also allows the DMA to potentially reconfigure the peripherals to any of several preset configurations simply by referencing different lists.
  • the DMA can also be triggered by an external signal creating a dynamic system that can reconfigure the SFRs, e.g., of the CIPs in response to external stimuli.
  • the proposed solution is simpler than requiring two DMA controllers as it is a modification of an existing DMA controller design. It also eliminates the need to cross connect two different DMA controllers. It should be smaller, faster, and has a smaller SFR foot print than a pair of DMA controllers.
  • the DMA controller can be further enhanced by comprising an operation mode register that allows to control the DMA controller to operate in either the conventional operating mode or the indirect operating mode as will be explained in more detail below.
  • the DMA controller may comprise a first address pointer register 102, a second address pointer register 104, a first byte counter 106, control logic 108, a second byte counter 110, a two-input multiplexer 112 and a data latch 118.
  • the multiplexer 112 may be coupled to a memory address bus 114 and the data latch 118 may be coupled to a memory data bus 116.
  • the control logic 108 may communicate with bus arbitration logic (not shown).
  • the first and second address pointer registers 102 and 104 increment sequentially with a counter (not shown) and point to sequential memory locations.
  • the first address pointer register 102 contains an address of a memory location from which data is to be retrieved.
  • the second address pointer register 104 contains an address of another memory location to which data is to be written.
  • the memory (not shown) may be for example but is not limited to flash program memory, firmware memory, random access memory (RAM), inter alia.
  • the data is first read from the memory location specified by the first address pointer register 102, wherein the multiplexer 112 couples a source address from the first address pointer register 102 to the address bus 114 coupled to the memory bus (not shown).
  • the contents (data) of that memory (source) location are read via the data bus 116 and stored in the data latch 118.
  • the multiplexer 112 couples a destination address from the second address pointer register 104 to the address bus 114 and a memory (destination) location at that address is written to with the contents (data) stored in the data latch 118 via the data bus 116.
  • the address bus 114 and data bus 116 may be coupled to a memory (not shown).
  • FIG. 2 depicted is a schematic block diagram of a programmable arbitrary sequence DMA controller, according to specific example embodiments of this disclosure.
  • a programmable arbitrary sequence DMA controller generally referenced by the number 200, provides a better and more efficient way to handle arbitrary sequence DMA transfers is shown in Figure 2.
  • the programmable arbitrary sequence DMA controller 200 may comprise a first address pointer register 202, a second address pointer register 204, a first byte counter 206, a control logic 208, a second byte counter 210, a multiplexer 212 having outputs coupled to an address bus 214, a data latch 218 having outputs and inputs coupled to a first data bus 216, an address latch 220 having inputs coupled to a second data bus 222, and bus arbitration logic 228 in communication with the control logic 208.
  • the first data bus 216 may be coupled to a data memory 226 and the second data bus 222 may be coupled to a program memory 224.
  • the data memory 226 may be, for example but is not limited to, an eight-bit memory, and the program memory 224 may be, for example but is not limited to, a fourteen-bit memory. Addressing of either memory may be over the address bus 214.
  • the program memory 224 may contain indirect destination addresses to which the data is to be transferred to or read from.
  • the program memory 224 coupled to the second data bus 222 may be, for example but is not limited to, a non-volatile random-access memory (RAM) such as a flash programmable memory.
  • the data memory 226 may be volatile or non-volatile RAM.
  • the data memory 226 and the program memory 224 may have the same bit width and be comprised of a single memory. Operation of the programmable arbitrary sequence DMA controller shown in Figure 2 is more fully disclosed hereinafter with reference to Figures 3 and 4 and the descriptions thereof.
  • the second data bus 222 may be coupled to the same or a different memory as the first data bus 216.
  • the address latch 220 is coupled to and reads and stores indirect destination addresses from the program memory 224 via the second data bus 222.
  • the data latch 218 may read and write data to/from its associated memory via the first data bus 216.
  • the control logic 208 may communicate with bus arbitration logic 228.
  • the byte counters 206 and 210 may be used to count the number of memory bytes being transferred.
  • an operating mode register 250 is provided.
  • the operating mode register can allow to operate in either the conventional mode or the indirect mode, for example, by clearing or setting one bit 255 in register 250. Other configurations may be possible and more than one bit in register 250 may be used to define the actual operation mode.
  • address latch 220 When operating in the conventional operating mode, address latch 220 will not be used and the DMA controller will function as described above with Fig. 1.
  • the operating mode register can be a memory mapped special function register 250 or unused bits of an already present configuration register may be used for setting the indirect or conventional DMA operating mode.
  • step 302 DMA transfers begin.
  • step 304 a CIP SFR address stored in memory at a memory address specified by a first address pointer register 202 is read and then stored in an address latch 220 in step 306, e.g., from program memory 224 via second data bus 222.
  • step 308 CIP configuration data stored in data memory 226 at a memory address specified by a second address pointer register 204 is read, utilizing address bus 214 and second data bus 222, and is stored in the data latch 218 in step 310.
  • step 312 the CIP configuration data stored in the data latch 218 of step 310 is written into the CIP SFR (memory) address, which is a particular address in data memory 226, stored in the address latch 220, utilizing address bus 214 and first data bus 216.
  • CIP SFR memory
  • step 402 DMA transfers begin.
  • step 404 a CIP SFR address stored in memory, e.g., program memory 224, at a memory address specified by a first address pointer register 202 is read, utilizing address bus 214 and second data bus 222, and then stored in an address latch 220 in step 406 by coupling the address latch 220 to the second data bus 222 and program memory 224.
  • step 408 CIP configuration data stored in the CIP SFR which is a particular address in data memory 226, at a memory address specified by the address latch 220 is read, by coupling the address latch 220 to and utilizing address bus 214 and first data bus 216, and then is stored in the data latch 218 in step 410.
  • step 412 the CIP configuration data stored in the data latch 218 is written into a memory address of data memory 226 specified by a second address pointer register 204, utilizing address bus 214 and data bus 216.
  • Sequential memory locations 520 which may represent a portion of program memory 224, may be used to store the addresses of non- sequential memory locations 530-544, which may represent a portion of data memory 226.
  • the non-sequential memory locations 530-544 may be memory-mapped to special function registers of various peripherals for storing data, e.g., configuration data.
  • the registers may comprise at least one special function register (SFR) 560 of a core independent peripheral (CIP) 562 that has a non sequential memory location 544.
  • SFR 560 may be a peripheral register. Addresses for the non- sequential memory locations 530-544 may be stored in the sequential memory locations 520a-n and accessed as described hereinabove.
  • the non- sequential memory locations 530-544 may be used primarily for SFR 560 addresses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

A programmable arbitrary sequence direct memory access, DMA, controller accesses sequentially addressed memory locations (source or destination) using address pointer registers (202,204). Each sequentially addressed memory location containing an indirect memory address is stored in an address latch (230) and used to access the actual non-sequential memory location to be accessed by the DMA transfer.

Description

PROGRAMMABLE ARBITRARY SEQUENCE DIRECT MEMORY ACCESS CONTROLLER FOR CONFIGURING MULTIPLE CORE INDEPENDENT
PERIPHERALS
RELATED PATENT APPLICATION
This application claims priority to commonly owned United States Provisional Patent Application Serial Number 62/811,400; filed February 27, 2019; entitled“Programmable Arbitrary Sequence Direct Memory Access Controller for Configuring Multiple Core Independent Peripherals,” by Keith Edwin Curtis; and is hereby incorporated by reference herein for all purposes.
TECHNICAL FIELD
The present disclosure relates to direct memory access (DMA) control and, more particularly, a programmable arbitrary sequence DMA controller for configuring multiple core independent peripherals (CIPs).
BACKGROUND
A core independent peripheral is considered to be a peripheral that does not need to be controlled by the CPU to perform its function. For example, a conventional analog-to-digital converter must be controlled by the CPU to sample each value and the CPU must store the result once it is obtained. A core independent version of such an analog-to-digital converter may be still configured by the CPU but once it has been configured, it may operate independently from the CPU and for example may be independently triggered and store results in specific locations. Other core independent peripherals may be implemented which allows to free the CPU from control tasks and, thus, enhance processing power of a microcontroller. One of the main advantages to core independent peripherals (CIPs) is that they can be reconfigured on-the-fly to change the performance or operation of the CIP, a pseudo peripheral. Unfortunately, the CIP configuration registers may be scattered across multiple memory mapped special function register (SFR) address banks. Using program firmware to do a CIP reconfiguration is also relatively slow and incurs a latency time in response to an external signal.
One method that can be used is configuring together two DMA peripherals, one which accesses the SFR address list from memory, and then programs the second DMA peripheral with these SFR addresses which then makes the actual CIP reconfiguration data transfers to the CIP SFRs. This is very inefficient in that multiple registers are duplicated, and the writing speed is slower. It also requires the two DMA peripherals be cross-connected in such a way as to trigger each other. If either DMA peripheral hits an error or a fault the DMA operation fails.
SUMMARY
Therefore, what is needed is a programmable arbitrary sequence direct memory access (DMA) controller that may be triggered externally and can also jump to different non sequential memory locations in a programmable order.
According to an embodiment, a programmable arbitrary sequence direct memory access (DMA) controller may comprise: a first address pointer register; a second address pointer register; a data latch coupled to a first data bus; an address latch coupled to a second data bus; a multiplexer having a first input coupled to the first address pointer register, a second input coupled to the address latch, a third input coupled to the second address pointer register, and an output coupled to an address bus; and control logic coupled to and controlling the first and second address pointer registers, the address latch, the multiplexer and the data latch.
According to a further embodiment, the control logic may communicate with bus arbitration logic. According to a further embodiment, the data latch may write to and read from the first data bus. According to a further embodiment, the first data bus may be coupled to a data memory. According to a further embodiment, the second data bus may be coupled to a program memory. According to a further embodiment, the program memory may be a non volatile memory. According to a further embodiment, the non-volatile memory may be a flash programmable memory. According to a further embodiment, the data memory may be a random-access memory (RAM). According to a further embodiment, the first and second data buses may be coupled to a memory. According to a further embodiment, first and second byte counters may communicate with the control logic and may count a number of data bytes transferred.
According to another embodiment, a method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller may comprise the steps of: reading a register address stored at a memory address specified by a first address pointer register; storing the register address in an address latch; reading configuration data stored at another memory address specified by a second address pointer register; storing the configuration data in a data latch; and writing the configuration data stored in the data latch to a register at the register address stored in the address latch.
According to a further embodiment of the method may comprise the step of coupling the data latch to a first data bus and data memory. According to a further embodiment of the method may comprise the step of coupling the address latch to a second data bus and program memory. According to a further embodiment of the method, the register may be a peripheral register. According to a further embodiment of the method, peripheral register may be a special function register. According to a further embodiment of the method, the special function register may be associated with a core independent peripheral (CIP).
According to yet another embodiment, a method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller comprise the steps of: reading a register address stored at a memory address specified by a first address pointer register; storing the register address in an address latch; reading configuration data stored in a peripheral register having a memory address specified by the register address in the address latch; storing the configuration data in a data latch; and writing the configuration data to a memory at an address specified by a second address pointer register.
According to a further embodiment of the method may comprise the step of coupling the data latch to a first data bus and data memory. According to a further embodiment of the method may comprise the step of coupling the address latch to a second data bus and program memory. According to a further embodiment of the method, the register may be a peripheral register. According to a further embodiment of the method, the peripheral register may be a special function register. According to a further embodiment of the method, the special function register may be associated with a core independent peripheral (CIP).
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete understanding of the present disclosure may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
Figure 1 illustrates a prior art schematic block diagram of a direct memory access (DMA) controller;
Figure 2 illustrates a schematic block diagram of a programmable arbitrary sequence DMA controller, according to specific example embodiments of this disclosure; Figure 3 illustrates a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 loading new configuration data into an arbitrary sequence memory location, according to specific example embodiments of this disclosure;
Figure 4 illustrates a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 reading existing configuration data from an arbitrary sequence memory location, according to specific example embodiments of this disclosure; and
Figure 5 illustrates a schematic block diagram of sequential and non-sequential memory locations.
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the forms disclosed herein.
DETAILED DESCRIPTION
Embodiments of the present disclosure may comprise a programmable arbitrary sequence DMA controller. One side of a memory system address (source or destination) is accessed normally (sequentially) using source/destination address registers and a counter. The second side of the memory system (destination or source) is accessed indirectly. An address register holds an address of a memory location. The memory location holds the actual location to be accessed. Using this method, for example but without limitation, a list of special function register (SFR) addresses may be programmed into memory and when the DMA is triggered, the data is transferred to the SFR addresses in the order dictated by a list in the program memory. SFRs are generally registers for configuring and controlling functionality of various peripherals. For easy access to these registers, they are memory mapped to the data memory space.
According to specific example embodiments of this disclosure, the programmable arbitrary sequence DMA controller can copy the contents of multiple peripherals to memory, or from memory to the peripheral SFRs, without the requirement that the addresses of the SFRs be in sequential order. It also allows the DMA to potentially reconfigure the peripherals to any of several preset configurations simply by referencing different lists. The DMA can also be triggered by an external signal creating a dynamic system that can reconfigure the SFRs, e.g., of the CIPs in response to external stimuli.
The proposed solution is simpler than requiring two DMA controllers as it is a modification of an existing DMA controller design. It also eliminates the need to cross connect two different DMA controllers. It should be smaller, faster, and has a smaller SFR foot print than a pair of DMA controllers. In another embodiment, the DMA controller can be further enhanced by comprising an operation mode register that allows to control the DMA controller to operate in either the conventional operating mode or the indirect operating mode as will be explained in more detail below.
Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower-case letter suffix.
Referring to Figure 1, depicted is a prior art schematic block diagram of a direct memory access (DMA) controller. The DMA controller may comprise a first address pointer register 102, a second address pointer register 104, a first byte counter 106, control logic 108, a second byte counter 110, a two-input multiplexer 112 and a data latch 118. The multiplexer 112 may be coupled to a memory address bus 114 and the data latch 118 may be coupled to a memory data bus 116. The control logic 108 may communicate with bus arbitration logic (not shown).
The first and second address pointer registers 102 and 104 increment sequentially with a counter (not shown) and point to sequential memory locations. The first address pointer register 102 contains an address of a memory location from which data is to be retrieved. The second address pointer register 104 contains an address of another memory location to which data is to be written. The memory (not shown) may be for example but is not limited to flash program memory, firmware memory, random access memory (RAM), inter alia.
The data is first read from the memory location specified by the first address pointer register 102, wherein the multiplexer 112 couples a source address from the first address pointer register 102 to the address bus 114 coupled to the memory bus (not shown). The contents (data) of that memory (source) location are read via the data bus 116 and stored in the data latch 118. Then the multiplexer 112 couples a destination address from the second address pointer register 104 to the address bus 114 and a memory (destination) location at that address is written to with the contents (data) stored in the data latch 118 via the data bus 116. The address bus 114 and data bus 116 may be coupled to a memory (not shown).
The aforementioned memory data transfer operation works well when the memory address locations are sequential but not so well when they are not since non- sequential memory address locations may not be feasible to cache and/or will add to memory addressing latency times. One way to do non- sequential DMA transfers requires two of the DMA controllers shown in Figure 1. This is very inefficient in that multiple registers are duplicated, and the writing speed is slower. It also requires the two DMA controllers be cross-connected in such a way as to trigger each other. If either hits an error or a fault, the data transfer(s) fails.
Referring to Figure 2, depicted is a schematic block diagram of a programmable arbitrary sequence DMA controller, according to specific example embodiments of this disclosure. A programmable arbitrary sequence DMA controller, generally referenced by the number 200, provides a better and more efficient way to handle arbitrary sequence DMA transfers is shown in Figure 2. The programmable arbitrary sequence DMA controller 200 may comprise a first address pointer register 202, a second address pointer register 204, a first byte counter 206, a control logic 208, a second byte counter 210, a multiplexer 212 having outputs coupled to an address bus 214, a data latch 218 having outputs and inputs coupled to a first data bus 216, an address latch 220 having inputs coupled to a second data bus 222, and bus arbitration logic 228 in communication with the control logic 208.
The first data bus 216 may be coupled to a data memory 226 and the second data bus 222 may be coupled to a program memory 224. The data memory 226 may be, for example but is not limited to, an eight-bit memory, and the program memory 224 may be, for example but is not limited to, a fourteen-bit memory. Addressing of either memory may be over the address bus 214. The program memory 224 may contain indirect destination addresses to which the data is to be transferred to or read from. The program memory 224 coupled to the second data bus 222 may be, for example but is not limited to, a non-volatile random-access memory (RAM) such as a flash programmable memory. The data memory 226 may be volatile or non-volatile RAM. The data memory 226 and the program memory 224 may have the same bit width and be comprised of a single memory. Operation of the programmable arbitrary sequence DMA controller shown in Figure 2 is more fully disclosed hereinafter with reference to Figures 3 and 4 and the descriptions thereof. The second data bus 222 may be coupled to the same or a different memory as the first data bus 216. The address latch 220 is coupled to and reads and stores indirect destination addresses from the program memory 224 via the second data bus 222. The data latch 218 may read and write data to/from its associated memory via the first data bus 216. The control logic 208 may communicate with bus arbitration logic 228. The byte counters 206 and 210 may be used to count the number of memory bytes being transferred.
For allowing the DMA controller to operate in a conventional mode as shown in Fig. 1, an operating mode register 250 is provided. The operating mode register can allow to operate in either the conventional mode or the indirect mode, for example, by clearing or setting one bit 255 in register 250. Other configurations may be possible and more than one bit in register 250 may be used to define the actual operation mode. When operating in the conventional operating mode, address latch 220 will not be used and the DMA controller will function as described above with Fig. 1. The operating mode register can be a memory mapped special function register 250 or unused bits of an already present configuration register may be used for setting the indirect or conventional DMA operating mode.
References to core independent peripheral (CIP) and special function register (SFR) address and data will be used herein for illustrative purposes as shown in Figures 3 and 4 and the descriptions thereof hereinafter. One having ordinary skill in the art of digital electronics and the benefit of this disclosure will readily understand and be able to apply the teachings of this disclosure to other applications and peripheral register configuration writing and reading requiring indirect DMA addressing.
Referring to Figure 3, depicted is a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 loading new configuration data into an arbitrary sequence memory location, according to specific example embodiments of this disclosure. The arbitrary sequence memory location is determined by a memory address stored in another memory location. In step 302 DMA transfers begin. A) In step 304 a CIP SFR address stored in memory at a memory address specified by a first address pointer register 202 is read and then stored in an address latch 220 in step 306, e.g., from program memory 224 via second data bus 222. B) In step 308 CIP configuration data stored in data memory 226 at a memory address specified by a second address pointer register 204 is read, utilizing address bus 214 and second data bus 222, and is stored in the data latch 218 in step 310. C) In step 312 the CIP configuration data stored in the data latch 218 of step 310 is written into the CIP SFR (memory) address, which is a particular address in data memory 226, stored in the address latch 220, utilizing address bus 214 and first data bus 216. Thus, only three DMA transfers are required to perform indirect addressing to configure or update a CIP SFR. These DMA transfers may be repeated for each CIP SFR required to be loaded or updated, e.g., for a plurality of CIP SFRs.
Referring to Figure 4, depicted is a schematic flow diagram of the operation of the programmable arbitrary sequence DMA controller of Figure 2 reading existing configuration data from an arbitrary sequence memory location, according to specific example embodiments of this disclosure. The arbitrary sequence memory location is determined by a memory address stored in another memory location specified by in an address pointer register. In step 402 DMA transfers begin. A) In step 404 a CIP SFR address stored in memory, e.g., program memory 224, at a memory address specified by a first address pointer register 202 is read, utilizing address bus 214 and second data bus 222, and then stored in an address latch 220 in step 406 by coupling the address latch 220 to the second data bus 222 and program memory 224. B) In step 408 CIP configuration data stored in the CIP SFR which is a particular address in data memory 226, at a memory address specified by the address latch 220 is read, by coupling the address latch 220 to and utilizing address bus 214 and first data bus 216, and then is stored in the data latch 218 in step 410. C) In step 412 the CIP configuration data stored in the data latch 218 is written into a memory address of data memory 226 specified by a second address pointer register 204, utilizing address bus 214 and data bus 216. Thus, only three DMA transfers are required to perform indirect addressing to read the contents of a CIP SFR and store it in a memory location defined by the first address pointer register 202. These DMA transfers may be repeated for each CIP SFR required to be read, e.g., for a plurality of CIP SFRs.
Referring to Figure 5, depicted is a schematic block diagram of sequential and non sequential memory locations. Sequential memory locations 520, which may represent a portion of program memory 224, may be used to store the addresses of non- sequential memory locations 530-544, which may represent a portion of data memory 226. The non-sequential memory locations 530-544 may be memory-mapped to special function registers of various peripherals for storing data, e.g., configuration data. The registers may comprise at least one special function register (SFR) 560 of a core independent peripheral (CIP) 562 that has a non sequential memory location 544. Alternatively, SFR 560 may be a peripheral register. Addresses for the non- sequential memory locations 530-544 may be stored in the sequential memory locations 520a-n and accessed as described hereinabove. The non- sequential memory locations 530-544 may be used primarily for SFR 560 addresses.
The present disclosure has been described in terms of one or more embodiments, and it should be appreciated that many equivalents, alternatives, variations, and modifications, aside from those expressly stated, are possible and within the scope of the disclosure. While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein.

Claims

CLAIMS What is claimed is:
1. A programmable arbitrary sequence direct memory access (DMA) controller, comprising:
a first address pointer register;
a second address pointer register;
a data latch coupled to a first data bus;
an address latch coupled to a second data bus;
a multiplexer having a first input coupled to the first address pointer register, a second input coupled to the address latch, a third input coupled to the second address pointer register, and an output coupled to an address bus; and
control logic coupled to and controlling the first and second address pointer registers, the address latch, the multiplexer and the data latch.
2. The programmable arbitrary sequence DMA controller according to claim 1, further comprising a control register configured to control an operating mode of the DMA controller, wherein when operating in a first mode, the DMA controller is configured to use the first address pointer register for storing a source address and the second address pointer register for storing a destination address, and when operating in a second mode, the DMA controller is configured to receive a source or a destination address in the address latch from the second data bus.
3. The programmable arbitrary sequence DMA controller according to claim 2, wherein one bit in the control register determines whether the DMA controller operates in the first or second mode.
4. The programmable arbitrary sequence DMA controller according to any of claims 1-3, wherein the control logic communicates with bus arbitration logic.
5. The programmable arbitrary sequence DMA controller according to any of claims 1-4, wherein the data latch writes to and reads from the first data bus.
6. The programmable arbitrary sequence DMA controller according to any of claims 1-5, wherein the first data bus is coupled to a data memory.
7. The programmable arbitrary sequence DMA controller according to any of claims 1-6, wherein the second data bus is coupled to a program memory.
8. The programmable arbitrary sequence DMA controller according to claim 7, wherein the program memory is a non-volatile memory.
9. The programmable arbitrary sequence DMA controller according to claim 8, wherein the non-volatile memory is a flash programmable memory.
10. The programmable arbitrary sequence DMA controller according to claim 6, wherein the data memory is a random-access memory (RAM).
11. The programmable arbitrary sequence DMA controller according to any of claims 1-10, wherein the first and second data buses are coupled to a memory.
12. The programmable arbitrary sequence DMA controller according to any of claims 1-11, further comprising first and second byte counters communicating with the control logic and counting a number of data bytes transferred.
13. A method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller, said method comprising the steps of:
reading a register address stored at a memory address specified by a first address pointer register;
storing the register address in an address latch;
reading configuration data stored at another memory address specified by a second address pointer register;
storing the configuration data in a data latch; and
writing the configuration data stored in the data latch to a register at the register address stored in the address latch.
14. The method according to claim 13, wherein the register is a peripheral register.
15. The method according to claim 14, wherein the peripheral register is a special function register.
16. The method according to claim 15, wherein the special function register is associated with a core independent peripheral (CIP).
17. The method according to any of claims 13-16, further comprising the step of coupling the data latch to a first data bus and data memory.
18. The method according to any of claims 13-17, further comprising the step of coupling the address latch to a second data bus and program memory.
19. The method according to any of claims 13-18, wherein the DMA controller is configurable to operate in a direct addressing mode in which the first address pointer register stores a source address and the second address pointer register stores a destination address.
20. A method for indirect memory addressing with a programmable arbitrary sequence direct memory access (DMA) controller, said method comprising the steps of:
reading a register address stored at a memory address specified by a first address pointer register;
storing the register address in an address latch;
reading configuration data stored in a peripheral register having a memory address specified by the register address in the address latch;
storing the configuration data in a data latch; and
writing the configuration data to a memory at an address specified by a second address pointer register.
21. The method according to claim 20, wherein the register is a peripheral register.
22. The method according to claim 21, wherein the peripheral register is a special function register.
23. The method according to claim 22, wherein the special function register is associated with a core independent peripheral (CIP).
24. The method according to any of claims 20-23, further comprising the step of coupling the data latch to a first data bus and data memory.
25. The method according to any of claims 20-24, further comprising the step of coupling the address latch to a second data bus and program memory.
26. The method according to any of claims 20-25, wherein the DMA controller is configurable to operate in a direct addressing mode in which the first address pointer register stores a source address and the second address pointer register stores a destination address.
PCT/US2019/038390 2019-02-27 2019-06-21 Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals WO2020176123A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980092913.1A CN113474761B (en) 2019-02-27 2019-06-21 Programmable random sequence direct memory access controller for configuring multiple core independent peripheral devices
DE112019006932.2T DE112019006932T5 (en) 2019-02-27 2019-06-21 PROGRAMMABLE DIRECT MEMORY ACCESS CONTROLLER IN ANY ORDER FOR CONFIGURATION OF SEVERAL CORE INDEPENDENT PERIPHERAL DEVICES

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962811400P 2019-02-27 2019-02-27
US62/811,400 2019-02-27
US16/377,439 US10983936B2 (en) 2019-02-27 2019-04-23 Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals
US16/377,439 2019-04-23

Publications (1)

Publication Number Publication Date
WO2020176123A1 true WO2020176123A1 (en) 2020-09-03

Family

ID=72141137

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2019/038390 WO2020176123A1 (en) 2019-02-27 2019-06-21 Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals

Country Status (4)

Country Link
US (1) US10983936B2 (en)
CN (1) CN113474761B (en)
DE (1) DE112019006932T5 (en)
WO (1) WO2020176123A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10983936B2 (en) * 2019-02-27 2021-04-20 Microchip Technology Incorporated Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2186719A (en) * 1986-02-13 1987-08-19 Intelligent Instrumentation Peripheral dma controller for data acquisition system
US5678063A (en) * 1995-04-19 1997-10-14 National Instruments Corporation System and method for performing efficient random write operations
EP2089804A2 (en) * 2006-07-25 2009-08-19 Microchip Technology Incorporated Peripheral supplied addressing in a simple dma

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0333231B1 (en) * 1988-03-18 1995-06-14 Nec Corporation Microcomputer system capable of accessing to memory at high speed
US5513374A (en) * 1993-09-27 1996-04-30 Hitachi America, Inc. On-chip interface and DMA controller with interrupt functions for digital signal processor
US6202106B1 (en) * 1998-09-09 2001-03-13 Xilinx, Inc. Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller
US6189082B1 (en) * 1999-01-29 2001-02-13 Neomagic Corp. Burst access of registers at non-consecutive addresses using a mapping control word
US20180107591A1 (en) * 2011-04-06 2018-04-19 P4tents1, LLC System, method and computer program product for fetching data between an execution of a plurality of threads
US9489009B2 (en) * 2014-02-20 2016-11-08 Samsung Electronics Co., Ltd. System on chip, bus interface and method of operating the same
US10225944B2 (en) * 2016-01-29 2019-03-05 Ncr Corporation Mounting plinth for self-service terminal (SST)
US10360164B1 (en) * 2018-01-19 2019-07-23 Microchip Technology Incorporated Direct memory access adapter
US10983936B2 (en) * 2019-02-27 2021-04-20 Microchip Technology Incorporated Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2186719A (en) * 1986-02-13 1987-08-19 Intelligent Instrumentation Peripheral dma controller for data acquisition system
US5678063A (en) * 1995-04-19 1997-10-14 National Instruments Corporation System and method for performing efficient random write operations
EP2089804A2 (en) * 2006-07-25 2009-08-19 Microchip Technology Incorporated Peripheral supplied addressing in a simple dma

Also Published As

Publication number Publication date
DE112019006932T5 (en) 2021-12-02
CN113474761B (en) 2024-07-26
CN113474761A (en) 2021-10-01
US10983936B2 (en) 2021-04-20
US20200272588A1 (en) 2020-08-27

Similar Documents

Publication Publication Date Title
US8370606B2 (en) Switching data pointers based on context
US8037228B2 (en) Bridge device with page-access based processor interface
JP4819301B2 (en) Boot system and method using NAND flash memory
US7617383B2 (en) Circular register arrays of a computer
US20030056071A1 (en) Adaptable boot loader
US20160179388A1 (en) Method and apparatus for providing programmable nvm interface using sequencers
GB2396711A (en) Memory controller with programmable timing and control registers for data transfers which have a distinct sequence of phases.
KR19980079678A (en) Serial-Parallel Bus Interface and Method for Maximizing Data in Data Processing System
JP2008192150A (en) Method, integrated circuit, system and computer program for initializing programmable logic device, using direct memory access
JP4226085B2 (en) Microprocessor and multiprocessor system
US10002102B2 (en) Low-pin microcontroller device with multiple independent microcontrollers
EP2396723B1 (en) Microcontroller with special banking instructions and method therefor
JP6757791B2 (en) Computer device with in-memory processing and narrow data port
EP1984827B1 (en) An electronic device having a memory element and method of operation therefor
US10983936B2 (en) Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals
JP6334831B2 (en) TIGERSHARC DSP boot management chip and method
CN111742303B (en) Apparatus and method for accessing metadata when debugging a device
EP4018326A1 (en) Three tiered hierarchical memory systems
US11755211B2 (en) Overhead reduction in data transfer protocol for NAND memory
KR100534613B1 (en) apparatus and method for booting system using flash memory
US8816718B1 (en) Variable response mode for synchronous data read
CN111052100A (en) Bit-operable direct memory access
JP4363431B2 (en) Data transfer method
JP4132516B2 (en) Field programmable gate array
CN114546907B (en) Data sending and receiving method, device, equipment and storage medium

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19739480

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19739480

Country of ref document: EP

Kind code of ref document: A1