WO2020175581A1

WO2020175581A1 - Delta-sigma modulation apparatus and communication device

Info

Publication number: WO2020175581A1
Application number: PCT/JP2020/007860
Authority: WO
Inventors: 小林　隆宏
Original assignee: 京セラ株式会社
Priority date: 2019-02-26
Filing date: 2020-02-26
Publication date: 2020-09-03
Also published as: JPWO2020175581A1; JP7213947B2

Abstract

The present invention is provided with: a subtractor 1 that calculates the difference between an input digital signal and a feedback signal; an integrator 2 that integrates this difference; a quantizer 3 that quantizes an integrated value obtained by the integrator 2 and sequentially outputs a one-bit output digital signal; a one-bit DA converter 20 that converts the output digital signal to an analog signal; and a feedback unit 15 that generates a feedback signal on the basis of a current output bit value of the output digital signal and at least one past output bit value obtained before the current output bit value.

Description

\\0 2020/175 581 1 卩 (: 17 2020 /007860

Specification

Title of invention: Delta-sigma modulator and communication device

Technical field

The present disclosure relates to a delta-sigma modulator and communication equipment.

Background technology

[0002] Conventionally, a delta-sigma modulator for converting an input signal into a 1-bit digital signal has been widely used. It is known that the delta-sigma modulator can push the quantization error to the high frequency region due to the noise shaving characteristic.

[0003] A delta-sigma modulator is a subtractor that calculates the difference between an input digital signal and a feedback signal, an integrator that integrates the calculated difference, and a quantized integrated value obtained by the integrator. A quantizer for sequentially outputting output digital signals of bits and a delay device for delaying the output bit value of the output digital signals at this time and outputting as a feedback signal are provided (for example, refer to Patent Document 1).

Prior art documents

Patent literature

Patent Document 1: Japanese Patent Laid-Open No. 20 15 _ 1 1 9 2 4 7

Summary of the invention

[0005] A delta-sigma modulator according to a first aspect is a subtractor that calculates a difference between an input digital signal and a feedback signal, an integrator that integrates the difference, and an integral obtained by the multiplier. A quantizer that quantizes the values and sequentially outputs a 1-bit output digital signal, and a 1-bit that converts the output digital signal into an analog signal.

11 0 8 1^3 1 0 9) Transducer, current output cabbit value of the output digital signal, and at least one past output cabbit value obtained in the past from the current output cabbit value. And a feedback section for generating the feedback signal based on the above.

A communication device according to a second aspect is the delta-sigma modulator according to the first aspect. \¥0 2020/175581 2 卩 (: 171-1? 2020 /007860

Prepare

Brief description of the drawings

FIG. 1 is a diagram showing a configuration of a delta-sigma modulator according to an embodiment.

[Fig. 2] Fig. 2 is a diagram showing an example of an output digital signal output by a delta-sigma modulation unit and an analog signal output by a 1-bit quadrature converter according to an embodiment.

FIG. 3 is a diagram showing an example of the operation of the coefficient derivation device according to the embodiment.

FIG. 4 is a diagram showing an example of the operation of the feedback unit according to the embodiment.

[Fig. 5] Fig. 5 is a diagram illustrating a configuration example of a transmission unit of a communication device including the delta-sigma modulator according to the embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0008] In the delta-sigma modulator, the output digital signal is converted to an analog signal at the output side of the quantizer.

1: Yes 8 31 0 9) A converter may be provided. Here, when the bit rate of the output digital signal increases, the output waveform of the 1-bit tro-8 converter is affected by the previously output bit sequence, and the output waveform does not reach the amplitude that should be originally output, and the output waveform changes. There is a case of dullness.

However, a general delta-sigma modulator treats an output digital signal as an ideal rectangular wave of constant amplitude and generates a feedback signal. Therefore, there is a concern that the actual output waveform and the feedback signal waveform may deviate from each other, and an appropriate delta-sigma modulation operation may not be performed.

Therefore, the present disclosure makes it possible to perform Delta Sigma modulation operation with improved performance even when the bit rate is high.

[001 1] Embodiments will be described with reference to the drawings. In the description of the drawings, the same or similar parts are ^denoted by the same or similar symbols.

[0012] FIG. 1 is a diagram showing a configuration of a delta-sigma modulator 100 according to an embodiment.

As shown in FIG. 1, the delta-sigma modulator 100 includes a delta-sigma modulator.

It has 10 and 1-bit octal converter 20. \¥0 2020/175581 3 卩 (: 171-1? 2020 /007860

[0014] The delta-sigma modulator 10 performs delta-sigma modulation processing on a multi-bit input digital signal synchronized with a clock signal, and sequentially outputs a 1-bit output digital signal to a 1-bit tro converter 20. Output. The delta-sigma modulator 10 synchronizes at a high clock frequency (for example, 10

Above), output digital signal with high bit rate can be output.

The 1-bit eight-to-one converter 20 converts the output digital signal output from the delta-sigma modulator 10 into an analog signal, and outputs the analog signal. For example,

The 1-bit 8-to-8 converter 20 outputs a positive power supply voltage (100) when the output digital signal output bit value is “1”. On the other hand, when the output bit value of the output digital signal is “1”, the 1-bit 8-to-8 converter 20 outputs 0 [V] or a negative power supply voltage (-○○).

The delta-sigma modulation unit 10 has a subtractor 1, an integrator 2, a quantizer 3, and a feedback unit 15.

The subtractor 1 calculates the difference between the input digital signal and the feedback signal, and outputs the difference signal representing the calculated difference to the integrator 2. For example, the subtractor 1 calculates the difference by subtracting the feedback signal from the input cadence signal. Here, the feedback signal corresponds to the output digital signal (output output value) one clock before.

The integrator 2 integrates the difference signal output from the subtractor 1, and outputs the integrated value obtained by the integration to the quantizer 3.

The quantizer 3 quantizes the integrated value output from the integrator 2 and sequentially outputs a 1-bit output digital signal. For example, the quantizer 3 compares the integrated value output from the integrator 2 with the reference value, and if the integrated value is larger than the reference value, "1" is displayed. If the integrated value is less than the reference value, "_ 1 Is a binarizer that outputs each

[0020] The feedback section 15 is provided with the output digital signal (current output bit value) output from the quantizer 3 and at least one output signal obtained in the past from the current output bit value. A feedback signal is generated based on the bit value and. \¥0 2020/175 581 4 卩 (: 17 2020 /007860

The feedback unit 15 outputs the generated feedback signal to the subtractor 1.

The feedback unit 15 has a memory 4, a coefficient derivation unit 5, a delay unit 6, and a multiplication unit 7.

The memory 4 holds the output digital signal (output bit value) output from the quantizer 3. The memory 4 outputs to the coefficient derivator 5 at least one past output bit value obtained in the past from the present output bit value of the quantizer 3. For example, memory 4 has a total of 2 bits, which is the previous output cavit value obtained immediately before the present output cavit value and the pre-preceding output cabit value obtained before the present output cavit value. Output to the coefficient deriving unit 5.

[0023] The coefficient derivation unit 5 derives a coefficient based on the current output bit value output from the quantizer 3 and at least one past output bit value output from the memory 4. The coefficient derivation unit 5 outputs the derived coefficient to the multiplier 7. The coefficient is, for example, a value within the range of 0 to 1, and is a weighting coefficient used for weighting when generating the feedback signal. Details of the operation of the coefficient derivation unit 5 will be described later.

The delay unit 6 delays the current output cabbit value output from the quantizer 3, and outputs the delayed output cabbit value to the multiplier 7. For example, the delay unit 6 delays the current output bit value output from the quantizer 3 by one clock.

[0025] The multiplier 7 is an example of a feedback signal generator. The multiplier 7 multiplies the output bit value output from the delay unit 6 by the coefficient output from the coefficient derivation unit 5, and outputs the multiplication result as a feedback signal. In other words, the multiplier 7 weights the output cabbit value output from the delay device 6 using the weighting coefficient output from the coefficient deriving device 5, and outputs the weighted output cabbit value. Note that this processing is not limited to the multiplier 7 and may be a method using a table.

FIG. 2 is a diagram showing an example of an output digital signal output by the delta-sigma modulation unit 10 (quantizer 3) and an analog signal output by the 1-bit converter 20. \¥0 2020/175581 5 卩 (: 171-1? 2020 /007860

[0027] In the example shown in FIG. 2, the output digital signals are 1", "1", and "1".

, “1”, “one 1”, “1”, “one 1”, “1” and so on.

[0028] The 1-bit 8-to-8 converter 20 outputs a positive power supply voltage (100) if the output digital value of the output digital signal is "1". The 1-bit 8-to-8 converter 20 outputs 0 [V] or a negative power supply voltage (○○) if the output bit value of the output digital signal is "1 1".

[0029] Here, as the bit rate increases, the output of the 1-bit eight-to-eight converter 20 does not become an ideal rectangular wave with a constant amplitude, but the waveform is significantly distorted. Specifically, the amplitude of the analog signal corresponding to the current output bit value decreases due to the effect of the pattern of output bit values that precede the current output bit value.

[0030] In the example shown in Fig. 2, the output digital signal changes like "1!!,, ", |,, "-1,,, "|,," in the period from time 4 to time 8. Do

.. In such a case, the amplitude corresponding to the output bit value “1” in the output waveform of the 1-bit 8-to-8 converter 20 does not reach the power supply voltage (100). In other words, the output waveform of the 1-bit converter 20 does not reach the amplitude that should be output, and the output waveform becomes blunt.

The coefficient deriving unit 5 derives a coefficient according to the transition pattern of the output digital signal so that such distortion (change in amplitude) is reflected in the feedback signal.

[0032] For example, the amplitude corresponding to the current output bit value may be determined due to the influence of the previously output 2 bits. In this case, the coefficient derivation unit 5 derives the coefficient by combining the previously output 2 bits and the output bit value this time.

FIG. 3 is a diagram showing an example of the operation of the coefficient derivation unit 5. However, the operation example shown in Fig. 3 is an example, and the coefficient can be arbitrarily determined by actual operation or simulation.

[0034] As shown in Fig. 3, the coefficient derivation unit 5 has a table that determines a coefficient by a combination of the previously output 2-bit value and the current output bit value. In Figure 3 \¥0 2020/175581 6

In the example shown, when the output bit value this time is “1” and the previous output bit value is “one 1”, a weighting factor less than 1 is set. This is because the amplitude does not rise completely when the output digital signal changes from “_ 1” to “1” at high bit rate.

FIG. 4 is a diagram showing an example of the operation of the feedback unit 15.

[0036] As shown in Fig. 4, when the output bit values change in the order of "·!,,, “_·!,,, “·!,,”, the coefficient derivation unit 5 uses, for example, “0! .9” is output. In this case, the multiplier 7 multiplies the output bit value “1” at this time by the coefficient “0.9”. This causes the multiplier 7 to adjust the feedback signal and It outputs 0.9” to the subtractor as a feedback signal.

[0037] FIG. 5 is a diagram showing a configuration example of a transmission unit of a communication device including the delta-sigma modulator 100 according to an embodiment. The communication device may be any device as long as it has a function of wireless communication. The delta-sigma modulator 100 may be installed in equipment other than communication equipment.

As shown in FIG. 5, the transmission unit of the communication device according to the embodiment includes a carrier modulation unit 110, a delta-sigma modulator 100, a filter 120, and a radio 1300. And an antenna 140.

[0039] Carrier modulation section 110 performs carrier modulation on the transmission signal and outputs the transmission signal after carrier modulation to delta-sigma modulation apparatus 100.

[0040] The delta-sigma modulator 100 performs delta-sigma modulation and 1-bit conversion on the transmission signal output from the carrier modulator 110. As a result, the delta-sigma modulator 100 outputs a rectangular wave analog signal to the filter 120.

[0041] The filter 120 is a mouth-pass filter or a band-pass filter. The filter 120 performs a filtering process on the rectangular wave analog signal output from the delta-sigma modulator 100, and outputs the filtered analog signal to the radio device 130.

[0042] The radio 1330 up-converts the analog signal output from the filter 120. \¥0 2020/175 581 7

Then, the radio signal is output from the antenna 140.

The delta-sigma modulator 100 according to the above-described embodiment may be integrated on a semiconductor substrate to configure the delta-sigma modulator 100 as a semiconductor integrated circuit.

Although the embodiments have been described in detail above with reference to the drawings, the specific configuration is not limited to the above, and various design changes can be made without departing from the scope of the invention. Is.

[0045] The present application is based on Japanese Patent Application No. 209 1-0 3 2 4 0 4 (February 2 201 1 2

6th application), all the contents of which are incorporated in the present specification.

Claims

The scope of the claims

[Claim 1] A subtractor for calculating the difference between the input digital signal and the feedback signal, and an integrator for integrating the difference,

A quantizer that quantizes the integrated value obtained by the integrator and sequentially outputs a 1-bit output digital signal,

A 1-bit D A (D i g i t a l t o A n a l o g) converter that converts the output digital signal into an analog signal,

A feedback unit that generates the feedback signal based on the current output bit value of the output digital signal and at least one past output bit value obtained in the past from the current output bit value. And with

Delta-sigma modulator.

[Claim 2] The feedback unit has a memory that holds the at least one past output bit value, and the present output bit value and the at least one past output bit value stored in the memory. Adjust the feedback signal based on the combination with the value

The delta-sigma modulator according to claim 1.

[Claim 3] The feedback unit is

A coefficient derivator for deriving a coefficient based on the current output bit value and the at least one past output bit value;

A delay device that delays the current output cabit value, a feedback signal generator that applies the coefficient to the current output cabit value delayed by the delay device, and outputs the feedback signal, Have

The delta-sigma modulator according to claim 2.

[Claim 4] The at least one past outgoing bit value includes a previous outgoing bit value obtained immediately before the current outgoing bit value. \\0 2020/175581 9 (:171? 2020/007860) The delta-sigma modulator according to any one of claims 1 to 3.

[Claim 5] The at least one past outgoing bit value includes a previous outgoing bit value obtained immediately before the current outgoing bit value,

The delta-sigma modulator according to claim 3, wherein the coefficient derivation unit derives a coefficient of less than 1 when the current output bit value and the previous output bit value are different.

[Claim 6] The delta-sigma modulator according to any one of claims 1 to 5 is provided.

Communication equipment.