WO2020166160A1

WO2020166160A1 - Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Info

Publication number: WO2020166160A1
Application number: PCT/JP2019/045399
Authority: WO
Inventors: 凌平川崎
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2019-02-12
Filing date: 2019-11-20
Publication date: 2020-08-20
Also published as: JP2020129774A

Abstract

In a solid-state imaging element which performs AD conversion for each pixel, deterioration in image quality due to failure of a circuit is prevented.　An analog to digital conversion unit converts an analog pixel signal to a digital signal and holds the converted signal. A read circuit reads any bit of the digital signal as a read bit. A redundant read circuit reads any bit of the digital signal as a read bit. A failure detection unit detects whether failure occurs in a data read circuit. A read side selection unit selects one of the bit from the read circuit and the bit from the redundant read circuit in accordance with whether the failure occurs, and outputs the selected bit.

Description

Solid-state imaging device, imaging device, and method for controlling solid-state imaging device

The present technology relates to a solid-state imaging device, an imaging device, and a method for controlling the solid-state imaging device. More specifically, the present invention relates to a solid-state image sensor that converts an analog signal into a digital signal for each pixel, an image pickup apparatus, and a method for controlling the solid-state image sensor.

Conventionally, solid-state imaging devices that convert an analog signal into a digital signal for each pixel have been used in imaging devices and the like for the purpose of increasing the speed of AD (Analog to Digital) conversion. For example, a solid-state imaging device provided with a pixel circuit that generates a pixel signal, a storage unit that holds a time code when the comparison result of the pixel signal and the reference signal is inverted, and a transfer circuit that transfers the time code is proposed. (For example, refer to Patent Document 1). An analog pixel signal is converted into a digital time code for each pixel by the comparison unit and the storage unit.

International publication WO2018/037902

In the above-mentioned conventional technology, by performing AD conversion for each pixel, the speed of AD conversion can be made faster than that for AD conversion for each column. However, in the configuration in which the AD conversion is performed for each pixel, the circuit of the solid-state imaging device becomes complicated as compared with the configuration in which the AD conversion is performed for each column, and in addition to the photoelectric conversion element, the transfer transistor and the floating diffusion layer, as described above. In addition, a storage unit, a transfer circuit, etc. are further required for each pixel. Therefore, when AD conversion is performed for each pixel, the probability of circuit failure is higher than when AD conversion is performed for each column. For example, when a failure occurs in the storage unit or the transfer circuit due to an initial failure or deterioration over time, pixel data having a normal value cannot be output and a defective pixel occurs. The image quality of the image picked up by this defective pixel may deteriorate.

The present technology was created in view of such circumstances, and it is an object of the present invention to prevent deterioration of image quality due to a circuit failure in a solid-state image sensor that performs AD conversion for each pixel.

The present technology has been made in order to solve the above-described problems, and a first aspect thereof is that an analog-to-digital conversion unit that converts an analog pixel signal into a digital signal and holds the digital pixel signal, and the digital signal is used. A read circuit that reads any of the bits as a read bit, a redundant read circuit that reads any bit of the digital signal as a read bit, a failure detection unit that detects whether or not a failure has occurred in the read circuit, and the failure. According to whether or not the read bit from the read circuit and the read bit from the redundant circuit are selected and output, a solid-state image sensor, and a control method therefor are provided. is there. This brings about the effect that one of the read bits of the read circuit and the redundant read circuit is selected depending on whether or not a failure has occurred.

Further, in the first aspect, the read circuit is arranged in each of a plurality of repeaters, the plurality of repeaters are divided into a plurality of groups each including a predetermined number of repeaters, and the predetermined number of repeaters are The read side selection unit may be shared. This brings about the effect that a predetermined number of repeaters share the read side selection unit.

In the first aspect, the read circuit may be arranged in each of the plurality of repeaters, and all the plurality of repeaters may share the read side selection unit. This brings about the effect that all the repeaters share the read side selection unit.

Further, in the first aspect, a predetermined number of the read circuits and the redundant read circuits are arranged in a repeater, and the failure detection unit detects whether a failure has occurred in each of the predetermined number of read circuits. You may. This brings about the effect that the presence or absence of a failure in a predetermined number of read circuits is detected for each repeater.

Further, in the first aspect, a predetermined number of the redundant read circuits may be arranged in the repeater. This brings about an effect that it is possible to cope with a failure of a plurality of read transfer circuits.

Also, in the first aspect, a write circuit that supplies any bit of the digital signal to the analog-digital conversion unit as a write bit, and any bit of the digital signal to the analog-digital conversion unit. And a write side which supplies the digital signal by selecting either the write bit from the write circuit or the write bit from the redundant write circuit depending on whether or not the failure has occurred. A selection unit may be further included, and the failure detection unit may detect whether or not a failure has occurred in at least one of the write circuit and the read circuit. This brings about the effect that either the write circuit or the redundant write circuit is selected depending on whether or not a failure has occurred.

Further, in the first aspect, the analog-digital conversion unit includes a latch unit that holds the digital signal and a redundant latch unit, and the read circuit and the redundant read circuit read the read bit from the latch unit. May be. As a result, the read bit is read from the redundant latch unit when a failure occurs.

Further, in the first aspect, the redundant latch unit includes a redundant write latch and a redundant read latch, the redundant write circuit supplies the write bit to the redundant write latch, and the redundant read circuit, The read bit may be read from the redundant read latch. This brings about the effect that the write bit is held in the redundant write latch and the read bit is read from the redundant read latch.

Moreover, in this 1st side surface,
The pixel signal includes a reset level when the pixel is initialized and a signal level when the exposure is completed, and the read circuit and the redundant read circuit change the bit corresponding to the reset level to a reset level read bit. And the bit corresponding to the signal level is read as a signal level read bit, and the read side selection unit selects the reset level read bit from the read circuit and the redundant circuit from the redundant circuit depending on whether the failure occurs. A reset level read side selection unit that selects one of the reset level read bits, the signal level read bit from the read circuit and the signal level read bit from the redundant circuit depending on whether the failure has occurred. And a signal level read side selection unit for selecting any one of the above. This brings about the effect that the read bits corresponding to the reset level and the signal level are read.

In the first aspect, the redundant read latch includes a reset level redundant read latch and a signal level redundant read latch, and the redundant read circuit reads the reset level read bit from the reset level redundant read latch. The signal level read bit may be read from the signal level redundant read latch. This brings about the effect that the reset level read bit is read from the reset level redundant read latch and the signal level read bit is read from the signal level redundant read latch.

The second aspect of the present technology is
An analog-to-digital conversion unit that converts an analog pixel signal into a digital signal and holds the digital signal, a read circuit that reads any bit of the digital signal as a read bit, and a redundancy that reads any bit of the digital signal as a read bit. A read circuit, a failure detection unit that detects whether or not a failure has occurred in the read circuit, and either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred. The image pickup apparatus includes a read-side selection unit that selects and outputs the signal and a signal processing unit that processes the data output from the read-side selection unit. This brings about an effect that either read data or redundant data is processed depending on whether or not a failure has occurred.

It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. It is a figure showing an example of a layered structure of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a light sensing chip in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a circuit chip in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a cluster in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a repeater in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a write repeater in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a circuit in a write repeater in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a write bit transfer circuit in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a reset level read repeater in a 1st embodiment of this art. It is a circuit diagram showing an example of composition of a circuit in a reset level read repeater in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a signal level read repeater in a 1st embodiment of this art. It is a circuit diagram showing an example of composition of a pixel and a comparison part in a 1st embodiment of this art. It is a circuit diagram showing an example of composition of a voltage conversion circuit, a control circuit, and a NOR gate in a 1st embodiment of this art. It is a figure which shows an example of the connection relation of the pixel and the circuit in a cluster in 1st Embodiment of this technique. It is a block diagram showing an example of 1 composition of a storage part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a latch part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a latch circuit in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a reset level read latch and a signal level read latch in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a redundant latch circuit in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a selection part in a 1st embodiment of this art. It is a circuit diagram showing an example of composition of a writing side selection part in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a reset level reading side selection part in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a signal level read side selection part in a 1st embodiment of this art. It is a figure showing an example of control of a reset level read side selection part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a logic circuit in a 1st embodiment of this art. It is a figure for explaining control by the side of writing in a 1st embodiment of this art. It is a figure for explaining control by the side of reading in a 1st embodiment of this art. It is a flow chart which shows an example of operation of the solid-state image sensing device in a 1st embodiment of this art. It is a circuit diagram showing an example of composition of a writing side selection part in a modification of a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a selection part in a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of a selection part in a 3rd embodiment of this art. It is a block diagram showing a schematic example of composition of a vehicle control system. It is explanatory drawing which shows an example of the installation position of an imaging part.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (an example of selecting a redundant circuit when a failure occurs)
2. Second embodiment (an example in which a plurality of repeaters share a selection unit that selects a redundant circuit when a failure occurs)
3. Third embodiment (an example in which all repeaters share a selection unit that selects a redundant circuit when a failure occurs)
4. Application example to mobile

<1. First Embodiment>
[Example of configuration of imaging device]
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The image pickup apparatus 100 is an apparatus for picking up image data, and includes an optical unit 110, a solid-state image pickup element 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the imaging device 100, for example, a digital camera such as a digital still camera, a smartphone having an imaging function, a personal computer, a vehicle-mounted camera, or the like is assumed.

The optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200. The solid-state imaging device 200 is to generate image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal of a predetermined frequency that indicates the timing of image pickup. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.

The DSP circuit 120 executes predetermined signal processing on the image data from the solid-state image sensor 200. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.

The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to the operation of the user.

The bus 150 is a common path for the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.

The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.

[Configuration example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection part such as a via. In addition to vias, Cu-Cu bonding or bumps may be used for connection.

FIG. 3 is a plan view showing a configuration example of the light-receiving chip 201 according to the first embodiment of the present technology. A pixel region 210,

V drivers

231, 232, an H driver 233, and a DAC (Digital to Analog Converter) 234 are arranged on the light receiving chip 201. Further, in the pixel region 210, a plurality of pixel blocks 211 are arranged in a two-dimensional grid pattern. A plurality of pixels 220 are arranged in each pixel block 211. For example, the pixel block 211 has eight pixels 220 arranged in 2 rows×4 columns. The number of pixels in the pixel block 211 is not limited to eight. Further, one H driver 233 and one DAC 234 are arranged, but the configuration is not limited to this. For example, the H driver 233 side may be the north side, and one H driver and one DAC may be arranged on the north side. Further, although the DAC 234 is arranged on the light receiving chip 201, it is not limited to this configuration. It is also possible to arrange the DAC 234 on the circuit chip 202 and connect it to the signal line for transmitting the lamp signal on the light receiving chip 201 by Cu-Cu connection or the like.

The pixel 220 is for generating an analog signal by photoelectric conversion.

The

V drivers

231 and 232 drive the pixels 220 in the row to be read. For example, the V driver 231 drives an odd row, and the V driver 232 drives an even row. Further, the H driver 233 drives the pixels 220 in units of columns. The rows driven by the

V drivers

231 and 232 do not necessarily have to be divided into even rows and odd rows. For example,

Vdrivers

231 and 232 could drive the same row for the purpose of faster settling.

The DAC 234 generates a ramp-shaped analog ramp signal as a reference signal by DA (Digital to Analog) conversion. The DAC 234 supplies the generated reference signal to all pixels in the pixel area 210.

FIG. 4 is a block diagram showing a configuration example of the circuit chip 202 according to the first embodiment of the present technology. On the circuit chip 202,

V drivers

241 and 242,

H drivers

251 and 252,

logic circuits

260 and 270, an AD conversion circuit area 290, a time code generation section 280, and

selection sections

600 and 601 are arranged. To be done.

A plurality of clusters 300 are arranged in a two-dimensional lattice in the AD conversion circuit area 290. The cluster 300 is provided for each pixel block 211. If the number of pixel blocks 211 is B (B is an integer), B clusters 300 are also provided. The pixel blocks 211 and the clusters 300 are connected one to one.

The cluster 300 converts an analog pixel signal from the corresponding pixel block 211 into a digital signal for each pixel and supplies the digital signal to the

logic circuits

260 and 270 as pixel data.

The

V drivers

241 and 242 drive the circuits in the cluster 300 to generate digital signals. For example, the V driver 241 drives a circuit corresponding to an odd row, and the V driver 242 drives a circuit corresponding to an even row. Alternatively,

V drivers

241 and 242 drive the circuits in the same row.

The

H drivers

251 and 252 drive the transfer circuit in the cluster 300 to transfer the digital signal to the

logic circuits

260 and 270 as pixel data. For example, the H driver 251 drives a transfer circuit corresponding to an odd row of the cluster 300 to transfer a digital signal to the logic circuit 270. On the other hand, the H driver 252 drives the transfer circuit corresponding to the even row of the cluster 300 to transfer the digital signal to the logic circuit 260.

The

logic circuits

260 and 270 perform various signal processing such as CDS (Correlated Double Sampling) processing for each pixel on the transferred pixel data. Further, a mode signal MODE indicating the mode of the solid-state image sensor 200 is input to the

logic circuits

260 and 270. The modes of the solid-state imaging device 200 include a test mode and an imaging mode. Here, the test mode is a mode for detecting the presence/absence of a failure of a circuit in the AD conversion circuit area 290. On the other hand, the image pickup mode is a mode for picking up image data without detecting a failure. The test mode is set at the time of factory shipment, repair, or the like.

In the test mode, the

logic circuits

260 and 270 detect the presence/absence of a circuit failure in the AD conversion circuit area 290 based on the pixel data. On the other hand, in the imaging mode, the

logic circuits

260 and 270 perform signal processing on the pixel data and supply image data composed of the processed pixel data to the DSP circuit 120.

The time code generator 280 generates a time code indicating the time within the period when the reference signal from the DAC 234 changes. The time code generator 280 is realized by, for example, a counter. As the counter, for example, a Gray code counter is used, and the code format of the time code is, for example, Gray code. By using the gray code, it is possible to reduce the power consumption of the transfer circuit in the AD conversion circuit area 290 as compared with the case where the binary code is used. The time code generator 280 supplies the generated time code to the AD conversion circuit area 290 via the logic circuit 260.

The

selection units

600 and 601 select a part of a plurality of main bit lines in the AD conversion circuit area 290 and connect them to the logic circuit 260, the logic circuit 270, and the time code generation unit 280. Details of the wiring method and connection method of the main bit lines will be described later.

[Example of cluster configuration]
FIG. 5 is a block diagram showing a configuration example of the cluster 300 according to the first embodiment of the present technology. In this cluster 300, a plurality of comparison units 310 and

storage units

400 and 401 are arranged. The comparison unit 310 is arranged for each pixel in the pixel block 211. When there are eight pixels 220 in the pixel block 211, eight comparison units 310 are arranged. In the figure, a part of the differential input circuit in the comparison unit 310 is arranged in the light receiving chip 201 as illustrated in FIG. 12 described later.

Also, in the AD conversion circuit area 290, the repeater 500 is arranged for each column of the cluster 300. When the number of columns of the cluster 300 is C (C is an integer), C repeaters 500 are also arranged.

Further, each of the eight comparison units 310 is connected to the eight pixels 220 in the pixel block 211 corresponding to the cluster 300 on a one-to-one basis.

The repeater 500 transfers the time code from the time code generation unit 280 to the cluster 300 via the

selection units

600 and 601 and transfers the time code from the cluster 300 to the

logic circuits

260 and 270 through the

selection units

600 and 601. Is. This time code is a digital signal indicating the time within the period in which the reference signal changes in a slope shape.

The comparison unit 310 compares the pixel signal from the corresponding pixel 220 and the reference signal. The comparison unit 310 outputs the comparison result to the

storage units

400 and 401.

The

storage units

400 and 401 hold a time code (that is, a digital signal) as pixel data when the comparison result is inverted. The storage unit 400 is connected to the four comparison units 310 on the left side and holds pixel data of four pixels corresponding to the comparison units 310. The storage unit 401 is connected to the four comparison units 310 on the right side and holds pixel data of four pixels corresponding to the comparison units 310. As a result, the analog pixel signal is converted into digital pixel data. Then, the

storage units

400 and 401 output the held pixel data to the

logic circuits

260 and 270 via the repeater 500.

[Example of repeater configuration]
FIG. 6 is a block diagram showing a configuration example of the repeater 500 according to the first embodiment of the present technology. The repeater 500 includes a reset level read repeater 510, a signal level read repeater 520 and a write repeater 530.

The write repeater 530 transfers the time code from the

selection unit

600 or 601 to the

storage units

400 and 401 via the local bit line LBLW.

The reset level read repeater 510 reads the reset level from the

storage units

400 and 401 in order via the local bit line LBLR and transfers it to the

selection units

600 and 601. Here, the reset level is the level of the pixel signal when the pixel 220 is initialized.

The signal level read repeater 520 sequentially reads the signal levels from the

storage units

400 and 401 via the local bit line LBLR and transfers the signal levels to the

selection units

600 and 601. Here, the signal level is the level of the pixel signal when the exposure of the pixel 220 is completed.

[Example of write repeater configuration]
FIG. 7 is a block diagram showing a configuration example of the write repeater 530 according to the first embodiment of the present technology. The write repeater 530 includes a left side transfer control section 540, a right side transfer control section 550, and a plurality of write data transfer circuits 560. When each of

storage units

400 and 401 holds four pixels, four write data transfer circuits 560 are arranged.

The left transfer control unit 540 controls the write data transfer circuit 560 and the write redundant data transfer circuit 580 to transfer the time code to the left storage unit 400. The right side transfer control unit 550 controls the write data transfer circuit 560 and the write redundant data transfer circuit 580 to transfer the time code to the right side storage unit 401.

The write data transfer circuit 560 transfers the time code to the

storage units

400 and 401 as write data. The write data transfer circuit 560 is connected to the

selection unit

600 or 601 via N+1 (N is an integer) main bit lines WB, where N is the number of bits of the time code and one bit is a redundant circuit described later. It

Here, in the test mode, the

logic circuits

260 and 270 detect, for each of the plurality of paths for transferring the time code, of the circuits in the AD conversion circuit area 290, whether or not a failure has occurred in the circuit on that path. To do. As described above, the time code is transferred to the

storage units

400 and 401 by the write repeater 530 and held in them. Then, the reset level read repeater 510 and the signal level read repeater 520 read the time code from the

storage units

400 and 401 and transfer it to the

logic circuits

260 and 270. Therefore, when an abnormality occurs in the read time code, it can be estimated that a circuit on the path from the write repeater 530 to the reset level read repeater 510 and the signal level read repeater 520 has failed. If the time code is N bits, the time code is transferred via N routes. For each of these paths, the presence or absence of a fault in the circuit on that path is detected.

When no failure occurs, the driver such as the H driver 251 controls each of the four write data transfer circuits 560 to transfer the time code. On the other hand, when a failure occurs in the nth path out of the N paths, the driver transfers the time data via the remaining path except the path corresponding to the nth path and the redundant path. This allows the repeater 500 to transfer accurate time data even if a failure occurs in any of the N paths.

FIG. 8 is a circuit diagram showing a configuration example of a circuit in the write repeater 530 according to the first embodiment of the present technology. The write data transfer circuit 560 includes a plurality of write bit transfer circuits 570 for each cluster 300. If the time code is N (N is an integer) bits, N write bit transfer circuits 570 and redundant write bit transfer circuit 570-1 are provided.

The N write bit transfer circuits 570 transfer the N-bit time code to the

storage unit

400 or 401 under the control of the

H drivers

251 and 252. The bit from the n-th (n is an integer from 0 to N−1) write bit transfer circuit 570 is transferred via the local bit line LBLW<n>. On the other hand, the redundant write bit transfer circuit 570-1 transfers any bit in the time code to the

storage unit

400 or 401 when a failure occurs in any of the N paths.

The left-side transfer control unit 540 includes a buffer 541,

inverters

542 and 543, and a NAND (negative logical product) gate 544 for each of the N write bit transfer circuits 570 and the redundant write bit transfer circuit 570-1. That is, the buffer 541, the

inverters

542 and 543, and the NAND gate 544 are provided by N+1 each.

The inverter 543 inverts the control signal and outputs it to the buffer 541 and the inverter 543. The Nth inverter 543 inverts the control signal LENW to be transferred to the left storage unit 400.

The buffer 541 outputs a control signal. The buffer 541 and the inverter 543 are alternately arranged in series along the vertical direction, and the buffer 541 outputs the signal from the inverter 543 in the previous stage to the inverter 543 in the subsequent stage.

The inverter 542 inverts the signal from the inverter 543 and outputs it to the corresponding circuit of the N write bit transfer circuits 570 and the redundant write bit transfer circuit 570-1.

The N NAND gates 544 are connected in series along the vertical direction. The Nth NAND gate 544 outputs the NAND of the clock signal MCKIN and the control signal MCKEN for validating or invalidating the clock signal to the NAND gate 544 in the subsequent stage and the corresponding write bit transfer circuit 570. .. The nth NAND gate 544 outputs the NAND of the clock signal from the previous stage and the control signal MCKEN to the NAND gate 544 in the subsequent stage and the corresponding write bit transfer circuit 570.

The right transfer controller 550 includes a buffer 551 and

inverters

552 and 553 for each of the N write bit transfer circuits 570 and the redundant write bit transfer circuit 570-1. That is, the buffer 551 and N+1

inverters

552 and 553 are provided, respectively.

The connection configuration of the buffer 551 and the

inverters

552 and 553 is the same as that of the corresponding circuit in the left transfer control unit 540 except that the control signal RENW for transferring to the storage unit 401 on the right side is input instead of the control signal LENW. Is the same as. The control signals LENW and RENW are supplied by the H driver 251 and the like.

[Configuration example of write bit transfer circuit]
FIG. 9 is a circuit diagram showing a configuration example of the write bit transfer circuit 570 in the first embodiment of the present technology. The write bit transfer circuit 570 includes an AND (logical product) gate 571,

inverters

572 and 576,

buffers

573 and 577, a flip-flop 574, and an N-type transistor 575.

The AND gate 571 outputs the logical product of the inverted value of the clock signal from the NAND gate 544 and the control signal MCKEN to the clock terminal of the flip-flop 574.

The flip-flop 574 holds the corresponding bit in the time code. The flip-flop 574 outputs the held bit from the output terminal Q.

The inverter 572 and the buffer 573 are connected in a loop. The input terminal of the inverter 572 and the output terminal of the buffer 573 are commonly connected to the corresponding left local bit line LBLW<n>. The output terminal of the inverter 572 and the input terminal of the buffer 573 are commonly connected to the output terminal Q of the flip-flop 574. The inverter 572 inverts the input signal according to the inverted value of the control signal LENW. The buffer 573 outputs the signal from the flip-flop 574 to the left local bit line LBLW<n> according to the control signal WEN instructing the writing. The control signal WEN is supplied by the H driver 251 and the like.

The inverter 576 and the buffer 577 are connected in a loop. The input terminal of the inverter 576 and the output terminal of the buffer 577 are commonly connected to the corresponding right local bit line LBLW<n>. The output terminal of the inverter 576 and the input terminal of the buffer 577 are commonly connected to the output terminal Q of the flip-flop 574. The inverter 576 inverts the input signal according to the inverted value of the control signal RENW. The buffer 577 outputs the signal from the flip-flop 574 to the right local bit line LBLW<n> according to the control signal WEN.

The N-type transistor 575 is inserted between the output terminal Q of the flip-flop 574 and the terminal of a predetermined reference potential (ground potential or the like). As the N-type transistor 575, for example, a MOS (Metal-Oxide-Semiconductor) transistor is used. A control signal REPINI instructing initialization is input to the gate of the N-type transistor 575. The control signal REPINI is supplied by the H driver 251 and the like.

With the above connection configuration, the write bit transfer circuit 570 transfers bits to the left storage unit 400 according to the control signals WEN and LENW, and transfers bits to the right storage unit 401 according to the control signals WEN and RENW.

The circuit configuration of the redundant write bit transfer circuit 570-1 is similar to that of the write bit transfer circuit 570 illustrated in FIG.

[Configuration example of reset level read repeater]
FIG. 10 is a block diagram showing a configuration example of the reset level read repeater 510 according to the first embodiment of the present technology. The reset level read repeater 510 includes a left transfer control unit 511, a plurality of reset level read data transfer circuits 512, and a right transfer control unit 514. When each of

storage units

400 and 401 holds four pixels, four reset level read data transfer circuits 512 are arranged for each repeater 500.

The configurations of the left transfer control unit 511 and the right transfer control unit 514 are the same as the left transfer control unit 540 and the right transfer control unit 550 in the write repeater 530. The reset level read data transfer circuit 512 has the same configuration as the write data transfer circuit 560 in the write repeater 530.

The m-th reset level read data transfer circuit 512 is connected to the

selection unit

600 or 601 via the local bit line PB<m>. The reset level redundant data transfer circuit 513 is connected to the

selection unit

600 or 601 via N+1 main bit lines PB.

FIG. 11 is a circuit diagram showing a configuration example of a circuit in the reset level read repeater 510 according to the first embodiment of the present technology. In this reset level read repeater 510, N reset level read bit transfer circuits 513 and redundant reset level read bit transfer circuit 513-1 are arranged in reset level read data transfer circuit 512. The configuration of these circuits is similar to that of the write bit transfer circuit 570.

When no failure occurs, the

H drivers

251 and 252 control the N reset level read bit transfer circuits 513 to read the reset level from one of the storage unit 400 and the storage unit 401, and then reset from the other. Read the level. Then, the reset level read data transfer circuit 512 transfers the data corresponding to the reset level to the

logic circuit

260 or 270 via the

selection unit

600 or 601. Hereinafter, the data transferred by the reset level read data transfer circuit 512 will be referred to as “reset level read data”. The driver stops the transfer operation of the reset level redundant data transfer circuit 513.

On the other hand, when a failure occurs in the nth path, the driver such as the H driver 251 stops the nth of the N reset level read bit transfer circuits 513, and resets the reset level read data to the remaining circuits. Of these, N-1 bits are transferred. Further, the driver controls the redundant reset level read data transfer circuit 513-1 to transfer the remaining 1 bit of the data corresponding to the reset level.

[Configuration example of signal level read repeater]
FIG. 12 is a block diagram showing a configuration example of the signal level read repeater 520 according to the first embodiment of the present technology. The signal level read repeater 520 includes a left transfer control section 521, a plurality of signal level read data transfer circuits 522, and a right transfer control section 524. When each of the

storage units

400 and 401 holds four pixels, four signal level read data transfer circuits 522 are arranged for each repeater 500.

The configurations of the left side transfer control unit 521 and the right side transfer control unit 524 are the same as the left side transfer control unit 540 and the right side transfer control unit 550 in the write repeater 530. The configuration of the signal level read data transfer circuit 522 is similar to that of the write data transfer circuit 560 in the write repeater 530. That is, the signal level read data transfer circuit 522 is provided with N signal level read bit transfer circuits and redundant signal level read bit transfer circuits.

The m-th signal level read data transfer circuit 522 is connected to the

selection unit

600 or 601 via the local bit line DB<m>. The signal level redundant data transfer circuit 523 is connected to the

selection unit

600 or 601 via the N+1 main bit lines DB.

When no failure occurs, the

H drivers

251 and 252 control the four signal level read data transfer circuits 522 to read the signal level from one of the storage unit 400 and the storage unit 401, and then the other signal from the other. Read the level. Then, the signal level read data transfer circuit 522 transfers the data corresponding to the signal level to the

logic circuit

260 or 270 via the

selection unit

600 or 601. Hereinafter, the data transferred by the signal level read data transfer circuit 522 will be referred to as “signal level read data”. The driver stops the transfer operation of the signal level redundant data transfer circuit 523.

On the other hand, when a failure occurs in the nth path, the driver such as the H driver 251 stops the nth of the N signal level read bit transfer circuits and causes the remaining circuits to read the signal level read data. Transfer N-1 bits. Further, the driver controls the redundant signal level read bit transfer circuit to transfer the remaining 1 bit of the data corresponding to the signal level.

[Configuration Example of Pixel and Comparison Unit]
FIG. 13 is a circuit diagram illustrating a configuration example of the pixel 220 and the comparison unit 310 according to the first embodiment of the present technology. The pixel 220 includes an emission transistor 222, a photodiode 223, a transfer transistor 224, a floating diffusion layer 225, and a reset transistor 226. Further, the comparison unit 310 includes a differential input circuit 320, a voltage conversion circuit 330, a control circuit 340, a NOR (negative logical sum) gate 350, and inverters 361 and 362. The differential input circuit 320 includes differential transistors 227 and 228, a current source transistor 229, and P-

type transistors

321 and 322. The differential transistors 227 and 228 in the differential input circuit 320 and the current source transistor 229 are arranged in the light receiving chip 201, for example. The circuits after the P-

type transistors

321 and 322 are arranged in the circuit chip 202.

The photodiode 223 is to generate electric charge by photoelectric conversion. The discharging transistor 222 discharges electric charges from the photodiode 223 when discharging is instructed by a drive signal OFG from a driver such as the V driver 231.

The transfer transistor 224 transfers the electric charge from the photodiode 223 to the floating diffusion layer 225 at the end of exposure when the transfer is instructed by the transfer signal TX from the driver.

The floating diffusion layer 225 accumulates the transferred charges and generates an analog pixel signal SIG having a voltage corresponding to the accumulated charge amount.

The reset transistor 226 initializes the floating diffusion layer 225 when initialization is instructed by the reset signal AZ from the driver.

The level of the pixel signal SIG when the pixel 220 is initialized corresponds to the reset level. The level of the pixel signal SIG corresponding to the exposure amount at the end of exposure corresponds to the signal level. The circuit of the pixel 220 is not limited to the circuit illustrated in the figure as long as it can generate the pixel signal SIG. For example, the drain transistor 222 may be omitted.

Also, for example, N-type MOS transistors are used as the differential transistors 227 and 228. The drains of the differential transistors 227 and 228 are connected to the circuits in the circuit chip 202 via the

signal lines

208 and 209. The gate of the differential transistor 228 is connected to the floating diffusion layer 225, and the gate of the differential transistor 227 is connected to the DAC 234. The sources of the differential transistors 227 and 228 are commonly connected to the current source transistor 229.

The current source transistor 229 supplies a constant current. As the current source transistor 229, for example, an N-type MOS transistor is used. The current source transistor 229 is inserted between the common node of the differential transistors 227 and 228 and the terminal of a predetermined reference potential (ground potential or the like).

The P-

type transistors

321 and 322 are connected in parallel to the terminal of the power supply voltage VDDH. The gate of the P-type transistor 321 is connected to its drain and the gate of the P-type transistor 322. The drain of the P-type transistor 321 is connected to the drain of the differential transistor 227 via the signal line 208. The drain of the P-type transistor 322 is connected to the drain of the differential transistor 228 via the signal line 209, and is also connected to the voltage conversion circuit 330.

With the connection configuration described above, the circuit including the P-

type transistors

321 and 322, the differential transistors 227 and 228, and the current source transistor 229 is a differential input circuit 320 that compares the analog pixel signal SIG with the reference signal RMP. Function as.

The voltage conversion circuit 330 converts the voltage of the output signal from the differential input circuit 320. By changing to a voltage of a lower system, the low breakdown voltage transistor can be used in the circuit in the subsequent stage. As a result, the area of the circuit in the subsequent stage can be reduced. The voltage conversion circuit 330 supplies the converted signal to the control circuit 340.

The control circuit 340 accelerates the inversion transition of the output signal of the voltage conversion circuit 330.

The NOR gate 350 supplies the NAND of the signal from the control circuit 340 and the drive signal from the driver to the inverter 361.

The inverter 361 inverts the signal from the NOR gate 350 and supplies it as the comparison result XVCO to the inverter 362 and the

storage units

400 and 401.

The inverter 362 inverts the comparison result XVCO and supplies it as the comparison result VCO to the

storage unit

400 or 401.

The circuit composed of the control circuit 340, the NOR gate 350, and the inverters 361 and 362 functions as a positive feedback circuit that feeds back a part of the output to the input and accelerates the inverted transition of the comparison result VCO.

It should be noted that although the circuits in the subsequent stages of the P-

type transistors

321 and 322 are arranged on the circuit chip 202 and the other circuits are arranged on the light receiving chip 201, the circuits arranged on the respective chips are not limited to this configuration.

Also, if the voltage of the system is changed to a lower system but there is little need to reduce the circuit area of the subsequent stage, the voltage conversion circuit 330 may be omitted. In this case, it is necessary to use high breakdown voltage transistors in the subsequent circuit.

FIG. 14 is a circuit diagram showing a configuration example of the voltage conversion circuit 330, the control circuit 340, and the NOR gate 350 according to the first embodiment of the present technology.

The voltage conversion circuit 330 includes a P-type transistor 331 and N-

type transistors

332 and 333. For example, MOS transistors are used as these transistors.

The P-type transistor 331 is connected to the terminal of the power supply voltage VDDH in parallel with the P-

type transistors

321 and 322. The gate of the P-type transistor 331 is connected to the drain of the P-type transistor 322.

The N-

type transistors

332 and 333 are connected in series between the drain of the P-type transistor 331 and the terminal of the reference potential (ground potential or the like). The gate of the N-type transistor 332 is connected to the terminal of the power supply voltage VDDL lower than the power supply voltage VDDH, and the drive signal INI1 from the driver such as the V driver 241 is input to the gate of the N-type transistor 333. The connection point of the N-

type transistors

332 and 333 is connected to the control circuit 340 and the NOR gate 350.

The control circuit 340 also includes P-

type transistors

341 and 342. For example, MOS transistors are used as these transistors. P-

type transistors

341 and 342 are connected in series between the terminal of power supply voltage VDDL and the connection point of N-

type transistors

332 and 333. The drive signal INI2 from a driver such as the V driver 231 is input to the gate of the P-type transistor 341, and the feedback signal PFB from the NOR gate 350 is input to the gate of the P-type transistor 342.

The NOR gate 350 also includes P-

type transistors

355 and 356 and N-

type transistors

354 and 357. For example, MOS transistors are used as these transistors. P-

type transistors

355 and 356 are connected in series to the terminal of power supply voltage VDDL. N-

type transistors

354 and 357 are connected in parallel between P-type transistor 356 and a terminal of a reference potential (ground potential or the like).

The gates of the N-type transistor 354 and the P-type transistor 355 are commonly connected to the control circuit 340. A drive signal TESTVCO from a driver such as the V driver 241 is input to the gates of the N-type transistor 357 and the P-type transistor 356. The drive signal TESTVCO is a signal for forcibly inverting the signal at the end of AD conversion and outputting the comparison result VCO. The feedback signal PFB is output from the connection point of the N-type transistor 357 and the P-type transistor 356 to the control circuit 340.

Note that the circuit configurations of the voltage conversion circuit 330, the control circuit 340, and the NOR gate 350 are not limited to the circuits illustrated in FIG. 14 as long as the functions described in FIG. 13 can be realized.

FIG. 15 is a perspective view showing an example of a connection relationship between the pixel 220 and the comparison unit 310 according to the first embodiment of the present technology.

The coordinates of the pixel 220 in the X (X is an integer) row and the Y (Y is an integer) column in the pixel block 211 are (X, Y). The four pixels of the coordinates (0,0), (0,1), (1,0) and (1,1) on the left side are connected to the four comparison units 310 on the left side. Further, the four pixels of the coordinates (0, 2), (0, 3), (1, 2), and (1, 3) on the right side are connected to the four comparison units 310 on the right side. In the figure, “CM” indicates the comparison unit 310, and “MEM” indicates the

storage units

400 and 401.

[Example of configuration of storage unit]
FIG. 16 is a block diagram showing a configuration example of the storage unit 400 according to the first embodiment of the present technology. The storage unit 400 includes a plurality of latch units 410. When the number of comparison units 310 is four, four latch units 410 are provided.

The latch unit 410 holds the time code transferred by the repeater 500 via the local bit line LBLW as pixel data when the comparison result VCO of the corresponding comparison unit 310 is inverted. Further, the latch unit 410 outputs each of the reset level and the signal level in the held pixel data to the repeater 500 via the local bit line LBLR. The configuration of the redundant latch unit 460 is similar to that of the latch unit 410.

The driver such as the V driver 241 supplies the control signal WORD<m> to the m-th latch unit 410 and the control signal WORD<3> to the redundant latch unit 460. Further, the driver supplies N-bit control signals LATTRP and LATTRD to the three latch units 410 and the redundant latch unit 460.

The control signal WORD<m> is a signal for instructing the output of the data held in the m-th circuit (latch unit 410). The control signal LATTRP includes N control signals LATTRP<n>, and the control signal LATTRP<n> is a signal instructing the output of the n-th bit in the reset level. The control signal LATTRD includes N control signals LATTRD<n>, and the control signal LATTRD<n> is a signal instructing the output of the n-th bit in the signal level.

[Latch section configuration example]
FIG. 17 is a block diagram showing a configuration example of the latch unit 410 according to the first embodiment of the present technology. The latch unit 410 includes N latch circuits 420 and a redundant latch circuit 470.

The latch circuit 420 holds any bit in the time code. Here, the latch unit 410 is connected to the N local bit lines LBLW and the N local bit lines LBLR. The n-th local bit line LBLW<n> and the n-th local bit line LBLR<n> are connected to the n-th latch circuit 420. Each of the local bit lines LBLR<n> is not one, but includes a bit line for transferring a reset level and a bit line for transferring a signal level, as described later with reference to FIG.

Further, the control signals LATTRP<n> and LATTRD<n> are input to the nth latch circuit 420, and the control signal WORD<m> and the comparison result VCO<m> are input to the N latch circuits 420, respectively. To be done.

The N latch circuits 420 hold the N-bit time code from the repeater 500 when the comparison result VCO<m> is inverted. Then, these latch circuits 420 sequentially output the reset level and the signal level to the repeater 500. The configuration of the redundant latch circuit 470 is similar to that of the latch circuit 420.

[Latch circuit configuration example]
FIG. 18 is a block diagram showing a configuration example of the latch circuit 420 according to the first embodiment of the present technology. The latch circuit 420 includes a write latch 430, a reset level read latch 440 and a signal level read latch 450.

The write latch 430 holds any bit in the time code (that is, write data) when the comparison result VCO<m> is inverted. The write latch 430 includes inverters 431 to 434.

The inverter 431 inverts the bit transferred via the local bit line LBLW<n> when the comparison result VCO<m> is inverted from the low level to the high level. The inverter 431 outputs the inverted bit to the inverter 432.

The inverter 432 inverts the bit from the inverter 431 and outputs it to the inverters 433 and 434.

The inverter 434 inverts the bit from the inverter 432 and outputs it to the inverter 432 when the comparison result XVCO<m> is at a high level.

The inverter 433 inverts the bit from the inverter 432 and outputs it to the reset level read latch 440 and the signal level read latch 450.

Note that the circuit configuration of the write latch 430 is not limited to the circuit illustrated in the figure as long as it can hold a bit when the comparison result VCO<m> is inverted.

The reset level read latch 440 holds the bit from the write latch 430 under the control of the driver such as the V driver 241. The driver causes the reset level read latch 440 to hold the bit in the time code (that is, the reset level) when the pixel 220 is initialized. Here, the local bit line LBLR<n> includes a local bit line LBLP<n> for transferring a reset level and a local bit line LBLD<n> for transferring a signal level. The reset level read latch 440 outputs the bit to the repeater 500 via the local bit line LBLP<n>.

The signal level read latch 450 holds the bit from the write latch 430 under the control of the driver such as the V driver 241. The driver causes the signal level read latch 450 to hold the bit in the time code (that is, the signal level) at the end of the exposure. The signal level read latch 450 outputs the bit to the repeater 500 via the local bit line LBLD<n>.

FIG. 19 is a circuit diagram showing a configuration example of the reset level read latch 440 and the signal level read latch 450 according to the first embodiment of the present technology. The reset level read latch 440 includes an N-type transistor 441, a P-type transistor 442, and

inverters

443, 444 and 445. On the other hand, the signal level read latch 450 includes an N-type transistor 451, a P-type transistor 452, and

inverters

453, 454 and 455. As the N-type transistor 441, the P-type transistor 442, the N-type transistor 451, and the P-type transistor 452, for example, MOS transistors are used.

The N-type transistor 441 and the P-type transistor 442 are connected in parallel between the output terminal of the write latch 430 and the input terminal of the inverter 443. Further, the control signal LATTRP<n> is input to the gate of the N-type transistor 441, and XLATTRP<n> which is the inverted control signal LATTRP<n> is input to the gate of the P-type transistor 442.

The inverter 443 inverts the input bit and outputs it to the inverter 444.

The inverter 444 inverts the bit from the inverter 443 when the control signal LATTRP<n> is at a high level, and outputs it to the

inverters

443 and 445.

The inverter 445 inverts the bit from the inverter 444 when the control signal WORD<m> is at a high level and outputs the bit to the repeater 500 via the local bit line LBLP<n>.

The circuit configuration of the signal level read latch 450 is the same as that of the reset level read latch 440. However, the control signal LATTRD<n> is input to the signal level read latch 450, and the bit is output via the local bit line LBLD<n>.

Note that the circuit configurations of the reset level read latch 440 and the signal level read latch 450 are not limited to the configurations illustrated in the figure as long as they can hold bits in accordance with control signals.

[Configuration example of redundant latch circuit]
FIG. 20 is a block diagram showing a configuration example of the redundant latch circuit 470 according to the first embodiment of the present technology. The redundant latch circuit 470 includes a redundant write latch 471, a reset level redundant read latch 472 and a signal level redundant read latch 473.

The circuit configuration of the redundant write latch 471 is similar to that of the write latch 430 illustrated in FIG. The circuit configurations of the reset level redundant read latch 472 and the signal level redundant read latch 473 are similar to those of the reset level read latch 440 and the signal level read latch 450 illustrated in FIG. The circuit including the redundant read latch 472 and the signal level redundant read latch 473 is an example of the redundant read latch described in the claims.

[Example of configuration of selection unit]
FIG. 21 is a block diagram illustrating a configuration example of the

selection units

600 and 601 according to the first embodiment of the present technology. Each of the

selection units

600 and 601 includes a writing side selection unit 610 and a reading side selection unit 620.

The selection unit 600 includes, for example, a writing-side selection unit 610 connected to the odd-numbered repeaters 500 and a reading-side selection unit 620 connected to the even-numbered repeaters 500. On the other hand, the selection unit 601 includes a writing-side selection unit 610 connected to the even-numbered repeaters 500 and a reading-side selection unit 620 connected to the odd-numbered repeaters 500. In the figure, the odd-numbered write-side selection units 610 are arranged on the north side and the even-numbered write-side selection units 610 are arranged on the south side, but the configuration is not limited to this. It is also possible to arrange all the writing side selection units 610 on the north side or the south side. The same applies to the reading side selection unit 620.

The write side selection unit 610 selects N of the N write bit transfer circuits 570 and the redundant write bit transfer circuit 570-1 depending on whether or not a failure has occurred. When there is no failure, the write side selection unit 610 selects N write bit transfer circuits 570 and outputs the time code to those circuits. On the other hand, when a failure occurs in the nth path out of the N paths, the write side selection unit 610 causes the N−1 write bit transfer circuits 570 and the redundant write bit transfer circuit 570 excluding the circuit corresponding to the nth path. -1 and are selected and the time code is output to those circuits.

The read side selection unit 620 selects N of N+1 routes depending on whether or not a failure has occurred. The read side selection unit 620 includes a reset level read side selection unit 630 and a signal level read side selection unit 640.

When there is no failure, the reset level read side selection unit 630 selects the reset level read data from the N reset level read bit transfer circuits 513 and transfers them to the

logic circuit

260 or 270. On the other hand, when a failure occurs in the nth path of the N paths, the reset level read side selection unit 630 is redundant with the N−1 reset level read bit transfer circuits 513 excluding the circuit corresponding to the nth path. The reset level read bit transfer circuit 513-1 is selected and the data from them is transferred to the

logic circuit

260 or 270.

When there is no failure, the signal level read side selection unit 640 selects the signal level read data from the N signal level read bit transfer circuits and transfers them to the

logic circuit

260 or 270. On the other hand, when a failure occurs in the nth path out of the N paths, the signal level read side selection unit 640 determines the N-1 signal level read bit transfer circuits and the redundant signal except the circuit corresponding to the nth path. Select the level read bit transfer circuit and transfer the data from them to the

logic circuit

260 or 270.

[Example of configuration of writing side selection unit]
FIG. 22 is a circuit diagram showing a configuration example of the write side selection unit 610 according to the first embodiment of the present technology. The writing side selection unit 610 includes N selectors 611. To simplify the description, consider four selectors 611 out of N.

The selector 611 selects one of the two output destinations according to the selection signal and outputs the time code to the selected output destination. The time code generator 280 individually generates the time codes <0> to <3> and supplies them to the input terminals of the four selectors 611. Here, the selection signal is a signal instructing the output destination. Here, the time code <n> indicates the n-th bit of the time code.

The 0th selector 611 selects one of the main bit lines WB<0> and WB<1> according to the selection signal WSEL<0>, and outputs the time code <0> to the bit line.

The first selector 611 selects one of the main bit lines WB<1> and WB<2> according to the selection signal WSEL<1> and outputs the time code <1> to the bit line.

The second selector 611 selects one of the main bit lines WB<2> and WB<3> according to the selection signal WSEL<2> and outputs the time code <2> to the bit line.

The third selector 611 selects one of the main bit lines WB<3> and WB<4> according to the selection signal WSEL<3> and outputs the time code <3> to the bit line.

A write bit transfer circuit 570 is connected to each of the main bit lines WB<0> to WB<3>, and a redundant write bit transfer circuit 570-1 is connected to the main bit line WB<4>.

Further, the selector 611 is composed of, for example, N-

type transistors

612 and 614 and P-

type transistors

613 and 615. For example, MOS transistors are used as these transistors.

In the 0th selector 611, the N-type transistor 612 and the P-type transistor 613 are connected in parallel between the main bit line WB<0> and the time code generator 280. The N-type transistor 614 and the P-type transistor 615 are connected in parallel between the main bit line WB<1> and the time code generator 280.

A corresponding selection signal (WSEL<0> or the like) is input to the gate of the N-type transistor 612, and an inverted signal (XWSEL<0> or the like) of the selection signal is input to the gate of the P-type transistor 613. It A signal (XWSEL<0> or the like) obtained by inverting a corresponding selection signal is input to the gate of the N-type transistor 614, and a corresponding selection signal (WSEL<0> or the like) is input to the gate of the P-type transistor 615. To be done. The circuit configurations of the first and subsequent selectors 611 are the same as those of the zeroth selector.

Also, the selection signal is supplied by the

logic circuit

260 or 270 via a control line wired in the horizontal direction. It should be noted that this control line can be wired in the vertical direction. Further, instead of the logic circuit 260 or the like, a driver such as the H driver 251 can supply the selection signal.

When there is no failure, the

logic circuit

260 or 270 causes the main bit lines WB<0> to WB<3> to be selected by the selection signal, and the time codes <0> to <3> to be transmitted through the four write bits. Transfer to the transfer circuit 570.

On the other hand, when a failure occurs in the nth path, the logic circuit 260 or the like causes the selection signal to select the four local bit lines except the nth path. Then, the logic circuit 260 or the like transfers the time codes <0> to <3> to the three write bit transfer circuits 570 and the redundant write bit transfer circuit 570-1 via these local bit lines.

[Example of configuration of reset level read side selection unit]
FIG. 23 is a circuit diagram showing a configuration example of the reset level read side selection unit 630 according to the first embodiment of the present technology. The reset level read side selection unit 630 includes N selectors 631. To simplify the explanation, consider four selectors 631 out of N.

The selector 631 selects one of the two input sources according to the selection signal and outputs the data from the selected input source to the

logic circuit

260 or 270. Here, the selection signal is a signal indicating the input source.

The 0th selector 631 selects one of the main bit lines PB<0> and PB<1> according to the selection signal PSEL<0> and outputs the data from the bit line.

The first selector 631 selects one of the main bit lines PB<1> and PB<2> according to the selection signal PSEL<1> and outputs the data from the bit line.

The second selector 631 selects one of the main bit lines PB<2> and PB<3> according to the selection signal PSEL<2> and outputs the data from the bit line.

The third selector 631 selects one of the main bit lines PB<3> and PB<4> according to the selection signal PSEL<3> and outputs the data from the bit line.

A reset level read bit transfer circuit 513 is connected to each of the main bit lines PB<0> to PB<3>, and a redundant reset level read bit transfer circuit 513-1 is connected to the local bit line PB<4>. To be done. The circuit configuration of the selector 631 is similar to that of the selector 611.

When there is no failure, the

logic circuit

260 or 270 causes the selection signal to select the main bit lines PB<0> to PB<3> and transfers the reset level read bit from these bit lines to the logic circuit 260 or the like.

On the other hand, when a failure occurs in the n-th path, the logic circuit 260 or the like causes the selection signal to select the four main bit lines except the m-th path. Then, the logic circuit 260 or the like transfers the reset level read bits from those bit lines to the logic circuit 260 or the like.

[Example of configuration of signal level reading side selection unit]
FIG. 24 is a circuit diagram showing a configuration example of the signal level reading side selection unit 640 in the first embodiment of the present technology. The signal level read side selection unit 640 includes N selectors 641. To simplify the description, consider four selectors 641 out of N.

The selector 641 selects one of the two input sources according to the selection signal and outputs the data from the selected input source to the

logic circuit

260 or 270. Here, the selection signal is a signal indicating the input source.

The 0th selector 641 selects one of the main bit lines DB<0> and DB<1> according to the selection signal DSEL<0>, and outputs the data from the bit line.

The first selector 641 selects one of the main bit lines DB<1> and DB<2> according to the selection signal DSEL<1> and outputs the data from the bit line.

The second selector 641 selects one of the main bit lines DB<2> and DB<3> according to the selection signal DSEL<2> and outputs the data from the bit line.

The third selector 641 selects one of the main bit lines PB<3> and PB<4> according to the selection signal DSEL<3> and outputs the data from the bit line.

A signal level read bit transfer circuit is connected to each of the local bit lines DB<0> to DB<3>, and a redundant signal level read bit transfer circuit is connected to the local bit line PB<4>. The circuit configuration of the selector 641 is similar to that of the selector 611.

When there is no failure, the

logic circuit

260 or 270 causes the selection bit to select the main bit lines DB<0> to DB<3> and transfers the signal level read bit from these bit lines to the logic circuit 260 or the like.

On the other hand, when a failure occurs in the nth path, the logic circuit 260 or the like causes the selection signal to select the four main bit lines except the nth path. Then, the logic circuit 260 or the like transfers the signal level read bits from those bit lines to the logic circuit 260 or the like.

FIG. 25 is a diagram illustrating an example of control of the reset level reading side selection unit 630 according to the first embodiment of the present technology. In the figure, a is a diagram showing an example of the state of the reset level read side selection unit 630 when there is no failure. B in the figure is a diagram showing an example of the state of the reset level read side selection unit 630 when a failure occurs in the 0th path. FIG. 7C is a diagram showing an example of the state of the reset level read side selection unit 630 when a failure occurs in the first path.

As illustrated in a in the figure, when there is no failure, the

logic circuit

260 or 270 causes the main bit lines PB<0> to DB<3> to be selected by the selection signal. As a result, the reset level read bit of 4 bits is read out through those main bit lines.

On the other hand, when a failure occurs in the 0th path, the logic circuit 260 or the like causes the main bit lines PB<1> to DB<4> to be selected by the selection signal. As a result, 3 bits of the reset level read data are read out through the main bit lines PB<1> to PB<3>, and the remaining bits are read out through the local bit line DB<4>.

When a failure occurs in the first path, the logic circuit 260 or the like causes the selection signal to select the main bit lines PB<0>, PB<2>, PB<3> and PB<4>. As a result, 3 bits of the reset level read data are read out through the main bit lines PB<0>, PB<2> and PB<3>, and the remaining bits are read out through the main bit line PB<4>. Read out.

Similarly, if a failure occurs in the second or third route, the four lines except the main bit line corresponding to that route are selected. In this selection, the bit selections of the write data transfer circuit 560, the reset level read data transfer circuit 512, and the signal level read data transfer circuit 522 are synchronized.

If a circuit on the path that transfers the time code fails, AD conversion may not be performed normally, pixel data with an abnormal value may be generated, and the image quality of the image data may deteriorate. Here, the circuits whose failure is to be detected are the write bit transfer circuit 570 illustrated in FIG. 8, the reset level read bit transfer circuit 513 illustrated in FIG. 11, the signal level read bit transfer circuit (not shown), and the latch. And circuit. The latch circuit is a circuit in the latch unit 410 illustrated in FIG.

Then, when a failure occurs in the circuit, the selection unit 600 selects a redundant circuit instead of the failed circuit and transfers the time data to the redundant circuit. As a result, the time data is transferred through the circuit having no failure, and the deterioration of the image quality of the image data can be prevented. Here, the redundant circuit includes a redundant write bit transfer circuit 570-1 illustrated in FIG. 8, a redundant reset level read bit transfer circuit 513-1 illustrated in FIG. 11, and a redundant signal level read bit transfer circuit (not shown). And a redundant latch circuit. The redundant latch circuit is a circuit in the redundant latch unit 460 illustrated in FIG.

[Example of logic circuit configuration]
FIG. 26 is a block diagram showing a configuration example of the logic circuit 270 according to the first embodiment of the present technology. The logic circuit 270 includes a selector 271, a signal processing unit 272, a failure detection unit 273, and a selection control unit 274. The configuration of the logic circuit 260 is similar to that of the logic circuit 270.

The signal processing unit 272 performs various kinds of signal processing such as CDS processing and demosaic processing for obtaining the difference between the reset level and the signal level for each pixel. The signal processing unit 272 supplies each of the processed pixel data to the DSP circuit 120.

The selector 271 selects an output destination according to the mode signal MODE and outputs the pixel data of the selection unit 601. The mode signal MODE indicates any one of a plurality of modes including an imaging mode and a test mode. In the test mode, the selector 271 outputs pixel data to the failure detection unit 273, and in the imaging mode, the selector 271 outputs pixel data to the signal processing unit 272.

In the test mode, the failure detection unit 273 detects whether or not there is a failure in a circuit (such as the reset level read bit transfer circuit 513) on the path for each time code transfer path. In the test mode, for example, a predetermined test image provided with a known test pattern is captured. The pixel value of each pixel of this test image is input in advance to the failure detection unit 273 as an expected value.

In the test mode, the failure detection unit 273 compares the pixel data of the image data of the captured test image with the expected value for each pixel. Then, the failure detection unit 273 determines a pixel whose difference from the expected value exceeds a predetermined allowable value as a defective pixel, and determines that the circuit on the path corresponding to the defective pixel has a failure.

For example, assume that the connection relationship between the circuits in the cluster 300 is as illustrated in FIG. In this case, the time code is transferred via the four routes for each column of the cluster 300 (in other words, the repeater 500). Two pixels at coordinates (0,0) and (0,3) in FIG. 14 are transferred via the 0th path. Two pixels with coordinates (0,1) and (0,2) are transferred via the first path. Further, the two pixels with coordinates (1,0) and (1,3) are transferred via the second path. Also, the two pixels at coordinates (1,1) and (1,2) are transferred via the third path. Therefore, the failure detection unit 273 can identify the circuit in which the failure has occurred from the coordinates of the defective pixel. Then, the failure detection unit 273 supplies the detection result to the selection control unit 274 and the driver such as the V driver 241.

The selection control unit 274 controls the connection destinations of the

selection units

600 and 601 by the selection signals WSEL, PSEL, and DSEL based on the failure detection result.

FIG. 27 is a diagram for explaining control on the writing side according to the first embodiment of the present technology. Although there are N paths for transferring the time code, only one path and only one write bit transfer circuit 570 are provided in the figure for the purpose of simplifying the description.

The time code generator 280 generates a digital time code and supplies it to the writing side selector 610. The write bit transfer circuit 570 supplies the bit in the digital signal (that is, the time code) to the storage unit 400 in the cluster 300 as the write bit. The write bit transfer circuit 570 is an example of the write circuit described in the claims.

Also, the comparison unit 310 in the cluster 300 compares the analog pixel signal SIG with a predetermined reference signal RMP and supplies the comparison result VCO to the storage unit 400. The N write latches 430 in the storage unit 400 hold write data (that is, time code) as pixel data when the comparison result VCO is inverted. As a result, the analog pixel signal SIG is converted into a digital signal (pixel data). The cluster 300 is an example of the analog-digital conversion unit in the claims.

The failure detection unit 273 detects whether or not a failure has occurred in the path including the write bit transfer circuit 570 in the test mode. When a failure occurs, the write side selection unit 610 selects the redundant write bit transfer circuit 570-1 under the control of the selection control unit 274 and supplies any bit of the time data. Then, the redundant write bit transfer circuit 570-1 supplies the bit to the storage section 400. The redundant write bit transfer circuit 570-1 is an example of the redundant write circuit described in the claims.

The redundant write latch 471 holds the bit from the redundant write bit transfer circuit 570-1 when the comparison result VCO is inverted.

FIG. 28 is a diagram for explaining control on the reading side in the first embodiment of the present technology. Although there are N paths for transferring the time code, only one path and only one reset level read bit transfer circuit 513-1 are shown in the figure for the purpose of simplifying the description.

The N reset level read latches 440 hold the time code corresponding to the reset level. The reset level read bit transfer circuit 513 reads the bit in the digital signal (that is, the time code) as the reset level read bit and supplies it to the reset level read side selection unit 630.

The failure detection unit 273 detects whether or not a failure has occurred in the path including the reset level read bit transfer circuit 513 in the test mode. When a failure occurs, the reset level redundant read latch 472 holds any bit of the time code corresponding to the reset level. The reset level redundant bit transfer circuit 513-1 reads the bit in the digital signal (time code) as the reset level read 0 bit and supplies it to the reset level read side selection unit 630.

Then, the reset level read side selection unit 630 selects the bit from the redundant reset level read bit transfer circuit 513-1 according to the control of the selection control unit 274 and outputs it to the signal processing unit 271. The signal level read control is the same as the reset level read control illustrated in FIG.

The reset level read bit transfer circuit 513-1 and the signal level read bit transfer circuit are examples of the read unit described in the claims. The redundant reset level read bit transfer circuit 513-1 and the redundant signal level read bit transfer circuit are examples of the redundant read unit described in the claims.

As illustrated in FIGS. 27 and 28, whether or not there is a failure in the path from the write bit transfer circuit 570 to the reset level read bit transfer circuit 513 and the signal level read bit transfer circuit via the storage unit 400. To be detected. When a failure occurs, the

selection units

600 and 601 select a redundant circuit (such as the reset level redundant bit transfer circuit 513-1) and input/output data. As a result, the redundant circuit transfers the data instead of the failed circuit, so that the deterioration of the image quality due to the failure of the circuit can be prevented.

[Operation example of solid-state image sensor]
FIG. 29 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. The operation of the solid-state image sensor 200 is started, for example, when the test mode is set.

The solid-state imaging device 200 captures a test image (step S901), and the failure detection unit 273 in the solid-state imaging device 200 detects whether or not a failure has occurred in the circuit on the path for transferring the time code (step). S902).

The selection control unit 274 determines whether or not there is a failure (step S903). When there is a failure (step S903: Yes), the selection control unit 274 selects a redundant circuit (step S904).

If there is no failure (step S903: No), or after step S904, the solid-state imaging device 200 switches to the imaging mode and images the image data (step S905). After step S905, the solid-state imaging device 200 ends the operation for capturing an image.

As described above, in the first embodiment of the present technology, when a failure occurs, the read side selection unit 620 uses the redundant reset level read bit transfer circuit 513-1 instead of the bit from the failed circuit. Select the bit of. As a result, it is possible to prevent data transfer by the circuit in which the failure has occurred. As a result, it is possible to prevent the image quality of the image data from being degraded by the circuit in which the failure has occurred.

[Modification]
In the above-described first embodiment, a 1-bit redundant circuit (such as the reset level redundant bit transfer circuit 513-1) is arranged for each N-bit time code, and a failure occurs in any of the N paths. At that time, the redundant circuit transferred the time code. However, in this configuration, when a failure occurs in two or more of the N paths, the number of redundant circuits may be insufficient and the time code may be transferred by the failed circuit. The solid-state image sensor 200 of the modified example of the first embodiment is different from that of the first embodiment in that a plurality of redundant circuits are arranged for each time code.

FIG. 30 is a circuit diagram showing a configuration example of the write side selection unit 610 in the modification example of the first embodiment of the present technology. The write side selection unit 610 according to the modified example of the first embodiment includes switches 651 to 662. The switches 651 to 653 form the 0th distribution circuit 650, and the switches 654 to 656 form the 1st distribution circuit 650. The switches 657 to 659 form a second distribution circuit 650, and the switches 660 to 662 form a third distribution circuit 650.

Further, in the modification of the first embodiment, two write redundant bit transfer circuits 570-1 are arranged for every N bits. Further, a main bit line WB<5> is further wired on the write side. A redundant write bit transfer circuit 570-1 is connected to each of main bit lines WB<4> and WB<5>.

The distribution circuit 650 selects one of three output destinations according to a 3-bit selection signal and outputs a time code.

The 0th distribution circuit 650 outputs the time code <0> to any of the main bit lines WB<0> to WB<2>. The first distribution circuit 650 outputs the time code <1> to any of the main bit lines WB<1> to WB<3>. The second distribution circuit 650 outputs the time code <2> to any of the main bit lines WB<2> to WB<4>. The third distribution circuit 650 outputs the time code <3> to any of the main bit lines WB<3> to WB<5>.

The distribution circuit 650 is composed of, for example, N-

type transistors

671, 673 and 675 and P-

type transistors

672, 674 and 676. For example, MOS transistors are used as these transistors.

In the 0th distribution circuit 650, the N-type transistor 671 and the P-type transistor 672 are connected in parallel between the main bit line WB<0> and the time code generator 280. N-type transistor 673 and P-type transistor 674 are connected in parallel between main bit line WB<1> and time code generator 280. N-type transistor 675 and P-type transistor 676 are connected in parallel between main bit line WB<2> and time code generator 280.

The selection signal WSEL<0> is input to the gate of the N-type transistor 671, and the selection signal WSEL<1> is input to the gate of the P-type transistor 672. The selection signal WSEL<1> is input to the gate of the N-type transistor 673, and the selection signal WSEL<2> is input to the gate of the P-type transistor 674. The selection signal WSEL<2> is input to the gate of the N-type transistor 675, and the selection signal WSEL<0> is input to the gate of the P-type transistor 676. The configuration of the first and subsequent distribution circuits 650 is the same as that of the zeroth distribution circuit 650.

The

logic circuit

260 or 270 controls the distribution circuit 650 by setting one of the bits of the selection signals WSEL<0> to <2> to the high level and the rest to the low level, thereby controlling one of the three output destinations. To select. Similarly, for the switches 654 and thereafter, a 3-bit selection signal is input to each distribution circuit 650.

For example, when a failure occurs in the 0th and 1st paths, the logic circuit 260 or the like causes the 0th distribution circuit 650 to select the main bit line WB<2> and causes the 1st distribution circuit 650 to select the main bit line WB<2>. Select WB<3>. Further, the logic circuit 260 or the like causes the third distribution circuit 650 to select the main bit line WB<4> and the fourth distribution circuit 650 to select the main bit line WB<5>. As a result, the solid-state imaging device 200 can prevent data transfer by the circuit in which the failure has occurred, even when two of the four paths have a failure.

The redundant circuits after the redundant write bit transfer circuit 570-1, that is, the redundant reset level read bit transfer circuit 513-1, the redundant signal level read bit transfer circuit, and the redundant latch circuit illustrated in FIG. They are arranged one by one. Similarly to the write side selection unit 610, four distribution circuits 650 are arranged in the reset level read side selection unit 630 and the signal level read side selection unit 640, and four of the six main bit lines are selected. And read the data.

As described above, according to the modified example of the first embodiment of the present technology, two redundant circuits (such as the redundant write bit transfer circuit 570-1) are arranged for every N bits, so that two of the N paths are provided. Even if one of the circuits fails, it is possible to prevent data transfer by the circuit in which the failure has occurred.

<2. Second Embodiment>
In the above-described first embodiment, the write-side selection unit 610 and the read-side selection unit 620 are arranged for each repeater 500, but the larger the number of repeaters 500, the write-side selection unit 610 and the read-side selection unit. The number of each of the 620 increases. As a result, the circuit scale of the solid-state image sensor 200 may increase. The solid-state imaging device 200 of the second embodiment is different from that of the first embodiment in that a plurality of repeaters 500 share a set of a write-side selection unit 610 and a read-side selection unit 620.

FIG. 31 is a block diagram illustrating a configuration example of the

selection units

600 and 601 according to the second embodiment of the present technology. In the second embodiment, all the repeaters 500 are divided into a plurality of groups each including a plurality (eg, four) of repeaters 500. The writing side selection unit 610 and the reading side selection unit 620 are arranged one by one for each group.

A plurality of (eg, four) repeaters 500 in the group are commonly connected to the write side selection unit 610, and these repeaters 500 share the write side selection unit 610. The read side selection unit 620 is also commonly connected to a plurality of (for example, four) repeaters 500 in the group, and these repeaters 500 share the read side selection unit 620. In this configuration, the redundant circuit described above is arranged for each repeater 500, and the bit line selection pattern is shared by the plurality of repeaters 500 sharing the write side selection unit 610 and the read side selection unit 620. It should be noted that although all the write side selection units 610 are arranged on the north side and all the read side selection units 620 are arranged on the south side, the present invention is not limited to this configuration. All the write side selection units 610 may be arranged on the south side, and all the read side selection units 620 may be arranged on the north side. Further, the odd-numbered writing-side selection units 610 may be arranged on one of the south side and the north side (North side, etc.), and the even-numbered writing-side selection units 610 may be arranged on the other side (South side, etc.). The same applies to the reading side selection unit 620.

As described above, in the second embodiment of the present technology, the plurality of repeaters 500 share the write side selection unit 610 and the read side selection unit 620. As a result, the circuit scale of the solid-state imaging device 200 can be reduced as compared with the first embodiment in which the write side selection unit 610 and the read side selection unit 620 are arranged for each repeater 500.

<3. Third Embodiment>
In the above-described first embodiment, the write side selection unit 610 and the read side selection unit 620 are arranged for each repeater 500. However, as the number of repeaters 500 increases, the write side selection unit 610 and the read side selection unit 620. The number of each of the 620 increases. As a result, the circuit scale of the solid-state image sensor 200 may increase. The solid-state imaging device 200 according to the third embodiment is different from that according to the first embodiment in that all the repeaters 500 share a set of a write side selection unit 610 and a read side selection unit 620.

FIG. 32 is a block diagram showing a configuration example of the

selection units

600 and 601 according to the third embodiment of the present technology. In the selection unit 600 of the third embodiment, the write-side selection unit 610 is commonly connected to all the repeaters 500, and these repeaters 500 share the write-side selection unit 610. Further, in the selection unit 601, the read side selection unit 620 is commonly connected to all the repeaters 500, and these repeaters 500 share the read side selection unit 620. In this configuration, the above-mentioned redundant circuit is arranged for each repeater 500, and the selection pattern of the bit line is shared by the repeaters 500. ‥

As described above, in the third embodiment of the present technology, all the repeaters 500 share the write side selection unit 610 and the read side selection unit 620. As a result, the circuit scale of the solid-state imaging device 200 can be reduced as compared with the first embodiment in which the write side selection unit 610 and the read side selection unit 620 are arranged for each repeater 500.

<4. Application to mobiles>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. May be.

FIG. 33 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 33, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a voice image output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, and a steering angle of the vehicle. It functions as a steering mechanism for adjustment and a control device such as a braking device that generates a braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a winker, or a fog lamp. In this case, the body system control unit 12020 may receive radio waves or signals of various switches transmitted from a portable device that substitutes for a key. The body system control unit 12020 receives input of these radio waves or signals and controls the vehicle door lock device, power window device, lamp, and the like.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle exterior information detection unit 12030 causes the image capturing unit 12031 to capture an image of the vehicle exterior and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects in-vehicle information. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.

The microcomputer 12051 calculates a control target value of the driving force generation device, the steering mechanism or the braking device based on the information on the inside and outside of the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or impact mitigation of a vehicle, follow-up traveling based on an inter-vehicle distance, vehicle speed maintenance traveling, a vehicle collision warning, or a vehicle lane departure warning. It is possible to perform cooperative control for the purpose.

In addition, the microcomputer 12051 controls the driving force generation device, the steering mechanism, the braking device, or the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's It is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The voice image output unit 12052 transmits an output signal of at least one of a voice and an image to an output device capable of visually or audibly notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 33, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 34 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 34, the image pickup unit 12031 includes

image pickup units

12101, 12102, 12103, 12104, and 12105.

The

imaging units

12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle. The image capturing unit 12101 provided on the front nose and the image capturing unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The

imaging units

12102 and 12103 included in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that FIG. 34 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the

imaging units

12102 and 12103 provided on the side mirrors, and the imaging range 12114 indicates The imaging range of the imaging part 12104 provided in a rear bumper or a back door is shown. For example, by overlaying image data captured by the image capturing units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera including a plurality of image capturing elements, or may be an image capturing element having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). In particular, the closest three-dimensional object on the traveling path of the vehicle 12100, which travels in the substantially same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), can be extracted as a preceding vehicle by determining it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation of the driver.

For example, the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to convert three-dimensional object data regarding a three-dimensional object into another three-dimensional object such as a two-wheeled vehicle, an ordinary vehicle, a large vehicle, a pedestrian, and a utility pole. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or more than the set value and there is a possibility of collision, the microcomputer 12051 outputs the audio through the audio speaker 12061 and the display unit 12062. A driver can be assisted for avoiding a collision by outputting an alarm to the driver and performing forced deceleration or avoidance steering through the drive system control unit 12010.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the imaging units 12101 to 12104. To recognize such a pedestrian, for example, a procedure for extracting a feature point in an image captured by the image capturing units 12101 to 12104 as an infrared camera, and a pattern matching process on a series of feature points indicating the contour of an object to determine whether or not the pedestrian is a pedestrian. Is performed by the procedure for determining. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 causes the recognized pedestrian to have a rectangular contour line for emphasis. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian or the like at a desired position.

Above, an example of the vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, for example, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to prevent image quality deterioration due to a circuit failure and obtain a more easily-viewed captured image, thus reducing driver fatigue.

Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a correspondence relationship. Similarly, the matters specifying the invention in the claims and the matters having the same names in the embodiments of the present technology have a correspondence relationship. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the scope of the invention.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, or as a program for causing a computer to execute the series of procedures or a recording medium storing the program. You can catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described in the present specification are merely examples, and the effects are not limited, and there may be other effects.

In addition, the present technology may have the following configurations.
(1) An analog-digital converter that converts an analog pixel signal into a digital signal and holds the digital signal,
A read circuit that reads out any bit of the digital signal as a read bit;
A redundant read circuit for reading any bit of the digital signal as a read bit;
A failure detection unit that detects whether or not a failure has occurred in the read circuit,
A solid-state imaging device comprising: a read-side selection unit that selects and outputs either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred.
(2) The read circuit is arranged in each of a plurality of repeaters,
The plurality of repeaters, each of which is divided into a plurality of groups of a predetermined number of repeaters,
The solid-state imaging device according to (1), wherein the predetermined number of repeaters share the read side selection unit.
(3) The read circuit is arranged in each of the plurality of repeaters,
The solid-state imaging device according to (1), wherein all of the plurality of repeaters share the read side selection unit.
(4) A predetermined number of the read circuits and the redundant read circuits are arranged in a repeater,
The solid-state imaging device according to (1), wherein the failure detection unit detects whether or not a failure has occurred in each of the predetermined number of read circuits.
(5) The solid-state imaging device according to (4), in which a predetermined number of redundant read circuits are arranged in the repeater.
(6) A write circuit that supplies any bit of the digital signal to the analog-digital conversion unit as a write bit,
A redundant write circuit that supplies any bit of the digital signal to the analog-to-digital converter as a write bit;
Further comprising a write side selection unit that selects one of the write bit from the write circuit and the write bit from the redundant write circuit to supply the digital signal, depending on whether or not the failure has occurred,
The solid-state imaging device according to any one of (1) to (5), wherein the failure detection unit detects whether or not a failure has occurred in at least one of the write circuit and the read circuit.
(7) The analog-digital conversion unit includes a latch unit that holds the digital signal and a redundant latch unit,
The read circuit and the redundant read circuit are the solid-state imaging device according to (6), wherein the read bit is read from the latch unit.
(8) The redundant latch unit includes a redundant write latch and a redundant read latch,
The redundant write circuit supplies the write bit to the redundant write latch,
The solid-state imaging device according to (7), wherein the redundant read circuit reads the read bit from the redundant read latch.
(9) The pixel signal includes a reset level when the pixel is initialized and a signal level when the exposure is completed,
The read circuit and the redundant read circuit read the bit corresponding to the reset level as a reset level read bit, and read the bit corresponding to the signal level as a signal level read bit,
The read side selection unit,
A reset level read side selection unit that selects either the reset level read bit from the read circuit or the reset level read bit from the redundant circuit depending on whether or not the failure has occurred;
(8) The above-mentioned (8), further comprising: a signal level read side selection unit that selects either the signal level read bit from the read circuit or the signal level read bit from the redundant circuit depending on whether or not the failure has occurred. Solid-state image sensor.
(10) The redundant read latch includes a reset level redundant read latch and a signal level redundant read latch,
The solid-state imaging device according to (9), wherein the redundant read circuit reads the reset level read bit from the reset level redundant read latch and reads the signal level read bit from the signal level redundant read latch.
(11) An analog-digital conversion unit that converts an analog pixel signal into a digital signal and holds the digital signal,
A read circuit that reads out any bit of the digital signal as a read bit;
A redundant read circuit for reading any bit of the digital signal as a read bit;
A failure detection unit that detects whether or not a failure has occurred in the read circuit,
A read side selection unit that selects and outputs either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred, and data output from the read side selection unit. And an image pickup device including a signal processing unit that processes the image.
(12) An analog-digital conversion procedure for converting an analog pixel signal into a digital signal and holding the digital signal,
A read procedure in which the read circuit reads any bit of the digital signal as a read bit;
A redundant read procedure in which the redundant read circuit reads any bit of the digital signal as a read bit;
A failure detection procedure for detecting whether or not a failure has occurred in the read circuit,
A method of controlling a solid-state imaging device, comprising: a read-side selection procedure for selecting and outputting either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred.

100 image pickup device 110 optical part 120 DSP circuit 130 display part 140 operation part 150 bus 160 frame memory 170 storage part 180 power supply part 200 solid-state image sensor 201 light receiving chip 202 circuit chip 210 pixel area 211 pixel block 220 pixel 222 discharge transistor 223 photodiode 224 Transfer transistor 225 Floating diffusion layer 226 Reset transistor 227, 228 Differential transistor 229

Current source transistor

231, 232, 241, 242

V driver

233, 251, 252 H driver 234 DAC
260, 270

Logic circuit

271, 611, 631, 641 Selector 272 Signal processing unit 273 Failure detection unit 274 Selection control unit 280 Time code generation unit 290 AD conversion circuit area 300 Cluster 310 Comparison unit 320

Differential input circuit

321, 322, 331 , 341, 342, 355, 356, 442, 452, 613, 615, 672, 674, 676 P-type transistor 330

voltage conversion circuit

332, 333, 354, 357, 441, 451, 575, 612, 614, 671, 673. , 675 N-type transistor 340 Control circuit 350 NOR gate 361, 362, 431-434, 443-445, 453-455, 542, 543, 552, 572, 576

Inverter

400, 401 Storage section 410 Latch section 420 latch circuit 430 write latch 440 reset level read latch 450 signal level read latch 470 redundant latch circuit 471 redundant write latch 472 reset level redundant read latch 473 signal level redundant read latch 500 repeater 510 reset level read

repeater

511, 521, 540 left transfer Control unit 512 Reset level read data transfer circuit 513 Reset level read bit transfer circuit 513-1 Redundant reset level read

bit transfer circuit

514, 524, 550 Right side transfer control unit 520 Signal level read repeater 522 Signal level read data transfer circuit 530

Write repeater

541, 551, 573, 577 Buffer 544 NAND (Negative AND) Gate 560 Write Data Transfer Circuit 570 Write Bit Transfer Circuit 570-1 Redundant Write Bit Transfer Circuit 571 AND (AND) Gate 574 Flip-

Flop

600, 601 Selector 610 Write side selection unit 620 Read side selection unit 630 Reset level read side selection unit 640 Signal level read side selection unit 650 Distribution circuit 651 to 662 switch 12031 Imaging unit

Claims

An analog-to-digital conversion unit that converts an analog pixel signal into a digital signal and holds the digital signal,
A read circuit that reads out any bit of the digital signal as a read bit;
A redundant read circuit for reading any bit of the digital signal as a read bit;
A failure detection unit that detects whether or not a failure has occurred in the read circuit,
A solid-state imaging device comprising: a read-side selection unit that selects and outputs either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred.
The read circuit is arranged in each of the plurality of repeaters,
The plurality of repeaters, each of which is divided into a plurality of groups of a predetermined number of repeaters,
The solid-state imaging device according to claim 1, wherein the predetermined number of repeaters share the read side selection unit.
The read circuit is arranged in each of the plurality of repeaters,
The solid-state imaging device according to claim 1, wherein all of the plurality of repeaters share the read side selection unit.
A predetermined number of the read circuits and the redundant read circuit are arranged in a repeater,
The solid-state imaging device according to claim 1, wherein the failure detection unit detects whether or not a failure has occurred in each of the predetermined number of read circuits.
The solid-state image sensor according to claim 4, wherein a predetermined number of the redundant read circuits are arranged in the repeater.
A write circuit that supplies any bit of the digital signal to the analog-digital conversion unit as a write bit,
A redundant write circuit that supplies any bit of the digital signal to the analog-to-digital converter as a write bit;
Further comprising a write side selection unit that selects one of the write bit from the write circuit and the write bit from the redundant write circuit to supply the digital signal, depending on whether or not the failure has occurred,
The solid-state image sensor according to claim 1, wherein the failure detection unit detects whether or not a failure has occurred in at least one of the write circuit and the read circuit.
The analog-digital conversion unit includes a latch unit that holds the digital signal and a redundant latch unit,
7. The solid-state image sensor according to claim 6, wherein the read circuit and the redundant read circuit read the read bit from the latch unit.
The redundant latch unit includes a redundant write latch and a redundant read latch,
The redundant write circuit supplies the write bit to the redundant write latch,
The solid-state imaging device according to claim 7, wherein the redundant read circuit reads the read bit from the redundant read latch.
The pixel signal includes a reset level when the pixel is initialized and a signal level when the exposure is completed,
The read circuit and the redundant read circuit read the bit corresponding to the reset level as a reset level read bit, and read the bit corresponding to the signal level as a signal level read bit,
The read side selection unit,
A reset level read side selection unit that selects either the reset level read bit from the read circuit or the reset level read bit from the redundant circuit depending on whether or not the failure has occurred;
9. The signal level read side selection unit for selecting either the signal level read bit from the read circuit or the signal level read bit from the redundant circuit depending on whether or not the failure has occurred. Solid-state image sensor.
The redundant read latch comprises a reset level redundant read latch and a signal level redundant read latch,
10. The solid-state imaging device according to claim 9, wherein the redundant read circuit reads the reset level read bit from the reset level redundant read latch and reads the signal level read bit from the signal level redundant read latch.
An analog-to-digital conversion unit that converts an analog pixel signal into a digital signal and holds the digital signal,
A read circuit that reads out any bit of the digital signal as a read bit;
A redundant read circuit for reading any bit of the digital signal as a read bit;
A failure detection unit that detects whether or not a failure has occurred in the read circuit,
A read side selection unit that selects and outputs either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred, and data output from the read side selection unit. And an image pickup device including a signal processing unit that processes the image.
An analog-digital conversion procedure for converting an analog pixel signal into a digital signal and holding it
A read procedure in which the read circuit reads any bit of the digital signal as a read bit;
A redundant read procedure in which the redundant read circuit reads any bit of the digital signal as a read bit;
A failure detection procedure for detecting whether or not a failure has occurred in the read circuit,
A method of controlling a solid-state imaging device, comprising: a read-side selection procedure for selecting and outputting either the read bit from the read circuit or the read bit from the redundant circuit depending on whether or not the failure has occurred.