WO2020164201A1 - Tft阵列基板的缺陷检测方法 - Google Patents

Tft阵列基板的缺陷检测方法 Download PDF

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WO2020164201A1
WO2020164201A1 PCT/CN2019/087581 CN2019087581W WO2020164201A1 WO 2020164201 A1 WO2020164201 A1 WO 2020164201A1 CN 2019087581 W CN2019087581 W CN 2019087581W WO 2020164201 A1 WO2020164201 A1 WO 2020164201A1
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image
array substrate
denoising
tft array
pixels
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French (fr)
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陈思宇
邓宇帆
金羽锋
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/84Systems specially adapted for particular applications
    • G01N21/88Investigating the presence of flaws or contamination
    • G01N21/95Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis

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  • the present invention relates to the field of display technology, and in particular to a defect detection method of a TFT array substrate.
  • liquid crystal display devices LCD
  • cathode ray tube Cathode Ray Tube, CRT
  • the liquid crystal display device has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • backlight liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle is to place liquid crystal molecules between two parallel glass substrates. There are many small vertical and horizontal wires in the middle of the substrate, and the liquid crystal molecules are controlled to change the direction by energizing or not, and the light from the backlight module is refracted to produce a picture.
  • a liquid crystal display panel consists of a color filter (CF) substrate, a thin film transistor (TFT) array substrate, and a liquid crystal (Liquid Crystal, LC) sandwiched between the color filter substrate and the thin film transistor array substrate.
  • sealant frame (Sealant) its molding process generally includes: the front-stage array process (film, yellow light, etching and peeling), the middle-stage cell process (TFT array substrate and color film substrate bonding) and after Segment module assembly process (drive chip and printed circuit board pressing).
  • the front-end array process is mainly to form TFT substrates to control the movement of liquid crystal molecules;
  • the middle-stage cell-forming process is mainly to add liquid crystal between the TFT array substrate and the color film substrate;
  • the back-end module assembly process is mainly to drive the chip pressing
  • the integration with the printed circuit board drives the rotation of liquid crystal molecules to display images.
  • the TFT array substrate when the TFT array substrate is manufactured, defects are often formed on the TFT array substrate, including point defects, fibrous defects, irregular foreign body defects, color halo defects, etc. If the defective TFT array substrate is combined with The color film substrate is combined into a cell, and the finally produced liquid crystal display panel will have display defects. Therefore, in the prior art, the TFT array substrate is tested for defects to identify the defect position and type on the TFT array substrate before the cell is formed.
  • the texture background of the surface image of the TFT array substrate is generally eliminated, but due to the truncation effect, it will affect Eliminate the effect of TFT array substrate surface texture background, thereby affecting the effect of defect extraction, so that the existing defect detection methods of TFT array substrate can detect relatively large defects and cannot effectively identify the defect types of TFT array substrates. .
  • the purpose of the present invention is to provide a defect detection method for a TFT array substrate, which can simply and accurately detect the types of defects on the TFT array substrate.
  • the present invention provides a defect detection method for a TFT array substrate, which includes the following steps:
  • Step S1 Provide a TFT array substrate, and obtain an original image of the TFT array substrate;
  • Step S2 performing denoising processing on the original image to generate a denoising image
  • Step S3 Perform regular structure texture background removal processing on the denoised image to generate an image to be determined
  • Step S4 performing defect extraction on the to-be-determined image to obtain description parameters of the defect of the TFT array substrate;
  • Step S5 using the description parameter of the defect of the TFT array substrate and the preset reference description parameter to determine the type of the defect of the TFT array substrate.
  • step S1 an automatic optical inspection machine is used to obtain the original image of the TFT array substrate.
  • the original image of the TFT array substrate includes a plurality of original pixels arranged in an array.
  • the step S2 is specifically: processing the original image using a full variational model to form a denoised image, the denoising image including a plurality of denoising pixels corresponding to a plurality of original pixels and arranged in an array.
  • the pixel values of the multiple denoising pixels of the denoising image are Wherein, ⁇ is a preset parameter, S i is the i-th pixel value of the plurality of pixels denoising denoising pixels, G i a plurality of original pixels with the pixels corresponding to the i-th denoising the i-th original pixel Pixel value, In order to perform the first-order difference operation on the pixel values of multiple denoising pixels of the denoising image, the difference operation value corresponding to the i-th denoising pixel, Means When it is the minimum value, the pixel values of multiple denoising pixels of the corresponding denoising image, i is a positive integer.
  • the step S3 includes:
  • Step S31 Obtain the smallest repeating unit in the denoising image
  • Step S32 Divide the denoising image into a plurality of blocks to be processed arranged in an array according to the minimum repeating unit, adjacent blocks to be processed are connected, the sizes of the multiple blocks to be processed are the same, and the multiple blocks to be processed Including a reference block that coincides with a minimum repeating unit and a block to be calculated except the reference block;
  • Step S33 Calculate the corresponding cross power spectra between the multiple blocks to be calculated and the reference block using the preset cross power spectrum calculation formula, and perform inverse Fourier transform on the multiple cross power spectra to generate multiple cross power spectra correspondingly.
  • Correlation surface function take the abscissa and ordinate corresponding to the peak value in each cross-correlation surface function as the horizontal displacement and vertical displacement of the block to be calculated corresponding to the cross-correlation surface function relative to the reference block, according to The horizontal displacement and vertical displacement of each block to be calculated relative to the reference block obtain the correspondence between each denoising pixel in each block to be calculated and each denoising pixel in the reference block, and then The pixel values of the multiple denoising pixels in the multiple modules to be calculated of the noisy image are formed by subtracting the pixel values of the corresponding denoising pixels in the reference block and taking the pixel values of the multiple denoising pixels in the reference block to 0.
  • An image to be determined where the image to be determined includes a plurality of
  • the preset cross power spectrum calculation formula is:
  • P k (u, v) is the value of the u-th row and v-th column in the cross power spectrum
  • F 0 (u, v) is the u-th row and v-th row in the matrix generated by Fourier transform of the reference block
  • the value of the column, F k (u, v) is the value of the u-th row and the v-th column of the matrix generated after Fourier transform is performed on the k-th to-be-calculated block among the multiple to-be-calculated blocks
  • It is the conjugate complex number of F k (u, v), u, v, and k are all positive integers.
  • the step S4 specifically includes:
  • Step S41 Perform binarization processing on the pixel values of multiple pixels to be determined in the image to be determined by using a preset binarization processing formula
  • Step S42 Calculate the row coordinates and column coordinates of the centroid of the image to be determined in the image to be determined, and mark the pixel to be determined with a pixel value of 1 in the image to be determined after binarization processing as a defective pixel;
  • Step S43 Obtain the distance between each defective pixel and the centroid, and form a histogram of the corresponding relationship between the distance between the defective pixel and the centroid and the number of defective pixels as a description parameter of the defect of the TFT array substrate.
  • the preset binarization processing formula is:
  • I(x,y) is the pixel value of the processed pixel in the xth row and yth column in the image to be determined before binarization
  • I′(x,y) is the pixel value of the xth row and yth column in the image to be determined
  • T is a preset threshold
  • x and y are both positive integers.
  • the step S5 specifically includes: providing multiple preset reference histograms as preset multiple reference description parameters, each reference histogram corresponding to a defect type, and calculating the correspondence between the distance between the defective pixel and the centroid and the number of defective pixels
  • the multiple Bhattacharyya distances between the histogram of the relationship and the multiple reference histograms, and the defect type corresponding to the reference histogram corresponding to the maximum value of the multiple Bhattachya distances is selected as the defect type of the TFT array substrate.
  • the present invention also provides a defect detection method for a TFT array substrate, which includes the following steps:
  • Step S1 Provide a TFT array substrate, and obtain an original image of the TFT array substrate;
  • Step S2 performing denoising processing on the original image to generate a denoising image
  • Step S3 Perform regular structure texture background removal processing on the denoised image to generate an image to be determined
  • Step S4 performing defect extraction on the to-be-determined image to obtain description parameters of the defect of the TFT array substrate;
  • Step S5 using the description parameter of the defect of the TFT array substrate and the preset reference description parameter to determine the type of the defect of the TFT array substrate.
  • step S1 an automatic optical inspection machine is used to obtain the original image of the TFT array substrate.
  • the original image of the TFT array substrate includes a plurality of original pixels arranged in an array.
  • the defect detection method of the TFT array substrate of the present invention obtains the original image of the TFT array substrate and performs denoising processing on the original image to generate a denoising image, and performing regular structure texture background removal processing on the denoising image to generate a Determine the image, extract the defect of the image to be determined to obtain the description parameter of the defect of the TFT array substrate, use the description parameter of the defect of the TFT array substrate and the preset reference description parameter to judge the type of the defect of the TFT array substrate, which can be simple and accurate Groundly detect the types of defects on the TFT array substrate.
  • FIG. 1 is a flowchart of the defect detection method of the TFT array substrate of the present invention
  • step S2 of the TFT array substrate of the present invention is a schematic diagram of step S2 of the TFT array substrate of the present invention.
  • 3 to 5 are schematic diagrams of step S3 of the TFT array substrate of the present invention.
  • the present invention provides a defect detection method for a TFT array substrate, which includes the following steps:
  • Step S1 Provide a TFT array substrate, and obtain an original image of the TFT array substrate.
  • an automatic optical inspection machine (AOI) is used to obtain the original image of the TFT array substrate.
  • the original image of the TFT array substrate includes a plurality of original pixels arranged in an array.
  • Step S2 performing denoising processing on the original image to generate a denoising image 10 as shown in FIG. 2.
  • the step S2 is specifically: processing the original image by using the total variation model to form a denoised image 10, the denoising image 10 includes a plurality of arrays corresponding to a plurality of original pixels. Denoising pixels.
  • the pixel values of the multiple denoising pixels of the denoising image 10 are Wherein, ⁇ is a preset parameter, S i is the i-th pixel value of the plurality of pixels denoising denoising pixels, G i a plurality of original pixels with the pixels corresponding to the i-th denoising the i-th original pixel Pixel value, In order to perform the first-order difference operation on the pixel values of the multiple denoising pixels of the denoising image 10, the difference operation value corresponding to the i-th denoising pixel, Means When it is the minimum value, the pixel values of the multiple denoising pixels of the corresponding denoising image 10, i is a positive integer.
  • Step S3 referring to Fig. 5, performing regular structure texture background removal processing on the denoising image 10 to generate an image 20 to be determined.
  • the step S3 includes:
  • Step S31 referring to FIG. 3, obtain the smallest repeating unit 11 in the denoising image 10.
  • scanning can be started from the upper left corner of the denoising image 10, and the first repeating unit with the smallest area is selected as the smallest repeating unit 11.
  • Step S32 referring to FIG. 4, the denoising image 10 is divided into a plurality of blocks to be processed arranged in an array according to the minimum repeating unit 11, adjacent blocks to be processed are connected, and the sizes of the multiple blocks to be processed are the same ,
  • the multiple blocks to be processed include a reference area 12 block overlapping a minimum repeating unit 11 and a block to be calculated 13 except the reference block.
  • Step S33 Calculate the corresponding cross power spectra between the multiple blocks to be calculated and the reference block using the preset cross power spectrum calculation formula, and perform inverse Fourier transform on the multiple cross power spectra to generate multiple cross power spectra correspondingly.
  • Correlation surface function take the abscissa and ordinate corresponding to the peak value in each cross-correlation surface function as the horizontal displacement and vertical displacement of the block to be calculated corresponding to the cross-correlation surface function relative to the reference block, according to The horizontal displacement and vertical displacement of each block to be calculated relative to the reference block obtain the correspondence between each denoising pixel in each block to be calculated and each denoising pixel in the reference block, and then The pixel values of the multiple denoising pixels in the multiple modules to be calculated of the noisy image are formed by subtracting the pixel values of the corresponding denoising pixels in the reference block and taking the pixel values of the multiple denoising pixels in the reference block to 0.
  • the image to be determined includes a plurality of pixels to be
  • P k (u, v) is the value of the u-th row and v-th column in the cross power spectrum
  • F 0 (u, v) is the u-th row and v-th row in the matrix generated by Fourier transform of the reference block
  • the value of the column, F k (u, v) is the value of the u-th row and the v-th column of the matrix generated after Fourier transform is performed on the k-th to-be-calculated block among the multiple to-be-calculated blocks
  • It is the conjugate complex number of F k (u, v), u, v, and k are all positive integers.
  • Step S4 Perform defect extraction on the to-be-determined image 20 to obtain defect description parameters of the TFT array substrate.
  • step S4 specifically includes:
  • Step S41 Binarize the pixel values of the multiple pixels to be determined in the image 20 to be determined by using a preset binarization processing formula.
  • Step S42 Calculate the row coordinates and column coordinates of the centroid of the image to be determined 20 in the image to be determined 20, and mark the pixel to be determined with a pixel value of 1 in the image to be determined 20 after binarization processing as a defective pixel.
  • Step S43 Obtain the distance between each defective pixel and the centroid, and form a histogram of the corresponding relationship between the distance between the defective pixel and the centroid and the number of defective pixels as a description parameter of the defect of the TFT array substrate.
  • the preset binarization processing formula is:
  • I (x, y) is the pixel value of the processed pixel in the x-th row and y-th column in the image 20 to be determined before binarization processing
  • I'(x, y) is the x-th row y in the image 20 to be determined
  • T is a preset threshold
  • x and y are both positive integers.
  • Step S5 using the description parameter of the defect of the TFT array substrate and the preset reference description parameter to determine the type of the defect of the TFT array substrate.
  • the step S5 specifically includes: providing multiple preset reference histograms as preset multiple reference description parameters, each reference histogram corresponding to a defect type, and calculating the size of the defective pixel and the centroid and the defective pixel
  • the multiple Bhattacharyya distances between the histogram corresponding to the quantity and the multiple reference histograms, and the defect type corresponding to the reference histogram corresponding to the maximum value of the multiple Bhattachya distances is selected as the defect type of the TFT array substrate.
  • the defect detection method of the TFT array substrate of the present invention performs denoising processing on the original image after acquiring the original image of the TFT array substrate to generate a denoising image, and performing regular structure, texture, and background removal processing on the denoising image to produce a pending determination
  • the image specifically uses the mutual power of the image to remove the regular TFT unit background in the denoising image, and then performs defect extraction on the image to be determined to obtain the description parameters of the defect of the TFT array substrate, specifically using the distance between the defective pixel and the center of mass and The histogram of the corresponding relationship between the number of defective pixels is used as the description parameter of the defect of the TFT array substrate.
  • the description parameter of the defect of the TFT array substrate and the preset reference description parameter are used to determine the type of the defect of the TFT array substrate.
  • the histogram of the corresponding relationship between the distance of the center of mass and the number of defective pixels is calculated with multiple reference histograms for the Bhattachya distance, and the defect type corresponding to the reference histogram corresponding to the maximum value of the multiple Bhattachya distances is selected as the TFT array substrate Defect type, can detect the defect type on the TFT array substrate simply and accurately. Compared with the prior art, there is no need for manual defect detection of the TFT array substrate, which saves production costs, and does not require a large number of image samples and complex parameter calculations. Meet the actual production needs.
  • the defect detection method of the TFT array substrate of the present invention obtains the original image of the TFT array substrate and performs denoising processing on the original image to generate a denoised image, and performing regular structure texture background removal processing on the denoised image produces a pending determination Image, perform defect extraction on the image to be determined to obtain the description parameters of the defect of the TFT array substrate, and use the description parameters of the defect of the TFT array substrate and the preset reference description parameters to determine the type of the defect of the TFT array substrate, which can simply and accurately Detect the types of defects on the TFT array substrate.

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Abstract

本发明提供一种TFT阵列基板的缺陷检测方法。本发明的TFT阵列基板的缺陷检测方法在获取TFT阵列基板的原始图像后对原始图像进行去噪处理产生去噪图像,对去噪图像进行规则结构纹理背景去除处理产生待判定图像,对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数,利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型,能够简单准确地对TFT阵列基板上的缺陷类型进行检测。

Description

TFT阵列基板的缺陷检测方法 技术领域
本发明涉及显示技术领域,尤其涉及一种TFT阵列基板的缺陷检测方法。
背景技术
在显示技术领域,液晶显示装置(Liquid Crystal Display,LCD)等平板显示装置已经逐步取代阴极射线管(Cathode Ray Tube,CRT)显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点,得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置,其包括液晶显示面板及背光模组(backlight module),其工作原理是在两片平行的玻璃基板当中放置液晶分子,两片玻璃基板中间有许多垂直和水平的细小电线,通过通电与否来控制液晶分子改变方向,将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(Color Filter,CF)基板、薄膜晶体管(Thin Film Transistor,TFT)阵列(Array)基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(Liquid Crystal,LC)及密封胶框(Sealant)组成,其成型工艺一般包括:前段阵列制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT阵列基板与彩膜基板贴合)及后段模组组装制程(驱动芯片与印刷电路板压合)。其中,前段阵列制程主要是形成TFT基板,以便于控制液晶分子的运动;中段成盒制程主要是在TFT阵列基板与彩膜基板之间添加液晶;后段模组组装制程主要是驱动芯片压合与印刷电路板的整合,进而驱动液晶分子转动,显示图像。
现有技术中在制作TFT阵列基板时,TFT阵列基板上往往会形成缺陷,包括点状缺陷、纤维状缺陷、不规则异物缺陷、彩晕状缺陷等等,若将有缺陷的TFT阵列基板与彩膜基板对组成盒,最终制得的液晶显示面板将存在显示不良,因此现有技术中会在对组成盒前对TFT阵列基板进行缺陷检测以识别TFT阵列基板上的缺陷位置及类型。现有的TFT阵列基板的缺陷检测方法中,由于TFT阵列基板存在依次排列的重复结构,为了便于提取缺陷,一般会对TFT阵列基板表面图像的纹理背景进行消除,但由于存在截断效应,会影响消除TFT阵列基板表面纹理背景的效果,从而影响缺陷的提取效果,使得现有的TFT阵列基板的缺陷检测方法进能够对比较大的 缺陷实现检测并不能对TFT阵列基板的缺陷类型进行有效的识别。
发明内容
本发明的目的在于提供一种TFT阵列基板的缺陷检测方法,能够简单准确地对TFT阵列基板上的缺陷类型进行检测。
为实现上述目的,本发明提供一种TFT阵列基板的缺陷检测方法,包括如下步骤:
步骤S1、提供TFT阵列基板,获取所述TFT阵列基板的原始图像;
步骤S2、对所述原始图像进行去噪处理产生去噪图像;
步骤S3、对所述去噪图像进行规则结构纹理背景去除处理产生待判定图像;
步骤S4、对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数;
步骤S5、利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型。
所述步骤S1中,利用自动光学检测机获取TFT阵列基板的原始图像。
所述TFT阵列基板的原始图像包括呈阵列式排布的多个原始像素。
所述步骤S2具体为:利用全变分模型对原始图像进行处理从而形成去噪图像,所述去噪图像包括分别与多个原始像素对应且呈阵列式排布的多个去噪像素。
所述去噪图像的多个去噪像素的像素值为
Figure PCTCN2019087581-appb-000001
Figure PCTCN2019087581-appb-000002
其中,λ为预设的参数,S i为多个去噪像素中第i个去噪像素的像素值,G i为多个原始像素中与第i个去噪像素对应的第i个原始像素的像素值,
Figure PCTCN2019087581-appb-000003
为对去噪图像的多个去噪像素的像素值进行一阶差分运算后第i个去噪像素对应的差分运算值,
Figure PCTCN2019087581-appb-000004
表示
Figure PCTCN2019087581-appb-000005
为最小值时对应的去噪图像的多个去噪像素的像素值,i为正整数。
所述步骤S3包括:
步骤S31、获取去噪图像中的最小重复单元;
步骤S32、依据最小重复单元将去噪图像划分为阵列排布的多个待处理区块,相邻的待处理区块相连接,多个待处理区块的尺寸相同,多个待处理区块包括与一最小重复单元重合的参考区块及除了参考区块外的待计算区块;
步骤S33、利用预设的互功率谱计算公式分别计算多个待计算区块与参考区块之间的对应的互功率谱,对多个互功率谱进行傅里叶逆变换对应产生多个互相关曲面函数,取每个互相关曲面函数中的峰值对应的横坐标及纵坐标分别作为该互相关曲面函数对应的待计算区块相对于参考区块的水平位移量及竖直位移量,依据每一待计算区块相对于参考区块的水平位移量及竖直位移量获取每一待计算区块中的各去噪像素与参考区块中各去噪像素之间的对应关系,将去噪图像的多个待计算模块中多个去噪像素的像素值分别减去参考区块中对应的去噪像素的像素值并将参考区块中多个去噪像素的像素值取0而形成待判定图像,所述待判定图像包括阵列排布的多个待判定像素。
所述预设的互功率谱计算公式为:
Figure PCTCN2019087581-appb-000006
其中,P k(u,v)为互功率谱中第u行第v列的值,F 0(u,v)为对参考区块进行傅里叶变换后产生的矩阵中第u行第v列的值,F k(u,v)为对多个待计算区块中第k个待计算区块进行傅里叶变换后产生的矩阵中第u行第v列的值,
Figure PCTCN2019087581-appb-000007
为F k(u,v)的共轭复数,u、v、k均为正整数。
所述步骤S4具体包括:
步骤S41、利用预设的二值化处理公式对所述待判定图像的多个待判定像素的像素值进行二值化处理;
步骤S42、计算所述待判定图像的质心在待判定图像中的行坐标及列坐标,将待判定图像中进行二值化处理后像素值为1的待判定像素记为缺陷像素;
步骤S43、获取每个缺陷像素与质心的距离,形成缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图作为TFT阵列基板的缺陷的描述参 数。
所述预设的二值化处理公式为:
Figure PCTCN2019087581-appb-000008
其中,I(x,y)为待判定图像中第x行第y列的处理像素进行二值化处理前的像素值,I′(x,y)为待判定图像中第x行y列的待判定像素进行二值化处理后的像素值,T为预设的阈值,x、y均为正整数。
所述步骤S5具体为:提供预设的多个参考直方图作为预设的多个参考描述参数,每一参考直方图与一缺陷类型对应,计算缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图同多个参考直方图之间的多个巴氏距离,选取多个巴氏距离中的最大值对应的参考直方图所对应的缺陷类型作为TFT阵列基板的缺陷类型。
本发明还提供一种TFT阵列基板的缺陷检测方法,包括如下步骤:
步骤S1、提供TFT阵列基板,获取所述TFT阵列基板的原始图像;
步骤S2、对所述原始图像进行去噪处理产生去噪图像;
步骤S3、对所述去噪图像进行规则结构纹理背景去除处理产生待判定图像;
步骤S4、对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数;
步骤S5、利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型。
所述步骤S1中,利用自动光学检测机获取TFT阵列基板的原始图像。
所述TFT阵列基板的原始图像包括呈阵列式排布的多个原始像素。
本发明的有益效果:本发明的TFT阵列基板的缺陷检测方法在获取TFT阵列基板的原始图像后对原始图像进行去噪处理产生去噪图像,对去噪图像进行规则结构纹理背景去除处理产生待判定图像,对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数,利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型,能够简单准确地对TFT阵列基板上的缺陷类型进行检测。
附图说明
为了能更进一步了解本发明的特征以及技术内容,请参阅以下有关本发明的详细说明与附图,然而附图仅提供参考与说明用,并非用来对本发明加以限制。
附图中,
图1为本发明的TFT阵列基板的缺陷检测方法的流程图;
图2为本发明的TFT阵列基板的步骤S2的示意图;
图3至图5为本发明的TFT阵列基板的步骤S3的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果,以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1,本发明提供一种TFT阵列基板的缺陷检测方法,包括如下步骤:
步骤S1、提供TFT阵列基板,获取所述TFT阵列基板的原始图像。
具体地,所述步骤S1中,利用自动光学检测机(AOI)获取TFT阵列基板的原始图像。
具体地,所述TFT阵列基板的原始图像包括呈阵列式排布的多个原始像素。
步骤S2、对所述原始图像进行去噪处理产生如图2所示的去噪图像10。
具体地,所述步骤S2具体为:利用全变分模型对原始图像进行处理从而形成去噪图像10,所述去噪图像10包括分别与多个原始像素对应且呈阵列式排布的多个去噪像素。
具体地,所述去噪图像10的多个去噪像素的像素值为
Figure PCTCN2019087581-appb-000009
其中,λ为预设的参数,S i为多个去噪像素中第i个去噪像素的像素值,G i为多个原始像素中与第i个去噪像素对应的第i个原始像素的像素值,
Figure PCTCN2019087581-appb-000010
为对去噪图像10的多个去噪像素的像素值进行一阶差分运算后第i个去噪像素对应的差分运算值,
Figure PCTCN2019087581-appb-000011
表示
Figure PCTCN2019087581-appb-000012
为最小值时对应的去噪图像10的多个去噪像素的像素值,i为正整数。
步骤S3、请参阅图5,对所述去噪图像10进行规则结构纹理背景去除 处理产生待判定图像20。
具体地,所述步骤S3包括:
步骤S31、请参阅图3,获取去噪图像10中的最小重复单元11。此步骤中,可从去噪图像10的左上角开始扫描,选取第一个面积最小的重复单元作为最小重复单元11。
步骤S32、请参阅图4,依据最小重复单元11将去噪图像10划分为阵列排布的多个待处理区块,相邻的待处理区块相连接,多个待处理区块的尺寸相同,多个待处理区块包括与一最小重复单元11重合的参考区12块及除了参考区块外的待计算区块13。
步骤S33、利用预设的互功率谱计算公式分别计算多个待计算区块与参考区块之间的对应的互功率谱,对多个互功率谱进行傅里叶逆变换对应产生多个互相关曲面函数,取每个互相关曲面函数中的峰值对应的横坐标及纵坐标分别作为该互相关曲面函数对应的待计算区块相对于参考区块的水平位移量及竖直位移量,依据每一待计算区块相对于参考区块的水平位移量及竖直位移量获取每一待计算区块中的各去噪像素与参考区块中各去噪像素之间的对应关系,将去噪图像的多个待计算模块中多个去噪像素的像素值分别减去参考区块中对应的去噪像素的像素值并将参考区块中多个去噪像素的像素值取0而形成如图5所示的待判定图像,所述待判定图像包括阵列排布的多个待判定像素。
进一步地,所述预设的互功率谱计算公式为:
Figure PCTCN2019087581-appb-000013
其中,P k(u,v)为互功率谱中第u行第v列的值,F 0(u,v)为对参考区块进行傅里叶变换后产生的矩阵中第u行第v列的值,F k(u,v)为对多个待计算区块中第k个待计算区块进行傅里叶变换后产生的矩阵中第u行第v列的值,
Figure PCTCN2019087581-appb-000014
为F k(u,v)的共轭复数,u、v、k均为正整数。
步骤S4、对所述待判定图像20进行缺陷提取获取TFT阵列基板的缺陷的描述参数。
具体地,所述步骤S4具体包括:
步骤S41、利用预设的二值化处理公式对所述待判定图像20的多个待判定像素的像素值进行二值化处理。
步骤S42、计算所述待判定图像20的质心在待判定图像20中的行坐标及列坐标,将待判定图像20中进行二值化处理后像素值为1的待判定像素记为缺陷像素。
步骤S43、获取每个缺陷像素与质心的距离,形成缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图作为TFT阵列基板的缺陷的描述参数。
进一步地,所述预设的二值化处理公式为:
Figure PCTCN2019087581-appb-000015
其中,I(x,y)为待判定图像20中第x行第y列的处理像素进行二值化处理前的像素值,I′(x,y)为待判定图像20中第x行y列的待判定像素进行二值化处理后的像素值,T为预设的阈值,x、y均为正整数。
步骤S5、利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型。
具体地,所述步骤S5具体为:提供预设的多个参考直方图作为预设的多个参考描述参数,每一参考直方图与一缺陷类型对应,计算缺陷像素与质心的尺寸和缺陷像素数量的相应关系的直方图同多个参考直方图之间的多个巴氏距离,选取多个巴氏距离中的最大值对应的参考直方图所对应的缺陷类型作为TFT阵列基板的缺陷类型。
需要说明的是,本发明的TFT阵列基板的缺陷检测方法在获取TFT阵列基板的原始图像后对原始图像进行去噪处理产生去噪图像,对去噪图像进行规则结构纹理背景去除处理产生待判定图像,具体为利用图像的互功率去除去噪图像中的规律的TFT单元背景,对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数,具体为利用缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图作为TFT阵列基板的缺陷的描述参数,利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型,具体为利用缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图同多个参考直方图进行巴氏距离计算,选取多个巴氏距离中的最大值对应的参考直方图所对应的缺陷类型作为TFT阵列基板的缺陷类型,能够简单准确地对TFT阵列基板上的缺陷类型进行检测,相比于现有技术,无需人工进行TFT阵列基板的缺陷检测,节约生产成本, 也无需大量图像样本和复杂参数计算,可满足实际生产需要。
综上所述,本发明的TFT阵列基板的缺陷检测方法在获取TFT阵列基板的原始图像后对原始图像进行去噪处理产生去噪图像,对去噪图像进行规则结构纹理背景去除处理产生待判定图像,对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数,利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型,能够简单准确地对TFT阵列基板上的缺陷类型进行检测。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种TFT阵列基板的缺陷检测方法,包括如下步骤:
    步骤S1、提供TFT阵列基板,获取所述TFT阵列基板的原始图像;
    步骤S2、对所述原始图像进行去噪处理产生去噪图像;
    步骤S3、对所述去噪图像进行规则结构纹理背景去除处理产生待判定图像;
    步骤S4、对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数;
    步骤S5、利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型。
  2. 如权利要求1所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S1中,利用自动光学检测机获取TFT阵列基板的原始图像。
  3. 如权利要求1所述的TFT阵列基板的缺陷检测方法,其中,所述TFT阵列基板的原始图像包括呈阵列式排布的多个原始像素。
  4. 如权利要求3所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S2具体为:利用全变分模型对原始图像进行处理从而形成去噪图像,所述去噪图像包括分别与多个原始像素对应且呈阵列式排布的多个去噪像素。
  5. 如权利要求4所述的TFT阵列基板的缺陷检测方法,其中,所述去噪图像的多个去噪像素的像素值为
    Figure PCTCN2019087581-appb-100001
    其中,λ为预设的参数,S i为多个去噪像素中第i个去噪像素的像素值,G i为多个原始像素中与第i个去噪像素对应的第i个原始像素的像素值,
    Figure PCTCN2019087581-appb-100002
    为对去噪图像的多个去噪像素的像素值进行一阶差分运算后第i个去噪像素对应的差分运算值,
    Figure PCTCN2019087581-appb-100003
    表示
    Figure PCTCN2019087581-appb-100004
    Figure PCTCN2019087581-appb-100005
    为最小值时对应的去噪图像的多个去噪像素的像素值,i为正整数。
  6. 如权利要求4所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S3包括:
    步骤S31、获取去噪图像中的最小重复单元;
    步骤S32、依据最小重复单元将去噪图像划分为阵列排布的多个待处理区块,相邻的待处理区块相连接,多个待处理区块的尺寸相同,多个待处理区块包括与一最小重复单元重合的参考区块及除了参考区块外的待计算区块;
    步骤S33、利用预设的互功率谱计算公式分别计算多个待计算区块与参考区块之间的对应的互功率谱,对多个互功率谱进行傅里叶逆变换对应产生多个互相关曲面函数,取每个互相关曲面函数中的峰值对应的横坐标及纵坐标分别作为该互相关曲面函数对应的待计算区块相对于参考区块的水平位移量及竖直位移量,依据每一待计算区块相对于参考区块的水平位移量及竖直位移量获取每一待计算区块中的各去噪像素与参考区块中各去噪像素之间的对应关系,将去噪图像的多个待计算模块中多个去噪像素的像素值分别减去参考区块中对应的去噪像素的像素值并将参考区块中多个去噪像素的像素值取0而形成待判定图像,所述待判定图像包括阵列排布的多个待判定像素。
  7. 如权利要求6所述的TFT阵列基板的缺陷检测方法,其中,所述预设的互功率谱计算公式为:
    Figure PCTCN2019087581-appb-100006
    其中,P k(u,v)为互功率谱中第u行第v列的值,F 0(u,v)为对参考区块进行傅里叶变换后产生的矩阵中第u行第v列的值,F k(u,v)为对多个待计算区块中第k个待计算区块进行傅里叶变换后产生的矩阵中第u行第v列的值,
    Figure PCTCN2019087581-appb-100007
    为F k(u,v)的共轭复数,u、v、k均为正整数。
  8. 如权利要求6所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S4具体包括:
    步骤S41、利用预设的二值化处理公式对所述待判定图像的多个待判定像素的像素值进行二值化处理;
    步骤S42、计算所述待判定图像的质心在待判定图像中的行坐标及列坐标,将待判定图像中进行二值化处理后像素值为1的待判定像素记为缺陷像素;
    步骤S43、获取每个缺陷像素与质心的距离,形成缺陷像素与质心的尺 寸和缺陷像素数量的相应关系的直方图作为TFT阵列基板的缺陷的描述参数。
  9. 如权利要求8所述的TFT阵列基板的缺陷检测方法,其中,所述预设的二值化处理公式为:
    Figure PCTCN2019087581-appb-100008
    其中,I(x,y)为待判定图像中第x行第y列的处理像素进行二值化处理前的像素值,I′(x,y)为待判定图像中第x行y列的待判定像素进行二值化处理后的像素值,T为预设的阈值,x、y均为正整数。
  10. 如权利要求8所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S5具体为:提供预设的多个参考直方图作为预设的多个参考描述参数,每一参考直方图与一缺陷类型对应,计算缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图同多个参考直方图之间的多个巴氏距离,选取多个巴氏距离中的最大值对应的参考直方图所对应的缺陷类型作为TFT阵列基板的缺陷类型。
  11. 一种TFT阵列基板的缺陷检测方法,包括如下步骤:
    步骤S1、提供TFT阵列基板,获取所述TFT阵列基板的原始图像;
    步骤S2、对所述原始图像进行去噪处理产生去噪图像;
    步骤S3、对所述去噪图像进行规则结构纹理背景去除处理产生待判定图像;
    步骤S4、对所述待判定图像进行缺陷提取获取TFT阵列基板的缺陷的描述参数;
    步骤S5、利用TFT阵列基板的缺陷的描述参数及预设的参考描述参数判断TFT阵列基板的缺陷的类型;
    其中,所述步骤S1中,利用自动光学检测机获取TFT阵列基板的原始图像。
    其中,所述TFT阵列基板的原始图像包括呈阵列式排布的多个原始像素。
  12. 如权利要求11所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S2具体为:利用全变分模型对原始图像进行处理从而形成去噪图像,所述去噪图像包括分别与多个原始像素对应且呈阵列式排布的多个去噪像 素。
  13. 如权利要求12所述的TFT阵列基板的缺陷检测方法,其中,所述去噪图像的多个去噪像素的像素值为
    Figure PCTCN2019087581-appb-100009
    其中,λ为预设的参数,S i为多个去噪像素中第i个去噪像素的像素值,G i为多个原始像素中与第i个去噪像素对应的第i个原始像素的像素值,
    Figure PCTCN2019087581-appb-100010
    为对去噪图像的多个去噪像素的像素值进行一阶差分运算后第i个去噪像素对应的差分运算值,
    Figure PCTCN2019087581-appb-100011
    表示
    Figure PCTCN2019087581-appb-100012
    Figure PCTCN2019087581-appb-100013
    为最小值时对应的去噪图像的多个去噪像素的像素值,i为正整数。
  14. 如权利要求12所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S3包括:
    步骤S31、获取去噪图像中的最小重复单元;
    步骤S32、依据最小重复单元将去噪图像划分为阵列排布的多个待处理区块,相邻的待处理区块相连接,多个待处理区块的尺寸相同,多个待处理区块包括与一最小重复单元重合的参考区块及除了参考区块外的待计算区块;
    步骤S33、利用预设的互功率谱计算公式分别计算多个待计算区块与参考区块之间的对应的互功率谱,对多个互功率谱进行傅里叶逆变换对应产生多个互相关曲面函数,取每个互相关曲面函数中的峰值对应的横坐标及纵坐标分别作为该互相关曲面函数对应的待计算区块相对于参考区块的水平位移量及竖直位移量,依据每一待计算区块相对于参考区块的水平位移量及竖直位移量获取每一待计算区块中的各去噪像素与参考区块中各去噪像素之间的对应关系,将去噪图像的多个待计算模块中多个去噪像素的像素值分别减去参考区块中对应的去噪像素的像素值并将参考区块中多个去噪像素的像素值取0而形成待判定图像,所述待判定图像包括阵列排布的多个待判定像素。
  15. 如权利要求14所述的TFT阵列基板的缺陷检测方法,其中,所述预设的互功率谱计算公式为:
    Figure PCTCN2019087581-appb-100014
    其中,P k(u,v)为互功率谱中第u行第v列的值,F 0(u,v)为对参考区块进行傅里叶变换后产生的矩阵中第u行第v列的值,F k(u,v)为对多个待计算区块中第k个待计算区块进行傅里叶变换后产生的矩阵中第u行第v列的值,
    Figure PCTCN2019087581-appb-100015
    为F k(u,v)的共轭复数,u、v、k均为正整数。
  16. 如权利要求14所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S4具体包括:
    步骤S41、利用预设的二值化处理公式对所述待判定图像的多个待判定像素的像素值进行二值化处理;
    步骤S42、计算所述待判定图像的质心在待判定图像中的行坐标及列坐标,将待判定图像中进行二值化处理后像素值为1的待判定像素记为缺陷像素;
    步骤S43、获取每个缺陷像素与质心的距离,形成缺陷像素与质心的尺寸和缺陷像素数量的相应关系的直方图作为TFT阵列基板的缺陷的描述参数。
  17. 如权利要求16所述的TFT阵列基板的缺陷检测方法,其中,所述预设的二值化处理公式为:
    Figure PCTCN2019087581-appb-100016
    其中,I(x,y)为待判定图像中第x行第y列的处理像素进行二值化处理前的像素值,I′(x,y)为待判定图像中第x行y列的待判定像素进行二值化处理后的像素值,T为预设的阈值,x、y均为正整数。
  18. 如权利要求16所述的TFT阵列基板的缺陷检测方法,其中,所述步骤S5具体为:提供预设的多个参考直方图作为预设的多个参考描述参数,每一参考直方图与一缺陷类型对应,计算缺陷像素与质心的距离和缺陷像素数量的相应关系的直方图同多个参考直方图之间的多个巴氏距离,选取多个巴氏距离中的最大值对应的参考直方图所对应的缺陷类型作为TFT阵列基板的缺陷类型。
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