WO2020155253A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

Info

Publication number
WO2020155253A1
WO2020155253A1 PCT/CN2019/076169 CN2019076169W WO2020155253A1 WO 2020155253 A1 WO2020155253 A1 WO 2020155253A1 CN 2019076169 W CN2019076169 W CN 2019076169W WO 2020155253 A1 WO2020155253 A1 WO 2020155253A1
Authority
WO
WIPO (PCT)
Prior art keywords
scan
low level
level
electrode
vgl2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/076169
Other languages
English (en)
French (fr)
Inventor
康志聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US16/982,794 priority Critical patent/US11079642B2/en
Publication of WO2020155253A1 publication Critical patent/WO2020155253A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • the pixels are charged by the data signal on the data line to control the display gray scale of the pixels, thereby displaying a certain image. Due to the parasitic capacitance between the source and the gate of the switching device in the pixel, the change of the scan signal on the scan line will be coupled to the pixel electrode through the parasitic capacitance, causing the potential of the pixel electrode to change, causing kickback. back) phenomenon, which in turn causes the display screen to flicker, which reduces the display quality.
  • a storage capacitor is also provided in the pixel, and the larger the storage capacitor, the better the effect of maintaining the potential in the pixel.
  • the existing storage capacitor is formed by a non-transparent common line or scan line and a transparent pixel electrode, and the storage capacitor is changed by changing the overlap area between the scan line or the common line and the pixel electrode.
  • the aperture ratio of the pixel will decrease.
  • the display brightness will be reduced accordingly.
  • the display brightness will be reduced.
  • the power consumption of the required backlight light source increases, resulting in a waste of energy.
  • the main purpose of the present application is to provide a display panel, which aims to solve the technical problem of the decrease in aperture ratio caused by the increase of the storage capacitance of the pixel. While ensuring the aperture ratio of the pixels in the display panel, it reduces the problem caused by kickback. The flashing, thereby improving the display effect.
  • the present application provides a display panel, the display panel includes a plurality of data lines, a plurality of scan lines and a plurality of pixels, the scan line includes a main scan electrode and a branch scan electrode, the same scan line The main scan electrode and the branch scan electrode are electrically connected, and at least part of the branch scan electrode extends along the extension direction of the data line and is arranged adjacent to the data line; the pixel includes a pixel electrode, the The pixel electrode partially overlaps the branch scan electrode to form a storage capacitor.
  • the present application also proposes a display panel, the display panel includes a plurality of data lines; a plurality of scan lines and a plurality of pixels, the scan line includes a main scan electrode and a branch scan electrode, the same scan
  • the main scan electrode and the branch scan electrode of the line are electrically connected, and at least part of the branch scan electrode extends along the extension direction of the data line and is arranged adjacent to the data line;
  • the pixel includes a pixel electrode, so
  • the pixel electrode partially overlaps the branch scan electrode to form a storage capacitor, one pixel electrode partially overlaps the two branch scan electrodes, and the two scan electrodes are separately provided on both sides of the pixel electrode.
  • the pixel electrode partially overlaps the branch scan electrode and/or the main scan electrode of the scan line in the previous stage, or the pixel electrode overlaps the branch scan electrode and/or the scan electrode of the scan line in the next stage.
  • the main scan electrodes partially overlap.
  • the present application also provides a display device, the display device includes a display panel, the display panel includes a plurality of data lines, a plurality of scan lines and a plurality of pixels, the scan line includes a main scan electrode and Branch scan electrodes, the main scan electrodes and the branch scan electrodes of the same scan line are electrically connected, and at least part of the branch scan electrodes extend along the extension direction of the data line and are arranged adjacent to the data line;
  • the pixel includes a pixel electrode, and the pixel electrode partially overlaps the branch scan electrode to form a storage capacitor.
  • the display panel includes multiple data lines, multiple scan lines, and multiple pixels.
  • the scan lines include main scan electrodes and branch scan electrodes.
  • the main scan electrodes and branch scan electrodes of the same scan line are electrically connected, at least partially
  • the branch scan electrode extends along the extension direction of the data line and is arranged adjacent to the data line; the pixel includes a pixel electrode, and the pixel electrode partially overlaps the branch scan electrode to form a storage capacitor.
  • the scan electrode can also shield the data signal on the data line from interfering with the potential of the pixel electrode, so that the minimum distance between the pixel electrode and the data line can be further reduced, thereby avoiding the sacrifice of the pixel aperture ratio, even
  • the effect of increasing the aperture ratio can be achieved by reducing the minimum distance between the pixel electrode and the data line.
  • the increase in the aperture ratio reduces the power consumption of the required backlight light source and helps to save energy.
  • the size of the storage capacitor is positively related to the overlap area between the pixel electrode and the scan electrode. By adjusting the overlap area between the pixel electrode and the scan electrode, the required storage capacitor can be obtained to reduce the potential of the pixel electrode.
  • the kickback caused by the influence of the scanning signal alleviates the flicker in the display screen and improves the display effect.
  • FIG. 1 is a schematic diagram of the structure of an exemplary display panel
  • FIG. 2 is a schematic diagram of the circuit structure of the display panel in FIG. 1;
  • FIG. 3 is a schematic diagram of signal timing of the display panel in FIG. 1;
  • FIG. 4 is a schematic diagram of another example of the structure of a display panel
  • FIG. 5 is a schematic diagram of the circuit structure of the display panel in FIG. 4;
  • FIG. 6 is a schematic diagram of signal timing of the display panel in FIG. 4;
  • FIG. 7 is a schematic structural diagram of an embodiment of a display panel of the present application.
  • FIG. 8 is a schematic structural diagram of another embodiment of a display panel of the present application.
  • FIGS. 7 and 8 are schematic diagrams of the circuit structure of the display panel in FIGS. 7 and 8;
  • FIGS. 7 and 8 are schematic diagrams of signal timing of a specific example of the display panel in FIGS. 7 and 8;
  • FIGS. 7 and 8 are schematic diagrams of signal timing of another specific example of the display panel in FIGS. 7 and 8;
  • FIGS. 7 and 8 are schematic diagrams of signal timing of another specific example of the display panel in FIGS. 7 and 8;
  • FIG. 13 is a schematic structural diagram of another embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of still another embodiment of the present application.
  • FIGS. 13 and 14 are schematic diagrams of the circuit structure of the display panel in FIGS. 13 and 14;
  • FIG. 16 is a schematic diagram of signal timing of the display panel in FIG. 13 and FIG. 14.
  • FIG. 1 shows a schematic structural diagram of an exemplary display panel.
  • the display panel includes multiple pixels (shown in Figure 1 is a pixel and its surrounding data line and scan line structure), multiple data lines 200', multiple Scan line 300' and multiple common lines 400'.
  • the pixels are usually arranged in a rectangular array, and the pixels include a pixel electrode 110' and a switching device 120'.
  • the switching device 120' is usually a thin film transistor TFT'. Under the action of the scanning signal on the scan line, the thin film transistor TFT' controls the data line to charge the corresponding pixel.
  • a display panel includes three types of pixels: red pixels, green pixels, and blue pixels.
  • At least one red pixel, one green pixel, and one blue pixel form a pixel group to display a color image according to the principle of spatial color mixing.
  • the pixel generates a certain gray scale under the joint action of the scan signal G(n)' on the scan line 300' and the data signal on the data line 200'.
  • the common line 400' includes a common electrode 410', and the pixel electrode 110' and the common electrode 410' at least partially overlap to form a storage capacitor.
  • the common electrode 410' overlaps a part of the pixel electrode 110' to form a storage capacitor.
  • FIG. 2 is a schematic diagram of the circuit structure of the display panel in FIG.
  • FIG. 3 is a schematic diagram of signal timing of the display panel in FIG. 1, where Vcom' is the level of the common signal on the common line 400', and Vgh' is the high level of the scan signal G(n)' on the scan line 300' , Vgl' is the low level of the scan signal G(n)' on the scan line 300'.
  • FIG 4 shows a schematic diagram of the structure of a display panel in another example.
  • the display panel includes a plurality of pixels (shown in Figure 4 is the structure of one pixel and its surrounding data lines and scan lines), multiple data lines 200' and multiple Scan lines 300'.
  • the pixel includes a pixel electrode 110' and a switching device 120'.
  • the switching device 120' is usually a thin film transistor TFT', which controls the data line to charge the corresponding pixel under the action of the scan signal on the scan line.
  • a portion of the scan line 300' of the previous level extends in the direction of the pixel of the current level to form a scan electrode 310', wherein the scan line of the previous level refers to a scan line adjacent to the pixel of the current level and is electrically connected to the pixel of the previous level.
  • the pixel electrode 110' and the scan electrode 310' at least partially overlap to form a storage capacitor.
  • the scan electrode 310' overlaps with part of the pixel electrode 110' to form a storage capacitor.
  • FIG. 5 is a schematic diagram of the circuit structure of the display panel in FIG.
  • Cst' is the storage capacitance of the pixel
  • Clc' is the liquid crystal capacitance of the pixel
  • Cgs' is the parasitic capacitance between the source and gate of the switching device 120' in the pixel.
  • the storage capacitor is related to the overlap area of the pixel electrode and the common electrode, or the pixel electrode and the scan electrode. The larger the overlap area, the larger the storage capacitor Cst.
  • the pixel electrode is usually made of transparent indium tin oxide (ITO)
  • the scan electrode and common electrode are usually made of non-transparent metal. In the examples shown in FIGS.
  • the non-transparent scan electrode and common electrode will reduce the light-transmitting area in the pixel, that is, the aperture ratio of the pixel will decrease, the overall display brightness of the display panel will decrease, or the energy consumption of the required backlight light source will increase.
  • the present application proposes a display panel, which aims to reduce the kickback of the pixel level while maintaining the pixel aperture ratio to improve the display effect.
  • the display panel includes a plurality of data lines 200, a plurality of scan lines 300, and a plurality of pixels.
  • the scan lines 300 include a main scan electrode 310 and a branch scan electrode 320.
  • the main scan electrode 310 and the branch scan electrode 320 of the line 300 are electrically connected, and at least part of the branch scan electrode 320 extends along the extension direction of the data line 200 and is arranged adjacent to the data line 200;
  • the pixel includes a pixel electrode 110, and the pixel electrode 110 and the branch scan electrode
  • the electrodes 320 partially overlap to form a storage capacitor.
  • the data line 200 may extend along the longitudinal direction of the display panel, and a plurality of data lines 200 are arranged along the lateral direction of the display panel.
  • the scan line 300 includes a main scan electrode 310 and a branch scan electrode 320.
  • the main scan electrode 310 may extend in the lateral direction of the display panel, and a plurality of main scan electrodes 310 are arranged along the longitudinal direction of the display panel.
  • the longitudinal extension of the display panel partially extends in the horizontal direction, or the scan electrodes 320 entirely extend in the longitudinal direction of the display panel, that is, along the extension direction of the data line, and the plurality of scan electrodes 320 are arranged in the horizontal direction of the display panel.
  • the scan electrode 320 is arranged adjacent to the data line 200. Since the scan electrode 320 is usually made of metal, it can form a shield for the data signal on the data line 200, thereby reducing the interference of the data signal on the pixel level of the pixel electrode. .
  • the pixel includes a pixel electrode 110, and the pixel electrode 110 partially overlaps the branch scan electrode 320 to form a storage capacitor.
  • the pixel electrode 110 can be The data line 200 extends in the direction to increase the overlap area between the pixel electrode 110 and the branch scan electrode 320, thereby increasing the storage capacitance while increasing the aperture ratio of the pixel.
  • the display panel includes a plurality of data lines 200, a plurality of scan lines 300 and a plurality of pixels.
  • the scan line 300 includes a main scan electrode 310 and a branch scan electrode 320.
  • the main scan electrode 310 and the branch scan electrode 320 of the same scan line 300 The scan electrode 320 is electrically connected. At least part of the scan electrode 320 extends along the extension direction of the data line 200 and is arranged adjacent to the data line 200; the pixel includes a pixel electrode 110, and the pixel electrode 110 partially overlaps the scan electrode 320 to form a storage capacitor .
  • the scan electrode 320 By providing the scan electrode 320 adjacent to the data line 200, and the scan electrode 320 and the pixel electrode 110 together form a storage capacitor, the space between the pixel electrode 110 and the data line 200 is fully utilized. At the same time, the scan electrode 320 can also shield the data signal on the data line 200 from interfering with the potential of the pixel electrode 110, so that the minimum distance between the pixel electrode 110 and the data line 200 can be further reduced, thereby avoiding the opening of the pixel. The sacrifice of the rate can even achieve the effect of increasing the aperture rate by reducing the minimum distance between the pixel electrode 110 and the data line 200. The increase in the aperture ratio reduces the power consumption of the required backlight light source and helps to save energy.
  • the size of the storage capacitor is positively related to the overlap area between the pixel electrode and the scan electrode.
  • the required storage capacitor can be obtained to reduce the potential of the pixel electrode.
  • the kickback caused by the influence of the scanning signal alleviates the flicker in the display screen and improves the display effect.
  • the pixel electrode 110 partially overlaps the main scan electrode 310 and the branch scan electrode 320 to form a storage capacitor.
  • the pixel electrode 110 partially overlaps the main scan electrode 310 in addition to the branch scan electrode 320, which helps to further increase the overlap area between the pixel electrode 110 and the scan line 300, thereby increasing the storage capacitance to reduce The backlash of the pixel level on the small pixel electrode prevents flicker of the display panel.
  • the pixel electrode 110 extends in the direction of the main scan electrode 320 to form an overlapping area, which further increases the aperture ratio of the pixel, so that the display brightness of the display panel is stronger, or the power consumption of the required backlight light source is smaller. Improve the display effect of the display panel.
  • one pixel electrode 110 partially overlaps with two scan electrodes 320, and the two scan electrodes 320 are separately provided on both sides of the pixel electrode 110.
  • the scan electrodes 320 are provided on both sides of the pixel electrode 110, which helps to further increase the storage capacitance and avoid the flicker of the display screen due to the kickback of the pixel level;
  • the support provided on both sides The scan electrode 320 does not adversely affect the aperture ratio of the pixel, and the pixel electrode 110 extends to both sides, which helps to further increase the aperture ratio of the pixel;
  • one side of the scan electrode 320 is located between the pixel electrode 110 and the data line Between 200, it helps to strengthen the shielding effect of the data signal on the data line 200 on both sides of the pixel electrode 110, thereby making the pixel level on the pixel electrode 110 more stable and improving the display effect.
  • the pixel electrode 110 partially overlaps the branch scan electrode 320 and/or the main scan electrode 310 of the previous scan line 300.
  • Cst is a storage capacitor formed by the pixel electrode 110 and the branch scan electrode 320 of the scan line 300 and/or the main scan electrode 310; It includes a switching device 120.
  • the switching device is usually a thin film transistor TFT.
  • the switching device 120 includes a source, a drain, and a gate.
  • Cgs is a parasitic capacitance formed between the source and the gate of the switching device; Clc is the liquid crystal capacitance of the pixel.
  • the scan signal G(n) on the scan line when the display panel is in an operating state, specifically when the pixels are charged, the scan signal G(n) on the scan line includes a high level Vgh and a first low level Vgl1.
  • the high level Vgh is higher than the first low level Vgl1, where the high-level falling edge of the scan signal G(n-1) on the previous scan line and the scan signal G(n) on the current scan line are high
  • the rising edge of the level is synchronized.
  • the pixel electrode extends in the direction of the main scan electrode 310 and/or the branch scan electrode 320, which increases the aperture ratio of the pixel.
  • the scan signal on the scan line 300 when the display panel is in the operating state, includes a high level Vgh, a first low level Vgl1, and a second low level Vgl2.
  • the level Vgh is higher than the first low level Vgl1, the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on the falling edge side of the high level, and the second low level Vgl2 is The second duration is equivalent to twice the first duration of the high level Vgh, where the high-level falling edge of the scan signal G(n-1) on the scan line of the previous level is the same as the scan signal G on the scan line of the current level.
  • the high-level rising edge of (n) is synchronized.
  • the scan signal G(n) of the current level changes from the high level Vgh to the second low level Vgl2, that is, when the scan line of the current level switches from on to off
  • the current level of scanning signal G(n-1) is converted from the second low level Vgl2 to the first low level Vgl1, the pixels of this level
  • Vgl1 is level
  • a pixel level change of ⁇ V23 (Vgl
  • the storage capacitor can satisfy the above-mentioned relational expression, so as to achieve a better display effect.
  • the scan signal on the scan line when the display panel is in the operating state, includes a high level Vgh, a first low level Vgl1, and a second low level Vgl2.
  • the level Vgh is higher than the first low level Vgl1
  • the first low level Vgl1 is higher than the second low level Vgl2
  • the second low level Vgl2 is located on the falling edge side of the high level Vgh
  • the second duration is equivalent to the first duration of the high level Vgh, where the high-level falling edge of the scan signal G(n-1) on the scan line of the previous level is the same as the scan signal G(n) on the scan line of the current level.
  • the rising edge of the high level is synchronized.
  • the pixel level changes the second term corresponds to the pixel level change of the current level of the scan signal G(n) from the high level Vgh to the second low level Vgl2; when the current scan signal G(n) changes from the second low level
  • the storage capacitor can satisfy the above-mentioned relational expression, so as to achieve a better display effect.
  • the pixel electrode 110 partially overlaps with the branch scan electrode 320 of the subsequent scan line 300 to form a storage capacitor, where the subsequent scan line refers to the current
  • the scan line adjacent to the first-level pixel is electrically connected to the next-level pixel.
  • the pixel electrode 110 partially overlaps the main scan electrode 310 and the branch scan electrode 320 of the scan line 300 of the subsequent stage to form a storage capacitor.
  • the pixel electrode 110 overlaps the main scan electrode 310 and the branch scan electrode 320, which helps increase the storage capacitor and the aperture ratio of the pixel.
  • FIG. 15 it is a schematic diagram of the circuit structure of the display panel in FIG. 13 and FIG. 14.
  • FIG. 16 it is a schematic diagram of signal timing of the display panel in FIG. 13 and FIG. 14.
  • the timing of the scanning signal can be controlled to realize the regulation of the change of the pixel level.
  • the scan signal on the scan line includes a high level Vgh, a first low level Vghl1, and a second low level Vgl2.
  • the high level Vgh1 is higher than the first low level Vgl1.
  • the first low level Vgl1 is higher than the second low level Vgl2, the second low level Vgl2 is located on the rising edge side of the high level Vgh, and the second duration of the second low level Vgl2 is equal to that of the high level Vgh
  • the first duration is equivalent, wherein the high-level falling edge of the scan signal G(n) on the scan line of the current level is synchronized with the high-level rising edge of the scan signal G(n+1) on the scan line of the next level.
  • the storage capacitor can satisfy the above-mentioned relational expression, so as to achieve a better display effect.
  • the display device includes a display panel.
  • the specific structure of the display panel refer to the above-mentioned embodiments, which will not be repeated here.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本申请公开了一种显示面板，包括多条数据线，多条扫描线和多个像素，同一扫描线的主扫描电极和支扫描电极电连接，像素电极与支扫描电极部分重叠以形成存储电容。

Description

显示面板和显示装置
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
在显示面板中，通过数据线上的数据信号为像素充电，以控制像素的显示灰度，从而显示一定的图像。由于像素中开关器件的源极和栅极之间存在寄生电容，导致扫描线上的扫描信号的变化将通过寄生电容耦合到像素电极上，使像素电极的电位发生变化，产生反冲（kick back）现象，进而导致显示画面出现闪烁，使显示质量下降。为了保持像素中像素电极的电位，在像素中还设置有存储电容，且存储电容越大，像素中电位保持效果越好。然而，现有的存储电容由非透明的公共线或扫描线与透明的像素电极共同形成，并通过改变扫描线或公共线与像素电极之间的重叠面积而改变存储电容。相应的，随着所需的存储电容的增大，像素的开口率将会减小，在背光光源功耗不变的情况下，显示亮度将会随之减弱，而为了维持显示亮度，又将导致所需的背光光源的功耗上升，造成能源的浪费。
发明内容
本申请的主要目的在于提供一种显示面板，旨在解决上述像素的存储电容增大导致其开口率减小的技术问题，在保障显示面板中像素开口率的同时，减小因反冲而导致的闪烁，从而改善显示效果。
为实现上述目的，本申请提供一种显示面板，所述显示面板包括多条数据线，多条扫描线和多个像素，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容。
为实现上述目的，本申请还提出一种显示面板，所述显示面板包括多条数据线；多条扫描线以及多个像素，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容，一所述像素电极与两所述支扫描电极部分重叠，两所述支扫描电极分设于所述像素电极的两侧，所述像素电极与前一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠，或所述像素电极与后一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
为实现上述目的，本申请还提出一种显示装置，所述显示装置包括显示面板，所述显示面板包括多条数据线，多条扫描线和多个像素，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容。
本申请技术方案中，显示面板包括多条数据线，多条扫描线和多个像素，扫描线包括主扫描电极和支扫描电极，同一扫描线的主扫描电极和支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；像素包括像素电极，像素电极与支扫描电极部分重叠，以形成存储电容。通过设置与数据线相邻的支扫描电极，并由支扫描电极与像素电极共同形成存储电容，充分利用了像素电极和数据线之间的空间。同时，支扫描电极还可以屏蔽数据线上的数据信号对像素电极的电位的干扰，使得像素电极和数据线之间的最小距离可以进一步减小，从而避免了对像素的开口率的牺牲，甚至可以通过减小像素电极和数据线之间的最小距离以实现增大开口率的效果。开口率的增大使所需的背光光源的功耗降低，有助于节约能源。存储电容的大小与像素电极和支扫描电极之间的重叠面积呈正相关关系，通过调节像素电极和支扫描电极之间的重叠面积，可以获得所需的存储电容，以减小像素电极的电位受到扫描信号的影响而产生的反冲，缓解显示画面中的闪烁现象，改善显示效果。
附图说明
图1是一范例的显示面板的结构示意图；
图2是图1中显示面板的电路结构示意图；
图3是图1中显示面板的信号时序示意图；
图4是另一范例的显示面板的结构示意图；
图5是图4中显示面板的电路结构示意图；
图6是图4中显示面板的信号时序示意图；
图7是本申请显示面板一实施例的结构示意图；
图8是本申请显示面板另一实施例的结构示意图；
图9是图7和图8中显示面板的电路结构示意图；
图10是图7和图8中显示面板一具体示例的信号时序示意图；
图11是图7和图8中显示面板另一具体示例的信号时序示意图；
图12是图7和图8中显示面板又一具体示例的信号时序示意图；
图13是本申请又一实施例的结构示意图；
图14是本申请再一实施例的结构示意图；
图15是图13和图14中显示面板的电路结构示意图；
图16是图13和图14中显示面板的信号时序示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为，包括三个并列的方案，以“A和/或B”为例，包括A方案，或B方案，或A和B同时满足的方案。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
图1所示是一范例的显示面板的结构示意图，显示面板包括多个像素（图1中所示为一个像素及其周围数据线和扫描线的结构），多条数据线200’、多条扫描线300’和多条公共线400’。其中，像素通常呈矩形阵列状排布，像素包括像素电极110’和开关器件120’。开关器件120’通常为薄膜晶体管TFT’，在扫描线上的扫描信号作用下，薄膜晶体管TFT’控制数据线向对应的像素充电。通常，在显示面板中包括红像素、绿像素和蓝像素三种像素，至少一红像素、一绿像素和一蓝像素形成一像素组，从而根据空间混色原理显示彩色画面。像素在扫描线300’上的扫描信号G(n)’和数据线200’上的数据信号的共同作用下，产生一定的显示灰度。为了保持像素电极110’上的电位，以保持显示效果，公共线400’包括公共电极410’，像素电极110’与公共电极410’至少部分重叠以形成存储电容。在图1中，公共电极410’与部分像素电极110’重叠而形成存储电容。图2所示是图1中显示面板的电路结构示意图，其中， Cst’为该像素的存储电容，即公共电极410’和像素电极110’之间形成的电容，Clc’为该像素的液晶电容，Cgs’为该像素中开关器件120’的源极和栅极之间的寄生电容。图3所示是图1中显示面板的信号时序示意图，其中，Vcom’为公共线400’上公共信号的电平，Vgh’为扫描线300’上扫描信号G(n)’的高电平，Vgl’为扫描线300’上扫描信号G(n)’的低电平。当扫描信号G(n)’由高电平Vgh’转换为低电平Vgl’，即扫描线由开启状态转换为关闭状态时，同一级像素电极110’上的像素电平P(n)’将会变化ΔV’，根据图2可知，ΔV’=(Vgh’-Vgl’)*Cgs’/(Cgs’+Cst’+Clc’)。
图4所示是另一范例中显示面板的结构示意图，显示面板包括多个像素（图4中所示为一个像素及其周围数据线和扫描线的结构），多条数据线200’和多条扫描线300’。其中，像素包括像素电极110’和开关器件120’。开关器件120’通常为薄膜晶体管TFT’，在扫描线上的扫描信号作用下控制数据线向对应的像素充电。前一级扫描线300’的一部分向本级像素方向延伸，形成扫描电极310’，其中，前一级扫描线是指与本级像素相邻的扫描线，并与前一级像素电连接，像素电极110’与扫描电极310’至少部分重叠以形成存储电容。在图4中，扫描电极310’与部分像素电极110’重叠而形成存储电容。图5所示是图4中显示面板的电路结构示意图，其中， Cst’为该像素的存储电容，Clc’为该像素的液晶电容，Cgs’为该像素中开关器件120’的源极和栅极之间的寄生电容。如图6所示，当扫描线300’上的扫描信号由高电平Vgh’转换为低电平Vgl’，即扫描线由开启状态转换为关闭状态时，像素电极110’上的像素电平P(n)’所产生的变化为ΔV’，其中，ΔV’=(Vgh’-Vgl’)*Cgs’/(Cgs’+Cst’+Clc’)。
根据上述范例可知，在显示面板中，为了尽可能减小像素电极上的像素电平的变化，以减少显示面板中画面的闪烁，改善显示效果，在其他条件不变的情况下，应尽可能增大存储电容。然而，存储电容与像素电极和公共电极，或像素电极和扫描电极的重叠面积有关，重叠面积越大，存储电容Cst越大。另一方面，考虑到虽然像素电极通常由透明的铟锡氧化物（ITO）制成，但扫描电极和公共电极通常是由非透明的金属制成，在图1和图4所示的范例中，非透明的扫描电极和公共电极将导致像素中透光面积的减小，即像素的开口率下降，使显示面板的显示亮度整体下降，或者所需的背光光源的能耗上升。
本申请提出一种显示面板，旨在保持像素开口率的同时，减小像素电平的反冲，以改善显示效果。在本申请的一实施例中，如图7所示，显示面板包括多条数据线200，多条扫描线300和多个像素，扫描线300包括主扫描电极310和支扫描电极320，同一扫描线300的主扫描电极310和支扫描电极320电连接，至少部分支扫描电极320沿数据线200的延伸方向延伸且与数据线200相邻设置；像素包括像素电极110，像素电极110与支扫描电极320部分重叠，以形成存储电容。
后文中将以液晶显示面板为例，对本申请的技术方案详细阐述。如图7所示，数据线200可以沿显示面板的纵向延伸，且多条数据线200沿显示面板的横向排布。扫描线300包括主扫描电极310和支扫描电极320，其中，主扫描电极310可以沿显示面板的横向延伸，且多条主扫描电极310沿显示面板的纵向排布，支扫描电极320可以部分沿显示面板的纵向延伸，部分沿横向延伸，或支扫描电极320整体沿显示面板的纵向延伸，即沿数据线的延伸方向延伸，且多条支扫描电极320沿显示面板的横向排布。支扫描电极320与数据线200相邻设置，由于支扫描电极320通常由金属制成，因此可以形成对数据线200上数据信号的屏蔽，从而减少了数据信号对像素电极的像素电平的干扰。像素包括像素电极110，像素电极110与支扫描电极320部分重叠以形成存储电容。当像素电极110与支扫描电极320的重叠面积越大时，存储电容越大。考虑到支扫描电极320对数据信号的屏蔽作用，在本实施例中，即使像素电极110与数据线200之间的距离较小，也能够保障正常的显示效果，因此，可以将像素电极110向数据线200的方向延伸，以增大像素电极110和支扫描电极320之间的重叠面积，从而在增大存储电容的同时增大像素的开口率。
在本实施例中，显示面板包括多条数据线200，多条扫描线300和多个像素，扫描线300包括主扫描电极310和支扫描电极320，同一扫描线300的主扫描电极310和支扫描电极320电连接，至少部分支扫描电极320沿数据线200的延伸方向延伸且与数据线200相邻设置；像素包括像素电极110，像素电极110与支扫描电极320部分重叠，以形成存储电容。通过设置与数据线200相邻的支扫描电极320，并由支扫描电极320与像素电极110共同形成存储电容，充分利用了像素电极110和数据线200之间的空间。同时，支扫描电极320还可以屏蔽数据线200上的数据信号对像素电极110的电位的干扰，使得像素电极110和数据线200之间的最小距离可以进一步减小，从而避免了对像素的开口率的牺牲，甚至可以通过减小像素电极110和数据线200之间的最小距离以实现增大开口率的效果。开口率的增大使所需的背光光源的功耗降低，有助于节约能源。存储电容的大小与像素电极和支扫描电极之间的重叠面积呈正相关关系，通过调节像素电极和支扫描电极之间的重叠面积，可以获得所需的存储电容，以减小像素电极的电位受到扫描信号的影响而产生的反冲，缓解显示画面中的闪烁现象，改善显示效果。
在本申请的另一实施例中，如图8所示，像素电极110与主扫描电极310和支扫描电极320部分重叠，以形成存储电容。像素电极110在与支扫描电极320部分重叠之外，还与主扫描电极310部分重叠，有助于进一步增大像素电极110和扫描线300之间的重叠面积，从而增大存储电容，以减小像素电极上像素电平的反冲，避免显示面板的闪烁。并且，像素电极110向主扫描电极320的方向延伸以形成重叠区域，进一步增大了像素的开口率，从而使显示面板的显示亮度更强，或者所需的背光光源的功耗更小，以改善显示面板的显示效果。
如图7和图8所示，一像素电极110与两支扫描电极320部分重叠，两支扫描电极320分设于像素电极110的两侧。第一，在像素电极110的两侧均设置支扫描电极320，有助于进一步增大存储电容，避免因像素电平的反冲而造成显示画面的闪烁；第二，设置于两侧的支扫描电极320不会对像素的开口率造成不良影响，且像素电极110向两侧延伸，有助于进一步增大像素的开口率；第三，支扫描电极320的一边位于像素电极110和数据线200之间，有助于加强对像素电极110两侧的数据线200上数据信号的屏蔽效果，从而使像素电极110上的像素电平更加稳定，改善显示效果。
如图7和图8所示，像素电极110与前一级扫描线300的支扫描电极320和/或主扫描电极310部分重叠，通过控制扫描信号的时序，能够减小像素电极110上像素电平的反冲，以避免显示画面的闪烁。如图9所示为图7和图8中显示面板的电路结构示意图，其中，Cst为像素电极110和扫描线300的支扫描电极320和/或主扫描电极310所形成的存储电容；像素还包括开关器件120，开关器件通常为薄膜晶体管TFT，开关器件120包括源极、漏极和栅极，Cgs为开关器件的源极和栅极之间形成的寄生电容；Clc为像素的液晶电容。
如图10所示，在一具体示例中，当显示面板处于运行状态时，具体为像素被充电时，扫描线上的扫描信号G(n)包括有高电平Vgh和第一低电平Vgl1，高电平Vgh高于第一低电平Vgl1，其中，前一级扫描线上扫描信号G(n-1)的高电平下降沿与本级扫描线上扫描信号G(n)的高电平上升沿相同步。当本级扫描线上扫描信号G(n)由高电平Vgh转换为第一低电平Vgl1，即本级扫描线控制本级像素由开启转换为关闭状态时时，本级像素的像素电极110上的像素电平变化为ΔV1=(Vgh-Vgl)*Cgs/(Cgs+Cst+Clc)。根据上述关系可知，随着存储电容Cst的增大，像素电平的变化越小，即反冲效应越弱，相应的，显示效果也越好。由于像素电极110与主扫描电极10和支扫描电极320之间的重叠面积的和大于范例中像素电极与扫描电极或公共电极的重叠面积，因此，在本实施例中，通过增大存储电容，有效减小了像素电平的变化，缓解了显示面板中画面闪烁的现象。并且，像素电极向主扫描电极310和/或支扫描电极320的方向延伸，同时增大了像素的开口率。
在另一具体示例中，如图11所示，当显示面板处于运行状态时，扫描线300上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，高电平Vgh高于第一低电平Vgl1，第一低电平Vgl1高于第二低电平Vgl2，第二低电平Vgl2位于高电平的下降沿侧，且第二低电平Vgl2的第二持续时长与高电平Vgh的第一持续时长的两倍相当，其中，前一级扫描线上扫描信号G(n-1)的高电平下降沿与本级扫描线上扫描信号G(n)的高电平上升沿相同步。当本级扫描信号G(n)从高电平Vgh转换为第二低电平Vgl2，即本级扫描线从开启转换为关闭状态时，本级像素的像素电极110上的像素电平变化为ΔV21=(Vgh-Vgl2)*Cgs/(Cgs+Cst+Clc)；当前一级扫描信号G(n-1)从第二低电平Vgl2转换为第一低电平Vgl1时，本级像素的像素电极上将产生ΔV22=(Vgl2-Vgl1)*Cst/(Cgs+Cst+Clc)的像素电平变化；当本级扫描信号G(n)从第二低电平Vgl2转换为第一低电平Vgl1时，本级像素的像素电极上将产生ΔV23=(Vgl2-Vgl1)*Cgs/(Cgs+Cst+Clc)的像素电平变化。为了尽量减小反冲效应，使显示画面尽可能保持稳定，根据图11所示可知，ΔV21、ΔV22和ΔV23之间应该满足ΔV21+ΔV22+ΔV23=0，即存储电容Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。在本示例中，可以通过改变像素电极110和扫描线300之间的重叠面积，使存储电容满足上述关系式，以实现较好的显示效果。
在又一具体示例中，如图12所示，当显示面板处于运行状态时，扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，高电平Vgh高于第一低电平Vgl1，第一低电平Vgl1高于第二低电平Vgl2，第二低电平Vgl2位于高电平Vgh的下降沿侧，且第二低电平Vgl2的第二持续时长与高电平Vgh的第一持续时长相当，其中，前一级扫描线上扫描信号G(n-1)的高电平下降沿与本级扫描线上扫描信号G(n)的高电平上升沿相同步。当前一级扫描信号G(n-1)从第二低电平Vgl2转换为第一低电平Vgl1，同时本级扫描信号G(n)从高电平Vgh转换为第二低电平Vgl2时，本级像素的像素电极110上所产生的像素电平的变化为ΔV31=(Vgl2-Vgl1)*Cst/(Cgs+Cst+Clc)+ (Vgh-Vgl2)*Cgs/(Cgs+Cst+Clc)，其中，第一项对应于前一级扫描信号G(n-1)从第二低电平Vgl2转换为第一低电平Vgl1的像素电平变化，第二项对应于本级扫描信号G(n)从高电平Vgh转换为第二低电平Vgl2的像素电平变化；当本扫描信号G(n)从第二低电平Vgl2转换为第一低电平Vgl1时，本级像素的像素电极上所产生的像素电平的变化为ΔV32=(Vgl2-Vgl1)*Cgs/(Cgs+Cst+Clc)。为了尽量减小反冲效应，ΔV31和ΔV31应满足ΔV31+ΔV32=0，即存储电容Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。在本示例中，可以通过改变像素电极110和扫描线300之间的重叠面积，使存储电容满足上述关系式，以实现较好的显示效果。
在本申请的又一实施例中，如图13所示，像素电极110与后一级扫描线300的支扫描电极320部分重叠，以形成存储电容，其中，后一级扫描线是指与本级像素相邻的扫描线，且与后一级像素电连接。
在本申请的再一实施例中，如图14所示，像素电极110与后一级扫描线300的主扫描电极310和支扫描电极320部分重叠，以形成存储电容。相比而言，像素电极110与主扫描电极310和支扫描电极320相重叠，有助于增大存储电容和像素的开口率。
如图15所示，为图13和图14中显示面板的电路结构示意图。如图16所示，为图13和图14中显示面板的信号时序示意图。为了更好地改善显示效果，可以通过控制扫描信号的时序，实现对像素电平的变化的调控。具体的，当显示面板处于运行状态时，扫描线上的扫描信号包括有高电平Vgh、第一低电平Vghl1和第二低电平Vgl2，高电平Vgh1高于第一低电平Vgl1，第一低电平Vgl1高于第二低电平Vgl2，第二低电平Vgl2位于高电平Vgh的上升沿侧，且第二低电平Vgl2的第二持续时长与高电平Vgh的第一持续时长相当，其中，本级扫描线上扫描信号G(n)的高电平下降沿与后一级扫描线上扫描信号G(n+1)的高电平上升沿相同步。当本级扫描线上的扫描信号G(n)从高电平Vgh转换为第一低电平Vgl1时，同时，后一级扫描线上的扫描信号G(n+1)从第二低电平Vgl2转换为高电平Vgh时，本级像素的像素电极110上所产生的像素电平的变化满足ΔV41=(Vgh-Vgl1)*Cgs/(Cgs+Cst+Clc)+(Vgl2-Vgh)*Cst/(Cgs+Cst+Clc)，其中，第一项对应于本级扫描信号G(n)从高电平Vgh转换为第一低电平Vgl1的像素电平变化，第二项对应于后一级扫描信号G(n+1)从第二第电平Vgl2转换为高电平Vgh的像素电平变化；当后一级扫描线上扫描信号G(n+1)从高电平Vgh转换为第一低电平Vgl1时，本级像素的像素电极110上对应的像素电平的变化为ΔV42=(Vgh-Vgl1)*Cst/(Cgs+Cst+Clc)。为了尽量减小反冲效应，ΔV41和ΔV42应满足ΔV41+ΔV42=0，即存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。在本实施例中，可以通过改变像素电极110和扫描线300之间的重叠面积，使存储电容满足上述关系式，以实现较好的显示效果。
进一步的，本申请还提出一种显示装置，显示装置包括显示面板，该显示面板的具体结构参照上述实施例，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    多条数据线；
    多条扫描线，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；以及，
    多个像素，所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容。
  2. 如权利要求1所述的显示面板，其中，所述像素电极与所述主扫描电极和所述支扫描电极部分重叠，以形成存储电容。
  3. 如权利要求2所述的显示面板，其中，一所述像素电极与两所述支扫描电极部分重叠，两所述支扫描电极分设于所述像素电极的两侧。
  4. 如权利要求2所述的显示面板，其中，所述像素电极与前一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
  5. 如权利要求4所述的显示面板，其中，当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平和第一低电平，所述高电平高于所述第一低电平，其中，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步。
  6. 如权利要求4所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的下降沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长的两倍相当，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  7. 如权利要求4所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的下降沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长相当，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  8. 如权利要求2所述的显示面板，其中，所述像素电极与后一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
  9. 如权利要求8所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的上升沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长相当，本级扫描线上扫描信号的高电平下降沿与后一级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  10. 如权利要求1所述的显示面板，其中，一所述像素电极与两所述支扫描电极部分重叠，两所述支扫描电极分设于所述像素电极的两侧。
  11. 如权利要求1所述的显示面板，其中，所述像素电极与前一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
  12. 如权利要求11所述的显示面板，其中，当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平和第一低电平，所述高电平高于所述第一低电平，其中，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步。
  13. 如权利要求11所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的下降沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长的两倍相当，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  14. 如权利要求11所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的下降沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长相当，前一级扫描线上扫描信号的高电平下降沿与本级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  15. 如权利要求1所述的显示面板，其中，所述像素电极与后一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
  16. 如权利要求15所述的显示面板，其中，所述像素还包括开关器件，所述开关器件包括源极、漏极和栅极，其中，源极和栅极之间形成寄生电容Cgs；
    当所述显示面板处于运行状态时，所述扫描线上的扫描信号包括有高电平Vgh、第一低电平Vgl1和第二低电平Vgl2，所述高电平Vgh高于所述第一低电平Vgl1，所述第一低电平Vgl1高于所述第二低电平Vgl2，所述第二低电平Vgl2位于所述高电平Vgh的上升沿侧，且所述第二低电平Vgl2的第二持续时长与所述高电平Vgh的第一持续时长相当，本级扫描线上扫描信号的高电平下降沿与后一级扫描线上扫描信号的高电平上升沿相同步；
    所述存储电容Cst满足Cst=(Vgh-Vgl1)*Cgs/(Vgl1-Vgl2)。
  17. 一种显示面板，其中，所述显示面板包括：
    多条数据线；
    多条扫描线，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；以及，
    多个像素，所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容，一所述像素电极与两所述支扫描电极部分重叠，两所述支扫描电极分设于所述像素电极的两侧，所述像素电极与前一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠，或所述像素电极与后一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
  18. 一种显示装置，其中，所述显示装置包括显示面板，所述显示面板包括：
    多条数据线；
    多条扫描线，所述扫描线包括主扫描电极和支扫描电极，同一所述扫描线的所述主扫描电极和所述支扫描电极电连接，至少部分所述支扫描电极沿所述数据线的延伸方向延伸且与所述数据线相邻设置；以及，
    多个像素，所述像素包括像素电极，所述像素电极与所述支扫描电极部分重叠，以形成存储电容。
  19. 如权利要求18所述的显示装置，其中，所述像素电极与所述主扫描电极和所述支扫描电极部分重叠，以形成存储电容。
  20. 如权利要求18所述的显示装置，其中，所述像素电极与前一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠；或，
    所述像素电极与后一级所述扫描线的所述支扫描电极和/或所述主扫描电极部分重叠。
PCT/CN2019/076169 2019-01-30 2019-02-26 显示面板和显示装置 Ceased WO2020155253A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/982,794 US11079642B2 (en) 2019-01-30 2019-02-26 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910097770.5 2019-01-30
CN201910097770.5A CN109613777B (zh) 2019-01-30 2019-01-30 显示面板和显示装置

Publications (1)

Publication Number Publication Date
WO2020155253A1 true WO2020155253A1 (zh) 2020-08-06

Family

ID=66021206

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/076169 Ceased WO2020155253A1 (zh) 2019-01-30 2019-02-26 显示面板和显示装置

Country Status (3)

Country Link
US (1) US11079642B2 (zh)
CN (1) CN109613777B (zh)
WO (1) WO2020155253A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117518655A (zh) * 2023-09-05 2024-02-06 惠州华星光电显示有限公司 显示面板、终端设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW351464U (en) * 1991-09-05 1999-01-21 Samsung Electronics Co Ltd Abstract liquid crystal display
JP2007034327A (ja) * 1995-05-08 2007-02-08 Semiconductor Energy Lab Co Ltd 表示装置
CN101887897A (zh) * 2009-05-13 2010-11-17 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102707526A (zh) * 2012-06-13 2012-10-03 深圳市华星光电技术有限公司 一种液晶显示面板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6014191A (en) * 1996-07-16 2000-01-11 Samsung Electronics Co., Ltd. Liquid crystal display having repair lines that cross data lines twice and cross gate lines in the active area and related repairing methods
JPH09230387A (ja) * 1997-01-23 1997-09-05 Casio Comput Co Ltd マトリックス型液晶表示装置
KR100260359B1 (ko) * 1997-04-18 2000-07-01 김영환 액정 표시 장치 및 그 제조방법
US5953088A (en) * 1997-12-25 1999-09-14 Kabushiki Kaisha Toshiba Liquid crystal display with shield electrodes arranged to alternately overlap adjacent pixel electrodes
US6421038B1 (en) * 1998-09-19 2002-07-16 Lg. Philips Lcd Co., Ltd. Active matrix liquid crystal display
CN101738804B (zh) * 2009-12-30 2011-10-05 友达光电股份有限公司 像素结构
CN101770125A (zh) * 2010-01-11 2010-07-07 深超光电（深圳）有限公司 双扫描线像素阵列基板
CN102156359B (zh) * 2010-06-13 2014-05-07 京东方科技集团股份有限公司 阵列基板、液晶面板和液晶显示器及驱动方法
CN102956214A (zh) * 2012-11-19 2013-03-06 京东方科技集团股份有限公司 一种公共电极驱动单元、液晶显示面板和液晶显示装置
CN104062781B (zh) * 2014-06-09 2016-08-24 深圳市华星光电技术有限公司 阵列基板及曲面显示装置
CN104834132B (zh) * 2015-05-11 2018-02-06 京东方科技集团股份有限公司 显示面板、调试画面闪烁的方法及装置、显示装置
TWI564645B (zh) * 2015-10-08 2017-01-01 友達光電股份有限公司 畫素陣列及畫素單元的修補方法
US10923064B2 (en) * 2017-04-17 2021-02-16 Sharp Kabushiki Kaisha Scanning signal line drive circuit and display device equipped with same
CN109116641A (zh) * 2018-10-22 2019-01-01 重庆惠科金渝光电科技有限公司 显示面板和显示装置
CN109192170B (zh) * 2018-10-23 2021-07-06 惠科股份有限公司 显示面板的馈穿补偿方法及装置、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW351464U (en) * 1991-09-05 1999-01-21 Samsung Electronics Co Ltd Abstract liquid crystal display
JP2007034327A (ja) * 1995-05-08 2007-02-08 Semiconductor Energy Lab Co Ltd 表示装置
CN101887897A (zh) * 2009-05-13 2010-11-17 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN102707526A (zh) * 2012-06-13 2012-10-03 深圳市华星光电技术有限公司 一种液晶显示面板

Also Published As

Publication number Publication date
US20210003898A1 (en) 2021-01-07
US11079642B2 (en) 2021-08-03
CN109613777B (zh) 2021-06-04
CN109613777A (zh) 2019-04-12

Similar Documents

Publication Publication Date Title
WO2020082413A1 (zh) 显示面板和显示装置
KR101143004B1 (ko) 시프트 레지스터 및 이를 포함하는 표시 장치
TWI404005B (zh) 光感測器及包含光感測器之顯示器裝置
JP3846057B2 (ja) 電気光学装置の駆動回路及び電気光学装置並びに電子機器
JP2018077505A (ja) ディスプレイパネル及びその駆動回路
CN1246817C (zh) 平板显示器及其驱动方法
CN104991363A (zh) 补偿反馈电压的像素单元电路
WO2020119557A1 (zh) 显示驱动方法和显示装置
WO2016000296A1 (zh) 低色偏液晶阵列基板及其驱动方法
WO2020155254A1 (zh) 显示面板的驱动方法及显示设备
WO2018126510A1 (zh) 一种阵列基板及显示装置
CN114464149A (zh) 像素单元及其驱动方法、液晶显示面板
CN106373966A (zh) 阵列基板、显示面板及显示装置
KR20200020328A (ko) Oled 표시패널과 이를 이용한 oled 표시 장치
KR101970800B1 (ko) 액정표시장치
WO2020024530A1 (zh) 驱动装置、显示装置及液晶显示器
WO2025020489A1 (zh) 像素电路及显示面板
WO2020155253A1 (zh) 显示面板和显示装置
WO2014071622A1 (zh) 一种双面显示装置及其控制方法
CN104951142B (zh) 一种触控显示面板和显示装置
KR20070122317A (ko) 액정 모듈, 액정 모듈의 구동 방법 및 액정표시장치
WO2023178750A1 (zh) 显示面板和显示装置
JPH06222741A (ja) 液晶表示装置の駆動方法および駆動回路
WO2014187124A1 (zh) 电极的电压控制方法及装置
WO2020077712A1 (zh) 显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19913468

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19913468

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19913468

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 25/01/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 19913468

Country of ref document: EP

Kind code of ref document: A1