WO2020155128A1 - Logarithmic amplifier - Google Patents

Abstract

The embodiment of the present application provides a logarithmic amplifier, relating to the technical field of circuit, and being able to solve the problem of low signal detection accuracy caused by big system error of the logarithmic amplifier. The logarithmic amplifier comprises a cascade amplifier, a summing circuit and a gain amplification circuit. The cascade amplifier comprises a first amplifier and a second amplifier cascaded to the first amplifier. The gain amplification circuit is used for performing gain amplification to an input signal of the logarithmic amplifier so as to obtain a first signal, the gain of the gain amplification circuit being larger than 1. The first amplifier is used for amplifying the input signal so as to obtain a second signal. The second amplifier is used for amplifying the second signal so as to obtain a third signal. The summing circuit is used for summing the first signal, the second signal and the third signal. The embodiment of the present application is used for illustrating the voltage logarithmic amplifier.

Description

A logarithmic amplifier Technical field

This application relates to the field of circuit technology, and in particular to a logarithmic amplifier.

Background technique

The logarithmic amplifier can convert the detected signal into a logarithmic form, effectively improving the dynamic range of signal detection, and is widely used in signal strength detection circuits (received signal strength indicator, RSSI) in various intermediate frequency or radio frequency signal links. The circuit is used for wireless local area network communication (Wireless Local Area Network Communication), wireless mobile communication (Wireless Mobile Communication) and digital mobile TV (Digital Video Telecom), etc.

When the logarithmic amplifier is a voltage amplifier, the basic schematic diagram of the voltage amplifier is shown in Figure 1. The gain of each voltage amplifier in Fig. 1 is A, and the output voltage V _out =V _in +Vo1+Vo2+Vo3+Vo4. When the input voltage V _in multiples of increment values A, / A ⁴ when, V _in and Vo1, Vo2, Vo3, Vo4 and system error (error) values shown in Table 1 as the initial value of V _in E.

Table 1

V in	Vo1	Vo2	Vo3	Vo4	error
E/A 4	E/A 3	E/A 2	E/A	E	To
E/A 3	E/A 2	E/A	E	AE	E/A 4
E/A 2	E/A	E	AE	AE	E/A 3
E/A	E	AE	AE	AE	E/A 2
E	AE	AE	AE	AE	E/A
AE	AE	AE	AE	AE	E

As can be seen from Table 1, AE is the output swing when each voltage amplifier is saturated, and E is the input swing of the logarithmic amplifier. Then the amplitude response curve of the ideal voltage amplifier can be shown in Figure 2. For how to get the error, when several voltage amplifiers are cascaded, the input of the first voltage amplifier and the output of all cascaded amplifiers can be added together to obtain an approximate logarithmic fitting relationship, and V _in is E/ Take A ⁴ and E/A ³ as examples. When V _in =E/A ⁴ , V _out =E/A ⁴ +E/A ³ +E/A ² +E/A+E, when V _{in is} amplified by A times to E/A ³ , V _out = ^{E / a 3 + E / a} 2 + E / a + E + AE, then V _out of the increment _{ΔV out = AE-E / a} 4, if the ^{AE >> E / a 4, ΔV} out ≈AE, i.e. when The input signal is increased by A times, and the output signal is increased by a fixed amplitude AE. According to this calculation, assuming an ideal logarithmic amplifier, when the error generated by each stage is negligible, it can be obtained that when the input signal changes from E/A ⁴ to AE, the output signal changes from E to E+5AE to reflect an approximate The logarithmic relationship is shown in Figure 3. Since it is a logarithmic approximation, there is a systematic error as the signal increases. For example, according to the previous analysis example, as shown _in Figure 3, when V _in =E, V _out =E+4AE, when V _in =AE, V _out =5AE, at this time ΔV _out =AE-E, the system error reaches E.

It can be seen that the basic principle of a logarithmic amplifier is approximated by a series of cascaded amplifiers, there must be system errors, and the system errors increase with the increase of the input signal, resulting in poor signal detection accuracy of the logarithmic amplifier.

Summary of the invention

The embodiment of the present application provides a logarithmic amplifier, which can solve the problem of large system error of the logarithmic amplifier and poor signal detection accuracy.

In a first aspect, a logarithmic amplifier is provided. The logarithmic amplifier includes a cascade amplifier, a summing circuit, and a gain amplifier circuit. The cascade amplifier includes: a cascaded first amplifier and a second amplifier; wherein: the gain amplifier circuit is used To gain amplify the input signal of the logarithmic amplifier to obtain the first signal, the gain of the gain amplifier circuit is greater than 1; the first amplifier is used to amplify the input signal to obtain the second signal; the second amplifier is used to The two signals are amplified to obtain the third signal; the summing circuit is used to sum the first signal, the second signal and the third signal. That is, this application adds an extra gain stage to the input of the traditional log amplifier, the gain of the extra gain stage is greater than 1, and the output signal of the extra gain stage replaces the signal at the input of the log amplifier to participate in the calculation of the log amplifier. And operation, through analysis, it can be obtained that the design of this application can effectively reduce the systematic error in each signal range.

In a possible design, the gain of each stage of the cascade amplifier is A, and the gain of the gain amplifier circuit is (A+1)/A. Comparing the system error with the traditional logarithmic amplifier shown in Figure 1 through calculation and analysis, when the gain of this additional gain stage is set to (A+1)/A, the system fitting error within each signal range can be reduced by A times.

In a possible design, the gain of each amplifier in the cascade amplifier is A, and the gain of the gain amplifier circuit is

m is a natural number greater than or equal to 2. By calculating and analyzing the system error of the traditional log amplifier shown in Figure 1, the gain of this additional gain stage is set as

When, the system fitting error within each signal range can be reduced by multiples of A. For example, when V _in from the E / ^{A. 4} increased E / ³ time A, the additional gain stage gain of (1 + 1 / A + 1 / A 2) , the systematic error is reduced from E / ^{A. 4} to the E / A ^6. Reduced A ² times.

In a possible design, the input end of the gain amplifier circuit is coupled with the input end of the logarithmic amplifier, and the output end of the gain amplifier circuit is coupled with the first input end of the summing circuit; the input end of the first amplifier is coupled with the logarithmic amplifier. The input of the first amplifier is coupled to the second input of the summing circuit; the input of the second amplifier is coupled to the output of the first amplifier, and the output of the second amplifier is coupled to the third of the summing circuit. Input coupling.

In a possible design, the cascaded amplifier further includes a third amplifier and a fourth amplifier cascaded with the first amplifier and the second amplifier, and the gains of the third amplifier and the fourth amplifier are the same as those of the first amplifier and the second amplifier. The gain of the third amplifier is the same; the third amplifier is used to amplify the third signal to obtain the fourth signal; the fourth amplifier is used to amplify the fourth signal to obtain the fifth signal; the summing circuit is specifically used to The signal, the second signal, the third signal, the fourth signal and the fifth signal are summed.

In a second aspect, a logarithmic amplifier is provided. The logarithmic amplifier includes a cascade amplifier, a summing circuit, a first gain amplifier circuit, a second gain amplifier circuit, and a third gain amplifier circuit; the cascade amplifier includes: a cascaded first An amplifier and a second amplifier; where: the first gain amplifier circuit is used to gain amplify the input signal of the logarithmic amplifier to obtain the first signal; the first amplifier is used to amplify the input signal to obtain the second signal; The second amplifier is used to amplify the second signal to obtain the third signal; the second gain amplifier circuit is used to amplify the second signal to obtain the fourth signal; the third gain amplifier circuit is used to amplify the third signal Amplify to obtain the fifth signal; the gains of the second gain amplifying circuit and the third gain amplifying circuit are both less than 1; and the summing circuit is used to sum the first signal, the fourth signal, and the fifth signal. That is, the present application adds an additional gain stage to the input end of the traditional logarithmic amplifier, the gain of the additional gain stage may be equal to 1, and the output signal of the additional gain stage replaces the signal at the input end of the logarithmic amplifier to participate in the logarithmic amplifier. Sum operation, and add a gain amplifier circuit to the circuit of each stage of the cascaded amplifier output to the summation circuit. The gain of the gain amplifier circuit is less than 1. It can be found through analysis that the design of this application can effectively reduce The systematic error within the range of each segment of the signal.

In a possible design, the gain of each stage of the cascade amplifier is A, the gain of the first gain amplifier circuit is 1, and the gain of the second gain amplifier circuit and the third gain amplifier circuit are both A/(A+ 1). After analysis of this design, the system error in each signal range can be reduced by A+1 times compared with the logarithmic amplifier provided in Figure 1.

In a possible design, the gain of each stage of the cascaded amplifier is A, the gain of the first gain amplifier circuit is 1, and the gain of the second gain amplifier circuit and the third gain amplifier circuit are both

m is a natural number greater than or equal to 2. After analysis of this design, the system error in each signal range can be reduced compared to the logarithmic amplifier provided in Figure 1.

Times. E.g,

When it is 1/(1+1/A+1/A ² ), this application can reduce the systematic error in each signal range by 1+A+A ² times compared with the logarithmic amplifier provided in FIG. 1.

In a possible design, the input terminal of the first gain amplifier circuit is coupled with the input terminal of the logarithmic amplifier, and the output terminal of the first gain amplifier circuit is coupled with the first input terminal of the summing circuit; The input terminal is coupled with the output terminal of the first amplifier, the output terminal of the second gain amplifier circuit is coupled with the second input terminal of the summing circuit; the input terminal of the third gain amplifier circuit is coupled with the output terminal of the second amplifier, and the third gain The output terminal of the amplifying circuit is coupled with the third input terminal of the summing circuit; the input terminal of the first amplifier is coupled with the input terminal of the logarithmic amplifier, and the output terminal of the first amplifier is coupled with the input terminal of the second amplifier.

In a possible design, the cascaded amplifier further includes a third amplifier and a fourth amplifier cascaded with the first amplifier and the second amplifier, and the gains of the third amplifier and the fourth amplifier are the same as those of the first amplifier and the second amplifier. The gain of the logarithmic amplifier is the same; the logarithmic amplifier also includes a fourth gain amplifier circuit and a fifth gain amplifier circuit; the gains of the fourth gain amplifier circuit and the fifth gain amplifier circuit are the same as those of the second gain amplifier circuit and the third gain amplifier circuit ; The third amplifier is used to amplify the third signal to obtain the sixth signal; the fourth amplifier is used to amplify the sixth signal to obtain the seventh signal; the fourth gain amplifier circuit is used to perform the sixth signal Amplify to obtain the eighth signal; the fifth gain amplifier circuit is used to amplify the seventh signal to obtain the ninth signal; the summing circuit is used to amplify the first signal, the fourth signal, the fifth signal, and the eighth signal. The ninth signal is summed.

In a third aspect, the present application provides a network device that includes a transceiver, a memory, and a processor, and the transceiver includes the logarithmic amplifier as described above.

Therefore, the present application adds an additional gain stage to the input end of the traditional logarithmic amplifier. The gain of the additional gain stage is greater than 1, and the output signal of the additional gain stage replaces the signal at the input end of the logarithmic amplifier to participate in the calculation of the logarithmic amplifier. And operation; or, this application adds an additional gain stage to the input of the traditional logarithmic amplifier, the gain of the additional gain stage may be equal to 1, and the output signal of the additional gain stage replaces the signal at the input of the logarithmic amplifier to participate in the logarithmic The summing operation of the amplifier, and adding a gain amplifying circuit to the circuit of each stage of the cascaded amplifier output to the summing circuit, the gain of the gain amplifying circuit is less than 1, which can be obtained through analysis. The design of this application can Effectively reduce the system error in each signal range.

Description of the drawings

Figure 1 is a schematic diagram of a logarithmic amplifier;

Figure 2 is a schematic diagram of the amplitude response curve of an ideal voltage amplifier;

Figure 3 is a schematic diagram of the amplitude response curve of an ideal voltage amplifier;

FIG. 4 is a schematic diagram of a network device including a logarithmic amplifier provided by an embodiment of the application;

FIG. 5 is a schematic diagram of the principle of a logarithmic amplifier provided by an embodiment of the application;

6 is a schematic diagram of the principle of a logarithmic amplifier provided by an embodiment of the application;

FIG. 7 is a schematic diagram of the principle of a logarithmic amplifier provided by an embodiment of the application;

FIG. 8 is a schematic diagram of the principle of a logarithmic amplifier provided by an embodiment of the application;

FIG. 9 is a structural intention of a network device provided by an embodiment of this application.

detailed description

This application can be applied to the RSSI of various intermediate frequency (IF) or radio frequency (IF) signal links, such as wireless network communication, wireless mobile communication and digital mobile TV, etc., and can be specifically used in RSSI Design of log amplifier.

The logarithmic amplifier of this application can be applied to various network equipment. For example, the logarithmic amplifier in the receiver of the network equipment can detect the input signal and realize the dynamic adjustment of the gain of the receiver; for example, the transmitter of the network equipment is transmitting The signal can be detected by a logarithmic amplifier, and then the transmitter transmit power can be dynamically adjusted. The characteristic of the logarithmic amplifier is to provide a large dynamic range detection capability while highlighting the cost advantage. For example, in a mobile communication system, Code Division Multiple Access (CDMA) and Global System for Mobile Communication (GSM) both need to adjust the power output of the base station to match the target mobile phone and the local base station for communication. The distance is required to minimize the possibility of overloading of mobile phones near the base station. Similarly, the base station also needs to adjust the gain of the receiving channel to increase the signal-to-noise ratio and reduce the bit error rate. Such a large number of logarithmic amplifiers are used in RSSI and transmit power control applications. In the design of intermediate frequency amplifiers in some radio receiving channels, logarithmic amplifiers can also be used. For example, the single-chip AD8307 can complete the signal reception and demodulation function, and the dynamic range can reach 92dBm after the front-end performs appropriate frequency matching.

As shown in FIG. 4, the network devices here may be, for example, base stations, terminal devices, and other devices.

The base station can be a device that can communicate with terminal devices. The base station can be a relay station or an access point. The base station can be a base transceiver station (BTS) in a GSM or CDMA network, or a NB (NodeB) in wideband code division multiple access (WCDMA), or a long-term evolution (Long Term Evolution, LTE) eNB or eNodeB (evolutional NodeB). The base station may also be a wireless controller in a cloud radio access network (cloud radio access network, CRAN) scenario. The base station can also be a network device in a 5G network or a network device in a public land mobile network (Public Land Mobile Network, PLMN) network that will evolve in the future; it can also be a wearable device or a vehicle-mounted device.

The terminal equipment can be user equipment (UE), access terminal, UE unit, UE station, mobile station, mobile station, remote station, remote terminal, mobile equipment, UE terminal, terminal, wireless communication equipment, UE agent or UE devices, etc. The access terminal can be a cell phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), and wireless communication Functional handheld devices, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminals in 5G networks or terminals in future evolution of PLMN networks, etc.

In the above application scenarios, in order to solve the problem of large logarithmic amplifier system error and poor signal detection accuracy, the present application provides a logarithmic amplifier. The logarithmic amplifier can reduce the signal error and improve the signal error by adding a gain amplifier circuit. Signal detection accuracy.

The logarithmic amplifier provided in this application will be described below.

This application provides a logarithmic amplifier 5, as shown in FIG. 5, the logarithmic amplifier includes a cascade amplifier C, a summing circuit Σ, and a gain amplifier circuit B. The cascade amplifier C includes: a cascaded first amplifier A1 and The second amplifier A2; where:

B gain amplifying circuit, a logarithmic amplifier input signal V _in 5 performs gain amplification, to obtain a first signal Vo0, gain amplifying circuit gain is greater than 1;

A first amplifier A1, an input signal V _in is amplified to obtain a second signal Vo1;

The second amplifier A2 is used to amplify the second signal Vo1 to obtain the third signal Vo2;

The summing circuit Σ is used to sum the first signal Vo0, the second signal Vo1 and the third signal Vo2 to obtain the output signal V _out . That is, V _out can be expressed as:

V _out ＝Vo0+Vo1+Vo2

Compared with the logarithmic amplifier of Fig. 1, the logarithmic amplifier provided in Fig. 5 of this application adds an additional gain stage at the input end of the logarithmic amplifier of Fig. 1. The output Vo0 of the gain amplifier circuit B replaces V _in at the output Position in the transfer function V _out .

The logarithmic amplifier of the present application may be a voltage logarithmic amplifier, and the first signal, the second signal, and the third signal may all be voltage signals.

In conjunction with FIG. 5, the configuration of the logarithmic amplifier 5, the gain of the amplifier circuit B and the input terminal of a logarithmic amplifier input terminal coupled to V 5 _in a, b and gain amplifying an output terminal B of the summing circuit 52 of the first circuit The input terminal c is coupled;

A first input terminal of amplifier A1 and the input terminal V d the logarithmic amplifier is coupled _in the output of the first amplifier A1 and the second input end e l Σ is a summing circuit coupled;

The input terminal f of the second amplifier A2 is coupled with the output terminal e of the first amplifier A1, and the output terminal g of the second amplifier A2 is coupled with the third input terminal m of the summing circuit Σ.

For the gain of the gain amplifier circuit greater than 1, in the first possible design, if the gain of each stage of the cascaded amplifier is A, the gain of the gain amplifier circuit can be (A+1)/A. The final system error when the gain of the gain amplifier circuit is (A+1)/A is compared with the system error in Table 1.

For comparison and description with Table 1 corresponding to FIG. 1, it can be understood that the cascade amplifier C in the logarithmic amplifier 5 shown in FIG. 5 may also include a third amplifier cascaded with the first amplifier A1 and the second amplifier A2. The amplifier A3 and the fourth amplifier A4, as shown in FIG. 6, the gains of the third amplifier A3 and the fourth amplifier A4 are the same as the gains of the first amplifier A1 and the second amplifier A2, and both are A.

The third amplifier A3 is used to amplify the third signal Vo2 to obtain the fourth signal Vo3;

The fourth amplifier A4 is used to amplify the fourth signal Vo3 to obtain the fifth signal Vo4;

The summing circuit Σ is used to sum the first signal Vo0, the second signal Vo1, the third signal Vo2, the fourth signal Vo3, and the fifth signal Vo4.

The input terminal h of the third amplifier A3 is coupled with the output terminal g of the second amplifier, the output terminal of the third amplifier A3 is coupled with the fourth input terminal n of the summing circuit Σ, and the input terminal j of the fourth amplifier A4 is coupled with the third amplifier The output terminal i of the fourth amplifier A4 is coupled to the fifth input terminal o of the summing circuit.

It can be understood that the number of cascaded amplifiers of the cascade amplifier C in the logarithmic amplifier 6 is not limited to include the first amplifier A1, the second amplifier A2, the third amplifier A3, and the fourth amplifier A4, and may include more The amplifier, for example, further includes a fifth amplifier, a sixth amplifier, and a seventh amplifier.

In case the gain amplifier circuit shown in FIG. 6 B is a B amplifier, and the gain of the amplifier B is (A + 1) / A when ^{_{V in = E / A 4,}} A is a cascode amplifier in each stage The gain of the amplifier, when E is the input swing of the logarithmic amplifier, if the gain of the gain amplifier circuit is (A+1)/A, then:

Vo0=[(A+1)/A]*E/A ⁴ Vo1=E/A ³ Vo2=E/A ² Vo3=E/A Vo4=E

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=[(A+1)/A]*E/A ⁴ +E/A ³ +E/A ² +E/A+E

Under the same premise, when the input signal V _in increases by A times, V _in =E/A ³ ,

Vo0=[(A+1)/A]*E/A ³ Vo1=E/A ² Vo2=E/A Vo3=E Vo4=AE

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=[(A+1)/A]*E/A ³ +E/A ² +E/A+E+AE

It can be obtained, when V _in from the E / A ⁴ increased E / A ^3, the increment ΔV _out V _out is:

ΔV _out ＝AE+[(A+1)/A]*E/A ³ -E/A ³ -[(A+1)/A]*E/A ⁴ ＝AE-E/A ⁵

In order to make the output signal of the logarithmic amplifier reflect an approximate logarithmic relationship, take ΔV _out =AE, and the system error is E/A ⁵ at this time. In this way, the logarithmic amplifier shown in Fig. 6 provided by this application is compared with the traditional FIG logarithmic amplifier 1 shown in comparison, it was found that when V _in from the E / a ⁴ increased E / ³ a, the systematic error is reduced from E / a ⁴ to the E / a ^5, a times i.e. reduced.

Similarly available, provided by the logarithmic amplifier of FIG. 6, the V _in = E / A ⁴ to V _in = AE range, according to a first possible design, the system error may be as shown in Table 2. It can be seen that this possible design can be seen. Comparing Table 2 with Table 1, the logarithmic amplifier of this application can reduce the system error in each signal range by A times.

Table 2

V in	Vo0	Vo1	Vo2	Vo3	Vo4	error
E/A 4	[(A+1)/A]*E/A 4	E/A 3	E/A 2	E/A	E	To
E/A 3	[(A+1)/A]*E/A 3	E/A 2	E/A	E	AE	E/A 5
E/A 2	[(A+1)/A]*E/A 2	E/A	E	AE	AE	E/A 4
E/A	[(A+1)/A]*E/A	E	AE	AE	AE	E/A 3
E	[(A+1)/A]*E	AE	AE	AE	AE	E/A 2
AE	[(A+1)/A]AE	AE	AE	AE	AE	E/A

The principle of a logarithmic amplifier is to approximate a logarithmic relationship with the sum of several cascaded amplifiers. There must be a fitting error, and the error increases with the increase of the input signal. In the present application a conventional logarithmic amplifier of the first stage adds the input terminal V _in an additional gain stage B, and the output of the gain stage B input V _in place of the first stage summing operand participation amplifier at this time can effectively reduce System fitting error of each signal range. For example, if the gain of this additional gain stage is set to (A+1)/A, the system fitting error within each signal range can be reduced by A times.

In the second possible design, when the gain of the gain amplifier B in Figure 5 or Figure 6 is greater than 1, if the gain of each amplifier stage in the cascade amplifier C is A, the gain of the gain amplifier circuit B can be

m is a natural number greater than or equal to 2. In other words, the gain of the gain amplifier circuit B may be the sum of the geometric sequence, the first term of the geometric sequence is 1, and the common ratio of the geometric sequence is 1/A.

In this design, the gain of the gain amplifier B can be 1+1/A, 1+1/A+1/A ² , 1+1/A+1/A ² +1/A ³ ... Among them, when the gain of the gain amplifier B is 1+1/A, it is the same as the first possible design.

The value of the gain of the gain amplifier B is described below with an example.

When the gain of each amplifier in the cascade amplifier C is A, AE is the output swing of each amplifier in the cascade amplifier C when it is saturated, and E is the input swing of each amplifier, the gain of the amplifier circuit B is When the gain is 1+1/A+1/A ² , the final system error is compared with the system error in Table 1.

Taking the logarithmic amplifier of this application as the logarithmic amplifier shown in Fig. 6 as an example, the gain amplifier circuit B is an amplifier B, and the gain of the amplifier B is 1+1/A+1/A ² , V _in = In the case of E/A ⁴ , then:

Vo0=(1+1/A+1/A ² )*E/A ⁴ Vo1=E/A ³ Vo2=E/A ² Vo3=E/A Vo4=E

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=(1+1/A+1/A ² )*E/A ⁴ +E/A ³ +E/A ² +E/A+E

Under the same premise, when the input signal V _in increases by A times, V _in =E/A ³ ,

Vo0=(1+1/A+1/A ² )*E/A ³ Vo1=E/A ² Vo2=E/A Vo3=E Vo4=AE

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=(1+1/A+1/A ² )*E/A ³ +E/A ² +E/A+E+AE

It can be obtained, when V _in from the E / A ⁴ increased E / A ^3, the increment ΔV _out V _out is:

ΔV _out ＝(1+1/A+1/A ² )*E/A ³ +E/A ² +E/A+E+AE-(1+1/A+1/A ² )*E/A ⁴ -E/A ³ -E/A ² -E/AE=AE-E/A ⁶

In order to make the output signal of the logarithmic amplifier reflect an approximate logarithmic relationship, take ΔV _out =AE, and the system error is E/A ⁶ at this time. In this way, the logarithmic amplifier shown in Figure 6 provided by this application is compared with the traditional a logarithmic amplifier for comparison shown in FIG. 1, it was found when V _in from the E / a ⁴ increased E / ³ a, the systematic error is reduced from E / a ⁴ to the E / a ^6, a ^2-fold reduced i.e. .

In the same way, according to the logarithmic amplifier provided in FIG. 6, in the range of V _in =E/A ⁴ to V _in =AE, according to the second possible design, the system error can be as shown in Table 3. It can be seen that this possible design, comparing Table 3 with Table 1, shows that the logarithmic amplifier of this application can reduce the system error in each signal range by A ² times.

table 3

V in	Vo0	Vo1	Vo2	Vo3	Vo4	error
E/A 4	(1+1/A+1/A 2 )*E/A 4	E/A 3	E/A 2	E/A	E	To
E/A 3	(1+1/A+1/A 2 )*E/A 3	E/A 2	E/A	E	AE	E/A 6
E/A 2	(1+1/A+1/A 2 )*E/A 2	E/A	E	AE	AE	E/A 5
E/A	(1+1/A+1/A 2 )*E/A	E	AE	AE	AE	E/A 4
E	(1+1/A+1/A 2 )*E	AE	AE	AE	AE	E/A 3
AE	(1+1/A+1/A 2 )AE	AE	AE	AE	AE	E/A 2

That is, a second possible design, the application of a first stage in the conventional logarithmic amplifier input terminal V _in an additional increase in gain stage B, and the output of the gain stage B V _in place of the first input stage participation The summing operation of the digital amplifier can effectively reduce the system fitting error of each signal range at this time. For example, if the gain of this additional gain stage is set to (1+1/A+1/A ² ), the system fitting error within each signal range can be reduced by A ² times.

This application may also have logarithmic amplifiers different from those designed in Figs. 5 and 6. As shown in Fig. 7, the logos in Figs. 7 and 8 have nothing to do with the logos in Figs. 5 and 6. The logarithmic amplifier 7 includes a cascade amplifier C, a summing circuit Σ, a first gain amplifier circuit P, a second gain amplifier circuit M, and a third gain amplifier circuit N. The cascade amplifier C includes a cascaded first amplifier A1 and a first Two amplifier A2, of which:

A first P gain amplifying circuit, a logarithmic amplifier input signal V _in 7 of the amplification gain, to obtain a first signal Vo0;

A first amplifier A1, an input signal V _in is amplified to obtain a second signal Voa1;

The second amplifier A2 is used to amplify the second signal VoA1 to obtain the third signal VoA2;

The second gain amplifying circuit M is used to amplify the second signal VoA1 to obtain the fourth signal Vo1;

The third gain amplifier circuit N is used to amplify the third signal VoA2 to obtain the fifth signal Vo2; the gains of the second gain amplifier circuit M and the third gain amplifier circuit N are both less than 1;

The summing circuit Σ is used to sum the first signal Vo0, the fourth signal Vo1 and the fifth signal Vo2 to obtain the output signal V _out . That is, V _out can be expressed as:

V _out ＝Vo0+Vo1+Vo2

Logarithmic amplifier of FIG. 7 of the present application provides a logarithmic amplifier compared to FIG. 1, increases the output levels of a P gain amplifying circuit, the cascode amplifier of FIG C is increased in a first stage of the logarithmic amplifier input V _in 1 of An additional gain stage, that is, the second gain amplifier circuit M and the third gain amplifier circuit N, the output Vo0 of the first gain amplifier circuit P replaces the position of Vin _in the output transfer function V _out , and the second gain amplifier circuit The output Vo1 of M replaces the position of the output of the first-stage amplifier A1 in the transfer function V _out , and the output Vo2 of the third gain amplifier circuit N replaces the position of the output of the second-stage amplifier A2 in the transfer function V _out .

In conjunction with FIG. 7, the configuration of the logarithmic amplifier 7, the first gain amplifying circuit with a P input terminal of the input terminal V _in is coupled to the logarithmic amplifier 7, a first gain amplifier and a summing circuit output terminal b of the circuit P The first input terminal c of Σ is coupled;

The input terminal p of the second gain amplifier circuit M is coupled with the output terminal e of the first amplifier A1, and the output terminal q of the second gain amplifier circuit N is coupled with the second input terminal l of the summing circuit Σ;

The input terminal r of the third gain amplifier circuit N is coupled with the output terminal g of the second amplifier A2, and the output terminal s of the third gain amplifier circuit N is coupled with the third input terminal m of the summing circuit Σ;

A first input terminal of amplifier A1 and d the logarithmic amplifier input coupled to V 7 _in the output of the first amplifier A1 and the terminal e of the second amplifier A2 is coupled to an input terminal f.

The difference between the logarithmic amplifier of the logarithmic amplifier illustrated in FIG. 7 or FIG. 7 and FIG. 6 may be 5: the number of amplifier 7, for a logarithmic amplifier input signal V _in 7 of the first amplifying gain The gain of the gain amplifier circuit P is 1. At this time, if the gain of each stage of the cascade amplifier C of the log amplifier 7 is the same as the gain of each stage of the cascade amplifier C of the log amplifier 5 or the log amplifier 6, The gain of the gain amplifying circuit for gain amplifying the output signal of each amplifier of the cascade amplifier C of the logarithmic amplifier 7 and the gain amplifying circuit B for gain amplifying the input signal of the logarithmic amplifier 5 or the logarithmic amplifier 6 The gain of can be the inverse of each other. For example, the gain of the second gain amplifier circuit M or the third gain amplifier circuit N and the gain of the gain amplifier circuit B are reciprocal of each other.

It should be noted that the value of the gain of the second gain amplifying circuit M and the value of the gain of the third amplifying circuit N may be the same or different. This application takes the same as an example for description.

Regarding that the gains of the second gain amplifying circuit M and the third gain amplifying circuit N are both less than 1, in the third possible design, if the gain of each stage of the cascade amplifier is A, the second gain amplifying circuit M and the third The gain of the gain amplifier circuit N can all be A/(A+1). Next, when the gain of the first gain amplifying circuit P is 1, the gains of the second gain amplifying circuit M and the third gain amplifying circuit N are both A/(A+1), the final system error is compared with the system error in Table 1. Comparison description.

In order to compare with Table 1 corresponding to Fig. 1, it can be understood that the cascaded amplifier C in the logarithmic amplifier 7 shown in Fig. 7 may also include a third cascaded amplifier A1 and a second amplifier A2. The amplifier A3 and the fourth amplifier A4, as shown in FIG. 8, the gains of the third amplifier A3 and the fourth amplifier A4 are the same as the gains of the first amplifier A1 and the second amplifier A2, both are A/(A+1).

The log amplifier 7 also includes a fourth gain amplifier circuit Q and a fifth gain amplifier circuit Z; the gains of the fourth gain amplifier circuit Q and the fifth gain amplifier circuit Z are the same as those of the second gain amplifier circuit M and the third gain amplifier circuit N. The gain is the same;

The third amplifier A3 is used to amplify the third signal VoA2 to obtain the sixth signal VoA3;

The fourth amplifier A4 is used to amplify the sixth signal VoA3 to obtain the seventh signal VoA4;

The fourth gain amplifying circuit Q is used to amplify the sixth signal VoA3 to obtain the eighth signal Vo3;

The fifth gain amplifying circuit Z is used to amplify the seventh signal VoA4 to obtain the ninth signal Vo4;

The summing circuit Σ is used to sum the first signal Vo0, the fourth signal Vo1, the fifth signal Vo2, the eighth signal Vo3, and the ninth signal Vo4.

The input terminal h of the third amplifier A3 is coupled with the output terminal of the second amplifier A2, the output terminal i of the third amplifier A3 is coupled with the input terminal j of the fourth amplifier, and the output terminal k of the fourth amplifier is coupled with the fifth gain amplifier circuit Z The input terminal v of the fourth gain amplifier circuit Q is coupled with the output terminal of the third amplifier A3, the output terminal u of the fourth gain amplifier circuit Q is coupled with the fourth input terminal n of the summing circuit Σ, and the fifth The output terminal w of the gain amplifier circuit Z is coupled with the fifth input terminal o of the summing circuit Σ.

It can be understood that the number of cascaded amplifiers of the cascade amplifier C in the logarithmic amplifier 8 is not limited to include the first amplifier A1, the second amplifier A2, the third amplifier A3, and the fourth amplifier A4, and may also include more The amplifier, for example, also includes a fifth amplifier, a sixth amplifier, and a seventh amplifier. Accordingly, the fifth amplifier, the sixth amplifier, and the seventh amplifier also correspond to the sixth gain amplifier circuit, the seventh gain amplifier circuit, and the eighth amplifier. Gain amplifier circuit.

The five circuits from the first gain amplifying circuit to the fifth gain amplifying circuit in FIG. 8 can all be implemented by amplifiers.

When V _in =E/A ⁴ , A is the gain of each amplifier in the cascade amplifier C, and E is the input swing of the logarithmic amplifier 8, if the gain of the first gain amplifier circuit in Figure 8 is 1, The gains of the second gain amplifying circuit M, the third gain amplifying circuit N, the fourth gain amplifying circuit Q, and the fifth gain amplifying circuit Z are all A/(A+1), then:

Vo0=E/A ⁴ Vo1=E/(A+1)A ² Vo2=E/(A+1)A Vo3=E/(A+1)

Vo4=EA/(A+1)

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=E/A ⁴ +E/(A+1)A ² +E/(A+1)A+E/(A+1)+EA/ (A+1)=(E+A ² E+A ³ E+A ⁴ E+A ⁵ E)/A ⁴ (A+1)

Under the same premise, when the input signal V _in increases by A times, V _in =E/A ³ ,

Vo0=E/A ³ Vo1=E/(A+1)A Vo2=E/(A+1) Vo3=EA/(A+1)

Vo4=EA ² /(A+1)

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=E/A ³ +E/(A+1)A+E/(A+1)+EA/(A+1)+EA ² /( A+1)

It can be obtained, when V _in from the E / A ⁴ increased E / A ^3, the increment ΔV _out V _out is:

ΔV _out ＝A ² E/(A+1)-E/A ⁴ (A+1)

In order to make the output signal of the logarithmic amplifier reflect an approximate logarithmic relationship, take ΔV _out =A ² E/(A+1), and the system error is E/A ⁴ (A+1). Figure 8 provides a logarithmic amplifier compared with the number of conventional amplifier shown in FIG. 1, it is found that when V _in from the E / a ⁴ increased E / ³ a, the system error from E / a ⁴ Reduced to E/A ⁴ (A+1), that is, reduced by A+1 times.

Similarly available, provided by the logarithmic amplifier of FIG. 8, in V _in = E / A ⁴ to V _in the range of = AE, according to a third possible design, system errors may be as shown in Table 4. It can be seen that this possible design, comparing Table 4 with Table 1, shows that the logarithmic amplifier of the present application can reduce the system error in each signal range by a factor of A+1.

Table 4

V in	Vo0	Vo1	Vo2	Vo3	Vo4	error
E/A 4	E/A 4	E/(A+1)A 2	E/(A+1)A	E/(A+1)	EA/(A+1)	To
E/A 3	E/A 3	E/(A+1)A	E/(A+1)	EA/(A+1)	EA 2 /(A+1)	E/A 4 (A+1)
E/A 2	E/A 2	E/(A+1)	EA/(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	E/A 3 (A+1)
E/A	E/A	EA/(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	E/A 2 (A+1)
E	E	EA 2 /(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	E/A(A+1)
AE	AE	EA 2 /(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	EA 2 /(A+1)	E/(A+1)

In Table 4, EA ² /(A+1) is the output swing when the second gain amplifying circuit Q to the fifth gain amplifying circuit Z are saturated, and E is the input swing of the logarithmic amplifier 8.

That is, in the conventional application of this first stage of the logarithmic amplifier input terminal V _in an additional increase in gain stage P, the output P and the gain stage input V _in place of the first stage summing operation involved in the logarithmic amplifier, In addition, a gain amplifier circuit is added to the circuit where each stage of the cascaded amplifier C outputs to the summing circuit. At this time, the system fitting error of each signal range can be effectively reduced. For example, the gain of the gain stage P is 1, and the gain of the gain amplifier circuit added to the circuit of each stage of the cascade amplifier C output to the summing circuit is A/(A+1), and the system fitting error within the range of each signal Can reduce A+1 times.

In the fourth possible design, the gain of the first gain amplifying circuit P in FIG. 7 or 8 is equal to 1, the second gain amplifying circuit M, the third gain amplifying circuit N, the fourth gain amplifying circuit Q, and the fifth When the gain amplifier circuit Z is less than 1, if the gain of each amplifier in the cascade amplifier C is A, the second gain amplifier circuit M, the third gain amplifier circuit N, the fourth gain amplifier circuit Q, and the fifth gain amplifier circuit The gain of Z can be

m is a natural number greater than or equal to 2. In other words, the gains of M, N, Q, and Z can be the reciprocal of the sum of the geometric sequence, the first term of the geometric sequence is 1, and the common ratio is 1/A.

In this design, the gains of M, N, Q and Z can be A/(1+A), 1/(1+1/A+1/A ² ), 1/1+1/A+1/A ² +1/A ³ ) and so on. Among them, when the gains of M, N, Q, and Z are A/(1+A), it is the same as the fourth possible design.

The gains of the gain amplifiers M, N, Q, and Z will be exemplified below.

The gain of each amplifier in the cascade amplifier C is A, EA ² /(A+1) is the output swing when the gain amplifier circuit of each amplifier in the cascade amplifier C is saturated, and E is the logarithmic amplifier 8 In the case of input swing, the final system error when the gain of the gain amplifier circuit M, N, Q, and Z is 1/(1+1/A+1/A ² ) is compared with the system error in Table 1.

Taking the logarithmic amplifier of the present application as the logarithmic amplifier 8 shown in FIG. 8 as an example, the gain amplifier circuits M, N, Q, and Z are one amplifier, and the gain of the amplifier is 1/(1+1/A+ 1/A ² ), _{in the} case of V _in =E/A ⁴ , then:

Vo0=E/A ⁴ Vo1=E/A(1+A+A ² ) Vo2=E/(1+A+A ² )

Vo3=AE/(1+A+A ² ) Vo4=A ² E/(1+A+A ² )

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=E/A ⁴ +E/A(1+A+A ² )+E/(1+A+A ² )+AE/(1+A +A ² )+A ² E/(1+A+A ² )=(E+AE+A ² E+A ³ E+A ⁴ E+A ⁵ E+A ⁶ E)/A ⁴ (1+A +A ² )

Under the same premise, when the input signal V _in increases by A times, V _in =E/A ³ ,

Vo0=E/A ³ Vo1=E/(1+A+A ² ) Vo2=AE/(1+A+A ² )

Vo3=A ² E/(1+A+A ² ) Vo4=A ³ E/(1+A+A ² )

At this time, V _out =Vo0+Vo1+Vo2+Vo3+Vo4=E/A ³ +E/(1+A+A ² )+AE/(1+A+A ² )+A ² E/(1+ A+A ² )+A ³ E/(1+A+A ² )

It can be obtained, when V _in from the E / A ⁴ increased E / A ^3, the increment ΔV _out V _out is:

ΔV _out ＝A ³ E/(1+A+A ² )-E/A ⁴ (1+A+A ² )

In order to make the output signal of the logarithmic amplifier reflect an approximate logarithmic relationship, take ΔV _out = A ³ E/(1+A+A ² ), and the system error is E/A ⁴ (1+A+A ² ), so that the present application is shown in Figure 8 provides a comparison of the logarithmic amplifier and logarithmic amplifier shown in FIG conventional, it can be found when V _in from the E / a ⁴ increased E / ³ a, the system The error is reduced from E/A ⁴ to E/A ⁴ (1+A+A ² ), which is reduced by 1+A+A ² times.

In the same way, according to the logarithmic amplifier provided in Fig. 8, in the range of V _in =E/A ⁴ to V _in =AE, according to the fourth possible design, the system error can be as shown in Table 5. It can be seen that this possible design can be seen. Comparing Table 5 with Table 1, the logarithmic amplifier of the present application can reduce the system error in each signal range by 1+A+A ² times.

table 5

V in	Vo0	Vo1	Vo2	Vo3	Vo4	error
E/A 4	E/A 4	E/A(1+A+A 2 )	E/(1+A+A 2 )	AE/(1+A+A 2 )	A 2 E/(1+A+A 2 )	To
E/A 3	E/A 3	E/(1+A+A 2 )	AE/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 3 E/(1+A+A 2 )	E/A 4 (1+A+A 2 )
E/A 2	E/A 2	AE/(A+1)	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	E/A 3 (1+A+A 2 )
E/A	E/A	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	E/A 2 (1+A+A 2 )
E	E	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	E/A(1+A+A 2 )
AE	AE	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	A 2 E/(1+A+A 2 )	E/(1+A+A 2 )

That is, in the conventional application of this first stage of the logarithmic amplifier input terminal V _in an additional increase in gain stage P, the output P and the gain stage input V _in place of the first stage summing operation involved in the logarithmic amplifier, In addition, a gain amplifier circuit is added to the circuit where each stage of the cascaded amplifier C outputs to the summing circuit. At this time, the system fitting error of each signal range can be effectively reduced. For example, the gain of the gain stage P is 1, and the gain of each amplifier stage of the cascade amplifier C output to the circuit of the summing circuit is 1/(1+1/A+1/A ² ), and each stage The system fitting error within the signal range can be reduced by (1+A+A ² ) times.

Referring to FIG. 9, the present application provides a network device 9 which may be a base station, terminal device, etc. The network device 9 includes a processor 902, a transceiver 903, a memory 901, and a bus 904. Among them, the transceiver 903, the processor 902, and the memory 901 are connected to each other through the bus 904; the transceiver 903 may include the functions of a receiver and a transmitter, and both the receiver and the transmitter may include the logarithmic amplifier involved in the above embodiments. 5. Or logarithmic amplifier 6, or logarithmic amplifier 7 or logarithmic amplifier 8, etc. The bus 904 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus or the like. The bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in FIG. 9 to represent, but it does not mean that there is only one bus or one type of bus.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application shall be covered by the protection scope of this application . Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (11)

1. A logarithmic amplifier, characterized in that, the logarithmic amplifier includes a cascade amplifier, a summing circuit and a gain amplifier circuit, the cascade amplifier includes: a cascaded first amplifier and a second amplifier; wherein:

   The gain amplifying circuit is used for gain amplifying the input signal of the logarithmic amplifier to obtain a first signal, and the gain of the gain amplifying circuit is greater than 1;

   The first amplifier is used to amplify the input signal to obtain a second signal;

   The second amplifier is used to amplify the second signal to obtain a third signal;

   The summing circuit is used to sum the first signal, the second signal, and the third signal.
2. The logarithmic amplifier according to claim 1, wherein the gain of each amplifier stage in the cascade amplifier is A, and the gain of the gain amplifier circuit is (A+1)/A.
3. The logarithmic amplifier of claim 1, wherein the gain of each stage of the amplifier in the cascade amplifier is A, and the gain of the gain amplifier circuit is

   

   m is a natural number greater than or equal to 2.
4. The logarithmic amplifier according to any one of claims 1-3, wherein the input end of the gain amplifier circuit is coupled with the input end of the logarithmic amplifier, and the output end of the gain amplifier circuit is coupled to the input end of the logarithmic amplifier. The first input terminal of the summing circuit is coupled;

   The input terminal of the first amplifier is coupled with the input terminal of the logarithmic amplifier, and the output terminal of the first amplifier is coupled with the second input terminal of the summing circuit;

   The input terminal of the second amplifier is coupled with the output terminal of the first amplifier, and the output terminal of the second amplifier is coupled with the third input terminal of the summing circuit.
5. The logarithmic amplifier according to any one of claims 1 to 4, wherein the cascade amplifier further comprises a third amplifier and a fourth amplifier cascaded with the first amplifier and the second amplifier, The gains of the third amplifier and the fourth amplifier are the same as the gains of the first amplifier and the second amplifier;

   The third amplifier is used to amplify the third signal to obtain a fourth signal;

   The fourth amplifier is used to amplify the fourth signal to obtain a fifth signal;

   The summing circuit is specifically configured to sum the first signal, the second signal, the third signal, the fourth signal, and the fifth signal.
6. A logarithmic amplifier, characterized in that the logarithmic amplifier includes a cascade amplifier, a summing circuit, a first gain amplifier circuit, a second gain amplifier circuit, and a third gain amplifier circuit; the cascade amplifier includes: The first amplifier and the second amplifier connected together; where:

   The first gain amplifying circuit is used for gain amplifying the input signal of the logarithmic amplifier to obtain a first signal;

   The first amplifier is used to amplify the input signal to obtain a second signal;

   The second amplifier is used to amplify the second signal to obtain a third signal;

   The second gain amplifying circuit is used to amplify the second signal to obtain a fourth signal;

   The third gain amplifying circuit is configured to amplify the third signal to obtain a fifth signal; the gains of the second gain amplifying circuit and the third gain amplifying circuit are both less than 1;

   The summing circuit is used to sum the first signal, the fourth signal, and the fifth signal.
7. The logarithmic amplifier according to claim 6, wherein the gain of each amplifier in the cascade amplifier is A, the gain of the first gain amplifying circuit is 1, and the second gain amplifying circuit and the The gain of the third gain amplifier circuit is A/(A+1).
8. The logarithmic amplifier according to claim 6, wherein the gain of each amplifier in the cascade amplifier is A, the gain of the first gain amplifying circuit is 1, and the second gain amplifying circuit and the The gain of the third gain amplifier circuit is

   

   m is a natural number greater than or equal to 2.
9. The logarithmic amplifier according to any one of claims 6-8, wherein the input of the first gain amplifying circuit is coupled to the input of the logarithmic amplifier, and the output of the first gain amplifying circuit Terminal is coupled with the first input terminal of the summing circuit;

   The input terminal of the second gain amplifier circuit is coupled with the output terminal of the first amplifier, and the output terminal of the second gain amplifier circuit is coupled with the second input terminal of the summing circuit;

   The input terminal of the third gain amplifier circuit is coupled with the output terminal of the second amplifier, and the output terminal of the third gain amplifier circuit is coupled with the third input terminal of the summing circuit;

   The input terminal of the first amplifier is coupled with the input terminal of the logarithmic amplifier, and the output terminal of the first amplifier is coupled with the input terminal of the second amplifier.
10. The logarithmic amplifier according to any one of claims 6-9, wherein the cascade amplifier further comprises a third amplifier and a fourth amplifier cascaded with the first amplifier and the second amplifier, The gains of the third amplifier and the fourth amplifier are the same as those of the first amplifier and the second amplifier; the logarithmic amplifier further includes a fourth gain amplifying circuit and a fifth gain amplifying circuit; the first Gains of the four-gain amplifying circuit and the fifth gain amplifying circuit are the same as the gains of the second gain amplifying circuit and the third gain amplifying circuit;

    The third amplifier is used to amplify the third signal to obtain a sixth signal;

    The fourth amplifier is used to amplify the sixth signal to obtain a seventh signal;

    The fourth gain amplifying circuit is used to amplify the sixth signal to obtain an eighth signal;

    The fifth gain amplifying circuit is used to amplify the seventh signal to obtain a ninth signal;

    The summing circuit is used to sum the first signal, the fourth signal, the fifth signal, the eighth signal, and the ninth signal.
11. A network device, wherein the network device includes a transceiver, a processor, and a memory, and the transceiver includes the logarithmic amplifier according to any one of claims 1-10.

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