WO2020143649A1 - 基于序列的信号处理方法与装置 - Google Patents

基于序列的信号处理方法与装置 Download PDF

Info

Publication number
WO2020143649A1
WO2020143649A1 PCT/CN2020/070821 CN2020070821W WO2020143649A1 WO 2020143649 A1 WO2020143649 A1 WO 2020143649A1 CN 2020070821 W CN2020070821 W CN 2020070821W WO 2020143649 A1 WO2020143649 A1 WO 2020143649A1
Authority
WO
WIPO (PCT)
Prior art keywords
sequence
signal
elements
sequences
signal processing
Prior art date
Application number
PCT/CN2020/070821
Other languages
English (en)
French (fr)
Inventor
刘显达
龚名新
曲秉玉
刘鹍鹏
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20738420.7A priority Critical patent/EP3879777A4/en
Priority to BR112021013420-4A priority patent/BR112021013420A2/pt
Publication of WO2020143649A1 publication Critical patent/WO2020143649A1/zh
Priority to US17/361,720 priority patent/US20210328842A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects
    • H04L27/262—Reduction thereof by selection of pilot symbols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2649—Demodulators
    • H04L27/265—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H04J13/0059—CAZAC [constant-amplitude and zero auto-correlation]
    • H04J13/0062—Zadoff-Chu
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure
    • H04L27/261—Details of reference signals
    • H04L27/2613—Structure of the reference signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
    • H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0044—Arrangements for allocating sub-channels of the transmission path allocation of payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2035—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using a single or unspecified number of carriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2614—Peak power aspects

Definitions

  • the present application relates to the field of communication technology, and in particular, to a sequence-based signal processing method and device.
  • DMRS demodulation reference signal
  • DMRS can be obtained based on Gold sequence, computer generated sequence (CGS) or Zadoff-Chu sequence (ZC sequence).
  • new radio access technology new radio access technology, NR
  • PUSCH physical uplink shared channel
  • DFT-s-OFDM discrete Fourier transform OFDM
  • BPSK binary phase shift keying
  • the upstream DMRS adopts the DFT-s-OFDM waveform and uses the ⁇ /2 BPSK modulation method
  • the DMRS uses a sequence based on the Gold sequence or the CGS sequence
  • the frequency flatness of the sequence may be poor, which is not conducive to proceeding Channel estimation
  • the DMRS uses the ZC sequence, it will cause the peak-to-average power ratio (PAPR) of the DMRS to be higher than the PAPR of the transmitted data, resulting in out-of-band spurious emissions and in-band pilot signals Signal loss, which in turn affects channel estimation performance.
  • PAPR peak-to-average power ratio
  • the sequence used by the existing DMRS cannot satisfy the communication application environment in which the reference signal is transmitted using PUSCH.
  • the present application provides a sequence-based signal processing method and device.
  • a first signal is generated based on the sequence.
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • a sequence-based signal processing method includes: determining a sequence ⁇ x n ⁇ including N elements, where N is equal to 18, and x n is in the sequence ⁇ x n ⁇ Element, the sequence ⁇ x n ⁇ is a sequence that satisfies a preset condition; according to the sequence ⁇ x n ⁇ , a first signal is generated; and the first signal is sent.
  • n traverses 0, 1, ..., N-1, for example, n can represent the index of each element in the sequence ⁇ x n ⁇ . M ⁇ 0,1,2,...,N-1 ⁇ , it should be understood that M may be an integer less than N.
  • Set sequence ⁇ s n ⁇ s n of elemental composition comprises at least one set of the first sequence.
  • x n y (n+M)
  • M The value of M involved in mod N depends on different situations. When determining the elements in the same sequence, the value of M is constant. When determining another sequence, the value of M can be 1 or other integer less than N.
  • the sequence in the first sequence set includes:
  • Condition 1 Use time-domain filtering.
  • the filter coefficient is [0.1, 1, 0.1] the PAPR is less than 2.89dB; when the filter coefficient is [0.16, 1, 0.16], the PAPR is less than 2.35dB; when the filter coefficient is [0.22 , 1,0.22], PAPR is less than 1.76dB; when the filter coefficient is [0.28, 1, 0.28], PAPR is less than 1.27dB.
  • Condition 2 The maximum normalized power of the frequency domain sequence corresponding to the sequence ⁇ s n ⁇ is less than 0.5dB, and the minimum normalized power is greater than -0.5dB, that is, the frequency domain flatness of the sequence ⁇ s n ⁇ is relatively good.
  • the first signal may also satisfy the above condition 1 and condition 2.
  • the PAPR of the transmitted first signal is smaller, which can save energy consumption of the transmitting end (eg, terminal device).
  • the frequency domain flatness of the transmitted first signal is good, which is beneficial to improve the performance of channel estimation using the first signal.
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • the modulation method of the first signal is ⁇ /2BPSK.
  • the first signal is a reference signal; or, the first signal is a signal used to carry communication information.
  • the first signal is a reference signal of a second signal
  • the modulation method of the second signal is ⁇ /2 binary phase shift keying BPSK.
  • the second signal is carried on the shared channel.
  • the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the second sequence set, and the second sequence set includes the first sequence Some or all sequences in the collection.
  • generating the first signal according to the sequence ⁇ x n ⁇ includes: performing discrete Fourier on the N elements in the sequence ⁇ x n ⁇ Fourier transform, comprising obtaining a sequence ⁇ f n ⁇ of N elements; the sequence ⁇ f n ⁇ of the N elements are mapped to N subcarriers, the frequency domain signal comprising N elements; according to the frequency Domain signal to generate the first signal.
  • the N subcarriers are continuous N subcarriers, or N subcarriers at equal intervals.
  • the first signal processing method before performing discrete Fourier transform on the N elements in the sequence ⁇ x n ⁇ , the first signal processing method further includes: Filtering the sequence ⁇ x n ⁇ ; or after performing a discrete Fourier transform on the N elements in the sequence ⁇ x n ⁇ , the first signal processing method further includes: performing a sequence ⁇ x n ⁇ Perform filtering.
  • ⁇ s n ⁇ set constituted by the element s n sequence consisting of at least equivalent sequence comprises a first sequence of the first or of the first sequence in the set.
  • the equivalent sequence is ⁇ q n ⁇
  • the set of sequences ⁇ s n ⁇ composed of elements s n includes at least one of the sequences in the first sequence set; the first signal is processed according to the N elements in the sequence ⁇ x n ⁇ .
  • the sequence in the first sequence set includes:
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the second sequence set, and the second sequence set includes the first sequence Some or all sequences in the collection.
  • the receiving the first signal and acquiring N elements in the sequence ⁇ x n ⁇ includes: acquiring the first element on consecutive N subcarriers Signal, or the first signal is acquired on N subcarriers at equal intervals; N elements in the sequence ⁇ f n ⁇ are acquired, N is a positive integer greater than 1, and the first signal is determined by the sequence ⁇ f n ⁇ map generation to the N subcarriers, f n is the sequence ⁇ f n ⁇ of elements; the sequence ⁇ f n ⁇ performs inverse discrete Fourier transform processing, acquisition sequence ⁇ x n ⁇ of the N Elements.
  • the first signal is a reference signal of the second signal
  • the modulation method of the second signal is ⁇ /2 binary phase shift keying BPSK.
  • ⁇ s n ⁇ set constituted by the element s n sequence consisting of at least equivalent sequence comprises a first sequence of the first or of the first sequence in the set.
  • the equivalent sequence is ⁇ q n ⁇
  • the first sequence set may include other feasible 18-length sequences in addition to the above sequences.
  • the first sequence set may further include a sequence: ⁇ 1,1,0,1,1,0,1,0,1,1,1,0,0,0,0,0,0,0,1 ⁇ .
  • a signal processing apparatus may be a communication device or a chip in the communication device, and the communication device or the chip has a design that implements the first aspect or any possible design.
  • the function of the sequence-based signal processing method can be realized by hardware, or can also be realized by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the above functions.
  • the communication device includes: a processing unit and a transceiver unit, the processing unit may be a processor, the transceiver unit may be a transceiver, the transceiver includes a radio frequency circuit, and optionally, the communication device further includes a storage unit
  • the storage unit may be, for example, a memory.
  • the communication device includes a storage unit, the storage unit is used to store computer-executed instructions, the processing unit is connected to the storage unit, and the processing unit executes the computer-executed instructions stored by the storage unit, so that all The communication device performs the sequence-based signal processing method in the first aspect or any possible design thereof.
  • the chip includes: a processing unit and a transceiver unit, the processing unit may be a processor, and the transceiver unit may be an input/output interface, a pin, or a circuit on the chip.
  • the processing unit may execute computer-executed instructions stored in the storage unit to cause the chip to execute the sequence-based signal processing method in the first aspect or any possible design thereof.
  • the storage unit may be a storage unit within the chip (eg, register, cache, etc.), and the storage unit may also be a storage unit within the communication device located outside the chip (eg, Read-only memory (read-only memory, ROM)) or other types of static storage devices (eg, random access memory (RAM)) that can store static information and instructions.
  • the processor mentioned in the third aspect may be a central processing unit (CPU), microprocessor or application specific integrated circuit (ASIC), or one or more used to control the An integrated circuit that executes a program of a sequence-based signal processing method in one aspect or any of its possible designs.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • the signal processing apparatus may be a communication device or a chip in a communication device, and the communication device or the chip has a design that implements the second aspect or any possible The function of the sequence-based signal processing method.
  • the above-mentioned functions can be realized by hardware, and can also be realized by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the above functions.
  • the communication device includes: a processing unit and a transceiver unit, the processing unit may be a processor, the transceiver unit may be a transceiver, the transceiver includes a radio frequency circuit, and optionally, the communication device further includes a storage unit
  • the storage unit may be, for example, a memory.
  • the communication device includes a storage unit, the storage unit is used to store computer-executed instructions, the processing unit is connected to the storage unit, and the processing unit executes the computer-executed instructions stored by the storage unit, so that all The communication device performs the sequence-based signal processing method in the second aspect or any possible design thereof.
  • the chip includes: a processing unit and a transceiver unit, the processing unit may be a processor, and the transceiver unit may be an input/output interface, a pin, or a circuit on the chip.
  • the processing unit may execute computer-executed instructions stored in the storage unit to cause the chip to execute the sequence-based signal processing method in the second aspect or any possible design thereof.
  • the storage unit may be a storage unit within the chip (eg, register, cache, etc.), and the storage unit may also be a storage unit within the communication device located outside the chip (eg, Read-only memory (read-only memory, ROM)) or other types of static storage devices (eg, random access memory (RAM)) that can store static information and instructions.
  • the processor mentioned in the fourth aspect may be a central processing unit (CPU), microprocessor or application specific integrated circuit (ASIC), or one or more used to control the The integrated circuit of the program execution of the sequence-based signal processing method of the second aspect or any possible design thereof.
  • CPU central processing unit
  • ASIC application specific integrated circuit
  • a communication system includes the signal processing apparatus provided in the third aspect of the embodiments of the present application, and the signal processing apparatus provided in the fourth aspect of the embodiments of the present application.
  • a computer-readable storage medium on which a computer program is stored, which when executed by a computer causes the computer to implement the method in any possible implementation manner of the first aspect or the second aspect .
  • a computer program product containing instructions, which when executed by a computer causes the computer to implement the method in any possible implementation manner of the first aspect or the second aspect.
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • FIG. 1 is a schematic flowchart of a sequence-based signal transmission method disclosed in an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a terminal device determining sequence ⁇ x n ⁇ disclosed in an embodiment of the present application
  • FIG. 3 is a schematic flowchart of generating a first signal by a terminal device disclosed in an embodiment of this application;
  • FIG. 4, FIG. 5 and FIG. 6 are schematic diagrams of the N-element sequence ⁇ x n ⁇ obtained by the embodiment of the present application to obtain the N-element sequence ⁇ f n ⁇ in the frequency domain via DFT;
  • N-element sequences ⁇ f n ⁇ in the frequency domain obtained by DFT and mapped to N sub-carriers which are disclosed in the embodiments of the present application and include N-element sequences ⁇ x n ⁇ ;
  • FIG. 9 is a schematic diagram of a network device processing a first signal disclosed in an embodiment of the present application.
  • 10 and 11 are schematic flowcharts of determining whether the frequency domain of a time-domain sequence is flat disclosed in an embodiment of the present application;
  • FIG. 12 is a schematic structural diagram of a signal processing device disclosed in an embodiment of the present application.
  • FIG. 13 is another schematic structural diagram of a signal processing device disclosed in an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a terminal device disclosed in an embodiment of this application.
  • 15 is a schematic structural diagram of another signal processing device disclosed in an embodiment of the present application.
  • 16 is another schematic structural diagram of another signal processing device disclosed in an embodiment of the present application.
  • 17 is a schematic structural diagram of a network device disclosed in an embodiment of this application.
  • FIG. 18 is a schematic structural diagram of a communication system disclosed in an embodiment of the present application.
  • a reference signal is usually used to obtain a channel estimation matrix, thereby demodulating data information.
  • the DMRS for PUSCH (which may be referred to as uplink DMRS) uses DFT-s-OFDM waveforms and uses ⁇ / 2 BPSK modulation method.
  • DMRS uses DFT-s-OFDM waveforms and uses ⁇ /2 BPSK modulation
  • it supports DMRS to use sequences based on Gold sequences and CGS.
  • the DMRS uses sequences based on the Gold sequence and the CGS, if proper filtering cannot be performed, the frequency flatness of the sequence will be poor, which is not conducive to channel estimation.
  • the ZC sequence is a sequence that satisfies the properties of a constant envelope zero auto-correlation (CAZAC) sequence.
  • the period of the ZC sequence is the length of the sequence, and satisfies the property of central symmetry.
  • ZC sequences have good autocorrelation and cross-correlation.
  • the DMRS uses a sequence based on the ZC sequence, it will cause the PAPR of the DMRS to be higher than the PAPR of the transmitted data, which results in spurious emission out of the pilot signal and in-band signal loss, affecting the channel estimation performance , Or it may result in limited uplink coverage.
  • sequence used by DMRS can be kept better Sequence frequency domain flatness, while maintaining a low PAPR value, embodiments of the present application provide a sequence-based signal processing method and device.
  • the sequence-based signal processing method is mainly described from the receiving side and the transmitting side in a communication system or a communication application environment.
  • the receiving side may be a network device, and the transmitting side may be a terminal device; or the receiving side may be a terminal device, and the transmitting side may be a network device.
  • the receiving side is a network device and the sending side is a terminal device as an example for description, but the present application is not limited to this.
  • the terminal equipment involved in the embodiments of the present application may be user equipment.
  • the user equipment may be a wired device or a wireless device.
  • the wireless device may be a handheld device with a wireless connection function or other processing device connected to a wireless modem, and a mobile terminal that communicates with one or more core networks via a wireless access network.
  • the wireless terminal may be a mobile phone, a mobile phone, a computer, a tablet, a personal digital assistant (PDA), a mobile internet device (MID), a wearable device, an e-book reader, and so on.
  • the wireless terminal may also be a portable, pocket-sized, handheld, built-in computer, or vehicle-mounted mobile device.
  • the wireless terminal may be a mobile station or an access point.
  • the network device involved in the embodiments of the present application may be a base station.
  • the base station may include various forms of macro base stations, micro base stations, relay stations, access point base station controllers, transmission and reception points, and so on. In systems using different wireless access technologies, the specific name of the base station may be different.
  • the demodulation reference signal involved in the embodiments of the present application is a reference signal that can be used to demodulate data or signaling. According to different transmission directions, it can be divided into uplink demodulation reference signal and downlink demodulation reference signal.
  • the demodulation reference signal may be the DMRS in the LTE protocol or the NR protocol, or may be other reference signals defined in future protocols for implementing the same or similar functions. This application does not limit this.
  • the DMRS can be carried on the physical shared channel and sent together with the data signal for demodulating the data signal carried on the physical shared channel.
  • the physical downlink shared channel (physical downlink link share channel, PDSCH) is sent together with the downlink data
  • the physical uplink shared channel (physical uplink link share channel, PUSCH) is sent together with the uplink data.
  • the DMRS can also be carried in the physical control channel and sent together with the control signaling for demodulating the control signaling carried in the physical control channel summary. For example, it is sent together with downlink control signaling in the PDCCH, or it is sent together with uplink control signaling in the PUCCH.
  • the demodulation reference signal may include a downlink demodulation reference signal for demodulating PDCCH or PDSCH, and may also include an uplink demodulation reference signal for demodulating PUCCH or PUSCH.
  • the demodulation reference signal is simply referred to as DMRS.
  • FIG. 1 is a schematic interaction diagram of a sequence-based signal processing method 100 provided by an embodiment of the present application. Taking the sending side as a terminal device and the receiving side as a network device as an example, the signal processing method 100 includes the following steps.
  • the terminal device comprises determining a sequence ⁇ x n ⁇ N elements, N is equal to 18, x n is the sequence ⁇ x n ⁇ elements, in order to meet a preset condition following sequence a sequence ⁇ x n ⁇ .
  • n traverses 0, 1, ..., N-1, for example, n can represent the index of each element in the sequence ⁇ x n ⁇ . M ⁇ 0,1,2,...,N-1 ⁇ , it should be understood that M may be an integer less than N.
  • Set sequence ⁇ s n ⁇ s n of elemental composition comprises at least one set of the first sequence.
  • sequences in the first sequence set include:
  • step 110 may be that the terminal device determines a sequence ⁇ x n ⁇ including N elements after joining the network. It may also be that when the terminal device accesses the network, the network device determines the sequence ⁇ b n ⁇ and allocates it to the terminal device, and the terminal device determines the sequence containing N elements based on the sequence ⁇ b n ⁇ ⁇ x n ⁇ . N is a positive integer greater than 1.
  • x n y (n+M)
  • M The value of M involved in mod N depends on different situations. When determining the elements in the same sequence, the value of M is constant. When determining another sequence, the value of M can be 1 or other integer less than N.
  • the set of sequences ⁇ s n ⁇ is pre-stored on the terminal device and the network device.
  • the network device determines the sequence to be used (set as the first sequence) from the set of sequences ⁇ s n ⁇ , and then configures the first sequence to the terminal device; after the terminal device learns that the first sequence is to be used according to the configuration of the network device, it can According to the above preset conditions, the sequence ⁇ x n ⁇ is generated.
  • the network device may send the first sequence number, identification, cell identification, or other information that can identify the first sequence to the terminal device.
  • the network device configures the first sequence to the terminal device.
  • the set of sequences ⁇ s n ⁇ is pre-stored on the terminal device and the network device.
  • the terminal device generates a corresponding sequence ⁇ x n ⁇ for each sequence in the set of sequences ⁇ s n ⁇ according to the foregoing preset condition.
  • the network device also generates a corresponding sequence ⁇ x n ⁇ for each sequence in the set of sequences ⁇ s n ⁇ according to the above preset conditions.
  • the network device selects the sequence to be used from these generated sequences ⁇ x n ⁇ Sequence (marked as the second sequence), and then send the second sequence to the terminal device.
  • the terminal device learns the sequence to be used ⁇ x n ⁇ according to the configuration of the network device, and may generate the first signal according to the sequence ⁇ x n ⁇ .
  • the network device may send the second sequence number, identification, cell identification, or other information that can identify the second sequence to the terminal device.
  • the network device configures the second sequence to the terminal device.
  • the modulation mode of the first signal is ⁇ /2 binary phase shift keying (BPSK).
  • the waveform of the first signal may be DFT-s-OFDM.
  • the terminal device generates a first signal according to the sequence ⁇ x n ⁇ .
  • the network device sends a first signal to the network device.
  • the network device receives the first signal sent by the terminal device.
  • the network device obtains the sequence ⁇ x n ⁇ , and processes the first signal according to the N elements in the sequence ⁇ x n ⁇ .
  • the CM value is also smaller.
  • the sequence ⁇ s n ⁇ has been verified and its CM values are very small, that is, the PAPR of the sequence ⁇ s n ⁇ is small.
  • Condition 1 Use time-domain filtering.
  • the filter coefficient is [0.1, 1, 0.1] the PAPR is less than 2.89dB; when the filter coefficient is [0.16, 1, 0.16], the PAPR is less than 2.35dB; when the filter coefficient is [0.22 , 1,0.22], PAPR is less than 1.76dB; when the filter coefficient is [0.28, 1, 0.28], PAPR is less than 1.27dB.
  • Condition 2 The maximum normalized power of the frequency domain sequence corresponding to the sequence ⁇ s n ⁇ is less than 0.5dB, and the minimum normalized power is greater than -0.5dB, that is, the frequency domain flatness of the sequence ⁇ s n ⁇ is relatively good.
  • the first signal may also satisfy the above condition 1 and condition 2.
  • the PAPR of the transmitted first signal is smaller, which can save energy consumption of the transmitting end (eg, terminal device).
  • the frequency domain flatness of the transmitted first signal is good, which is beneficial to improve the performance of channel estimation using the first signal.
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • the first signal is a reference signal.
  • the first signal may be any one of the following: uplink control information (uplink control information, UCI), DMRS, sounding reference signal (Sounding Reference Signal, SRS), phase tracking reference signal (Phase-tracking Reference Signal, PTRS), acknowledgement (acknowledgment, ACK) information, negative acknowledgement (negative acknowledgement (NACK) information, uplink scheduling request (SR) information.
  • uplink control information uplink control information
  • DMRS Downlink control information
  • SRS Sounding reference signal
  • phase tracking reference signal Phase tracking reference signal
  • PTRS Phase tracking Reference Signal
  • acknowledgement acknowledgement
  • NACK negative acknowledgement
  • NACK negative acknowledgement
  • SR uplink scheduling request
  • the first signal is a reference signal of the second signal
  • the modulation method of the second signal is ⁇ /2 binary phase shift keying BPSK.
  • the set of sequences ⁇ s n ⁇ includes one sequence or multiple sequences among all sequences in the first sequence set.
  • the set of sequences ⁇ s n ⁇ includes one or more of the partial sequences in the first set of sequences described above.
  • the set of sequences ⁇ s n ⁇ includes one sequence or multiple sequences in a second sequence set, and the second sequence set includes a partial sequence in the first sequence set.
  • the second sequence set includes the first 10 sequences among the 20 sequences included in the first sequence set described above.
  • the first sequence set may include other feasible 18-length sequences in addition to the above sequences.
  • the first sequence set may further include a sequence: ⁇ 1,1,0,1,1,0,1,0,1,1,1,0,0,0,0,0,0,0,1 ⁇ .
  • FIG. 2 is a schematic diagram of the terminal device determining sequence ⁇ x n ⁇ .
  • the process of the terminal device determining the sequence ⁇ x n ⁇ includes the following steps.
  • s n is an element in the sequence ⁇ s n ⁇
  • u is a non-zero complex number
  • n traverses 0, 1, ..., N-1, for example, n can represent the index of each element in the sequence, and N is 18.
  • the value of u is not fixed. For example, for all elements in the same sequence currently selected, the value of u may be the same. For the elements in different sequences, the value of u can be different.
  • the set of sequences ⁇ s n ⁇ is pre-stored on the terminal device and the network device.
  • the network device may send the first sequence number, identification, cell identification, or other information that can identify the first sequence to the terminal device.
  • the set of sequences ⁇ s n ⁇ is pre-stored on the terminal device and the network device.
  • the terminal device learns the sequence to use ⁇ b n ⁇ according to the configuration of the network device.
  • the network device may send the third sequence number, identification, cell identification, or other information that can identify the third sequence to the terminal device.
  • Step 2 The terminal device determines the sequence ⁇ x n ⁇ according to the following formula:
  • A is a non-zero complex number
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • step 120 The process of generating the first signal based on the sequence ⁇ x n ⁇ in step 120 is described below.
  • step 120 includes: ⁇ x n ⁇ of the N elements of a discrete Fourier transform sequence (discrete fourier transform, DFT), to obtain a sequence comprising N elements ⁇ f n ⁇ ; N elements in the sequence ⁇ f n ⁇ are mapped onto N subcarriers respectively to generate a first signal.
  • DFT discrete Fourier transform
  • the method before performing discrete Fourier transform on the N elements in the sequence ⁇ x n ⁇ , the method further includes: filtering the sequence ⁇ x n ⁇ .
  • the method further includes: filtering the sequence ⁇ x n ⁇ .
  • mapping the N elements in the sequence ⁇ f n ⁇ to N subcarriers respectively to generate the first signal includes: mapping the N elements in the sequence ⁇ f n ⁇ to N subcarriers respectively, generating The frequency domain signal of the element of N; the frequency domain signal is subjected to inverse fast Fourier transform to obtain the time domain signal; the cyclic prefix is added to the time domain signal to generate the first signal.
  • mapping the N elements in the sequence ⁇ f n ⁇ to N subcarriers respectively to generate the first signal includes: mapping the N elements in the sequence ⁇ f n ⁇ to N subcarriers respectively, generating The frequency domain signal of the element of N; use the frequency domain signal as the signal.
  • FIG. 3 is a schematic flowchart of the generation sequence ⁇ x n ⁇ . As shown in FIG. 3, the process of generating the sequence ⁇ x n ⁇ includes the following steps.
  • the terminal device performs DFT processing on the sequence ⁇ x n ⁇ containing N elements to obtain the sequence ⁇ f n ⁇ .
  • the filter may not be used.
  • the sequence ⁇ x n ⁇ may be processed using a filter first, and after the filtering process
  • the sequence ⁇ x n ⁇ of D is processed by DFT to obtain the sequence ⁇ f n ⁇ .
  • the terminal device may first perform DFT processing on the sequence ⁇ x n ⁇ and then use a filter for processing To get the sequence ⁇ f n ⁇ .
  • the terminal device maps the N elements in the sequence ⁇ f n ⁇ to N subcarriers, respectively, to obtain a frequency domain signal at N points.
  • the frequency domain signal at point N may be a frequency domain signal including N elements.
  • the terminal device maps the N elements in the sequence ⁇ f n ⁇ to consecutive N subcarriers, respectively.
  • the elements f 0 to f N-1 in the sequence ⁇ f n ⁇ are mapped to N consecutive subcarriers respectively, and the subcarrier labels are s+0, s+1, ..., s+N- 1.
  • s represents the index of the first subcarrier among the N subcarriers mapped by the sequence ⁇ f n ⁇ in the subcarriers in the communication system.
  • the terminal device maps the N elements in the sequence ⁇ f n ⁇ to the N sub-carriers in order of the sub-carriers from high to low.
  • Frequency domain subcarriers are the smallest unit of frequency domain resources, which are used to carry data information.
  • the terminal device sequentially maps the N elements in the sequence ⁇ f n ⁇ to the N sub-carriers in order of the sub-carriers from low to high.
  • An element in the sequence ⁇ f n ⁇ is mapped to a subcarrier, and this element is carried on this subcarrier. After the mapping, when the terminal device sends data via radio frequency, it is equivalent to sending this element on this subcarrier.
  • different terminal devices can occupy different subcarriers to send data.
  • the positions of the N sub-carriers among multiple sub-carriers existing in the communication system may be predefined, or configured by the network device through signaling.
  • the terminal device may map the N elements in the sequence ⁇ f n ⁇ to N subcarriers at equal intervals.
  • the interval between N subcarriers is 1, and the N subcarriers are distributed at equal intervals in the frequency domain.
  • the elements f 0 to f N-1 in the sequence ⁇ f n ⁇ are mapped to N equally spaced subcarriers respectively, and the subcarrier numbers are s+0, s+2, ..., s+2 (N-1).
  • the embodiment of the present application is not limited to the above manner for mapping the N elements in the sequence ⁇ f n ⁇ onto N subcarriers, respectively.
  • the terminal device performs inverse fast Fourier transform (IFFT) on the frequency domain signal including N elements to obtain a corresponding time domain signal, and adds a cyclic prefix to the time domain signal to generate a first signal.
  • IFFT inverse fast Fourier transform
  • the time domain signal obtained by the terminal device after performing IFFT on the frequency domain signal including N elements is an orthogonal frequency division multiplexing (orthogonal frequency division multiplexing, OFDM) symbol
  • the terminal device sends the first signal through radio frequency.
  • the terminal device sends the first signal through radio frequency. That is, the terminal device sends the first signal carrying the sequence ⁇ f n ⁇ on the N subcarriers.
  • the terminal device may send the first signal carrying the sequence ⁇ f n ⁇ on one OFDM symbol.
  • the first signal carrying the sequence ⁇ f n ⁇ may also be sent on multiple OFDM symbols.
  • step 120 includes: processing the N elements in the sequence ⁇ x n ⁇ with a shaping filter to obtain a sequence ⁇ f n ⁇ including N elements; by converting the sequence ⁇ f n ⁇ N elements of are mapped onto N subcarriers respectively to generate a first signal.
  • the N sub-carriers are consecutive N sub-carriers, or N sub-carriers at equal intervals.
  • the first signal in this application may be a reference signal, but this application is not limited thereto.
  • the first signal is a signal used to carry communication information.
  • the communication information can be carried by way of sequence selection or by sequence modulation. This application does not limit this.
  • the communication information is carried by way of sequence selection.
  • 2 n orthogonal sequences are allocated to a terminal device.
  • the 2 n orthogonal sequences may be 2 n cyclic shifts of a root sequence.
  • the 2 n orthogonal sequences can carry n bits. information. For example, suppose there are 4 sequences labeled 0, 1, 2, and 3, where 00 corresponds to sequence 0, 01 corresponds to sequence 1, 10 corresponds to sequence 2, and 11 corresponds to sequence 3, so that the 4 sequences can carry 2 bits of information.
  • the communication information is carried by sequence modulation.
  • a sequence is assigned to a user, and a modulation symbol is generated for the information that the user needs to transmit.
  • the modulation symbols include but are not limited to BPSK symbols, QPSK symbols, 8QAM symbols, 16QAM symbols, and so on.
  • the modulation symbol is multiplied by the sequence to generate the actual transmission sequence.
  • a BPSK symbol is 1 or -1.
  • the transmitted sequence may be a column ⁇ x n ⁇ or ⁇ -x n ⁇ .
  • the network terminal device by A sequence ⁇ b n ⁇ , and determining the network device configuration comprising the sequence ⁇ x n ⁇ N elements.
  • the first signal is a signal used to carry communication information, and the communication information is carried by a sequence modulation method, then the first signal carries different information through different values of A in the sequence ⁇ x n ⁇ of.
  • A may be a modulation symbol. At this time, after all the data information bits or control information bits are modulated, A is obtained. A is carried on N elements contained in the sequence ⁇ x n ⁇ , and A does not change with the change of n.
  • A is a constant.
  • A 1.
  • A may be a symbol known to both terminal equipment and network equipment.
  • A can also be expressed as amplitude.
  • A is a constant in a transmission time unit
  • A can be changed.
  • all N elements contained in the sequence ⁇ x n ⁇ are reference signals
  • A is the amplitude of the reference signal
  • the receiving side that is, the network device processes the first signal after receiving the first signal, will be described below.
  • step 130 the network device receives the first signal sent by the terminal device.
  • the network device receives the first signals on the N subcarriers according to the positions of the N subcarriers predefined or configured by the base station in the subcarriers of the communication system.
  • the network device acquires the first signals on the N sub-carriers on consecutive N sub-carriers, or on the N sub-carriers at equal intervals.
  • step 140 the network device acquires the sequence ⁇ x n ⁇ , and processes the first signal according to the N elements in the sequence ⁇ x n ⁇ .
  • the process of the network device acquiring N elements in the sequence ⁇ x n ⁇ includes: the network device receives the first signal on N subcarriers; removing the cyclic prefix of the first signal to obtain the time domain Signal; perform M-point DFT on the time domain signal to obtain a frequency domain signal including N elements, M is greater than or equal to N; based on the frequency domain signal including N elements, determine the N elements in the sequence ⁇ f n ⁇ ; Inverse discrete fourier transformation (IDFT) is performed on the sequence ⁇ f n ⁇ to obtain N elements in the sequence ⁇ x n ⁇ .
  • IDFT Inverse discrete fourier transformation
  • the process of the network device acquiring N elements in the sequence ⁇ x n ⁇ includes: the network device obtains the sequence according to the following formula ⁇ x n ⁇ to obtain N elements in the sequence ⁇ x n ⁇ :
  • s n is an element in the sequence ⁇ s n ⁇
  • u is a non-zero complex number
  • n traverses 0, 1, 2, ... N-1
  • N equals 18.
  • A is a non-zero complex number, M ⁇ 0,1,2,...,N-1 ⁇
  • the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the first sequence set.
  • the network device obtains the sequence ⁇ x n ⁇
  • the process of N elements includes: the network device obtains the sequence ⁇ x n ⁇ according to the following formula, and then obtains the N elements in the sequence ⁇ x n ⁇ :
  • b n is an element in the sequence ⁇ b n ⁇ , n traverses 0, 1, 2, ... N-1, and N equals 18.
  • A is a non-zero complex number, M ⁇ 0,1,2,...,N-1 ⁇ , the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the first sequence set.
  • the network device may directly use the N elements in the sequence ⁇ x n ⁇ to process the first One signal.
  • the first signal is a reference signal of the second signal.
  • the second signal is carried on the shared channel.
  • the network device can obtain the channel matrix H of the shared channel carrying the second signal.
  • the method further includes: demodulating the second signal according to the channel matrix.
  • the network device processes the first signal as shown in FIG. 9, and the network device obtains all possible sequences by traversing the locally stored sequence ⁇ x n ' ⁇ . Correlate the obtained sequence ⁇ x n ⁇ with all possible sequences of sequence ⁇ x n ′ ⁇ and perform maximum likelihood comparison to obtain the data transmitted by the terminal device.
  • the resulting sequence ⁇ x n ′ ⁇ is the sequence ⁇ x 1,n ′ ⁇
  • the resulting sequence ⁇ x n ′ ⁇ Is the sequence ⁇ x 2,n ′ ⁇
  • the resulting sequence ⁇ x n ′ ⁇ is the sequence ⁇ x 3,n ′ ⁇ , when the two-bit information is (1,1)
  • the obtained sequence ⁇ x n ′ ⁇ is the sequence ⁇ x 4, n ⁇ .
  • sequences ⁇ x 1,n ′ ⁇ , ⁇ x 2,n ′ ⁇ , ⁇ x 3,n ′ ⁇ , ⁇ x 4,n ′ ⁇ can be the same sequence of cyclic shift sequences, the sequence ⁇ x n ⁇ is related to ⁇ x 1,n ′ ⁇ , ⁇ x 2,n ′ ⁇ , ⁇ x 3,n ′ ⁇ , ⁇ x 4,n ′ ⁇ , and 4 correlation values are obtained.
  • the value of the two-bit information corresponding to the maximum correlation value is the data acquired by the network device.
  • the maximum correlation value is obtained by correlating the sequences ⁇ x n ⁇ and ⁇ x 1,n ′ ⁇ , then the two-bit information is (0,0), that is, the data acquired by the network device is bit information (0,0).
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • it satisfies NR systems or NR-like scenarios.
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • determining whether the frequency domain of a time-domain sequence is flat can be processed through the flow shown in FIG. 10 or FIG. 11.
  • the first type of maximum normalized power of the frequency domain sequence corresponding to a time domain sequence ⁇ x n ⁇ mentioned above is defined as a sequence
  • the first minimum normalized power of the frequency domain sequence corresponding to a time domain sequence ⁇ x n ⁇ is defined as the sequence The normalized minimum value.
  • the second type of maximum normalized power of the frequency domain sequence corresponding to the above-mentioned time domain sequence ⁇ x n ⁇ is defined as a sequence
  • the second minimum normalized power of the frequency domain sequence corresponding to a time domain sequence ⁇ x n ⁇ is defined as the sequence The normalized minimum value.
  • the sequence ⁇ x n ⁇ meet flatness better frequency-domain sequence, conditions where lower PAPR value, such that when the first signal is a carrier
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • an embodiment of the present application provides a sequence-based signal processing apparatus 1200.
  • the signal processing device 1200 may be a communication device or a chip in the communication device.
  • the signal processing apparatus 1200 corresponds to the terminal device in the foregoing method embodiment.
  • the signal processing device 1200 includes the following units.
  • sequences in the first sequence set include:
  • the processing unit 1210 is further configured to generate the first signal according to the sequence ⁇ x n ⁇ .
  • the transceiver unit 1220 is configured to send the first signal.
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the second sequence set, and the second sequence set includes a partial sequence or the entire sequence in the first sequence set.
  • the processing unit 1210 is configured to: perform discrete Fourier transform on the N elements in the sequence ⁇ x n ⁇ to obtain a sequence ⁇ f n ⁇ including N elements; convert the sequence ⁇ f The N elements in n ⁇ are mapped onto N subcarriers respectively to obtain a frequency domain signal including N elements; according to the frequency domain signal, a first signal is generated.
  • the N subcarriers are consecutive N subcarriers, or N subcarriers at equal intervals.
  • the processing unit 1210 for, prior to sequence ⁇ x n ⁇ of the N discrete Fourier transform element, a sequence ⁇ x n ⁇ filter; or by the processing unit 1210 to, after the ⁇ x n ⁇ of the N discrete Fourier transform element sequence, a sequence ⁇ x n ⁇ filter.
  • the first signal is a reference signal of the second signal
  • the modulation method of the second signal is ⁇ /2 binary phase shift keying BPSK.
  • processing unit 1210 may be implemented by a processor or a processor-related circuit.
  • the transceiver unit 1220 can be implemented by a transceiver or a transceiver-related circuit.
  • an embodiment of the present application further provides a signal processing device 1300.
  • the signal processing device 1300 includes a processor 1310, a memory 1320, and a transceiver 1330.
  • the memory 1320 stores instructions or programs, and the processor 1310 uses Instructions or programs stored in the execution memory 1320.
  • the processor 1310 is used to perform the operation performed by the processing unit 1210 in the foregoing embodiment
  • the transceiver 1330 is used to perform the operation performed by the transceiver unit 1220 in the foregoing embodiment.
  • the signal processing apparatus 1200 or the signal processing apparatus 1300 provided by the embodiments of the present application may correspond to the terminal device in the foregoing method embodiments, and the operations and/or operations of the various modules in the signal processing apparatus 1200 or the signal processing apparatus 1300 The functions are respectively for implementing the corresponding processes of the above-described methods, and for the sake of brevity, they are not repeated here.
  • Embodiments of the present application also provide a sequence-based signal processing device, which may be a terminal device or an integrated circuit or chip.
  • the signal processing apparatus may be used to perform the actions performed by the terminal device in the foregoing method embodiments.
  • FIG. 14 shows a simplified structural diagram of the terminal device. It is easy to understand and convenient to illustrate.
  • the terminal device uses a mobile phone as an example.
  • the terminal device includes a processor, a memory, a radio frequency circuit, an antenna, and input and output devices.
  • the processor is mainly used for processing communication protocols and communication data, as well as controlling terminal devices, executing software programs, and processing data of software programs.
  • the memory is mainly used to store software programs and data.
  • the radio frequency circuit is mainly used for the conversion of the baseband signal and the radio frequency signal and the processing of the radio frequency signal.
  • the antenna is mainly used to send and receive radio frequency signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, and keyboards, are mainly used to receive user input data and output data to the user. It should be noted that some types of terminal devices may not have input/output devices.
  • the processor When data needs to be sent, the processor performs baseband processing on the data to be sent, and outputs the baseband signal to the radio frequency circuit.
  • the radio frequency circuit processes the baseband signal after radio frequency processing, and then sends the radio frequency signal to the outside in the form of electromagnetic waves through the antenna.
  • the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor.
  • the processor converts the baseband signal into data and processes the data.
  • FIG. 14 only one memory and processor are shown in FIG. 14. In actual terminal equipment products, there may be one or more processors and one or more memories.
  • the memory may also be referred to as a storage medium or storage device.
  • the memory may be set independently of the processor, or may be integrated with the processor, which is not limited in the embodiments of the present application.
  • an antenna and a radio frequency circuit with a transceiver function can be regarded as a transceiver unit of a terminal device, and a processor with a processing function can be regarded as a processing unit of the terminal device.
  • the terminal device includes a transceiver unit 1410 and a processing unit 1420.
  • the transceiver unit may also be called a transceiver, a transceiver, a transceiver device, or the like.
  • the processing unit may also be called a processor, a processing board, a processing module, a processing device, and the like.
  • the device used to implement the receiving function in the transceiver unit 1410 may be regarded as a receiving unit, and the device used to implement the sending function in the transceiver unit 1410 may be regarded as a sending unit, that is, the transceiver unit 1410 includes a receiving unit and a sending unit.
  • the transceiver unit may sometimes be called a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may sometimes be called a receiver, a receiver, or a receiving circuit.
  • the sending unit may sometimes be called a transmitter, a transmitter, or a transmitting circuit.
  • transceiving unit 1410 is used to perform the sending operation and the receiving operation on the terminal device side in the above method embodiment
  • processing unit 1420 is used to perform other operations on the terminal device in addition to the transceiving operation in the above method embodiment.
  • the processing unit 1420 is configured to execute steps 110 and 120 in FIG. 1, and/or the processing unit 1420 is further configured to execute other processing steps on the terminal device side in the embodiments of the present application.
  • the transceiver unit 1410 is also used to perform the sending action on the terminal device side in step 120 in FIG. 1, and/or the transceiver unit 1410 is also used on other transceiver steps on the terminal device side in the embodiments of the present application.
  • the processing unit 1420 is configured to execute steps 310 to 330 in FIG. 3, and/or the processing unit 1420 is further configured to execute other processing steps on the terminal device side in the embodiments of the present application.
  • the transceiver unit 1410 is also used to perform other transceiver steps on the terminal device side in the embodiments of the present application.
  • the chip When the communication device is a chip, the chip includes a transceiver unit and a processing unit.
  • the transceiver unit may be an input-output circuit and a communication interface;
  • the processing unit is a processor or a microprocessor or an integrated circuit integrated on the chip.
  • an embodiment of the present application provides a sequence-based signal processing apparatus 1500.
  • the signal processing device 1500 may be a communication device or a chip in the communication device.
  • the signal processing apparatus 1500 corresponds to the network device in the foregoing method embodiment.
  • the signal processing device 1500 includes the following units.
  • the transceiver unit 1510 is configured to receive the first signal.
  • the set of sequences ⁇ s n ⁇ composed of elements s n includes at least one of the sequences in the first sequence set; the first signal is processed according to the N elements in the sequence ⁇ x n ⁇ .
  • sequences in the first sequence set include:
  • the first signal is generated based on the sequence ⁇ x n ⁇ .
  • the sequence ⁇ x n ⁇ can satisfy the conditions that the frequency domain flatness of the sequence is good and the PAPR value is low, so that when the first signal is carried by
  • the transmitted first signal can maintain a good sequence frequency domain flatness, and at the same time maintain a low PAPR value, which can meet the communication application environment for transmitting the reference signal.
  • the set of sequences ⁇ s n ⁇ includes at least one of the sequences in the second sequence set, and the second sequence set includes a partial sequence or the entire sequence in the first sequence set.
  • the transceiver unit 1510 is further configured to acquire the first signal on consecutive N subcarriers, or acquire the first signal on N equally spaced subcarriers.
  • the processing unit 1520 is also used to obtain N elements in the sequence ⁇ f n ⁇ , where N is a positive integer greater than 1, the first signal is generated by mapping the sequence ⁇ f n ⁇ onto N subcarriers, and f n is the sequence ⁇ f Elements in n ⁇ ; Inverse discrete Fourier transform is performed on the sequence ⁇ f n ⁇ to obtain N elements in the sequence ⁇ x n ⁇ .
  • the first signal is a reference signal of the second signal
  • the modulation method of the second signal is ⁇ /2 binary phase shift keying BPSK.
  • transceiver unit 1510 may be implemented by a transceiver or a transceiver-related circuit.
  • the processing unit 1520 may be implemented by a processor or a processor-related circuit.
  • an embodiment of the present application further provides a sequence-based signal processing device 1600.
  • the signal processing device 1600 includes a processor 1610, a memory 1620, and a transceiver 1630.
  • the memory 1620 stores instructions or programs for processing.
  • the device 1610 is used to execute instructions or programs stored in the memory 1620.
  • the processor 1610 is used to perform the operation performed by the processing unit 1520 in the foregoing embodiment
  • the transceiver 1630 is used to perform the operation performed by the transceiver unit 1510 in the foregoing embodiment.
  • the signal processing apparatus 1500 or the signal processing apparatus 1600 provided by the embodiments of the present application may correspond to the network equipment in the above method embodiments, and the operations and/or operations of each module in the signal processing apparatus 1500 or the signal processing apparatus 1600 The functions are respectively for implementing the corresponding processes of the above-described methods, and for the sake of brevity, they are not repeated here.
  • Embodiments of the present application also provide a sequence-based signal processing apparatus.
  • the signal processing apparatus may be a network device or a chip.
  • the second communication device may be used to perform the actions performed by the network device in the foregoing method embodiments.
  • FIG. 17 shows a simplified schematic structural diagram of a base station.
  • the base station includes 1710 parts and 1720 parts.
  • the 1710 part is mainly used for the transmission and reception of radio frequency signals and the conversion of the radio frequency signal and the baseband signal;
  • the 1720 part is mainly used for baseband processing and control of the base station.
  • the 1710 part can usually be called a transceiver unit, a transceiver, a transceiver circuit, or a transceiver.
  • the part 1720 is usually a control center of the base station, and may be generally referred to as a processing unit, which is used to control the base station to perform the action of the network device generating the first message in the above method embodiment.
  • a processing unit which is used to control the base station to perform the action of the network device generating the first message in the above method embodiment.
  • the transceiver unit of part 1710 may also be called a transceiver, or a transceiver, etc., which includes an antenna and a radio frequency unit, wherein the radio frequency unit is mainly used for radio frequency processing.
  • the device for realizing the receiving function in the part 1710 can be regarded as a receiving unit, and the device for implementing the sending function can be regarded as the sending unit, that is, the part 1710 includes a receiving unit and a sending unit.
  • the receiving unit may also be referred to as a receiver, receiver, or receiving circuit, etc.
  • the transmitting unit may be referred to as a transmitter, transmitter, or transmitting circuit, etc.
  • the 1720 part may include one or more single boards, and each single board may include one or more processors and one or more memories.
  • the processors are used to read and execute programs in the memory to implement baseband processing functions and control. If there are multiple boards, each board can be interconnected to increase processing power. As an optional embodiment, multiple boards may share one or more processors, or multiple boards may share one or more memories, or multiple boards may share one or more processes at the same time. Device.
  • the transceiver unit is used to perform the receiving operation on the network device side in step 130 in FIG. 1, and/or the transceiver unit is also used to perform other transceiver steps on the network device side in the embodiments of the present application.
  • the processing unit is used to perform the action of step 140, and/or the processing unit is also used to perform other processing steps on the network device side in the embodiments of the present application.
  • the chip When the communication device is a chip, the chip includes a transceiver unit and a processing unit.
  • the transceiver unit may be an input-output circuit and a communication interface;
  • the processing unit is a processor or a microprocessor or an integrated circuit integrated on the chip.
  • FIG. 18 is a communication system 1800 disclosed in an embodiment of the present application, including a first communication device 1810 and a second communication device 1820.
  • the first communication device 1810 is a device on the sending side.
  • the first communication device 1810 is a terminal device in the foregoing method embodiment.
  • the second communication device 1820 is a device on the receiving side.
  • the second communication device 1820 is a network device in the foregoing method embodiment.
  • the first communication device 1810 is used to determine the sequence ⁇ x n ⁇ including N elements, and perform DFT on the N elements in the sequence ⁇ x n ⁇ to obtain the sequence ⁇ f n ⁇ , and then map the sequence ⁇ f n ⁇ to On the N subcarriers, the first signal is generated and sent to the second communication device 1820.
  • the sequence ⁇ x n ⁇ is described in detail above, and will not be repeated here.
  • a first communication device 1810 transmits a first signal, obtaining the N elements of the sequence ⁇ f n ⁇ , the sequence ⁇ f n ⁇ perform IDFT processing to obtain the sequence ⁇ x n ⁇ N elements of and process the first signal according to the N elements of the sequence ⁇ x n ⁇ .
  • first communication devices 1810 and second communication devices 1820 are not limited.
  • the first communication device 1810 may be the communication devices disclosed in FIGS. 12, 13 and 14.
  • the first communication device 1810 may be used to perform corresponding operations performed by the terminal device in the foregoing method embodiments.
  • the second communication device 1820 may be the communication devices disclosed in FIGS. 15, 16 and 17.
  • the second communication device 1820 may be used to perform corresponding operations performed by the network device in the foregoing method embodiments.
  • the specific process and execution principle can refer to the above description, and no more details will be given here.
  • processors mentioned in the embodiments of the present application may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), and special integrated circuits ( Application Specific (Integrated Circuit, ASIC), ready-made programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electronically Erase Programmable Read Only Memory (Electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM ESDRAM
  • Synchlink DRAM SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
  • the memory storage module
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical, or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application essentially or part of the contribution to the existing technology or part of the technical solution can be embodied in the form of a software product
  • the computer software product is stored in a storage medium, including Several instructions are used to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application.
  • the foregoing storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

Abstract

本申请提供一种基于序列的信号处理方法与装置，该信号处理方法包括：确定包括N个元素的序列{x n}，该N等于18，该序列{x n}为满足预设条件的序列；根据该序列{x n}，生成第一信号；发送该第一信号。该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。

Description

基于序列的信号处理方法与装置
本申请要求于2019年01月09日提交中国专利局、申请号为201910020924.0、申请名称为“基于序列的信号处理方法与装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其是，涉及一种基于序列的信号处理方法与装置。
背景技术
在长期演进(long term evolution，LTE)系统中，使用解调参考信号(demodulation reference signal，DMRS)进行信道估计，从而进行信号解调。
目前，DMRS可以基于Gold序列、计算机生成序列(computer generated sequence，CGS)或Zadoff-Chu序列(ZC序列)获得。
在新无线电接入技术(new radio access technology，NR)中，可以支持物理上行共享信道(physical uplink shared channel，PUSCH)采用离散傅里叶变换扩频的正交频分复用多址接入(discrete fourier transform spread OFDM，DFT-s-OFDM)波形，且使用π/2的二进制相移键控(binary phase shift keying，BPSK)调制方法。
当上行DMRS采用DFT-s-OFDM波形且使用π/2的BPSK的调制方式时，若DMRS使用基于Gold序列或CGS序列的序列时，可能会导致序列的频率平坦度较差，从而不利于进行信道估计；若DMRS使用ZC序列时，会导致DMRS的峰均功率比(peak-to-average power ratio，PAPR)高于传输的数据的PAPR，从而导致导频信号带外杂散发射和带内信号损失，进而影响信道估计性能。
因此，现有DMRS所使用的序列，不能够满足利用PUSCH发送参考信号的通信应用环境。
发明内容
本申请提供一种基于序列的信号处理方法与装置，通过提供可以满足序列频域平坦度较好、PAPR值较低的条件的序列，基于该序列生成第一信号，当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
第一方面，提供一种基于序列的信号处理方法，所述信号处理方法包括：确定包括N个元素的序列{x n}，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列；根据所述序列{x n}，生成第一信号；发送所述第一信号。
所述预设条件为：x n＝y (n+M)mod N。其中，n遍历0，1，…，N-1，例如，n可以表示序列{x n}中各个元素的索引。M∈{0,1,2,...,N-1}，应理解，M可以为小于N的整 数。y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
Figure PCTCN2020070821-appb-000001
由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一。
b n＝u·(1-2·s n)中涉及的u的取值并非固定不变的。例如，针对当前选取的同一个序列中的所有元素，u的取值可以是相同的。针对不同序列中的元素，u的取值可以不同。
x n＝y (n+M)mod N中涉及的M的取值根据不同情况而定。在确定同一个序列中的元素时，M的取值恒定不变。确定另外一个序列时，M的取值可以取1或其他小于N的整数。
其中，所述第一序列集合中的序列包括：
{1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，{1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，{1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，{1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，{1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，{1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，{1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，{1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，{1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，{1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
仿真结果表明，上述描述的这些序列和其等价序列经π/2 BPSK调制后对应的序列{x n}可以满足如下条件：
条件一，使用时域滤波，当滤波系数为[0.1，1，0.1]时，PAPR小于2.89dB；当滤波系数为[0.16，1，0.16]时，PAPR小于2.35dB；当滤波系数为[0.22，1，0.22]时，PAPR小于1.76dB；当滤波系数为[0.28，1，0.28]时，PAPR小于1.27dB。
条件二，序列{s n}所对应的频域序列的最大归一化功率小于0.5dB，最小归一化功率大于-0.5dB，即序列{s n}的频域平坦度比较好。
例如，当第一信号的调制方式为π/2的BPSK时，第一信号也可满足上述条件一和条件二。
应理解，发送的第一信号的PAPR较小，可以节省发送端(例如终端设备)的能耗。发送的第一信号的频域平坦度较好，有利于提高利用第一信号进行信道估计的性能。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
例如，第一信号的调制方式为π/2 BPSK。
在一种可能的设计中，所述第一信号为参考信号；或者，所述第一信号为用于承载通信信息的信号。
结合第一方面，在第一方面的一种可能的实现方式，所述第一信号为第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
例如，第二信号承载于共享信道。
结合第一方面，在第一方面的一种可能的实现方式，所述序列{s n}的集合至少包括第二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
结合第一方面，在第一方面的一种可能的实现方式，根据所述序列{x n}，生成第一信号，包括：对所述序列{x n}中的N个元素进行离散傅里叶变换，获得包括N个元素的序列{f n}；将所述序列{f n}中的N个元素分别映射到N个子载波上，获得包括N个元素的频域信号；根据所述频域信号，生成所述第一信号。
结合第一方面，在第一方面的一种可能的实现方式，所述N个子载波为连续的N个子载波，或等间隔的N个子载波。
结合第一方面，在第一方面的一种可能的实现方式，在对所述序列{x n}中的N个元素进行离散傅里叶变换之前，所述第一信号处理方法还包括：对所述序列{x n}进行滤波；或在对所述序列{x n}中的N个元素进行离散傅里叶变换之后，所述第一信号处理方法还包括：对所述序列{x n}进行滤波。
在一种可能的设计中，由元素s n组成的序列{s n}构成的集合至少包括第一序列集合中的第一序列或所述第一序列中的等价序列。
在一种可能的设计中，所述等价序列为{q n}，所述等价序列{q n}中的元素q n满足q n＝s (n+M)mod N，M∈{0,1,2,...,N-1}，N为序列长度。
第二方面，提供一种基于序列的信号处理方法，所述信号处理方法包括：接收第一信号；获取序列{x n}中的N个元素，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列，所述预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
Figure PCTCN2020070821-appb-000002
由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；根据所述序列{x n}中的N个元素，对所述第一信号进行处理。
其中，所述第一序列集合中的序列包括：
{1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，{1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，{1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，{1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，{1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，{1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，{1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，{1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，{1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，{1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
结合第二方面，在第二方面的一种可能的实现方式，所述序列{s n}的集合至少包括第 二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
结合第二方面，在第二方面的一种可能的实现方式，所述接收第一信号，获取序列{x n}中的N个元素，包括：在连续的N个子载波上获取所述第一信号，或者，在等间隔的N个子载波上获取所述第一信号；获取序列{f n}中的N个元素，N为大于1的正整数，所述第一信号由所述序列{f n}映射至N个子载波上生成，f n为所述序列{f n}中的元素；对所述序列{f n}进行离散傅里叶反变换处理，获取序列{x n}中的N个元素。
结合第二方面，在第二方面的一种可能的实现方式，所述第一信号为第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
在一种可能的设计中，由元素s n组成的序列{s n}构成的集合至少包括第一序列集合中的第一序列或所述第一序列中的等价序列。
在一种可能的设计中，所述等价序列为{q n}，所述等价序列{q n}中的元素q n满足q n＝s (n+M)mod N，M∈{0,1,2,...,N-1}，N为序列长度。
可选地，所述第一序列集合中除了上述序列，还可以包括其它可行的18长度的序列。
例如，所述第一序列集合中还可以包括序列：{1,1,0,1,1,0,1,0,1,1,0,0,0,0,0,0,0,1}。
第三方面，提供一种信号处理装置，所述信号处理装置可以是通信设备，也可以是通信设备内的芯片，所述通信设备或所述芯片具有实现第一方面或其任意可能的设计中的基于序列的信号处理方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
所述通信设备包括：处理单元和收发单元，所述处理单元可以是处理器，所述收发单元可以是收发器，所述收发器包括射频电路，可选地，所述通信设备还包括存储单元，所述存储单元例如可以是存储器。当所述通信设备包括存储单元时，所述存储单元用于存储计算机执行指令，所述处理单元与所述存储单元连接，所述处理单元执行所述存储单元存储的计算机执行指令，以使所述通信设备执行第一方面或其任意可能的设计中的基于序列的信号处理方法。
所述芯片包括：处理单元和收发单元，所述处理单元可以是处理器，所述收发单元可以是所述芯片上的输入/输出接口、管脚或电路等。所述处理单元可执行存储单元存储的计算机执行指令，以使所述芯片执行第一方面或其任意可能的设计中的基于序列的信号处理方法。可选地，所述存储单元可以是所述芯片内的存储单元(例如，寄存器、缓存等)，所述存储单元还可以是所述通信设备内的位于所述芯片外部的存储单元(例如，只读存储器(read-only memory，ROM))或可存储静态信息和指令的其他类型的静态存储设备(例如，随机存取存储器(random access memory，RAM))等。
第三方面中提到的处理器可以是一个中央处理器(central processing unit，CPU)、微处理器或专用集成电路(application specific integrated circuit，ASIC)，也可以是一个或多个用于控制第一方面或其任意可能的设计的基于序列的信号处理方法的程序执行的集成电路。
第四方面，提供一种信号处理装置，所述信号处理装置可以是通信设备，也可以是通信设备内的芯片，所述通信设备或所述芯片具有实现第二方面或其任意可能的设计中的基于序列的信号处理方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的 软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
所述通信设备包括：处理单元和收发单元，所述处理单元可以是处理器，所述收发单元可以是收发器，所述收发器包括射频电路，可选地，所述通信设备还包括存储单元，所述存储单元例如可以是存储器。当所述通信设备包括存储单元时，所述存储单元用于存储计算机执行指令，所述处理单元与所述存储单元连接，所述处理单元执行所述存储单元存储的计算机执行指令，以使所述通信设备执行第二方面或其任意可能的设计中的基于序列的信号处理方法。
所述芯片包括：处理单元和收发单元，所述处理单元可以是处理器，所述收发单元可以是所述芯片上的输入/输出接口、管脚或电路等。所述处理单元可执行存储单元存储的计算机执行指令，以使所述芯片执行第二方面或其任意可能的设计中的基于序列的信号处理方法。可选地，所述存储单元可以是所述芯片内的存储单元(例如，寄存器、缓存等)，所述存储单元还可以是所述通信设备内的位于所述芯片外部的存储单元(例如，只读存储器(read-only memory，ROM))或可存储静态信息和指令的其他类型的静态存储设备(例如，随机存取存储器(random access memory，RAM))等。
第四方面中提到的处理器可以是一个中央处理器(central processing unit，CPU)、微处理器或专用集成电路(application specific integrated circuit，ASIC)，也可以是一个或多个用于控制第二方面或其任意可能的设计的基于序列的信号处理方法的程序执行的集成电路。
第五方面，提供一种通信系统，所述通信系统包括本申请实施例的第三方面提供的信号处理装置，以及本申请实施例的第四方面提供的信号处理装置。
第六方面，提供一种计算机可读存储介质，其上存储有计算机程序，所述计算机程序被计算机执行时使得所述计算机实现第一方面或第二方面的任一可能的实现方式中的方法。
第七方面，提供一种包含指令的计算机程序产品，所述指令被计算机执行时使得所述计算机实现第一方面或第二方面的任一可能的实现方式中的方法。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
附图说明
图1为本申请实施例公开的一种基于序列的信号发送方法的流程示意图；
图2为本申请实施例公开的一种终端设备确定序列{x n}的流程示意图；
图3为本申请实施例公开的终端设备生成第一信号的流程示意图；
图4、图5和图6为本申请实施例公开的包含N个元素的序列{x n}经DFT得到频域的包含N个元素的序列{f n}的示意图；
图7和图8为本申请实施例公开的包含N个元素序列{x n}经DFT得到的频域的包含N个元素的序列{f n}映射到N个子载波上的示意图；
图9为本申请实施例公开的网络设备处理第一信号的示意图；
图10和图11为本申请实施例公开的判断一个时域序列的频域是否平坦的流程示意图；
图12为本申请实施例公开的一种信号处理装置的结构示意图；
图13为本申请实施例公开的一种信号处理装置的另一结构示意图；
图14为本申请实施例公开的终端设备的结构示意图；
图15为本申请实施例公开的另一种信号处理装置的结构示意图；
图16为本申请实施例公开的另一种信号处理装置的另一结构示意图；
图17为本申请实施例公开的网络设备的结构示意图。
图18为本申请实施例公开的一种通信系统的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
本申请实施例的描述中，除非另有说明，“多个”是指两个或多于两个。另外，为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用“第一”、“第二”等字样，对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。此外，本申请实施例中的术语“包括”和“具有”不是排他的。例如，包括了一系列步骤或模块的过程、方法、系统、产品或设备没有限定于已列出的步骤或模块，还可以包括没有列出的步骤或模块。
在通信系统中，通常使用参考信号求取信道估计矩阵，从而解调数据信息。目前，在LTE系统，4G系统、4.5G系统，5G系统，以及NR系统或NR类似场景中，支持用于PUSCH的DMRS(可称为上行DMRS)采用DFT-s-OFDM波形，并使用π/2的BPSK调制方式。
在DMRS采用DFT-s-OFDM波形，并使用π/2的BPSK调制方式的场景下，支持DMRS使用基于Gold序列与CGS的序列。但是，在这种场景下，当DMRS使用基于Gold序列与CGS的序列时，若不能进行合适的筛选，会导致序列的频率平坦度较差，从而不利于进行信道估计。
当前，拟在NR中，支持DMRS采用基于ZC序列的序列。ZC序列是满足恒包络零自相关(constant amplitude zero auto-correlation，CAZAC)序列性质的序列。ZC序列的周期是其序列的长度，且满足中心对称的性质。此外，ZC序列有着良好的自相关性和互相关性。但是，在上述场景下，当DMRS使用基于ZC序列的序列时，会导致DMRS的PAPR高于传输的数据的PAPR，这导致导频信号带外杂散发射和带内信号损失，影响信道估计性能，或者导致上行覆盖受限。
为了在LTE系统、4G系统、4.5G系统、5G系统、NR系统或NR类似场景中，甚至其它具有更高要求的通信系统或通信应用环境中，使得DMRS所使用的序列，能够保持较好的序列频域平坦度，同时保持较低的PAPR值，本申请实施例提供了一种基于序列的信号处理方法与装置。
在本申请实施例中，主要从通信系统或通信应用环境中的接收侧和发送侧对基于序列 的信号处理方法进行描述。其中，接收侧可以是网络设备，发送侧可以是终端设备；或者接收侧可以是终端设备，发送侧可以是网络设备。为了便于理解与描述，下文实施例中均以接收侧为网络设备、发送侧为终端设备为例进行描述，但本申请不限于此。
在本申请实施例中涉及到的终端设备可以为用户设备。用户设备可以为有线设备，也可以为无线设备。其中，无线设备可以为具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备，经无线接入网与一个或多个核心网进行通信的移动终端。例如，无线终端可以为移动电话、手机、计算机、平板电脑、个人数码助理(personal digital assistant，PDA)、移动互联网设备(mobile internet device，MID)、可穿戴设备和电子书阅读器等。又如，无线终端也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动设备。再如，无线终端可以为移动站或接入点。
在本申请实施例中涉及到的网络设备可以为基站。基站可以包括各种形式的宏基站，微基站，中继站，接入点基站控制器，发送和接收点等等。在采用不同的无线接入技术的系统中，基站的具体名称可能会有所不同。
在本申请实施例中涉及的解调参考信号为可用于解调数据或信令的参考信号。根据传输方向的不同，可分为上行解调参考信号和下行解调参考信号。解调参考信号可以为LTE协议或NR协议中的DMRS，或者也可以为未来协议中定义的其他用于实现相同或相似功能的参考信号。本申请对此不做限定。
在LTE或NR协议中，DMRS可以承载在物理共享信道中与数据信号一起发送，以用于对物理共享信道中承载的数据信号进行解调。如，在物理下行共享信道(physical downlink share channel，PDSCH)中与下行数据一起发送，或者，在物理上行共享信道(physical uplink share channel，PUSCH)中与上行数据一起发送。DMRS还可以承载在物理控制信道中与控制信令一起发送，以用于对物理控制信道汇总承载的控制信令进行解调。如，在PDCCH中与下行控制信令一起发送，或者，在PUCCH中与上行控制信令一起发送。
在本申请实施例中，解调参考信号可包括用于解调PDCCH或PDSCH的下行解调参考信号，也可包括用于解调PUCCH或PUSCH的上行解调参考信号。下文中为方便说明，将解调参考信号简称为DMRS。
图1为本申请实施例提供的基于序列的信号处理方法100的示意性交互图。以发送侧为终端设备、接收侧为网络设备为例，该信号处理方法100包括如下步骤。
110，终端设备确定包括N个元素的序列{x n}，N等于18，x n为序列{x n}中的元素，序列{x n}为满足如下预设条件的序列。
该预设条件为：x n＝y (n+M)mod N。其中，n遍历0，1，…，N-1，例如，n可以表示序列{x n}中各个元素的索引。M∈{0,1,2,...,N-1}，应理解，M可以为小于N的整数。y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
Figure PCTCN2020070821-appb-000003
由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一。
其中，第一序列集合中的序列包括：
{1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，{1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，{1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}， {1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，{1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，{1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，{1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，{1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，{1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，{1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
可选地，步骤110的执行，可以是终端设备在入网后，确定包括N个元素的序列{x n}。也可以是，网络设备在终端设备接入网络时，由网络设备确定序列{b n}并配置给终端设备，由终端设备基于该序列{b n}确定包含N个元素的序列{x n}。N为大于1的正整数。
b n＝u·(1-2·s n)中涉及的u的取值并非固定不变的。例如，针对当前选取的同一个序列中的所有元素，u的取值可以是相同的。针对不同序列中的元素，u的取值可以不同。
x n＝y (n+M)mod N中涉及的M的取值根据不同情况而定。在确定同一个序列中的元素时，M的取值恒定不变。确定另外一个序列时，M的取值可以取1或其他小于N的整数。
可选地，作为一种实现方式。序列{s n}的集合预先存储于终端设备与网络设备上。网络设备从序列{s n}的集合中确定要使用的序列(记为第一序列)，然后向终端设备配置该第一序列；终端设备根据网络设备的配置获知要使用第一序列后，可以按照上述预设条件，生成序列{x n}。
例如，网络设备可以向终端设备发送该第一序列的编号、标识、小区标识或其它可标识该第一序列的信息。
再例如，当终端设备接入网络时，网络设备向终端设备配置第一序列。
可选地，作为另一种实现方式。序列{s n}的集合预先存储于终端设备与网络设备上。终端设备按照上述预设条件，针对序列{s n}的集合中的每种序列，均生成对应的序列{x n}。网络设备也按照上述预设条件，针对序列{s n}的集合中的每种序列，均生成对应的序列{x n}，网络设备从这些生成的序列{x n}中，选择要使用的序列(记为第二序列)，然后向终端设备该第二序列。终端设备根据网络设备的配置获知要使用的序列{x n}，可以根据该序列{x n}生成第一信号。
例如，网络设备可以向终端设备发送该第二序列的编号、标识、小区标识或其它可标识该第二序列的信息。
再例如，终端设备接入网络后，网络设备向终端设备配置该第二序列。
可选地，第一信号的调制方式为π/2的二进制相移键控(BPSK)。
例如，第一信号的波形可以为DFT-s-OFDM。
120，终端设备根据序列{x n}，生成第一信号。
130，向网络设备发送第一信号。相应地，网络设备接收终端设备发送的第一信号。
140，网络设备获取序列{x n}，并根据序列{x n}中的N个元素，对第一信号进行处理。
一般来说，PAPR比较低的序列，CM值也比较小。序列{s n}经过验证，其CM值都很小，即序列{s n}的PAPR较小。
仿真结果表明，上述描述的这些序列和其等价序列经π/2 BPSK调制后对应的序列{x n} 可以满足如下条件：
条件一，使用时域滤波，当滤波系数为[0.1，1，0.1]时，PAPR小于2.89dB；当滤波系数为[0.16，1，0.16]时，PAPR小于2.35dB；当滤波系数为[0.22，1，0.22]时，PAPR小于1.76dB；当滤波系数为[0.28，1，0.28]时，PAPR小于1.27dB。
条件二，序列{s n}所对应的频域序列的最大归一化功率小于0.5dB，最小归一化功率大于-0.5dB，即序列{s n}的频域平坦度比较好。
例如，当第一信号的调制方式为π/2的BPSK时，第一信号也可满足上述条件一和条件二。
应理解，发送的第一信号的PAPR较小，可以节省发送端(例如终端设备)的能耗。发送的第一信号的频域平坦度较好，有利于提高利用第一信号进行信道估计的性能。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
可选地，该第一信号为参考信号。
例如，该第一信号可以为下列中的任一种：上行控制信息(uplink control information,UCI)、DMRS、探测参考信号(Sounding Reference Signal，SRS)、相位追踪参考信号(Phase-tracking Reference Signal，PTRS)、确认应答(acknowledgment，ACK)信息、否定确认应答(negative acknowledgment，NACK)信息、上行调度请求(scheduling request，SR)信息。本申请实施例对此不作限定。
可选地，第一信号为第二信号的参考信号，第二信号的调制方式为π/2二进制相移键控BPSK。
可选地，在一些实施例中，序列{s n}的集合包括上述第一序列集合的全部序列中的一个序列或多个序列。
可选地，在一些实施例中，序列{s n}的集合包括上述第一序列集合的部分序列中的一个序列或多个序列。
作为示例，序列{s n}的集合包括第二序列集合中的一个序列或多个序列，该第二序列集合包括上述第一序列集合中的部分序列。
例如，第二序列集合包括前文描述的第一序列集合包括的20个序列中的前10个序列。
可选地，所述第一序列集合中除了上述序列，还可以包括其它可行的18长度的序列。
例如，所述第一序列集合中还可以包括序列：{1,1,0,1,1,0,1,0,1,1,0,0,0,0,0,0,0,1}。
作为示例，图2为终端设备确定序列{x n}的示意图。终端设备确定序列{x n}的流程包括如下步骤。
步骤1，终端设备确定序列{b n}，b n＝u·(1-2·s n)。其中，s n为序列{s n}中的元素，u为非零复数，n遍历0，1，…，N-1，例如，n可以表示序列中各个元素的索引，N为18。u的取值并非固定不变的。例如，针对当前选取的同一个序列中的所有元素，u的取值可以是相同的。针对不同序列中的元素，u的取值可以不同。
可选地，作为一种实现方式。序列{s n}的集合预先存储于终端设备与网络设备上。网络设备从序列{s n}的集合中确定要使用的序列(记为第一序列)，然后向终端设备配置该 第一序列；终端设备根据网络设备的配置获知要使用第一序列后，可以按照b n＝u·(1-2·s n)，生成序列{b n}。
例如，网络设备可以向终端设备发送该第一序列的编号、标识、小区标识或其它可标识该第一序列的信息。
可选地，作为另一种实现方式。序列{s n}的集合预先存储于终端设备与网络设备上。终端设备按照b n＝u·(1-2·s n)，针对序列{s n}的集合中的每种序列，均生成对应的序列{b n}。网络设备也按照b n＝u·(1-2·s n)，针对序列{s n}的集合中的每种序列，均生成对应的序列{b n}，网络设备从这些生成的序列{b n}中，选择要使用的序列(记为第三序列)，然后向终端设备该第三序列。终端设备根据网络设备的配置获知要使用的序列{b n}。
例如，网络设备可以向终端设备发送该第三序列的编号、标识、小区标识或其它可标识该第三序列的信息。
步骤2，终端设备根据如下公式确定序列{x n}：
x n＝A·b n·j n mod 2，
A为非零复数，
Figure PCTCN2020070821-appb-000004
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
下文描述在步骤120中，基于序列{x n}生成第一信号的过程。
可选地，在一些实施例中，步骤120包括：对序列{x n}中的N个元素进行离散傅里叶变换(discrete fourier transform，DFT)，获得包括N个元素的序列{f n}；将序列{f n}中的N个元素分别映射到N个子载波上，生成第一信号。
可选地，在对序列{x n}中的N个元素进行离散傅里叶变换之前，该方法还包括：对序列{x n}进行滤波。
可选地，在对序列{x n}中的N个元素进行离散傅里叶变换之后，该方法还包括：对序列{x n}进行滤波。
可选地，将序列{f n}中的N个元素分别映射到N个子载波上，生成第一信号，包括：将序列{f n}中的N个元素分别映射到N个子载波，生成包括N的元素的频域信号；将频域信号进行快速傅里叶反变换，获得时域信号；为时域信号添加循环前缀，生成第一信号。
可选地，将序列{f n}中的N个元素分别映射到N个子载波上，生成第一信号，包括：将序列{f n}中的N个元素分别映射到N个子载波，生成包括N的元素的频域信号；将所述频域信号作为所述信号。
作为示例，图3为生成序列{x n}的示意性流程图。如图3所示，生成序列{x n}的流程包括如下步骤。
310，终端设备对包含N个元素的序列{x n}进行DFT处理，得到序列{f n}。
可选地，如图4所示，在终端设备对序列{x n}进行DFT处理获得序列{f n}的过程中，可以不使用滤波器。
可选地，如图5所示，在终端设备对序列{x n}进行DFT处理获得序列{f n}的过程中，可 以先使用滤波器对序列{x n}进行处理，对滤波处理之后的序列{x n}进行DFT处理，获得序列{f n}。
可选地，如图6所示，在终端设备对序列{x n}进行DFT处理获得序列{f n}的过程中，可以先对序列{x n}进行DFT处理，再使用滤波器进行处理，得到序列{f n}。
320，终端设备将序列{f n}中的N个元素分别映射至N个子载波上，得到N点的频域信号。
N点的频域信号可以为包括N个元素的频域信号。
可选地，终端设备将序列{f n}中的N个元素分别映射至连续的N个子载波上。
如图7所示，将序列{f n}中的元素f 0到f N-1分别映射到N个连续的子载波，子载波标号为s+0,s+1,…,s+N-1。
在图7以及下文将提及的图8中，s表示序列{f n}映射的N个子载波中的第一个子载波在通信系统中的子载波中的索引。
在一种可能的示例中，终端设备将序列{f n}中的N个元素按照子载波从高到低的顺序，依次映射到N个子载波上。
其中，一个序列{f n}中元素映射到一个频域子载波。频域子载波是频域资源的最小单元，其用于承载数据信息。
在一种可能的示例中，终端设备将序列{f n}中的N个元素按照子载波从低到高的顺序，依次映射到N个子载波上。
将序列{f n}中的一个元素映射到一个子载波，就是在这个子载波上承载这个元素。映射之后，在该终端设备将数据通过射频发送时，相当于在这个子载波上发送这个元素。
在通信系统中，不同的终端设备可以占用不同的子载波发送数据。N个子载波在通信系统中所存在的多个子载波中的位置可以是预定义的，或者是网络设备通过信令配置的。
可选地，终端设备可以将序列{f n}中的N个元素分别映射至等间隔的N个子载波上。
例如，N个子载波之间的间隔为1，N个子载波在频域上是等间隔分布的。如图8所示，将序列{f n}中的元素f 0到f N-1分别映射到N个等间隔的子载波，子载波编号为s+0,s+2,…,s+2(N-1)。
本申请实施例对于将序列{f n}中的N个元素分别映射至N个子载波上的方式，并不仅限于以上方式。
330，终端设备对包括N个元素的频域信号进行快速傅立叶反变换(inverse fast Fourier transformation，IFFT)，获得对应的时域信号，并为该时域信号添加循环前缀，生成第一信号。
例如，终端设备对包括N个元素的频域信号进行IFFT后得到的时域信号是一个正交频分复用(orthogonal frequency division multiplexing，OFDM)符号
如果采用图3所示的方式生成第一信号，在上述实施例中的步骤130中，终端设备通过射频发送该第一信号。
终端设备将第一信号通过射频发出去。也就是说，该终端设备在该N个子载波上发送承载序列{f n}的第一信号。
在一个可能的示例中，该终端设备可以在一个OFDM符号上发送承载序列{f n}的第一信号。也可以在多个OFDM符号上发送承载序列{f n}的第一信号。
可选地，在一些实施例中，步骤120包括：采用成型滤波器处理序列{x n}中的N个元素，获得包括N个元素的序列{f n}；通过将序列{f n}中的N个元素分别映射到N个子载波上，生成第一信号。
可选地，N个子载波为连续的N个子载波，或等间隔的N个子载波。
前文已述，本申请中的第一信号可以为参考信号，但本申请并非限定于此。
可选地，在一些实施例中，该第一信号为用于承载通信信息的信号。
通信信息的承载方式可以是通过序列选择的方式承载，也可以是通过序列调制的方式承载。本申请对此不作限定。
可选地，通信信息的承载方式为通过序列选择的方式承载。
作为示例，为一个终端设备分配2 n个正交的序列，这2 n个正交的序列可以为1个根序列的2 n个循环移位，这2 n个正交的序列能够承载n比特信息。例如，假设有标号为0、1、2和3的4个序列，其中，00对应序列0，01对应序列1，10对应序列2，11对应序列3，这样4个序列能够承载2比特信息。
可选地，通信信息的承载方式为通过序列调制的方式承载。
作为示例，为一个用户分配1个序列，并且将该用户所需传输的信息生成调制符号。该调制符号包括但不限于BPSK符号、QPSK符号、8QAM符号、16QAM符号等。将该调制符号与该序列相乘，生成实际的发送序列。假设，一个BPSK符号为1或者-1，对于一个序列{x n}而言，基于该BPSK符号进行调制后，发送的序列可以为列{x n}或{-x n}。
在一种可能的示例中，在前文结合图2的描述中，终端设备在入网后，可以通过A和序列{b n}确定网络设备配置的包含N个元素的序列{x n}。
例如，该第一信号为用于承载通信信息的信号，且该通信信息的承载方式为序列调制的方式，则第一信号是通过序列{x n}中不同的A的取值，承载不同信息的。
可选地，A可以为调制符号。此时，一路数据信息比特或者控制信息比特经过调制后，得到A。A承载在序列{x n}所包含的N个元素上，A不随着n的变化而改变。
可选地，A为常数。例如A＝1。例如，A可以是终端设备和网络设备都已知的符号。A也可以表示是幅度。
需要说明的是，A在一个发射时间单元上是常数不代表A是固定不变的，在不同的时刻发送第一信号时，A可以是变的。例如，序列{x n}中包含的全部N个元素是参考信号，A是参考信号的幅度，终端设备在第一次发送第一信号时，可以按A＝1发送。终端设备在第二次发送第一信号时，可以按A＝2发送。
下文将描述接收侧，即网络设备接收到第一信号后，对第一信号的处理过程。
在步骤130中，网络设备接收终端设备发送的第一信号。
例如，该网络设备按照预定义的或者基站配置的N个子载波在通信系统的子载波中的位置接收N个子载波上的第一信号。
可选地，网络设备在连续的N个子载波上，或者，在等间隔的N个子载波上获取N个子载波上的第一信号。
在步骤140中，网络设备获取序列{x n}，并根据序列{x n}中的N个元素，处理第一信号。
可选地，作为一种实现方式，网络设备获取序列{x n}中的N个元素的过程包括：网络 设备在N个子载波上接收第一信号；去除第一信号的循环前缀，得到时域信号；对时域信号进行M点的DFT，获得包括N个元素的频域信号，M大于或等于N；基于包括N个元素的频域信号，确定序列{f n}中的N个元素；对该序列{f n}进行离散傅里叶反变换处理(inverse discrete fourier transformation，IDFT)，得到序列{x n}中的N个元素。
可选地，作为另一种实现方式，网络设备与终端设备已知使用的序列{s n}，网络设备获取序列{x n}中的N个元素的过程包括：网络设备按照如下公式获得序列{x n}，进而获得序列{x n}中的N个元素：
b n＝u·(1-2·s n)，
y n＝A·b n·j n mod 2，
x n＝y (n+M)mod N，
其中，s n为序列{s n}中的元素，u为非零复数，n遍历0，1,2，…N-1，N等于18。A为非零复数，
Figure PCTCN2020070821-appb-000005
M∈{0,1,2,...,N-1}，序列{s n}的集合至少包括上述第一序列集合中的序列之一。
可选地，作为再一种实现方式，网络设备与终端设备已知使用的序列{b n}，b n＝u·(1-2·s n)，网络设备获取序列{x n}中的N个元素的过程包括：网络设备按照如下公式获得序列{x n}，进而获得序列{x n}中的N个元素：
y n＝A·b n·j n mod 2，
x n＝y (n+M)mod N，
其中，b n为序列{b n}中的元素，n遍历0，1,2，…N-1，N等于18。A为非零复数，
Figure PCTCN2020070821-appb-000006
M∈{0,1,2,...,N-1}，序列{s n}的集合至少包括上述第一序列集合中的序列之一。
可选地，作为再一种实现方式，若网络设备与终端设备已知使用的序列{x n}，则在步骤140中，网络设备可以直接使用序列{x n}中的N个元素处理第一信号。
可选地，第一信号为第二信号的参考信号。例如，该第二信号承载于共享信道。
网络设备通过根据序列{x n}处理第一信号，可以的得到承载该第二信号的共享信道的的信道矩阵H。可选地，本方法还包括：根据该信道矩阵，解调该第二信号。
例如，网络设备对第一信号的处理过程如图9所示，网络设备通过遍历本地存储的序列{x n′}得到所有可能的序列。将获取的序列{x n}与序列{x n′}所有可能的序列分别相关处理并进行最大似然比较，获取终端设备传输的数据。
假设，对于两比特信息的取值组合为{(0,0),(0,1),(1,0),(1,1)}。当两比特信息为(0,0)时，得到的序列{x n′}是序列{x 1,n′},当两比特信息为(0,1)时，得到的序列{x n′}是序列{x 2,n′},当两比特信息为(1,0)时，得到的序列{x n′}是序列{x 3,n′},当两比特信息为(1,1)时，得到的序列{x n′}是序列{x 4,n′}。这4个序列{x 1,n′}，{x 2,n′}，{x 3,n′}，{x 4,n′}可以是同一个序列的循环移位序列，将序列{x n}与{x 1,n′}，{x 2,n′}，{x 3,n′}，{x 4,n′}分别相关，得到4个相关值。最大相关值对应的两比特信息的取值即为网络设备获取的数据。例如，最大相关值是 序列{x n}与{x 1,n′}相关得到的，则两比特信息是(0,0)，即网络设备获取的数据为比特信息(0,0)。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。尤其是，满足NR系统或NR类似场景。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
作为示例，判定一个时域序列的频域是否平坦可通过如图10或图11所示的流程进行处理。
如图10所示，上述涉及的一个时域序列{x n}对应的频域序列的第一种最大归一化功率定义为序列
Figure PCTCN2020070821-appb-000007
归一化后的最大值，一个时域序列{x n}对应的频域序列的第一种最小归一化功率定义为序列
Figure PCTCN2020070821-appb-000008
归一化后的最小值。
如图11所示，上述涉及的一个时域序列{x n}对应的频域序列的第二种最大归一化功率定义为序列
Figure PCTCN2020070821-appb-000009
归一化后的最大值，一个时域序列{x n}对应的频域序列的第二种最小归一化功率定义为序列
Figure PCTCN2020070821-appb-000010
归一化后的最小值。
上述可知，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
本文中描述的各个实施例可以为独立的方案，也可以根据内在逻辑进行组合，这些方案都落入本申请的保护范围中。
上文描述了本申请的方法实施例，下文将描述上文方法实施例对应的装置实施例。应理解，装置实施例的描述与方法实施例的描述相互对应，因此，未详细描述的内容可以参见前面方法实施例，为了简洁，这里不再赘述。
如图12所示，本申请实施例提供一种基于序列的信号处理装置1200。信号处理装置1200可以是通信设备，也可以是通信设备内的芯片。例如，该信号处理装置1200对应于上文方法实施例中的终端设备。该信号处理装置1200包括如下单元。
处理单元1210，用于确定包括N个元素的序列{x n}，N等于18，x n为序列{x n}中的元素，序列{x n}为满足预设条件的序列，预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
Figure PCTCN2020070821-appb-000011
由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一。
其中，第一序列集合中的序列包括：
{1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，{1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}， {1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，{1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，{1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，{1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，{1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，{1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，{1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，{1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
处理单元1210还用于，根据序列{x n}，生成第一信号。
收发单元1220，用于发送第一信号。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
可选地，在一些实施例中，序列{s n}的集合至少包括第二序列集合中的序列之一，第二序列集合包括第一序列集合中的部分序列或全部序列。
可选地，在一些实施例中，处理单元1210用于：对序列{x n}中的N个元素进行离散傅里叶变换，获得包括N个元素的序列{f n}；将序列{f n}中的N个元素分别映射到N个子载波上，获得包括N个元素的频域信号；根据频域信号，生成第一信号。
可选地，在一些实施例中，N个子载波为连续的N个子载波，或等间隔的N个子载波。
可选地，在一些实施例中，处理单元1210用于，在对序列{x n}中的N个元素进行离散傅里叶变换之前，对序列{x n}进行滤波；或处理单元1210用于，在对序列{x n}中的N个元素进行离散傅里叶变换之后，对序列{x n}进行滤波。
可选地，在一些实施例中，第一信号为第二信号的参考信号，第二信号的调制方式为π/2二进制相移键控BPSK。
应理解，处理单元1210可以采用处理器或处理器相关电路来实现。收发送单元1220可以由收发器或收发器相关电路实现。
如图13所示，本申请实施例还提供一种信号处理装置1300，该信号处理装置1300包括处理器1310，存储器1320与收发器1330，其中，存储器1320中存储指令或程序，处理器1310用于执行存储器1320中存储的指令或程序。存储器1320中存储的指令或程序被执行时，该处理器1310用于执行上述实施例中处理单元1210执行的操作，收发器1330用于执行上述实施例中收发单元1220执行的操作。
应理解，本申请实施例提供的信号处理装置1200或信号处理装置1300可对应于上文方法实施例中的终端设备，并且信号处理装置1200或信号处理装置1300中的各个模块的操作和/或功能分别为了实现上文描述的各个方法的相应流程，为了简洁，在此不再赘述。
本申请实施例还提供一种基于序列的信号处理装置，该信号处理装置可以是终端设备也可以是集成电路或芯片。该信号处理装置可以用于执行上述方法实施例中由终端设备所执行的动作。
当该信号处理装置为终端设备时，图14示出了一种简化的终端设备的结构示意图。 便于理解和图示方便，图14中，终端设备以手机作为例子。如图14所示，终端设备包括处理器、存储器、射频电路、天线以及输入输出装置。处理器主要用于对通信协议以及通信数据进行处理，以及对终端设备进行控制，执行软件程序，处理软件程序的数据等。存储器主要用于存储软件程序和数据。射频电路主要用于基带信号与射频信号的转换以及对射频信号的处理。天线主要用于收发电磁波形式的射频信号。输入输出装置，例如触摸屏、显示屏，键盘等主要用于接收用户输入的数据以及对用户输出数据。需要说明的是，有些种类的终端设备可以不具有输入输出装置。
当需要发送数据时，处理器对待发送的数据进行基带处理后，输出基带信号至射频电路，射频电路将基带信号进行射频处理后将射频信号通过天线以电磁波的形式向外发送。当有数据发送到终端设备时，射频电路通过天线接收到射频信号，将射频信号转换为基带信号，并将基带信号输出至处理器，处理器将基带信号转换为数据并对该数据进行处理。为便于说明，图14中仅示出了一个存储器和处理器。在实际的终端设备产品中，可以存在一个或多个处理器和一个或多个存储器。存储器也可以称为存储介质或者存储设备等。存储器可以是独立于处理器设置，也可以是与处理器集成在一起，本申请实施例对此不做限制。
在本申请实施例中，可以将具有收发功能的天线和射频电路视为终端设备的收发单元，将具有处理功能的处理器视为终端设备的处理单元。如图14所示，终端设备包括收发单元1410和处理单元1420。收发单元也可以称为收发器、收发机、收发装置等。处理单元也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将收发单元1410中用于实现接收功能的器件视为接收单元，将收发单元1410中用于实现发送功能的器件视为发送单元，即收发单元1410包括接收单元和发送单元。收发单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
应理解，收发单元1410用于执行上述方法实施例中终端设备侧的发送操作和接收操作，处理单元1420用于执行上述方法实施例中终端设备上除了收发操作之外的其他操作。
例如，在一种实现方式中，处理单元1420，用于执行图1中的步骤110和步骤120，和/或处理单元1420还用于执行本申请实施例中终端设备侧的其他处理步骤。收发单元1410还用于执行图1中步骤120中终端设备侧的发送动作，和/或收发单元1410还用于本申请实施例中终端设备侧的其他收发步骤。
例如，在另一种实现方式中，处理单元1420，用于执行图3中的步骤310至步骤330，和/或处理单元1420还用于执行本申请实施例中终端设备侧的其他处理步骤。收发单元1410还用于执行本申请实施例中终端设备侧的其他收发步骤。
当该通信装置为芯片时，该芯片包括收发单元和处理单元。其中，收发单元可以是输入输出电路、通信接口；处理单元为该芯片上集成的处理器或者微处理器或者集成电路。
如图15所示，本申请实施例提供一种基于序列的信号处理装置1500。信号处理装置1500可以是通信设备，也可以是通信设备内的芯片。例如，该信号处理装置1500对应于上文方法实施例中的网络设备。该信号处理装置1500包括如下单元。
收发单元1510，用于接收第一信号。
处理单元1520，用于获取序列{x n}中的N个元素，N等于18，x n为序列{x n}中的元 素，序列{x n}为满足预设条件的序列，预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
Figure PCTCN2020070821-appb-000012
由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；根据序列{x n}中的N个元素，对第一信号进行处理。
其中，第一序列集合中的序列包括：
{1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，{1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，{1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，{1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，{1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，{1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，{1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，{1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，{1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，{1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
因此，本申请实施例通过基于序列{x n}生成第一信号，该序列{x n}可以满足序列频域平坦度较好、PAPR值较低的条件，从而使得当第一信号为承载于PUSCH的信号的参考信号时，可以使得发送的第一信号保持较好的序列频域平坦度，同时保持较低的PAPR值，从而可以满足发送参考信号的通信应用环境。
可选地，在一些实施例中，序列{s n}的集合至少包括第二序列集合中的序列之一，第二序列集合包括第一序列集合中的部分序列或全部序列。
可选地，在一些实施例中，收发单元1510，还用于在连续的N个子载波上获取第一信号，或者，在等间隔的N个子载波上获取第一信号。
处理单元1520，还用于获取序列{f n}中的N个元素，N为大于1的正整数，第一信号由序列{f n}映射至N个子载波上生成，f n为序列{f n}中的元素；对序列{f n}进行离散傅里叶反变换处理，获取序列{x n}中的N个元素。
可选地，在一些实施例中，第一信号为第二信号的参考信号，第二信号的调制方式为π/2二进制相移键控BPSK。
应理解，收发单元1510可以由收发器或收发器相关电路实现。处理单元1520可以采用处理器或处理器相关电路来实现。
如图16所示，本申请实施例还提供一种基于序列的信号处理装置1600，该信号处理装置1600包括处理器1610，存储器1620与收发器1630，其中，存储器1620中存储指令或程序，处理器1610用于执行存储器1620中存储的指令或程序。存储器1620中存储的指令或程序被执行时，该处理器1610用于执行上述实施例中处理单元1520执行的操作，收发器1630用于执行上述实施例中收发单元1510执行的操作。
应理解，本申请实施例提供的信号处理装置1500或信号处理装置1600可对应于上文方法实施例中的网络设备，并且信号处理装置1500或信号处理装置1600中的各个模块的操作和/或功能分别为了实现上文描述的各个方法的相应流程，为了简洁，在此不再赘述。
本申请实施例还提供一种基于序列的信号处理装置，该信号处理装置可以是网络设备 也可以是芯片。该第二通信装置可以用于执行上述方法实施例中由网络设备所执行的动作。
当该信号处理装置为网络设备时，具体地，例如为基站。图17示出了一种简化的基站结构示意图。基站包括1710部分以及1720部分。1710部分主要用于射频信号的收发以及射频信号与基带信号的转换；1720部分主要用于基带处理，对基站进行控制等。1710部分通常可以称为收发单元、收发机、收发电路、或者收发器等。1720部分通常是基站的控制中心，通常可以称为处理单元，用于控制基站执行上述方法实施例中网络设备生成第一消息的动作。具体可参见上述相关部分的描述。
1710部分的收发单元，也可以称为收发机，或收发器等，其包括天线和射频单元，其中射频单元主要用于进行射频处理。可选的，可以将1710部分中用于实现接收功能的器件视为接收单元，将用于实现发送功能的器件视为发送单元，即1710部分包括接收单元和发送单元。接收单元也可以称为接收机、接收器、或接收电路等，发送单元可以称为发射机、发射器或者发射电路等。
1720部分可以包括一个或多个单板，每个单板可以包括一个或多个处理器和一个或多个存储器，处理器用于读取和执行存储器中的程序以实现基带处理功能以及对基站的控制。若存在多个单板，各个单板之间可以互联以增加处理能力。作为一种可选的实施方式，也可以是多个单板共用一个或多个处理器，或者是多个单板共用一个或多个存储器，或者是多个单板同时共用一个或多个处理器。
例如，在一种实现方式中，收发单元用于执行图1中步骤130中网络设备侧的接收操作，和/或收发单元还用于执行本申请实施例中网络设备侧的其他收发步骤。处理单元用于执行步骤140的动作，和/或处理单元还用于执行本申请实施例中网络设备侧的其他处理步骤。
当该通信装置为芯片时，该芯片包括收发单元和处理单元。其中，收发单元可以是输入输出电路、通信接口；处理单元为该芯片上集成的处理器或者微处理器或者集成电路。
图18为本申请实施例公开的一种通信系统1800，包括第一通信设备1810和第二通信设备1820。其中，第一通信设备1810是发送侧的设备，例如，第一通信设备1810为上文方法实施例中的终端设备。第二通信设备1820是接收侧的设备，例如，第二通信设备1820为上文方法实施例中的网络设备。
第一通信设备1810用于，确定包括N个元素的序列{x n}，并对序列{x n}中的N个元素进行DFT获得序列{f n}，然后将序列{f n}映射至N个子载波上，生成第一信号并发送给第二通信设备1820。序列{x n}的描述详见上文，这里不再赘述。
第二通信设备1820用于，接收第一通信设备1810发送第一信号，获取序列{f n}中的N个元素，对所述序列{f n}进行IDFT处理，得到序列{x n}中的N个元素，并根据序列{x n}中的N个元素对第一信号进行处理。
以上本申请实施例公开的通信系统中，第一通信设备1810和第二通信设备1820的个数并不进行限定。该第一通信设备1810可以为图12、图13和图14中公开的通信设备。可选的，第一通信设备1810可以用于执行上文方法实施例中涉及终端设备执行的相应操作。第二通信设备1820可以为图15、图16和图17中公开的通信设备。可选的，第二通信设备1820可以用于执行上文方法实施例中涉及网络设备执行的相应操作。具体过程以 及执行原理可以参照上述说明，这里不再进行赘述。
上述提供的任一种通信装置中相关内容的解释及有益效果均可参考上文提供的对应的方法实施例，此处不再赘述。
还应理解，本文中涉及的第一、第二、第三、第四以及各种数字编号仅为描述方便进行的区分，并不用来限制本发明实施例的范围。
应理解，本申请实施例中提及的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种基于序列的信号处理方法，其特征在于，包括：
    确定包括N个元素的序列{x n}，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列，所述预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
    Figure PCTCN2020070821-appb-100001
    由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；
    根据所述序列{x n}，生成第一信号；
    发送所述第一信号；
    其中，所述第一序列集合中的序列包括：
    {1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，
    {1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，
    {1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，
    {1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，
    {1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，
    {1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，
    {1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，
    {1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，
    {1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，
    {1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
  2. 根据权利要求1所述的信号处理方法，其特征在于，所述序列{s n}的集合至少包括第二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
  3. 根据权利要求1或2所述的信号处理方法，其特征在于，根据所述序列{x n}，生成第一信号，包括：
    对所述序列{x n}中的N个元素进行离散傅里叶变换，获得包括N个元素的序列{f n}；
    将所述序列{f n}中的N个元素分别映射到N个子载波上，获得包括N个元素的频域信号；
    根据所述频域信号，生成所述第一信号。
  4. 根据权利要求3所述的信号处理方法，其特征在于，所述N个子载波为连续的N个子载波，或等间隔的N个子载波。
  5. 根据权利要求3或4所述的信号处理方法，其特征在于，在对所述序列{x n}中的N个元素进行离散傅里叶变换之前，所述第一信号处理方法还包括：对所述序列{x n}进行滤波；或
    在对所述序列{x n}中的N个元素进行离散傅里叶变换之后，所述第一信号处理方法还包括：对所述序列{x n}进行滤波。
  6. 根据权利要求1至5中任一项所述的信号处理方法，其特征在于，所述第一信号为 第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
  7. 一种基于序列的信号处理方法，其特征在于，包括：
    接收第一信号，获取序列{x n}中的N个元素，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列，所述预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
    Figure PCTCN2020070821-appb-100002
    由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；
    根据所述序列{x n}中的N个元素，对所述第一信号进行处理；
    其中，所述第一序列集合中的序列包括：
    {1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，
    {1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，
    {1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，
    {1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，
    {1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，
    {1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，
    {1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，
    {1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，
    {1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，
    {1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
  8. 根据权利要求7所述的信号处理方法，其特征在于，所述序列{s n}的集合至少包括第二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
  9. 根据权利要求7或8所述的信号处理方法，其特征在于，所述接收第一信号，获取序列{x n}中的N个元素，包括：
    在连续的N个子载波上获取所述第一信号，或者，在等间隔的N个子载波上获取所述第一信号；
    获取序列{f n}中的N个元素，N为大于1的正整数，所述第一信号由所述序列{f n}映射至N个子载波上生成，f n为所述序列{f n}中的元素；
    对所述序列{f n}进行离散傅里叶反变换处理，获取序列{x n}中的N个元素。
  10. 根据权利要求7至9中任一项所述的信号处理方法，其特征在于，所述第一信号为第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
  11. 一种基于序列的信号处理装置，其特征在于，包括：
    处理单元，用于确定包括N个元素的序列{x n}，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列，所述预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
    Figure PCTCN2020070821-appb-100003
    由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；
    所述处理单元还用于，根据所述序列{x n}，生成第一信号；
    收发单元，用于发送所述第一信号；
    其中，所述第一序列集合中的序列包括：
    {1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，
    {1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，
    {1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，
    {1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，
    {1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，
    {1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，
    {1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，
    {1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，
    {1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，
    {1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
  12. 根据权利要求11所述的信号处理装置，其特征在于，所述序列{s n}的集合至少包括第二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
  13. 根据权利要求11或12所述的信号处理装置，其特征在于，所述处理单元用于：
    对所述序列{x n}中的N个元素进行离散傅里叶变换，获得包括N个元素的序列{f n}；
    将所述序列{f n}中的N个元素分别映射到N个子载波上，获得包括N个元素的频域信号；
    根据所述频域信号，生成所述第一信号。
  14. 根据权利要求13所述的信号处理装置，其特征在于，所述N个子载波为连续的N个子载波，或等间隔的N个子载波。
  15. 根据权利要求13或14所述的信号处理装置，其特征在于，所述处理单元用于，在对所述序列{x n}中的N个元素进行离散傅里叶变换之前，对所述序列{x n}进行滤波；或
    所述处理单元用于，在对所述序列{x n}中的N个元素进行离散傅里叶变换之后，对所述序列{x n}进行滤波。
  16. 根据权利要求11至15中任一项所述的信号处理装置，其特征在于，所述第一信号为第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
  17. 一种基于序列的信号处理装置，其特征在于，包括：
    收发单元，用于接收第一信号；
    处理单元，用于：
    获取序列{x n}中的N个元素，所述N等于18，x n为所述序列{x n}中的元素，所述序列{x n}为满足预设条件的序列，所述预设条件为：x n＝y (n+M)mod N，n的取值为0至N-1，M∈{0,1,2,...,N-1}，y n＝A·b n·j n mod 2，A为非零复数，元素b n＝u·(1-2·s n)，u为非零复数，
    Figure PCTCN2020070821-appb-100004
    由元素s n组成的序列{s n}的集合至少包括第一序列集合中的序列之一；
    根据所述序列{x n}中的N个元素，对所述第一信号进行处理；
    其中，所述第一序列集合中的序列包括：
    {1,0,1,1,0,1,1,1,0,0,0,0,0,1,1,1,0,0}，{1,1,0,0,0,1,0,0,1,0,1,1,0,0,0,1,1,1}，
    {1,0,1,1,0,0,1,0,1,0,1,0,0,1,0,0,0,1}，{1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,0,0,0}，
    {1,1,1,1,0,0,0,0,0,0,1,1,1,0,0,1,1,1}，{1,1,1,1,0,0,1,0,0,0,0,0,1,0,0,0,0,1}，
    {1,1,1,0,0,0,0,1,0,0,0,0,0,1,0,0,1,1}，{1,1,1,1,0,0,0,0,0,1,1,0,0,0,0,0,1,1}，
    {1,1,1,1,1,0,0,0,0,0,0,1,1,0,1,0,0,0}，{1,1,1,1,1,0,0,0,0,0,1,1,1,0,1,0,0,1}，
    {1,0,0,1,1,1,1,0,1,1,0,1,1,1,0,0,0,0}，{1,1,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1}，
    {1,0,0,1,0,1,0,1,0,0,1,1,1,1,1,0,0,0}，{1,1,1,1,0,0,0,1,1,0,1,1,0,0,0,0,0,1}，
    {1,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1,0,0}，{1,1,1,1,0,0,1,0,0,1,1,1,1,0,0,0,0,0}，
    {1,1,0,1,0,1,1,0,1,0,0,1,1,1,0,0,1,0}，{1,0,1,0,0,1,1,1,1,1,0,0,0,0,0,1,0,0}，
    {1,0,1,1,0,1,1,1,1,1,0,0,0,0,0,1,1,0}。
  18. 根据权利要求17所述的信号处理装置，其特征在于，所述序列{s n}的集合至少包括第二序列集合中的序列之一，所述第二序列集合包括所述第一序列集合中的部分序列或全部序列。
  19. 根据权利要求17或18所述的信号处理装置，其特征在于，所述收发单元，还用于在连续的N个子载波上获取所述第一信号，或者，在等间隔的N个子载波上获取所述第一信号；
    所述处理单元，还用于获取序列{f n}中的N个元素，N为大于1的正整数，所述第一信号由所述序列{f n}映射至N个子载波上生成，f n为所述序列{f n}中的元素；对所述序列{f n}进行离散傅里叶反变换处理，获取序列{x n}中的N个元素。
  20. 根据权利要求17至19中任一项所述的信号处理装置，其特征在于，所述第一信号为第二信号的参考信号，所述第二信号的调制方式为π/2二进制相移键控BPSK。
  21. 一种信号处理装置，其特征在于，包括：
    存储器，用于存储计算机指令；
    处理器，用于执行所述存储器中存储的计算机指令，所述计算机指令被执行时，使得所述处理器用于执行权利要求1-6，7-10中任一项所述的信号处理方法。
  22. 一种计算机可读存储介质，用于存储计算机程序，其特征在于，所述计算机程序用于执行权利要求1-6、7-10中任一项所述的信号处理方法的指令。
PCT/CN2020/070821 2019-01-09 2020-01-08 基于序列的信号处理方法与装置 WO2020143649A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP20738420.7A EP3879777A4 (en) 2019-01-09 2020-01-08 METHOD AND DEVICE FOR SEQUENCE-BASED SIGNAL PROCESSING
BR112021013420-4A BR112021013420A2 (pt) 2019-01-09 2020-01-08 Método de processamento de sinal baseado em sequência, aparelho, meio de armazenamento legível por computador e produto de programa de computador
US17/361,720 US20210328842A1 (en) 2019-01-09 2021-06-29 Sequence-based signal processing method and apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910020924.0A CN111431829A (zh) 2019-01-09 2019-01-09 基于序列的信号处理方法与装置
CN201910020924.0 2019-01-09

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/361,720 Continuation US20210328842A1 (en) 2019-01-09 2021-06-29 Sequence-based signal processing method and apparatus

Publications (1)

Publication Number Publication Date
WO2020143649A1 true WO2020143649A1 (zh) 2020-07-16

Family

ID=71520345

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/070821 WO2020143649A1 (zh) 2019-01-09 2020-01-08 基于序列的信号处理方法与装置

Country Status (5)

Country Link
US (1) US20210328842A1 (zh)
EP (1) EP3879777A4 (zh)
CN (2) CN111431829A (zh)
BR (1) BR112021013420A2 (zh)
WO (1) WO2020143649A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113383606A (zh) * 2019-02-01 2021-09-10 株式会社Ntt都科摩 用户终端以及无线通信方法
CN116800574A (zh) * 2022-03-17 2023-09-22 华为技术有限公司 一种安全ltf序列确定方法及相关装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106664279A (zh) * 2014-07-02 2017-05-10 华为技术有限公司 抑制mc‑cdma和衍生系统中papr的系统和方法
CN108833070A (zh) * 2017-09-08 2018-11-16 华为技术有限公司 基于序列的信号处理方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101005478B (zh) * 2007-01-18 2010-08-25 西安电子科技大学 降低ofdm系统峰均功率比papr的矩阵分块交织方法及装置
CN106817331A (zh) * 2015-12-02 2017-06-09 华为技术有限公司 通信系统中处理通信信号的方法和装置
US10412745B2 (en) * 2016-11-30 2019-09-10 Telefonaktiebolaget Lm Ericsson (Publ) Peak-to-average power ratio reduction in multiuser MIMO systems
CN109039978B (zh) * 2017-08-11 2020-03-20 华为技术有限公司 基于序列的信号处理方法、通信设备及通信系统
CN109474408B (zh) * 2017-09-08 2024-03-26 华为技术有限公司 基于序列的信号处理方法及装置
CN112532368B (zh) * 2017-11-16 2021-08-20 华为技术有限公司 基于序列的信号处理方法及信号处理装置
WO2019096268A1 (zh) * 2017-11-16 2019-05-23 华为技术有限公司 基于序列的信号处理方法及信号处理装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106664279A (zh) * 2014-07-02 2017-05-10 华为技术有限公司 抑制mc‑cdma和衍生系统中papr的系统和方法
CN108833070A (zh) * 2017-09-08 2018-11-16 华为技术有限公司 基于序列的信号处理方法及装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Pseudo-CR on SRv6 Impact on N4", 3GPP TSG CT WG4 MEETING #86-BIS, C4-187224, 19 October 2018 (2018-10-19), XP051574252 *
See also references of EP3879777A4

Also Published As

Publication number Publication date
US20210328842A1 (en) 2021-10-21
EP3879777A1 (en) 2021-09-15
CN111431829A (zh) 2020-07-17
CN112600785A (zh) 2021-04-02
BR112021013420A2 (pt) 2021-09-21
EP3879777A4 (en) 2022-02-16
CN112600785B (zh) 2022-04-12

Similar Documents

Publication Publication Date Title
CN115001924B (zh) 基于序列的信号处理方法及装置
US11606238B2 (en) Sequence-based signal processing method and signal processing apparatus
US11082269B2 (en) Signal processing method, signal processing apparatus, computer readable storage medium, and computer program product
CN108833070B (zh) 基于序列的信号处理方法及装置
JP7463477B2 (ja) 系列に基づく信号処理方法および装置
WO2020143649A1 (zh) 基于序列的信号处理方法与装置
US11252003B2 (en) Sequence-based signal processing method and apparatus
WO2019096268A1 (zh) 基于序列的信号处理方法及信号处理装置
WO2020143780A1 (zh) 信号处理的方法和装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20738420

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: CN2020070821

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2020738420

Country of ref document: EP

Effective date: 20210608

NENP Non-entry into the national phase

Ref country code: DE

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112021013420

Country of ref document: BR

ENP Entry into the national phase

Ref document number: 112021013420

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20210707