WO2020140766A1 - 包括乘累加模块的芯片、控制方法、电子设备及存储介质 - Google Patents

包括乘累加模块的芯片、控制方法、电子设备及存储介质 Download PDF

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WO2020140766A1
WO2020140766A1 PCT/CN2019/126829 CN2019126829W WO2020140766A1 WO 2020140766 A1 WO2020140766 A1 WO 2020140766A1 CN 2019126829 W CN2019126829 W CN 2019126829W WO 2020140766 A1 WO2020140766 A1 WO 2020140766A1
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point
operand
fixed
floating
multiply
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PCT/CN2019/126829
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French (fr)
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李嘉昕
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腾讯科技（深圳）有限公司
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Priority to US17/362,374 priority Critical patent/US20210326118A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4824—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices using signed-digit representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/556—Logarithmic or exponential functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of chips, and in particular to a chip including a multiply-accumulate module, a control method, an electronic device, and a storage medium.
  • the multiply-accumulate module is a basic calculation module on the chip, which is widely used in central processing unit (CPU), field programmable gate array (Field-Programmable Gate Array, FPGA), application specific integrated circuit (Application Specific Integrated) Circuits (ASIC), graphics processor (Graphics Processing Unit, GPU) or other artificial intelligence (Artificial Intelligence, AI) chip and other chips.
  • CPU central processing unit
  • FPGA Field-Programmable Gate Array
  • ASIC Application Specific Integrated Circuits
  • GPU Graphics Processing Unit
  • AI Artificial Intelligence
  • multiply-accumulate modules Take the chip used for neural network model calculation as an example.
  • the first multiply-accumulate module is called for operation; when floating-point operation is required, the second multiply-accumulate module is called for operation.
  • a chip including a multiply-accumulate module, a control method, an electronic device, and a storage medium are provided.
  • a chip including a multiply-accumulate module, the chip includes a multiply-accumulate module; the multiply-accumulate module includes: a first input terminal and a second input terminal for inputting a multiplied number, The upper input terminal for inputting the addition number, the mode selection terminal for selecting the fixed-point calculation mode or floating-point calculation mode, and the module output terminal;
  • the multiply-accumulate module also includes: fixed-point general unit, floating-point special unit and output selection unit;
  • the fixed-point universal unit is connected to the first input terminal, the second input terminal, the superior input terminal and the mode selection terminal respectively, and the fixed-point output terminal of the fixed-point universal unit is connected to the output selection unit and the floating-point dedicated unit respectively;
  • the floating-point dedicated unit is connected to the first input terminal, the second input terminal, the upper-level input terminal, the fixed-point output terminal, and the mode selection terminal, and the floating-point output terminal of the floating-point dedicated unit is connected to the output selection unit;
  • the output selection unit is used to set the calculation mode according to the selection signal input from the mode selection terminal.
  • the calculation mode is the fixed-point calculation mode
  • the fixed-point output terminal and the module output are turned on; when the calculation mode is the floating-point calculation mode, the floating point The output is connected to the output of the module.
  • control method which is applied to the chip as described in the above aspect, the method comprising:
  • the multiply-accumulate module in the control chip is in the corresponding calculation mode;
  • the calculation mode includes a fixed-point calculation mode and a floating-point calculation mode;
  • the first intermediate result is calculated by performing the multiplication part of the first operand A and the second operand B in the floating-point operation, and the first operand A and the second operand B are calculated.
  • the third operand C and the first intermediate result perform the addition part of the floating-point operation, and then output the floating-point operation result.
  • an electronic device including the chip described in the above aspect, and the chip is used to execute the control method described in the above aspect.
  • a non-volatile computer-readable storage medium storing computer-readable instructions, which when executed by one or more processors cause the one Or multiple processors execute the control method described in the above aspect.
  • FIG. 1 is a comparison diagram of the calculation accuracy of fixed-point shaping calculation and floating-point calculation provided by the related art
  • FIG. 2 is a schematic structural diagram of a multiply-accumulate module with an input bit width of 16 bits provided by the related art
  • FIG. 3 is a schematic structural diagram of a multiply-accumulate module with an input bit width of 8 bits provided by the related art
  • FIG. 4 is a schematic structural diagram of a multiply-accumulate module in a chip provided by an exemplary embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a fixed-point universal unit in a multiply-accumulate module provided by an exemplary embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of a floating-point dedicated unit in a multiply-accumulate module provided by an exemplary embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a multiply-accumulate module in a chip provided by another exemplary embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an application environment provided by an exemplary embodiment of the present application.
  • FIG. 9 is a flowchart of a control method provided by an exemplary embodiment of the present application.
  • FIG. 10 is a flowchart of a control method provided by another exemplary embodiment of the present application.
  • FIG. 11 is a flowchart of a control method provided by another exemplary embodiment of the present application.
  • FIG. 13 is a flowchart of a control method provided by another exemplary embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present application.
  • 15 is a schematic structural diagram when an electronic device provided by an exemplary embodiment of the present application is specifically implemented as a server.
  • Multiply-accumulate module In the digital signal processor or some microprocessors, the hardware circuit unit used to implement the multiply-accumulate operation is also called "multiplier accumulator”.
  • Fixed-point number A method of number representation used in computers, which stipulates that the position of the decimal point of all data in the machine is fixed. Two simple conventions are commonly used in computers: fix the position of the decimal point before the highest digit of the data, or after the lowest digit. The former is often called the fixed-point decimal, and the latter is the fixed-point integer. In the embodiments of the present application, a fixed-point number is taken as a fixed-point integer as an example for description.
  • the computer treats them as 0, which is called underflow; when it is greater than the maximum value that the fixed-point number can represent, the computer will not be able to represent it, called overflow, overflow and underflow collectively For overflow.
  • Floating-point (floating-point number): Another method used to identify numbers in computers, similar to scientific notation, any binary number N can always be written as:
  • M becomes the fractional part of floating-point number N (also called mantissa), which is a pure decimal;
  • E is the exponent part of floating-point number N (also called exponent), which is an integer.
  • This method of representation is equivalent to the position of the decimal point of a number that varies with the scale factor, and can float freely within a certain range, so it is called floating point identification.
  • N A *N B 2 (Ea+Eb) *(M a *M b ).
  • the multiply-accumulate module is widely used in CPU, GPU and AI chips.
  • the AI field as an example, with the development of face recognition, image classification and other emerging technologies, the calculation accuracy and speed of the multiply-accumulate module are increasingly higher.
  • the dynamic range of 32-bit floating point FP32 is much greater than that of 32-shaped Int32
  • the dynamic range of 16-bit floating point FP16 is much greater than the dynamic range of 16-bit Int16. It can be concluded that the dynamic range The larger, the higher the calculation accuracy. Therefore, adding a floating-point calculation mode to the multiply-accumulate module becomes a technical solution to improve calculation accuracy.
  • two multiply-accumulate modules are provided in the chip, which are used to support the fixed-point calculation mode and the floating-point calculation mode. That is, two sets of independent hardware structures need to be designed. One set of multiply-accumulate modules is used to support the fixed-point calculation mode, and the other set of multiply-accumulate modules is used to support the floating-point calculation mode, so as to improve the calculation accuracy of the multiply-accumulate module; there is one Problem, two sets of independent hardware structures will occupy a larger area on the chip and consume more energy.
  • FIG. 2 shows a circuit structure of a multiply-accumulate module for fixed-point calculation mode in a related art.
  • the multiply-accumulate module supports multiplication between two operands with a bit width of 16 bits.
  • the circuit includes Four multipliers ad and four adders ad are added, and each multiplier supports 8-bit multiplication.
  • 11 is the 15th to 8th bit of the first operand 1
  • 12 is the 7th to 0th bit of the first operand
  • 21 is the 15th to 8th bit of the second operand 21
  • 22 is the 7th bit to the 0th bit of the second operand 22.
  • the multiply-accumulate module needs to support a fixed-point calculation mode with a bit width lower than 16 bits
  • two sets of circuit structures as shown in FIG. 3 need to be added, and both sets of circuit structures support two operands with a bit width of 8 bits.
  • two sets of circuit structures include 2 multipliers ef and 2 adders ef; and the circuit structure corresponding to the floating-point calculation mode includes 4 multipliers and 6 adders.
  • the multiply-accumulate module for fixed-point calculations and the multiply-accumulate module for floating-point calculations are two independent hardware circuits, and the total number of multipliers and adders required is relatively large, and the chip needs to be occupied The larger the area, the greater the power consumption. Taking an AI chip with multiple multiply-accumulate modules as an example, these factors directly limit the manufacturability, yield, heat dissipation, and performance of the AI chip.
  • a larger hardware structure area results in a larger chip area, and a larger chip area results in higher costs, poor manufacturability, and a low yield rate; on the other hand, a larger hardware structure area results in larger power consumption As power consumption changes, heat dissipation will increase, and too high temperature will affect the overall performance of the chip.
  • the embodiments of the present application provide technical solutions compatible with fixed-point multiply-accumulate calculation and floating-point multiply-accumulate in the same multiply-accumulate module. Please refer to the following examples.
  • FIG. 4 is a schematic structural diagram of a multiply-accumulate module 100 in a chip provided by an exemplary embodiment of the present application.
  • the multiply-accumulate module 100 includes: a first input terminal A and a second input terminal B for inputting multiplied numbers; Enter the upper input terminal C_in of the addition number, the mode selection terminal mode for selecting the fixed-point calculation mode or floating-point calculation mode, and the module output terminal C_OUT.
  • the multiply-accumulate module 100 also includes a fixed-point general-purpose unit 120, a floating-point dedicated unit 140, and an output selection unit 160.
  • the fixed-point universal unit 120 is connected to the first input terminal A, the second input terminal B, the upper-level input terminal C and the mode selection terminal mode; the fixed-point output terminal of the fixed-point universal unit 120 is connected to the output selection unit 160 and the floating-point dedicated unit 140, respectively .
  • the floating-point dedicated unit 140 is connected to the first input terminal A, the second input terminal B, the upper-level input terminal C, the fixed-point output terminal and the mode selection terminal mode of the fixed-point universal unit 120 respectively; the floating-point output terminal of the floating-point dedicated unit 140 is connected to The output selection unit 160 is connected.
  • the output selection unit 160 is connected to the mode selection terminal mode; the output selection unit 160 is used to set the calculation mode according to the selection signal input by the mode selection terminal mode.
  • the calculation mode includes a fixed-point calculation mode and a floating-point calculation mode.
  • the fixed-point general-purpose unit 120 is used to multiply the first operand A input from the first input A and the second operand B input from the second input B, and input it with the upper-level input C_in Accumulates the third operand C, and outputs the fixed-point operation result from the fixed-point output;
  • the output selection unit 160 turns on the fixed-point output terminal of the fixed-point general-purpose unit 120 and the module output terminal C_OUT, and outputs the fixed-point operation result from the module output terminal C_OUT.
  • the fixed-point universal unit 120 is used to perform the multiplication part of the floating-point multiply-accumulate operation on the first operand A input from the first input and the second operand B input from the second input Calculate and output the first intermediate result from the fixed-point output of the fixed-point general unit 120.
  • the first intermediate result is input to the floating-point dedicated unit 140; the floating-point dedicated unit 140 is used to input the first operand A, the first The operand B input from the two input terminals, the third operand C input from the upper-level input terminal, and the first intermediate result input from the fixed-point output terminal of the fixed-point universal unit 120 are subjected to the addition part of the floating-point multiply-accumulate operation.
  • the output end outputs the floating-point operation result.
  • the output selection terminal 160 turns on the floating-point output terminal of the floating-point dedicated unit 140 and the module output terminal C_OUT, and outputs the floating-point operation result from the module output terminal C_OUT.
  • the chip provided in this embodiment is provided with a fixed-point general unit and a floating-point special unit in the multiply-accumulate module.
  • the floating-point special unit is connected to the fixed-point output of the fixed-point general unit, and the fixed-point general unit performs the fixed-point
  • the multiply-accumulate calculation in the calculation mode is completed by the fixed-point general unit and the floating-point special unit in the floating-point calculation mode.
  • the same multiply-accumulate module can realize both fixed-point multiply-accumulate operation and floating-point multiply-accumulate at the same time.
  • FIG. 5 shows a schematic structural diagram of a fixed-point universal unit 120 provided by an exemplary embodiment of the present application.
  • the fixed-point general-purpose unit 120 includes: a first multiplier 1, a second multiplier 2, a third multiplier 3 and a fourth multiplier 4, an adder 1, an adder 2, an adder 3, and a fixed-point result selection unit 215.
  • the first input terminal A is divided into a first sub-input terminal A1 and a first sub-input terminal A2, and the second input terminal B is divided into a second sub-input terminal B1 and a second sub-input terminal B2.
  • the upper-level input terminal C is divided into a higher-level sub-input terminal C1 and a higher-level sub-input terminal C2.
  • the input terminals of the first multiplier 1 are respectively connected to the first sub-input terminal A1 and the second sub-input terminal B1; the input terminals of the second multiplier 2 are respectively connected to the first sub-input terminal A2 and the second sub-input terminal B1;
  • the input terminals of the third multiplier 3 are respectively connected to the first sub-input terminal A1 and the second sub-input terminal B2;
  • the input terminals of the fourth multiplier 4 are respectively connected to the first sub-input terminal A2 and the second sub-input terminal B2.
  • the input of the adder 1 is connected to the output of the first multiplier 1 and the output of the second multiplier 2 respectively; the input of the adder 2 is connected to the output of the third multiplier 3 and the output of the fourth multiplier 4 respectively
  • the output terminal is connected; the input terminal of the adder 3 is connected to the output terminal of the adder 1, the output terminal of the adder 4, and the upper sub-input terminal C1; the input terminal of the adder 4 is connected to the output terminal of the adder 1 and the adder, respectively The output terminal of 2, the upper sub-input terminal C2, the first input terminal A, and the second input terminal B are connected.
  • the input terminal of the fixed-point result selection unit 215 is connected to the output terminal of the adder 3 and the output terminal of the adder 4, respectively.
  • the first operand A, the second operand B, and the third operand C are all 16-bit wide operands, and the first sub-input A1 is used to input the first operand A
  • the first sub-input A2 is used to input the first operation The second half of number A [7:0].
  • the second sub-input B1 is used to input the first half of the second operand B [15:8], and the second sub-input B2 is used to input the second half of the second operand B [7:0].
  • the upper sub-input C1 is used to input the first half of the third operand C [15:8], and the upper sub-input C2 is used to input the second half of the third operand C [7:0].
  • the fixed-point general-purpose unit 120 is used to calculate the product between the first operand A and the second operand B, and then add it to the third operand C.
  • FIG. 6 shows a schematic structural diagram of a floating-point dedicated unit 140 provided by an exemplary embodiment of the present application.
  • the floating-point dedicated unit 140 includes a first adder A, a second adder B, a third adder C, and a shift Unit 205, search unit 206, and floating point result output unit 207.
  • the input of the first adder A is connected to the output of the fixed-point universal unit 120 and the upper input C, respectively, and the third input D of the second adder B is connected to the fixed-point output of the fixed-point universal unit 120 and the upper input C,
  • the output terminals of the shift unit 205 are connected respectively, and the input terminal of the third adder C is connected to the output terminal of the fixed-point general-purpose unit 120 and the output terminal of the search unit 206, respectively.
  • the input terminal of the shift unit 205 is connected to the output terminal of the first adder A and the output terminal of the second adder B, respectively, and the input terminal of the search unit 206 is connected to the output terminal of the second adder B and the third adder C
  • the output terminals are respectively connected, and the floating-point result output unit 207 is connected to the output terminal of the second adder B and the output terminal of the search unit 206, respectively.
  • the floating-point dedicated unit 140 When the calculation mode is a floating-point calculation mode, input the first multiplication number from the first input terminal A To the multiply-accumulate module, input the second multiplier from the second input B To the multiply-accumulate module, input the first addition number from the upper input C To the multiply-accumulate module, the floating-point dedicated unit 140 performs floating-point operations.
  • the calculation formula is as follows:
  • This formula is a calculation formula for floating-point results
  • E 1 is the exponent part of the first multiplier
  • E 2 is the exponent part of the second multiplier
  • E 3 is the exponent part of the first addition number
  • S 1 is the sign bit of the first multiplier
  • S 2 is the first The sign bit of the second multiplication number
  • S 3 is the sign bit of the first addition number
  • M 1 is the fractional part of the first multiplication number
  • M 2 is the fractional part of the second multiplication number
  • M 3 is the fractional part of the first addition number
  • Offset is the relative offset value of the exponent caused by the rounding resulting from the calculated decimal result.
  • the integer part of the first/second/third operand is a fixed value
  • the first/second /The integer part of the third operand is removed
  • the integer part of the first/second/third operand needs to be added to the highest bit of the numerical value before the floating point calculation, and the decimal part M is stitched together To get the original first/second/third operand.
  • the exponent part of the first/second/third operand is an encoded value
  • the encoded value of the exponent part of the first/second/third operand needs to be decoded
  • the decoded value is the original exponential part
  • the fractional part of the first/second/third operand includes an integer (including 0)
  • the fractional part M of the first/second/third operand in One decimal place is padded before the decimal part M.
  • the corresponding actual value S*2 E *(0.M) includes the integer part 0; when the value of the exponent part is not 0, the corresponding actual value S* 2
  • the fractional part of E *(1.M) includes the integer part 1; in the above two cases, when calculating the fractional part 0.M and/or 1.M, it is necessary to add one digit before the fractional part M Integer bits, and then perform the operation.
  • the above calculation process is executed by the corresponding calculation unit of the floating point dedicated unit 140.
  • the corresponding calculation execution process is as follows:
  • the fixed-point universal unit 120 is used to convert the first operand
  • the fractional part of S 2 M 2 are multiplied to obtain a first intermediate result S 1 M 1 * S 2 M 2 , outputting a first intermediate result S 1 M 1 * S 2 M 2 from the designated output terminal; wherein the decimal part carries Sign bit; also used to convert the first operand
  • the exponent part E 1 and the second operand E 2 of the index part is added to obtain the first index and E 1 +E 2 ;
  • the first adder A is used to combine the first exponent sum E 1 +E 2 with the third operand
  • the negative value of the exponential part of E 3 is added to obtain the second exponent and E 1 +E 2 -E 3 ;
  • the shift unit is used to obtain the shift object and the shift bit number according to the second exponent and E 1 +E 2 -E 3 , the shift object is the first intermediate result S 1 M 1 *S 2 M 2 or the third operand The fractional part of S 3 M 3 .
  • the shifted object is the first intermediate result S 1 M 1 *S 2 M 2
  • the first intermediate result S 1 M 1 *S 2 M 2 is shifted according to the number of shifted bits to obtain the shifted first intermediate result ;
  • the shifted object is the third operand
  • the decimal part of S 3 M 3 the third operand
  • the fractional part of S 3 M 3 is shifted to obtain the shifted third operand Fractional part of
  • the second adder B is used to shift the shifted first intermediate result S 1 M 1 *S 2 M 2 and the third operand when the shifted object is the first intermediate result S 1 M 1 *S 2 M 2
  • the fractional parts of S 3 M 3 are added; or, when the shifted object is the third operand
  • the fractional part S 3 M 3 , the first intermediate result S 1 M 1 *S 2 M 2 and the shifted third operand Add the fractional parts of to get the decimal sum;
  • the search unit is used to obtain the decimal result S 1 M 1 *S 2 M 2 +S 3 M 3 according to the decimal and the relative offset value of the calculated exponent, and obtain the exponent result of the floating-point result from the third adder C E 1 +E 2 +offset;
  • the third adder C is used to add the relative offset value of the exponent to the sum of the first exponent E 1 +E 2 to obtain the exponent result E 1 +E 2 +offset of the floating-point result;
  • the floating point result output unit 207 is used to determine the sign bit of the floating point result according to the sign bit of the decimal sum; the sign bit of the floating point result, the decimal result S 1 M 1 *S 2 M 2 +S 3 M 3 and the exponent result E 1 +E 2 +offset is spliced together to produce floating-point operation results.
  • the fixed-point general unit 120 when calculating the first intermediate result by the fixed-point general unit 120, please refer to FIG. 5 and convert the first operand The fractional part S 1 M 1 and the second operand
  • the fractional part S 2 M 2 is input to the first multiplier 1 or the second multiplier 2 or the third multiplier 3 or the multiplier 4 through the first input A and the second input B respectively Multiplier 1, or second multiplier 2, or third multiplier 3, or multiplier 4 calculates the first operand
  • the product of the fractional part S 2 M 2 is selected and output to the floating point dedicated unit 140 by the fixed-point result selection unit.
  • the floating-point calculation mode calculates the first operand by the adder 4 in the fixed-point general unit 120 And the second operand The first exponent sum of the exponent part, please refer to Figure 5 and place the first operand The exponential part E 1 and the second operand The exponent part E 2 of the input is input to the adder 4 through the first input terminal A and the second input terminal B respectively, and the first exponent and E 1 +E 2 are calculated by the adder 4.
  • the chip provided in this embodiment is provided with a fixed-point general unit and a floating-point special unit in the multiply-accumulate module.
  • the floating-point special unit is connected to the fixed-point output of the fixed-point general unit, and the fixed-point general unit performs the fixed-point
  • the multiply-accumulate calculation in the calculation mode is completed by the fixed-point general unit and the floating-point special unit in the floating-point calculation mode.
  • the same multiply-accumulate module can realize both fixed-point multiply-accumulate operation and floating-point multiply-accumulate at the same time.
  • FIGS. 4 to 6 provide a multiply-accumulate module that supports both fixed-point operations and floating-point operations.
  • the above-mentioned fixed-point universal unit is also designed as a fixed-point universal unit supporting a scalable design.
  • the same multiply-accumulate operation module can support two high-bit width (such as 16bit) integer multiplication operations, and can also be compatible with multiple sets of lower-bit width (such as 8bit, 4bit, 2bit) integers Multiplication.
  • the same multiply-accumulate module can simultaneously support two features:
  • Table 2 shows the structure diagram of the input signal and output signal in the three calculation modes in this example.
  • the three calculation modes include: a first fixed-point calculation mode (8-bit integer multiply-accumulate operation), a second fixed-point calculation mode (16-bit integer multiply-accumulate operation), and a floating-point calculation mode (16-bit floating-point multiply-accumulate operation).
  • bit number possibilities such as 128bit, 64bit, 32bit, 16bit, 8bit, 4bit, and 2bit may also be used.
  • the multiply-accumulate module 100 When supporting scalable fixed-point operations, the multiply-accumulate module 100 further includes a data reorganizer 180, and the first input terminal A and the second input terminal B are connected to the fixed-point general unit 120 through the data reorganizer 180.
  • the data reorganizer 180 is used to reorganize and/or split the data of the first input terminal A and the second input terminal B.
  • the fixed-point calculation mode includes a first fixed-point calculation mode and a second fixed-point calculation mode.
  • the first fixed-point calculation mode is a fixed-point calculation mode with a low bit width k
  • the second fixed-point calculation mode is a fixed-point calculation mode with a high bit width 2 N
  • m is a divisor of 2 N.
  • the fixed-point general unit 120 is also used to multiply k sets of the first sub-operand A and the second sub-operand B after the calculation mode is the first fixed-point calculation mode with the k third sub-inputs of the upper-level input terminal C Operand C is accumulated separately, and the fixed-point operation result is output from the fixed-point output terminal;
  • the fixed-point general unit 120 is also used to multiply k sets of the fourth sub-operand D and the fifth sub-operand E after the calculation mode is the second fixed-point calculation mode with the k third sub-operations input by the upper-level input terminal C The number C is accumulated separately, and the fixed-point operation result is output from the fixed-point output terminal.
  • the first operand A and the second operand B can be combined into a first sub-operand A 1 and a second sub-operand B 1 , and a first sub-operand A 2 And the second sub-operand B 2 , and then multiply the first sub-operand A 1 /A 2 and the second sub-operand B 1 /B 2 to accumulate with the third sub-operand C 1 /C 2 , Output the result of the above operation from the fixed-point output terminal;
  • the first operand A and the second operand B can be split into a fourth sub-operand D 1 and a fifth sub-operand E 1 , and a fourth sub-operand D 2 And the fifth sub-operand E 2 , and then multiply the fourth sub-operand D 1 /D 2 and the fifth sub-operand E 1 /E 2 to accumulate with the third sub-operand C 1 /C 2 ,
  • the result of the above operation is output from the fixed-point output terminal.
  • the fixed-point general-purpose unit 120 includes a multiplier sub-unit 240, an adder sub-unit 260, and a fixed-point result selection unit 215;
  • the input terminal of the multiplier subunit 240 is connected to the data reorganizer 180, the input terminal of the adder subunit 260 is connected to the output terminal of the multiplier subunit 240 and the upper-level input terminal C, and the input terminal of the fixed-point result selection unit 215 is connected to the addition
  • the output terminal of the sub-unit 260 is connected, and the output terminal of the fixed-point result selection unit 215 is connected to the output selection unit 160.
  • the floating-point dedicated unit 140 includes a floating-point adder subunit 220, a shift unit 205, a search unit 206, and a floating-point result output unit 207;
  • the input terminal of the floating-point adder subunit 220 is connected to the data reassembler 180, the upper-level input terminal C, the output terminal of the adder subunit 260, the shift unit 205, and the search unit 206, respectively.
  • the output of the point adder subunit 220 is connected, the input of the search unit 206 is connected to the output of the floating-point adder subunit 220, and the floating-point result output unit 207 is connected to the input of the output of the floating-point adder subunit 220 Connected, the output of the floating-point result output unit 207 is connected to the output selection unit 160.
  • the data reorganizer 180 includes k groups of reorganization output terminals.
  • the i-th group of reorganization output terminals in the k groups of reorganization output terminals includes a first reorganization output terminal A i and a second reorganization output terminal B i ;
  • the fixed-point general unit includes Multipliers and Adders, h is the minimum value of the second bit width, h and X are positive integers;
  • the first input of the jth multiplier of the multipliers is connected to the first recombination output Af of the fth reorganization output, and the second input of the jth multiplier is recombined with the tth group
  • the jth multiplier is used to multiply the f-th sub-operand A f /D f of the first operand A with the t-th sub-operand B t /E t of the second operand B .
  • the data reorganizer 180 includes two groups of reorganization output terminals.
  • the two groups of reorganization output terminals include a first group of reorganization output terminals A 1 and a second group of reorganization output terminals B 1 , and a second group of reorganization output terminals.
  • the first recombination output A 2 and the second recombination output B 2 ; at this time, the fixed-point general unit 120 includes 4 multipliers and 4 adders. As shown in FIG.
  • the multiplier sub-unit 240 includes the first multiplier 1, The second multiplier 2, the third multiplier 3, and the fourth multiplier 4, and the adder subunit 260 include a fourth adder 1, a fifth adder 2, a sixth adder 3, and a seventh adder 4.
  • the structure of the fixed-point universal unit 120 is shown in FIG. 7, and the upper-level input terminal includes a first input terminal C 1 and a second input terminal C 2 ;
  • the input terminal of the first multiplier 1 is connected to the output terminal A 1 of the first recombination unit and the second output terminal B 1 respectively, and the input terminal of the second multiplier 2 is connected to the first recombination output terminal A 2 and the second recombination output terminal B 1 is connected respectively, the input terminal of the third multiplier 3 is connected to the first recombination output terminal A 1 and the second recombination output terminal B 2 respectively, and the input terminal of the fourth multiplier 4 is connected to the first recombination output terminal A 2 and the second The two recombination outputs B 2 are connected separately;
  • the input of the fourth adder 1 is connected to the output of the first multiplier 1 and the output of the second multiplier 2, respectively, the input of the fifth adder 2 and the output of the third multiplier 3, the fourth The outputs of the multiplier 4 are connected; the input of the sixth adder 3 is connected to the output of the fourth adder 1, the output of the fifth adder 4, and the first input C 1 ; the input of the adder 4 The terminal is connected to the output terminal of the adder 1, the output terminal of the adder 2, the second input terminal C 2 , the first input terminal A, and the second input terminal respectively;
  • the input terminal of the fixed-point result selection unit is connected to the output terminal of the adder 3 and the output terminal of the adder 4, respectively.
  • the third operand C input by the upper-level input terminal C includes a third sub-operand C 1 and a third sub-operand C 2 ;
  • the first multiplier 1 is used to multiply the data output by the first recombination output terminal A 1 and the data output by the second recombination output terminal B 1 to obtain a first product;
  • the second multiplier 2 Used to multiply the data output by the first recombination output A 2 and the data output by the second recombination output B 1 to obtain a second product;
  • the third multiplier 3 is used to output the first recombination output A 1
  • the data is multiplied by the data output from the second recombination output B 2 to obtain a third product;
  • the fourth multiplier 4 is used to multiply the data output from the first recombination output A 2 and the data output from the second recombination output B 2 Multiply to get the fourth product;
  • the fourth adder 1 is used to add the first product and the second product to obtain the first addition sum
  • the fifth adder 2 is used to add the third product and the fourth product to obtain the second addition sum
  • Six adder 3 is used to accumulate the first addition sum, the third sub-operand C 1 and the carry value of the adder 4 to obtain the third addition sum
  • the adder 4 is used to add the first addition sum and the second addition Sum and the third sub-operand C 2 accumulate to get the fourth addition sum;
  • the fixed-point result selection unit 215 is used to splice the third addition sum with the fourth addition sum to obtain a fixed-point operation result.
  • the first multiplier 1 is used to multiply the data output by the first recombination output terminal A 1 and the data output by the second recombination output terminal B 1 to obtain a first product;
  • the fourth multiplier 4 Used to multiply the data output by the first recombination output terminal A 2 and the data output by the second recombination output terminal B 2 to obtain a fourth product;
  • the fourth adder 3 is used to accumulate the first product and the third sub-operand C 1 to obtain a fifth addition sum;
  • the seventh adder 4 is used to accumulate the fourth product and the third sub-operand C 2 , Get the sixth addition sum;
  • the fixed-point result selection unit 215 is configured to join the fifth addition sum and the sixth addition sum to obtain a fixed-point output result.
  • the chip provided by this embodiment including the multiply-accumulate module is provided with a fixed-point general unit and a floating-point special unit in the multiply-accumulate module.
  • the floating-point special unit is connected to the fixed-point output of the fixed-point general unit and is used by the fixed-point general-purpose unit. Unit to complete the multiply-accumulate calculation in fixed-point calculation mode.
  • the fixed-point general unit and the floating-point special unit cooperate to complete the multiply-accumulate calculation in floating-point calculation mode.
  • the same multiply-accumulate module can realize both fixed-point multiply-accumulate operation and floating point.
  • Multiply-accumulate two operations because the fixed-point arithmetic unit and floating-point arithmetic unit are integrated in a circuit, and some devices share, reducing the total number of devices used, thereby reducing the occupied area of the fixed-point arithmetic unit and floating-point arithmetic unit on the chip, And reduce the power consumption of the chip in the multiply-accumulate operation.
  • the above multiply-accumulate module uses 4 multipliers and 7 adders.
  • 10 multipliers and 12 Adder comparison When implementing the above two fixed-point calculation modes and a floating-point calculation mode in the related technical solutions, 10 multipliers and 12 Adder comparison, reducing 5 adders and 6 multipliers.
  • any of the aforementioned multiply-accumulate modules may be applied to a neural network chip, as shown in FIG. 8, which is a schematic diagram of a chip structure including a neural network model provided by an exemplary embodiment.
  • the chip includes several pulsation arrays, and each pulsation array includes X*Y multiplying and accumulating modules;
  • the module output terminal of the multiply-accumulate module in row i, column j is connected to the upper-level input terminal of the multiply-accumulate module in column i+1, row j;
  • the module output terminal of the multiply-accumulate module in row i, column j is connected to the upper-level input terminal of the multiply-accumulate module in row i, column j+1.
  • the input end of the multiply-accumulate module in row i and column j of at least one pulsation array in the pulsation array is connected to the application layer, and the output end of the multiply-accumulate module in row p and row q of the pulsation array is connected to the application layer ;
  • the output terminal of the multiply-accumulate module in the pth row and the qth column of at least one pulsation array is the output terminal of the fixed-point result or floating-point result, and i, j, p, and q are positive integers.
  • the chip includes a 16*16 pulsation array, where the upper input of the multiply-accumulate module in row 3 and column 2 of the pulsation array and the module output of the multiply-accumulate module in row 2 and column 2 of the pulsation array
  • the upper input of the multiply-accumulate module in the third row and second column of the pulse array can also be connected to the module output of the multiply-accumulate module in the third row and first column of the pulse array.
  • the chip includes the neural network model including interface unit a, on-chip data storage array b, preprocessing engine c, convolution/matrix operation engine d, on-chip instruction storage h, execution unit g, control unit f and Other engines e.
  • the convolution/matrix operation engine d is composed of N layers of multiply-accumulate modules, and each layer includes at least one multiply-accumulate module, and N is a positive integer.
  • the input end of the on-chip data storage array b of the neural network chip is connected to the interface unit a, the preprocessing engine c, the convolution/matrix operation engine d and other engines e, and the output end is connected to the preprocessing engine c and the convolution/matrix operation engine d and other engines e; the input terminals of the preprocessing engine c, the convolution/matrix calculation engine d and the other engines e are respectively connected to the control unit f; the input terminal of the control unit f is connected to the output terminal of the execution unit g; the execution unit g The input end of is connected to the output end of the on-chip instruction storage h; the input end of the on-chip instruction storage h is connected to the output end of the interface unit a.
  • Interface unit a used for data input; on-chip data storage array b, used for temporary storage of intermediate results; preprocessing engine c, used for data preprocessing; convolution/matrix operation engine d, used for data operation; On-chip instruction storage h is used to store instructions; execution unit g is used to load and execute instructions; control unit f is used to control the processing of data by the engine; other engines e are used to perform other operations.
  • the above-mentioned multiply-accumulate module is integrated on a chip, and the above-mentioned chip is any one of CPU, GPU, FPGA, ASIC, or other AI chips.
  • FIG. 9 is a flowchart of a control method provided by an exemplary embodiment of the present application. The method is applied to any of the chips shown in FIG. 4 to FIG. 8 above.
  • the chip includes a multiply-accumulate module.
  • the method includes:
  • Step 301 Receive a first control signal.
  • the multiply-accumulate module includes a mode selection terminal, which is used to select a fixed-point calculation mode or a floating-point calculation mode.
  • the multiply-accumulate module receives the first control signal through the mode selection terminal, and the first control signal includes calculation mode information.
  • the first control signal is represented by a two-digit binary number, "00" is used to indicate the fixed-point calculation mode, and "10" is used to indicate the floating-point calculation mode.
  • step 302 the multiply-accumulate module in the control chip is in a corresponding calculation mode according to the first control signal.
  • the multiply-accumulate module includes a fixed-point general-purpose unit and a floating-point special unit; the multiply-accumulate module turns on the circuit of the fixed-point general-purpose unit or the floating-point special unit according to the calculation mode information in the first control signal.
  • the multiply-accumulate module When the circuit of the fixed-point general unit is on, the multiply-accumulate module is in fixed-point calculation mode; when the circuit of the floating-point special unit is on, the multiply-accumulate module is in floating-point calculation mode.
  • step 303 When the multiply-accumulate module is in the fixed-point calculation mode, step 303 is executed; when the multiply-accumulate module is in the floating-point calculation mode, step 305 is executed.
  • the binary "00” indicates the fixed-point calculation mode
  • the binary "10” indicates the floating-point calculation mode
  • the first control signal is "00”
  • the corresponding circuit in the multiply-accumulate module of the fixed-point calculation mode is turned on and executed Step 303
  • the first control signal is "10”
  • the corresponding circuit of the floating point calculation mode in the multiply-accumulate module is turned on, and step 305 is executed.
  • Step 303 when the calculation mode is in the fixed-point calculation mode, the first operand A and the second operand B are multiplied.
  • the multiply-accumulate module includes a first input terminal and a second input terminal to input the multiplication number, and a superior input terminal to input the addition number.
  • the multiply-accumulate module multiplies the first operand A input from the first input terminal and the second operand B input from the second input terminal through a multiplier.
  • Step 304 Accumulate the third operand C of the calculation result of the superior multiply-accumulate module to obtain and output the fixed-point operation result.
  • the multiply-accumulate module accumulates the product of the first operand A and the second operand B and the third operand C input from the upper-level input terminal through an adder to obtain the result of fixed-point operation; the fixed-point operation result is the final operation result, Output fixed-point operation results.
  • Step 305 when the calculation mode is in the floating-point calculation mode, the first operand A and the second operand B are subjected to the calculation of the multiplication part in the floating-point operation to obtain the first intermediate result.
  • the floating-point dedicated unit and the fixed-point general-purpose unit share a multiplier.
  • the multiply-accumulate module compares the fractional part of the first operand A and the second operand B through the multiplier in the fixed-point general-purpose unit Multiply and calculate to get the first intermediate result.
  • step 306 the first operand A, the second operand B, the third operand C, and the first intermediate result are subjected to the addition part of the floating-point operation, and the floating-point operation result is output.
  • the multiply-accumulate module adds the exponent parts of the first operand A, the second operand B, and the third operand C through the adder in the floating-point dedicated unit, and the decimal part of the third operand C and the first The intermediate result is added; the floating-point result output unit of the multiply-accumulate module combines the results of the addition operation of the exponent part and the decimal part to obtain and output the floating-point operation result.
  • the control method provided in this embodiment receives the first control signal; according to the first control signal, the multiply-accumulate module in the control chip is in the corresponding calculation mode; when the calculation mode of the multiply-accumulate module is in the fixed-point calculation mode At this time, fixed-point operation is performed. When the calculation mode of the multiply-accumulate module is in floating-point calculation mode, floating-point operation is performed.
  • This method realizes the compatibility of fixed-point operation and floating-point operation in a circuit. Since the fixed-point operation unit and floating-point operation unit are integrated in a circuit, the multiplier is shared, reducing the total number of devices used, thereby reducing the fixed-point operation unit and The area occupied by the floating-point arithmetic unit on the chip and the power consumption during the calculation.
  • the floating-point dedicated unit 140 performs floating-point operations.
  • the calculation formula is as follows:
  • This formula is a calculation formula for floating-point results
  • E 1 is the exponent part of the first multiplier
  • E 2 is the exponent part of the second multiplier
  • E 3 is the exponent part of the first addition number
  • S 1 is the sign bit of the first multiplier
  • S 2 is the first
  • S 3 is the sign bit of the first addition number
  • M 1 is the fractional part of the first multiplication number
  • M 2 is the fractional part of the second multiplication number
  • M 3 is the fractional part of the first addition number
  • Offset is the relative offset value of the exponent caused by the rounding resulting from the calculated decimal result.
  • step 305 to step 306 in FIG. 9 with step 3061 to step 3069 to describe in detail when the calculation mode is a floating-point calculation mode.
  • the steps are as follows:
  • Step 3061 Multiply the fractional part of the first operand A and the fractional part of the second operand B to obtain the first intermediate result.
  • the first operand A is the first multiplication number
  • the second operand B is the second multiplication number
  • the third operand C is the first addition number
  • the floating-point dedicated unit and the fixed-point general-purpose unit share a multiplier, and the multiply-accumulate module converts the first operand through the multiplier of the fixed-point general-purpose unit The fractional part S 1 M 1 and the second operand The fractional part of S 2 M 2 is multiplied to obtain the first intermediate result S 1 M 1 *S 2 M 2 .
  • Step 3062 Add the exponent part of the first operand A and the exponent part of the second operand B to obtain the first exponent sum.
  • the multiply-accumulate module also converts the first operand through the adder in the fixed-point universal unit The exponent part E 1 and the second operand The exponential part of E 2 is added to obtain the first exponent and E 1 +E 2 .
  • Step 3063 The first exponent sum is added to the negative value of the exponent part of the third operand C to obtain a second exponent sum.
  • the multiply-accumulate module combines the first exponent sum E 1 +E 2 with the first addition number through the adder in the floating-point dedicated unit The negative value of the exponential part of -E 3 is added to obtain the second exponent and E 1 +E 2 -E 3 .
  • Step 3064 Obtain the shift object and the number of shift bits according to the second exponent sum.
  • the shift object is the first intermediate result or the fractional part of the third operand C.
  • the multiply-accumulate module performs data processing on the second exponent and E 1 +E 2 -E 3 through the shift unit to obtain the shift object and the shift bit number of the shift object.
  • Step 3065 Shift the first intermediate result according to the shifted number of bits to obtain the shifted first intermediate result, or shift the fractional part of the third operand C according to the shifted number of bits to obtain the shifted third The fractional part of operand C.
  • the shifted object is the first intermediate result S 1 M 1 *S 2 M 2
  • the first intermediate result S 1 M 1 *S 2 M 2 is shifted according to the number of shifted bits to obtain the shifted first intermediate result ;
  • the shifted object is the third operand
  • the decimal part of S 3 M 3 the third operand The fractional part of S 3 M 3 is shifted to obtain the shifted third operand The decimal part.
  • Step 3066 Add the shifted first intermediate result to the fractional part of the third operand C, or add the first intermediate result to the fractional part of the shifted third operand C to obtain the decimal sum .
  • the shifted object is the first intermediate result S 1 M 1 *S 2 M 2
  • the shifted first intermediate result S 1 M 1 *S 2 M 2 and the third operand The fractional parts of S 3 M 3 are added; or, when the shifted object is the third operand
  • the fractional part S 3 M 3 , the first intermediate result S 1 M 1 *S 2 M 2 and the shifted third operand Add the fractional parts of to get the decimal sum.
  • Step 3067 According to the decimal sum, obtain the decimal place result, the sign bit of the floating point result, and calculate the relative offset value of the exponent.
  • the decimal result S 1 M 1 *S 2 M 2 +S 3 M 3 and the relative offset value of the exponent are calculated and calculated.
  • the multiply-accumulate module processes the decimal sum through the search unit to obtain the relative offset value offset of the decimal result and the exponent; obtains the sign bit of the decimal sum as the sign bit of the floating point result through the floating-point result output unit.
  • Step 3068 Add the relative offset value to the first exponent sum to obtain the exponent result of the floating-point result.
  • the multiply-accumulate module adds the relative offset value of the exponent to the first exponent and adds E 1 +E 2 through the adder to obtain the exponent result of the floating-point result, and updates the added result to the exponent result through the search unit To get the exponent result E 1 +E 2 +offset of the final floating point result.
  • step 3069 the sign bit, decimal result, and exponent result of the floating-point result are stitched together to obtain a floating-point result.
  • the multiply-accumulate module stitches together the sign bit, decimal result and exponent result of the floating-point result through the floating-point result output unit to obtain a floating-point result.
  • the control method provided in this embodiment receives the first control signal; according to the first control signal, the multiply-accumulate module in the control chip is in the corresponding calculation mode; when the calculation mode of the multiply-accumulate module is in the fixed-point calculation mode At this time, fixed-point operation is performed. When the calculation mode of the multiply-accumulate module is in floating-point calculation mode, floating-point operation is performed.
  • This method realizes the compatibility of fixed-point operation and floating-point operation in a circuit. Since the fixed-point operation unit and floating-point operation unit are integrated in a circuit, the multiplier is shared, reducing the total number of devices used, thereby reducing the fixed-point operation unit and The area occupied by the floating-point arithmetic unit on the chip and the power consumption during the calculation.
  • the fixed-point calculation mode includes the first fixed-point calculation mode and the second fixed-point calculation mode.
  • the first fixed-point calculation mode is an 8-bit wide fixed-point calculation mode
  • the second fixed-point calculation mode is a 16-bit wide fixed-point calculation mode as an example:
  • Step 401 Receive a first control signal.
  • the multiply-accumulate module includes a mode selection end, and the mode selection end is used to select the calculation mode of the multiply-accumulate module as a first fixed-point calculation mode, a second fixed-point calculation mode, or a floating-point calculation mode.
  • the multiply-accumulate module receives the first control signal through the mode selection terminal, and the first control signal includes calculation mode information.
  • the first control signal is represented by a two-digit binary number, with "00" representing the first fixed-point calculation mode, "01" representing the second fixed-point calculation mode, and "10" representing the floating-point calculation mode.
  • Step 402 According to the first control signal, control the multiply-accumulate module in the chip to be in the corresponding calculation mode.
  • the multiply-accumulate module includes a fixed-point general-purpose unit and a floating-point special unit; the multiply-accumulate module turns on the circuit of the fixed-point general-purpose unit or the floating-point special unit according to the calculation mode information in the first control signal.
  • the multiply-accumulate module When the circuit of the fixed-point general unit is on, the multiply-accumulate module is in fixed-point calculation mode; when the circuit of the floating-point special unit is on, the multiply-accumulate module is in floating-point calculation mode.
  • the selection of the calculation mode of the multiply-accumulate module is determined according to the needs of the program running of the application layer of the electronic device.
  • step 403 when the calculation mode is in the floating-point calculation mode, the first operand A and the second operand B are subjected to the calculation of the multiplication part in the floating-point operation to obtain the first intermediate result.
  • Step 404 Perform the addition part of the floating-point operation on the first operand A, the second operand B, the third operand C, and the first intermediate result, and then output the floating-point operation result.
  • Step 405 When the calculation mode is the first fixed-point calculation mode, multiply m sets of the first sub-operand A and the second sub-operand B.
  • One sub-operand A is multiplied with the second sub-operand B, and m and N are positive integers.
  • Step 406 accumulate with the m third sub-operands C input from the upper-level input end respectively, and output the fixed-point operation result from the fixed-point output end.
  • the multiply-accumulate module accumulates the result of multiplying the m sets of the first sub-operand A and the second sub-operand B by the adder with the m third sub-operands C input by the upper-level input terminal, and finally obtains the fixed-point operation result. And output fixed-point operation results through the fixed-point result selection unit.
  • the third operand C includes the third sub-operand C 1 and the third sub-operand C 2 ;
  • the calculation mode is the first fixed-point calculation mode, the first operand A is reorganized Includes the first sub-operand A 1 and the first sub-operand A 2 , and the second operand B after reorganization includes the second sub-operand B 1 and the second sub-operand B 2 ;
  • the operation process from step 405 to step 406 details as follows:
  • the multiply-accumulate module multiplies the first sub-operand A 1 and the second sub-operand B 1 by the first multiplier 1 to obtain the first product; the first sub-operand A 2 and the second by the fourth multiplier 4 Multiply the sub-operand B 2 to obtain the fourth product; accumulate the first product and the third sub-operand C 1 through the fourth adder 1 to obtain the fifth addition sum; sum the fourth product through the seventh adder 4
  • the third sub-operand C 2 is accumulated to obtain the sixth addition sum; the fifth addition sum and the sixth addition sum are spliced together by a fixed-point result selection unit to obtain a fixed-point operation result, and the fixed-point operation result is output.
  • the data bit width of the operand in the second fixed-point calculation mode is 16 bits, and m is 2, and the data bit width of the operand in the first fixed-point calculation mode is 8 bits.
  • Multiplier 1 multiplies the upper 8 bits of data 11 and the upper 8 bits of data 22 to obtain the first product "data 1*data 2" with a bit width of 16 bits; multiplier 4 multiplies the lower 8 bits of data 11 and the data 22 Multiply the lower 8 bits to get the second product "Data 1*Data 2" with a bit width of 16 bits;
  • Adder 1 accumulates the first product and the upper 24 bits of data 5 to obtain the fifth addition of 24 bits and "(data 1 * data 2) + upper 24 bits of data 5"; adder 3 adds the fourth product and data 5 The lower 24 bits of the total are added to get the sixth addition of 24 bits and "(data 1 * data 2) + lower 24 bits of data 5";
  • the fixed-point selection unit concatenates the fifth addition sum and the sixth addition sum to the upper 24 bits and the lower 24 bits, respectively, to obtain a 48-bit fixed-point operation result, and output the above-mentioned fixed-point operation result.
  • SIZE 16; the bit width of the operand is 16bit;
  • SUB_PART_SIZE 8; the bit width of the sub-operand is 8 bits;
  • SUB_PART_NUMBER SIZE/SUB_PART_SIZE; the number of groups is the operand bit width is 16bit/sub-operand bit width is 8bit, divided into 2 groups;
  • SUB_PART_H RANGE(SIZE_PART_NUMBER*SUB_PART_SIZE-1, SUB_PART_SIZE); the upper 8 bits are [15:8];
  • SUB_PART_L RANGE (SUB_PART_SIZE-1,0); the lower 8 bits are [7:0];
  • A1 unpack(A, SUB_PART_H); A1 is the upper 8 bits;
  • A0 unpack(A, SUB_PART_L); A0 is the lower 8 bits;
  • B1 unpack (B, SUB_PART_H); B1 is the upper 8 bits;
  • B0 unpack(B, SUB_PART_L); B0 is the lower 8 bits;
  • C1 C_IN_H; C1 is the upper 24 bits;
  • C0 C_IN_L; C0 is the lower 24 bits;
  • C_OUT_H A1*B1+C_IN_H; C_OUT_H is the calculation result of the upper 24 bits;
  • C_OUT_L A0*B0+C_IN_L; C_OUT_L is the calculation result of the lower 24 bits.
  • step 407 when the calculation mode is the second fixed-point calculation mode, m sets of the fourth sub-operand D and the fifth sub-operand E are multiplied.
  • the data reorganizer in the multiply-accumulate module splits the first operand A and the second operand B into m groups of fourth sub-operands D and fifth sub-operands E,
  • the bit width of the fourth/fifth sub-operand k the second bit width of the fourth/fifth operand 2 N /m; m groups of the fourth sub-operand D and the fifth sub-operand are multiplied E is multiplied.
  • Step 408 Accumulate the m third sub-operands C input from the upper-level input terminal respectively, and output the fixed-point operation result from the fixed-point output terminal.
  • the multiply-accumulate module accumulates the result of multiplying the above m sets of the fourth sub-operand D and the fifth sub-operand E with the m third sub-operands C input by the upper-level input through an adder, and finally obtains the fixed-point operation result, And output fixed-point operation results through the fixed-point result selection unit.
  • the third operand C includes the third sub-operand C 1 and the third sub-operand C 2 ;
  • the first operand A is split Includes the fourth sub-operand D 1 and the fourth sub-operand D 2 , and the second operand B is split into the fifth sub-operand E 1 and the fifth sub-operand E 2 ; the operations from step 407 to step 408
  • the process is as follows:
  • the multiply-accumulate module multiplies the fourth sub-operand D 1 and the fifth sub-operand E 1 by the first multiplier 1 to obtain the first product; the fourth sub-operand D 2 and the fifth by the second multiplier 2 Multiply the sub-operand E 1 to obtain the second product; multiply the fourth sub-operand D 1 and the fifth sub-operand E 2 by the third multiplier 3 to obtain the third product; Multiply the fourth sub-operand D 2 and the fifth sub-operand E 2 to obtain the fourth product;
  • the first product and the second product are accumulated by the fourth adder 1 to obtain the first addition sum; the third product and the fourth product are added by the fifth adder 2 to obtain the second addition sum; the sixth adder is obtained 3
  • the first addition sum, the second addition sum, the third sub-operand C 1 , and the carry value of the adder 4 are accumulated to obtain the third addition sum; the first addition sum and the second addition sum are obtained through the seventh adder 4 3.
  • the third sub-operand C 2 is accumulated to obtain a fourth addition sum; the third addition sum and the fourth addition sum are spliced together by a fixed-point result selection unit to obtain a fixed-point operation result.
  • the data bit width of the operand in the second fixed-point calculation mode is 16 bits, and m is 2; the 16-bit operands 3 and 16 bit operations are input at the first input terminal and the second input terminal.
  • Number 4, 48-bit data 3 is input to the upper-level input; after the data 1 is split by the data reorganizer, the data 1 is split into an 8-bit data 31 and an 8-bit data 32, and the above data 31 is the upper 8 bits of data 3 3.
  • Data 32 is the lower 8 bits of data 3.
  • data 4 is split into an 8-bit data 41 and an 8-bit data 42.
  • the above data 41 is the upper 8 bits of data 4
  • the data 42 is the lower 8 of data 4.
  • Bits; data 5 is split into high 24 bits and low 24 bits;
  • Multiplier 1 multiplies data 31 and data 41 to get the first product “data 31*data 41” with a bit width of 16 bits; multiplier 2 multiplies data 32 and data 41 to get the second product with a bit width of 16 bits “data 32*Data 41”; the multiplier 3 multiplies the data 31 and the data 42 to obtain the third product "data 31*data 42” with a bit width of 16 bits; the multiplier 4 multiplies the data 32 and the data 42 to obtain a bit width of 16 bits The fourth product "data 32 * data 42";
  • the adder 1 accumulates the first product "Data 31*Data 41” and the second product "Data 32*Data 41” to obtain a first adder with a bit width of 24 bits and "Data 31*Data 41+Data 32*Data 41";
  • the adder 2 adds the third product "Data 31*Data 42” and the fourth product "Data 32*Data 42” to obtain a second adder with a bit width of 16 bits and "Data 31*Data 42+Data 32*Data 42"
  • the adder 3 accumulates the high-order 8 bits of the first add-up, the high-order 24 bits of the data 5, and the carry value of the adder 4 to obtain a third add-up with a bit width of 24 bits.
  • the adder 4 reduces the first add-up by 16 Bits, the second addition sum, and the lower 24 bits of data 5 are accumulated to obtain the fourth addition sum with a bit width of 24 bits "(Data 31*Data 42+Data 32*Data 42)+(Data 31*Data 41+Data 32*Data 41 )+Lower 24 bits of data 5”, the third addition of 24 bits wide and the fixed-point result selection unit are spliced together to output the fixed-point operation result of 48 bits wide.
  • SIZE 16; the bit width of the operand is 16bit;
  • SUB_PART_SIZE 8; the bit width of the sub-operand is 8 bits;
  • SUB_PART_NUMBER SIZE/SUB_PART_SIZE; the number of groups is the operand bit width is 16bit/sub-operand bit width is 8bit, divided into 2 groups;
  • SUB_PART_H RANGE(SIZE_PART_NUMBER*SUB_PART_SIZE-1, SUB_PART_SIZE); the upper 8 bits are [15:8];
  • SUB_PART_L RANGE (SUB_PART_SIZE-1,0); the lower 8 bits are [7:0];
  • A1 unpack(A, SUB_PART_H); A1 is the upper 8 bits;
  • A0 unpack(A, SUB_PART_L); A0 is the lower 8 bits;
  • B1 unpack (B, SUB_PART_H); B1 is the upper 8 bits;
  • B0 unpack(B, SUB_PART_L); B0 is the lower 8 bits;
  • C1 C_IN_H; C1 is the upper 24 bits;
  • C0 C_IN_L; C0 is the lower 24 bits;
  • ADD1 shift(A1*B1, SUB_PART)+A0B1; the first addition sum of the first product and the second product;
  • ADD2 shift(A1*B0, SUB_PART)+A0B0; the second addition sum of the third product and the fourth product;
  • ADD3 C_IN_L+ADD2+ADD1_L; the first addition sum, the second addition sum, and the fourth addition sum of the lower 24 bits of the superior addition number;
  • ADD4 carry(ADD3)+ADD1_H+C_IN_H; the first addition sum, the upper 24 bits of the higher-order addition number, the third addition sum of the carry value of the third addition sum;
  • the control method provided in this embodiment receives the first control signal; according to the first control signal, the multiply-accumulate module in the control chip is in the corresponding calculation mode; when the calculation mode of the multiply-accumulate module is in the fixed-point calculation mode At this time, fixed-point operation is performed. When the calculation mode of the multiply-accumulate module is in floating-point calculation mode, floating-point operation is performed.
  • This method realizes the compatibility of fixed-point operation and floating-point operation in a circuit. Since the fixed-point operation unit and floating-point operation unit are integrated in a circuit, the multiplier is shared, reducing the total number of devices used, thereby reducing the fixed-point operation unit and The area occupied by the floating-point arithmetic unit on the chip and the power consumption during the calculation.
  • the control method provided in this embodiment also supports multiple sets of lower-width integer multiplication operations while supporting two high-bit width integer multiplication operations in one circuit, reducing the number of circuits that simultaneously support integer multiplication operations of different bit widths The total number of devices used in this reduces the area occupied by the fixed-point arithmetic unit on the chip and the power consumption during the calculation.
  • FIG. 14 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device is used to implement the control method provided in the above embodiments.
  • the electronic device includes at least one of a smart phone, a server, an Internet of Things (IoT) device, a cloud server, and an end-side device, specifically:
  • IoT Internet of Things
  • the electronic device 500 may include an RF (Radio Frequency) circuit 510, a memory 520 including one or more computer-readable storage media, an input unit 530, a display unit 540, a sensor 550, an audio circuit 560, WiFi (wireless fidelity, Wireless fidelity) module 570, including a processor 580 with one or more processing cores, and a power supply 590 and other components.
  • RF Radio Frequency
  • the RF circuit 510 can be used to receive and send signals during the transmission and reception of information or during a call. In particular, after receiving the downlink information of the base station, it is handed over to one or more processors 580; in addition, the data related to the uplink is sent to the base station .
  • the RF circuit 510 includes but is not limited to an antenna, at least one amplifier, a tuner, one or more oscillators, a subscriber identity module (SIM) card, a transceiver, a coupler, and an LNA (Low Noise Amplifier) , Duplexer, etc.
  • SIM subscriber identity module
  • the RF circuit 510 can also communicate with the network and other devices through wireless communication.
  • the wireless communication can use any communication standard or protocol, including but not limited to GSM (Global System of Mobile), GPRS (General Packet Radio Service), CDMA (Code Division Multiple Access) , Code division multiple access), WCDMA (Wideband Code Division Multiple Access, broadband code division multiple access), LTE (Long Term Evolution), email, SMS (Short Messaging Service, short message service), etc.
  • GSM Global System of Mobile
  • GPRS General Packet Radio Service
  • CDMA Code Division Multiple Access
  • Code division multiple access Code division multiple access
  • WCDMA Wideband Code Division Multiple Access
  • broadband code division multiple access LTE (Long Term Evolution)
  • email Short Messaging Service, short message service
  • the memory 520 may be used to store software programs and modules.
  • the processor 580 runs the software programs and modules stored in the memory 520 to execute various functional applications and data processing.
  • the memory 520 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the storage data area may store Data created by the use of the electronic device 500 (such as audio data, phone book, etc.), etc.
  • the memory 520 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.
  • the memory 520 may also include a memory controller to provide access to the memory 520 by the processor 580 and the input unit 530.
  • the input unit 530 may be used to receive input digital or character information, and generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control.
  • the input unit 530 may include an image input device 531 and other input devices 532.
  • the image input device 531 may be a camera or a photoelectric scanning device.
  • the input unit 530 may include other input devices 532.
  • other input devices 532 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), trackball, mouse, joystick, and so on.
  • the display unit 540 may be used to display information input by the user or provided to the user and various graphical user interfaces of the electronic device 500. These graphical user interfaces may be composed of graphics, text, icons, videos, and any combination thereof.
  • the display unit 540 may include a display panel 541.
  • the display panel 541 may be configured in the form of an LCD (Liquid Crystal), an OLED (Organic Light-Emitting Diode), or the like.
  • the electronic device 500 may further include at least one sensor 550, such as a light sensor, a motion sensor, and other sensors.
  • the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 541 according to the brightness of the ambient light, and the proximity sensor may close the display panel 541 when the electronic device 500 moves to the ear And/or backlight.
  • the gravity acceleration sensor can detect the magnitude of acceleration in various directions (generally three axes), and can detect the magnitude and direction of gravity when at rest, and can be used to identify mobile phone gesture applications (such as horizontal and vertical screen switching, related Games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tap), etc.
  • other sensors such as gyroscope, barometer, hygrometer, thermometer, infrared sensor, etc. can also be configured here No longer.
  • the audio circuit 560, the speaker 561, and the microphone 562 may provide an audio interface between the user and the electronic device 500.
  • the audio circuit 560 can transmit the received electrical signals into audio speakers 561, and the speakers 561 are converted into sound signals for output; on the other hand, the microphone 562 converts the collected sound signals into electrical signals, and the audio circuit 560 After receiving, it is converted into audio data, and then processed by the audio data output processor 580, and then sent to another electronic device through the RF circuit 510, or the audio data is output to the memory 520 for further processing.
  • the audio circuit 560 may further include an earplug jack to provide communication between the peripheral earphone and the electronic device 500.
  • WiFi is a short-distance wireless transmission technology.
  • the electronic device 500 can help users send and receive emails, browse web pages, and access streaming media through the WiFi module 570. It provides users with wireless broadband Internet access.
  • FIG. 14 shows the WiFi module 570, it can be understood that it is not a necessary component of the electronic device 500, and can be omitted without changing the scope of the essence of the invention as needed.
  • the processor 580 is the control center of the electronic device 500, uses various interfaces and lines to connect various parts of the entire mobile phone, runs or executes software programs and/or modules stored in the memory 520, and calls data stored in the memory 520 , Perform various functions and process data of the electronic device 500, so as to monitor the mobile phone as a whole.
  • the processor 580 may include one or more processing cores; preferably, the processor 580 may integrate an application processor and a modem processor, where the application processor mainly processes an operating system, a user interface, and application programs, etc.
  • the modem processor mainly handles wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 580.
  • the electronic device 500 further includes a chip 582 including a multiply-accumulate module as shown in any of FIGS. 4 to 8 described above.
  • the chip 582 including the multiply-accumulate module may implement the control method as provided in the above embodiment.
  • FIG. 14 shows a connection method of the chip 582 including the multiply-accumulate module in the electronic device 500, but the connection method of the chip 582 including the multiply-accumulate module in the electronic device 500 is not limited to the above method, but can also be connected with The functions that need to be implemented make adaptive connections. For example, when a chip 582 including a multiply-accumulate module is required to complete image processing, it can be directly connected to the image input device 531.
  • the electronic device 500 further includes a power supply 590 (such as a battery) that supplies power to various components.
  • a power supply 590 (such as a battery) that supplies power to various components.
  • the power supply can be logically connected to the processor 580 through the power management system, so as to realize functions such as charging, discharging, and power management through the power management system .
  • the power supply 590 may also include any component such as one or more DC or AC power supplies, a recharging system, a power failure detection circuit, a power converter or inverter, and a power status indicator.
  • the electronic device 500 may further include a Bluetooth module and the like, which will not be repeated here.
  • FIG. 15 shows a schematic structural diagram of a server provided by an embodiment of the present application.
  • the server is used to implement the control method provided in the above embodiments. Specifically:
  • the server 600 includes a central processing unit (CPU) 601, a system memory 604 including a random access memory (RAM) 602 and a read-only memory (ROM) 603, and a system bus 605 connecting the system memory 604 and the central processing unit 601.
  • the server 600 also includes a basic input/output system (I/O system) 606 that helps transfer information between various devices in the computer, and a large-capacity storage for storing the operating system 613, application programs 614, and other program modules 615 Device 607.
  • I/O system basic input/output system
  • the basic input/output system 606 includes a display 608 for displaying information and an input device 609 for a user to input information, such as a mouse and a keyboard.
  • the display 608 and the input device 609 are both connected to the central processing unit 601 through the input and output controller 610 connected to the system bus 605.
  • the basic input/output system 606 may further include an input-output controller 610 for receiving and processing input from many other devices such as a keyboard, a mouse, or an electronic stylus.
  • the input output controller 610 also provides output to a display screen, printer, or other type of output device.
  • the mass storage device 607 is connected to the central processing unit 601 through a mass storage controller (not shown) connected to the system bus 605.
  • the mass storage device 607 and its associated computer-readable medium provide non-volatile storage for the server 600. That is, the mass storage device 607 may include a computer-readable medium (not shown) such as a hard disk or CD-ROM drive.
  • the computer-readable media may include computer storage media and communication media.
  • Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data.
  • Computer storage media include RAM, ROM, EPROM, EEPROM, flash memory, or other solid-state storage technologies, CD-ROM, DVD, or other optical storage, tape cassettes, magnetic tape, magnetic disk storage, or other magnetic storage devices.
  • RAM random access memory
  • ROM read-only memory
  • EPROM Erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • flash memory or other solid-state storage technologies
  • CD-ROM, DVD or other optical storage
  • tape cassettes magnetic tape
  • magnetic disk storage or other magnetic storage devices.
  • the above-mentioned system memory 604 and mass storage device 607 may be collectively referred to as a memory.
  • the server 600 may also be run by a remote computer connected to the network through a network such as the Internet. That is, the server 600 can be connected to the network 612 through the network interface unit 611 connected to the system bus 605, or can also be used to connect to other types of networks or remote computer systems (not shown) .
  • the server 600 further includes a chip 616 including a multiply-accumulate module as shown in any one of FIGS. 4 to 8, and the multiply-accumulate module 616 is connected to other modules in the server 600 through a system bus.
  • the chip 616 including the multiply-accumulate module may implement the control method as provided in the above embodiment.
  • the program may be stored in a computer-readable storage medium.
  • the mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

一种包括乘累加模块的芯片、终端及控制方法，涉及芯片领域。上述芯片包括乘累加模块，乘累加模块包括定点通用单元、浮点专用单元和输出选择单元；定点通用单元和浮点专用单元分别与输出选择单元连接；定点通用单元还与浮点专用单元连接，定点通用单元与浮点专用单元共用一组乘法器。通过在芯片的乘累加模块中，将定点运算和浮点运算集成在一个电路上，使该乘累加模块在一个电路中实现定点运算，同时能够实现浮点运算；定点运算单元与浮点运算单元的乘法器的共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及运算时的功耗。

Description

包括乘累加模块的芯片、控制方法、电子设备及存储介质
本申请要求于2019年01月04日提交中国专利局，申请号为2019100085939、发明名称为“包括乘累加模块的芯片、终端及控制方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片领域，特别涉及一种包括乘累加模块的芯片、控制方法、电子设备及存储介质。
背景技术
乘累加模块是芯片上的一种基本计算模块，广泛应用于诸如中央处理器(Central Processing Unit，CPU)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、专用集成电路(Application Specific Intergrated Circuits，ASIC)、图形处理器(Graphics Processing Unit，GPU)或其他人工智能(Artificial Intelligence，AI)芯片之类的芯片上。
以用于神经网络模型计算的芯片为例，该芯片上同时存在两种乘累加模块：用于定点运算(也称整数运算)的第一种乘累加模块，和，用于浮点运算的第二种乘累加模块。当需要定点运算时，调用第一种乘累加模块进行运算；当需要浮点运算时，调用第二种乘累加模块进行运算。
由于需要在芯片上同时实现两种乘累加模块，导致该芯片的芯片面积和功耗较大。
发明内容
根据本申请提供的各种实施例，提供一种包括乘累加模块的芯片、控制方法、电子设备及存储介质。
根据本申请的一个方面，提供了一种包括乘累加模块的芯片，上述芯片中包括乘累加模块；该乘累加模块包括：用于输入乘法数的第一输入端和第二输入端、用于输入加法数的上级输入端、用于选择定点计算模式或浮点计 算模式的模式选择端和模块输出端；
乘累加模块还包括：定点通用单元、浮点专用单元和输出选择单元；
定点通用单元与第一输入端、第二输入端、上级输入端和模式选择端分别相连，定点通用单元的定点输出端分别与输出选择单元以及浮点专用单元相连；
浮点专用单元与第一输入端、第二输入端、上级输入端、定点输出端和模式选择端分别相连，浮点专用单元的浮点输出端与输出选择单元相连；及
输出选择单元，用于根据模式选择端输入的选择信号设置计算模式，在计算模式为定点计算模式时，将定点输出端与模块输出导通；在计算模式为浮点计算模式时，将浮点输出端与模块输出端导通。
根据本申请的另一方面，提供了一种控制方法，该方法应用于如上述方面所述的芯片中，该方法包括：
接收第一控制信号；
根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式；计算模式包括定点计算模式和浮点计算模式；
当计算模式处于定点计算模式时，将第一操作数A与第二操作数B相乘，之后与上级乘累加模块的计算结果第三操作数C累加，得到并输出定点运算结果；及
当计算模式处于浮点计算模式时，将第一操作数A与第二操作数B进行浮点运算中的乘法部分的计算得到第一中间结果，将第一操作数A、第二操作数B、第三操作数C和第一中间结果进行浮点运算中的加法部分运算后，输出浮点运算结果。
根据本申请的另一方面，提供了一种电子设备，所述电子设备中包括上述方面所述的芯片，所述芯片用于执行上述方面所述的控制方法。
根据本申请的另一方面，提供了一种非易失性的计算机可读存储介质，存储有计算机可读指令，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行上述方面所述的控制方法。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术提供的定点整形计算与浮点计算的计算精度的对比图；
图2是相关技术提供的输入位宽16bit的乘累加模块的结构示意图；
图3是相关技术提供的输入位宽8bit的乘累加模块的结构示意图；
图4是本申请一个示例性实施例提供的芯片中乘累加模块的结构示意图；
图5是本申请一个示例性实施例提供的乘累加模块中定点通用单元的结构示意图；
图6是本申请一个示例性实施例提供的乘累加模块中浮点专用单元的结构示意图；
图7是本申请另一个示例性实施例提供的芯片中乘累加模块的结构示意图；
图8是本申请一个示例性实施例提供的应用环境的结构示意图；
图9是本申请一个示例性实施例提供的控制方法的流程图；
图10是本申请另一个示例性实施例提供的控制方法的流程图；
图11是本申请另一个示例性实施例提供的控制方法的流程图；
图12是本申请另一个示例性实施例提供的控制方法的流程图；
图13是本申请另一个示例性实施例提供的控制方法的流程图；
图14是本申请一个示例性实施例提供的电子设备的结构示意图；
图15是本申请一个示例性实施例提供的电子设备具体实现为服务器时的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
首先对本申请涉及的若干个名词进行简介：
乘累加运算(Multiply Accumulate，MAC)：将第一操作数A和第二操作数B相乘后，将乘积与第三操作数C in相加的运算，也即C out＝A*B+C in。
乘累加模块：在数字信号处理器或一些微处理器中，用于实现乘累加运算的硬件电路单元，也称为“乘数累加器”。
定点数(fixed-point number)：计算机中采用的一种数的表示方法，约定机器中所有数据的小数点位置是固定不变的。在计算机中通常采用两种简单的约定：将小数点的位置固定在数据的最高位之前，或者是固定在最低位之后。一般常称前者为定点小数，后者为定点整数。本申请实施例中，以定点数为定点整数为例来进行说明。当数据小于定点数能表示的最小值时，计算机将它们作0处理，称为下溢；大于定点数能表示的最大值时，计算机将无法表示，称为上溢，上溢和下溢统称为溢出。
浮点数(floating-point number)：计算机中采用的另一种数的标识方法，与科学计数法相似，任意一个二进制数N，总可以写成：
N＝2 E*M；
式中M成为浮点数N的小数部分(也称尾数mantissa)，是一个纯小数；E为浮点数N的指数部分(也称阶码exponent)，是一个整数。这种表示方法相当于数的小数点位置随比例因子的不同，而在一定范围内可以自由浮动，所以称为浮点标识法。
浮点乘运算：对于第一浮点数N A＝2 E a*M a，第二浮点数N B＝2 E b*M b，两个浮点数的乘积如下：
N A*N B＝2 (Ea+Eb)*(M a*M b)。
乘累加模块作为基本的计算单元，在CPU、GPU和AI芯片中应用广泛。以AI领域为例，随着人脸识别、图像分类等新兴技术的发展，对乘累加模块的计算精度和速度要求越来越高。从图1中可以看出，32位浮点FP32的动态范围远大于32整形Int32的动态范围，16位浮点FP16的动态范围远大于16位整形Int16的动态范围，可以得出结论：动态范围越大，计算精度越高。因此，在乘累加模块中加入浮点计算模式成为提高计算精度的一种技术方案。
在相关技术中，芯片中同时设置有两种乘累加模块，分别用于支持定点计算模式和浮点计算模式。也即需要设计两套独立硬件结构，一套乘累加模 块用于支持定点计算模式，另一套乘累加模块用于支持浮点计算模式，以达到提高乘累加模块的计算精度；这就存在一个问题，两套独立硬件结构在芯片上会占用更大的面积，消耗更多的能耗。
如果还需要同时支持高位宽和低位宽的定点计算模式，比如高位宽则还要独立的一套硬件结构支持低位宽的定点计算模式。
示意性的，图2示出了一种相关技术中用于定点计算模式的乘累加模块的电路结构，该乘累加模块支持位宽16bit的2个操作数之间的乘法运算，该电路中包括了4个乘法器a-d和4个加法器a-d，每个乘法器支持8bit的乘法运算。图2中的11为第一操作数1的第15比特至第8比特，12为第一操作数的第7比特至第0比特；21为第二操作数21的第15比特至第8比特，22为第二操作数22的第7比特至第0比特。
在相关技术中，如若乘累加模块需要支持比16bit更低位宽的定点计算模式，则需要增加两组如图3所示的电路结构，两组电路结构均支持位宽8bit的2个操作数之间的乘法运算，两组电路结构中共包括2个乘法器e-f和2个加法器e-f；而浮点计算模式对应的电路结构中包括4个乘法器和6个加法器。
如果一个乘累加模块既需要支持位宽16bit的2个操作数之间的整数乘法运算，以及支持位宽8bit的2个操作数之间的整数乘法运算，还需要支持位宽16bit的2个操作数之间的浮点乘法计算，则需要10个乘法器和12个加法器。也即，相关技术中的硬件资源需求如表1所示：
表1
乘累加模块配置 乘法器 加法器
16比特整数乘累加模块 4 4
8比特整数乘累加模块 2 2
16比特浮点乘累加模块 4 6
16/8比特的整数乘累加模块 6 6
16/8比特的整数乘累加模块+浮点乘累加模块 10 12
在相关技术中，用于定点计算的乘累加模块和用于浮点计算的乘累加模块是两个互相独立的硬件电路，总体所需要的乘法器和加法器的个数较多，需要占用芯片较大的面积，功耗也很大。以具有多个乘累加模块的AI芯片为 例，这些因素直接会制约AI芯片的可制造性、良品率、散热和性能。也即，一方面硬件结构面积更大导致芯片面积更大，芯片面积更大导致成本变高、可制造性变差且良品率变低；另一方面，硬件结构面积更大导致功耗变大，功耗变大会导致散热变多，太高的温度会影响芯片的整体性能。
为了解决芯片上乘累加模块的占用面积以及功耗更大的问题，本申请实施例提供了在同一个乘累加模块中兼容定点乘累加计算和浮点乘累加的技术方案。请参考如下实施例。
图4是本申请的一个示例性实施例提供的芯片中的乘累加模块100的结构示意图，乘累加模块100包括：用于输入乘法数的第一输入端A和第二输入端B、用于输入加法数的上级输入端C_in、用于选择定点计算模式或浮点计算模式的模式选择端mode和模块输出端C_OUT。
乘累加模块100还包括定点通用单元120、浮点专用单元140和输出选择单元160。
定点通用单元120与第一输入端A、第二输入端B、上级输入端C和模式选择端mode分别相连；定点通用单元120的定点输出端分别与输出选择单元160以及浮点专用单元140相连。
浮点专用单元140与第一输入端A、第二输入端B、上级输入端C、定点通用单元120的定点输出端和模式选择端mode分别相连；浮点专用单元140的浮点输出端与输出选择单元160相连。
输出选择单元160与模式选择端mode相连；输出选择单元160用于根据模式选择端mode输入的选择信号设置计算模式。
可选的，计算模式包括定点计算模式和浮点计算模式。
在计算模式为定点计算模式时，定点通用单元120用于将第一输入端A输入的第一操作数A和第二输入端B输入的第二操作数B相乘后与上级输入端C_in输入的第三操作数C累加，从定点输出端输出定点运算结果；
输出选择单元160将定点通用单元120的定点输出端与模块输出端C_OUT导通，从模块输出端C_OUT输出定点运算结果。
在计算模式为浮点计算模式时，定点通用单元120用于对第一输入端输 入的第一操作数A和第二输入端输入的第二操作数B进行浮点乘累加运算中的乘法部分计算，从定点通用单元120的定点输出端输出第一中间结果，该第一中间结果输入浮点专用单元140；浮点专用单元140用于将第一输入端输入的第一操作数A、第二输入端输入的操作数B、上级输入端输入的第三操作数C和定点通用单元120的定点输出端输入的第一中间结果进行浮点乘累加运算中的加法部分运算后，从浮点输出端输出浮点运算结果。
输出选择端160将浮点专用单元140的浮点输出端与模块输出端C_OUT导通，从模块输出端C_OUT输出浮点运算结果。
综上所述，本实施例提供的芯片，通过在乘累加模块中设置定点通用单元和浮点专用单元，该浮点专用单元与定点通用单元的定点输出端相连，由定点通用单元来完成定点计算模式下的乘累加计算，由定点通用单元和浮点专用单元协同完成浮点计算模式下的乘累加计算，实现了同一个乘累加模块能够同时实现定点乘累加运算和浮点乘累加两种运算，由于定点运算单元与浮点运算单元集成在一个电路中，部分器件共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及减少了芯片在乘累加运算时的功耗。
图5示出了本申请的一个示例性实施例提供的定点通用单元120的结构示意图。该定点通用单元120包括：第一乘法器1、第二乘法器2、第三乘法器3和第四乘法器4、加法器1、加法器2、加法器3和定点结果选择单元215。
其中，第一输入端A分为第一子输入端A1和第一子输入端A2，第二输入端B分为第二子输入端B1和第二子输入端B2。上级输入端C分为上级子输入端C1和上级子输入端C2。
第一乘法器1的输入端分别与第一子输入端A1、第二子输入端B1相连；第二乘法器2的输入端分别与第一子输入端A2、第二子输入端B1相连；第三乘法器3的输入端分别与第一子输入端A1、第二子输入端B2相连；第四乘法器4的输入端分别与第一子输入端A2、第二子输入端B2相连。
加法器1的输入端分别与第一乘法器1的输出端、第二乘法器2的输出端相连；加法器2的输入端分别与第三乘法器3的输出端、第四乘法器4的输出端相连；加法器3的输入端分别与加法器1的输出端、加法器4的输出 端、上级子输入端C1相连；加法器4的输入端分别与加法器1的输出端、加法器2的输出端、上级子输入端C2、第一输入端A、第二输入端B相连。
定点结果选择单元215的输入端与加法器3的输出端、加法器4的输出端分别相连。
在一个示意性的例子中，第一操作数A、第二操作数B和第三操作数C均为16比特位宽的操作数，第一子输入端A1用于输入第一操作数A的前半部分[15:8]，也即第15比特至第8比特，第15比特为最左位置的比特，第0比特为最右位置的比特；第一子输入端A2用于输入第一操作数A的后半部分[7:0]。第二子输入端B1用于输入第二操作数B的前半部分[15:8]，第二子输入端B2用于输入第二操作数B的后半部分[7:0]。上级子输入端C1用于输入第三操作数C的前半部分[15:8]，上级子输入端C2用于输入第三操作数C的后半部分[7:0]。
在定点计算模式下，上述定点通用单元120用于计算第一操作数A和第二操作数B之间的乘积后，与第三操作数C相加得到。
图6示出了本申请的一个示例性实施例提供的浮点专用单元140的结构示意图，浮点专用单元140包括第一加法器A、第二加法器B、第三加法器C、移位单元205、搜索单元206和浮点结果输出单元207。
第一加法器A的输入端与定点通用单元120的输出端、上级输入端C分别相连，第二加法器B的第三输入端D与定点通用单元120的定点输出端、上级输入端C、移位单元205的输出端分别相连，第三加法器C的输入端与定点通用单元120的输出端、搜索单元206的输出端分别相连。
移位单元205的输入端与第一加法器A的输出端、第二加法器B的输出端分别相连，搜索单元206的输入端与第二加法器B的输出端、第三加法器C的输出端分别相连，浮点结果输出单元207与第二加法器B的输出端、搜索单元206的输出端分别相连。
在计算模式为浮点计算模式时，从第一输入端A输入第一乘法数
Figure PCTCN2019126829-appb-000001
至乘累加模块，从第二输入端B输入第二乘法数
Figure PCTCN2019126829-appb-000002
至乘累加模块，从上级输入端C输入第一加法数
Figure PCTCN2019126829-appb-000003
至乘累加模块，由浮点专用单元140进行浮点运算，计算公式如下：
E＝E 1+E 2+offset，该公式为指数部分的计算公式；
M＝S 1M 1*S 2M 2+S 3M 3，该公式为小数部分的计算公式；
Figure PCTCN2019126829-appb-000004
该公式为浮点结果的计算公式；
其中，E 1是第一乘法数的指数部分，E 2是第二乘法数的指数部分，E 3是第一加法数的指数部分；S 1是第一乘法数的符号位，S 2是第二乘法数的符号位，S 3是第一加法数的符号位；M 1是第一乘法数的小数部分，M 2是第二乘法数的小数部分，M 3是第一加法数的小数部分；offset是由计算得到的小数结果产生进位导致的指数的相对偏移值。
还需要说明的是，在一些实施例中，如果第一/第二/第三操作数的整数部分是固定值，在表示第一/第二/第三操作数时可以将第一/第二/第三操作数的整数部分去掉，那么在进行浮点计算之前还需要将第一/第二/第三操作数的整数部分添加到数值的比特位的最高位，与小数部分M拼接在一起，得到原始的第一/第二/第三操作数。
在一些事实例中，如果第一/第二/第三操作数的指数部分是经过编码后的数值，需要将第一/第二/第三操作数的指数部分的编码后的数值进行解码，解码得到的数值是原始的指数部分。
示意性的，编码方程式为E(实际)＝E(编码)-BIAS进行解码，其中，BIAS＝15；当输入的第一操作数的经过编码后的指数部分E(编码)为16时，根据编码方程进行解码，得到第一操作数的指数部分E(实际)为1。
在一些实施例中，当第一/第二/第三操作数的小数部分包括整数(包括0)时，则对第一/第二/第三操作数的小数部分M的计算过程中，在小数部分M之前补一位整数位。
示意性的，当指数部分数值是0的时候，相应的实际数值S*2 E*(0.M)中小数部分包括整数部分0；当指数部分数值非0的时候，相应的实际数值S*2 E*(1.M)中小数部分包括整数部分1；在上述两种情况下，则在对小数部分0.M和/或1.M进行计算时，需要在小数部分M之前补一位整数位，再进行运算。
上述运算过程由浮点专用单元140的相应的计算单元执行，对应的计算执行过程如下：
在计算模式为浮点计算模式时，定点通用单元120用于将第一操作数
Figure PCTCN2019126829-appb-000005
的小数部分S 1M 1和第二操作数
Figure PCTCN2019126829-appb-000006
的小数部分S 2M 2相乘，得到第一中间结果S 1M 1*S 2M 2，从定点输出端输出第一中间结果S 1M 1*S 2M 2；其中，小数部分携带有符号位；还用于将第一操作数
Figure PCTCN2019126829-appb-000007
的指数部分E 1与第二操作数
Figure PCTCN2019126829-appb-000008
的指数部分E 2相加，得到第一指数和E 1+E 2；
第一加法器A用于将第一指数和E 1+E 2与第三操作数
Figure PCTCN2019126829-appb-000009
的指数部分E 3的负值相加，得到第二指数和E 1+E 2-E 3；
移位单元用于根据第二指数和E 1+E 2-E 3得到移位对象和移位位数，移位对象是第一中间结果S 1M 1*S 2M 2或者第三操作数
Figure PCTCN2019126829-appb-000010
的小数部分S 3M 3。当移位对象为第一中间结果S 1M 1*S 2M 2时，根据移位位数对第一中间结果S 1M 1*S 2M 2移位得到移位后的第一中间结果；当移位对象为第三操作数
Figure PCTCN2019126829-appb-000011
的小数部分S 3M 3时，根据移位位数对第三操作数
Figure PCTCN2019126829-appb-000012
的小数部分S 3M 3移位得到移位后的第三操作数
Figure PCTCN2019126829-appb-000013
的小数部分；
第二加法器B用于当移位对象为第一中间结果S 1M 1*S 2M 2时，将移位后的第一中间结果S 1M 1*S 2M 2与第三操作数
Figure PCTCN2019126829-appb-000014
的小数部分S 3M 3相加；或者，当移位对象为第三操作数
Figure PCTCN2019126829-appb-000015
的小数部分S 3M 3时，将第一中间结果S 1M 1*S 2M 2与移位后的第三操作数
Figure PCTCN2019126829-appb-000016
的小数部分相加，得到小数和；
搜索单元用于根据小数和得到小数结果S 1M 1*S 2M 2+S 3M 3、以及计算得到指数的相对偏移值offset，并从第三加法器C得到浮点结果的指数结果E 1+E 2+offset；
第三加法器C用于将指数的相对偏移值offset与第一指数和相加E 1+E 2，得到浮点结果的指数结果E 1+E 2+offset；
浮点结果输出单元207用于根据小数和的符号位确定浮点结果的符号位；将浮点结果的符号位、小数结果S 1M 1*S 2M 2+S 3M 3和指数结果E 1+E 2+offset拼接在一起，产生浮点运算结果。
需要说明的是，在一些实施例中，通过定点通用单元120计算第一中间结果时，请参考图5，将第一操作数
Figure PCTCN2019126829-appb-000017
的小数部分S 1M 1和第二操作数
Figure PCTCN2019126829-appb-000018
的小数部分S 2M 2分别通过第一输入端A和第二输入端B输入第一乘法器1，或者第二乘法器2，或者第三乘法器3，或者乘法器4，通过第一乘法器1，或者第二乘法器2，或者第三乘法器3，或者乘法器4计算第一操作 数
Figure PCTCN2019126829-appb-000019
的小数部分S 1M 1和第二操作数
Figure PCTCN2019126829-appb-000020
的小数部分S 2M 2的乘积，通过定点结果选择单元选择输出第一中间结果至浮点专用单元140。
在一些实施例中，浮点计算模式通过定点通用单元120中的加法器4计算第一操作数
Figure PCTCN2019126829-appb-000021
和第二操作数
Figure PCTCN2019126829-appb-000022
的指数部分的第一指数和，请参考图5，将第一操作数
Figure PCTCN2019126829-appb-000023
的指数部分E 1和第二操作数
Figure PCTCN2019126829-appb-000024
的指数部分E 2分别通过第一输入端A和第二输入端B输入加法器4，通过加法器4计算得到第一指数和E 1+E 2。
综上所述，本实施例提供的芯片，通过在乘累加模块中设置定点通用单元和浮点专用单元，该浮点专用单元与定点通用单元的定点输出端相连，由定点通用单元来完成定点计算模式下的乘累加计算，由定点通用单元和浮点专用单元协同完成浮点计算模式下的乘累加计算，实现了同一个乘累加模块能够同时实现定点乘累加运算和浮点乘累加两种运算，由于定点运算单元与浮点运算单元集成在一个电路中，部分器件共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及减少了芯片在乘累加运算时的功耗。
上述图4至图6实施例提供了一种同时支持定点运算和浮点运算的乘累加模块。在可选实施例中，上述定点通用单元还被设计为支持可伸缩设计的定点通用单元。
定点通用单元的可伸缩体现在：同一个乘累加运算模块既能支持两个高位宽(比如16bit)的整数乘法运算，同时也能兼容多组更低位宽(比如8bit、4bit、2bit)的整数乘法运算。
在该实施例中，同一个乘累加模块能够同时支持两个特性：
第一，支持可伸缩的定点运算；
第二，同时支持定点运算和浮点运算。
采用这种设计，提供一个高复用度的硬件电路单元，把可伸缩的定点运算和浮点运算中所需要的各种乘法操作和加法操作尽可能地复用为通用计算单元，以便最大限度地提高结构复用率，节省硬件面积。
设第一操作数A和第二操作数B是乘累加模块的输入，它的输入数据位宽为2 N，N＝1，2，3...。输入的拆分模式为m，m＝2，4，8，16。那么分组 的个数k由以下方程式得到：
k＝2 N/m；
以N＝4,m＝2为例子说明，当DSP_MODE＝0支持两个16bit的乘累加运算，DSP_MODE＝1拆分成两组8bit的乘累加运算，DSP_MODE＝2支持两个16bit的浮点乘累加运算。
表2示出了该例子中的三种计算模式下的输入信号和输出信号的结构图。该三种计算模式包括：第一定点计算模式(8bit整数乘累加运算)、第二定点计算模式(16bit整数乘累加运算)、浮点计算模式(16bit浮点乘累加运算)。
表2
Figure PCTCN2019126829-appb-000025
需要说明的是，上述仅以16bit和8bit来举例说明。在不同实施例中，还可以采用128bit、64bit、32bit、16bit、8bit、4bit和2bit等其他比特数的可能性设计。
在支持可伸缩定点运算时，上述乘累加模块100还包括数据重组器180， 第一输入端A和第二输入端B通过数据重组器180与定点通用单元120相连。该数据重组器180用于对第一输入端A和第二输入端B的数据进行重组和/或拆分。
可选的，定点计算模式包括第一定点计算模式和第二定点计算模式。第一定点计算模式为低位宽k的定点计算模式，第二定点计算模式为高位宽2 N的定点计算模式，m为2 N的约数。
数据重组器180用于在计算模式为第一定点计算模式时，请参考图7，将来自第一输入端A的第一操作数A和来自第二输入端B的第二操作数B分别重组为m组第一子操作数A和第二子操作数B，第一/第二子操作数的比特位宽k＝第一/第二操作数的第一比特位宽2 N/m；在计算模式为第二定点计算模式时，将第一操作数A和第二操作数B拆分为k组第四子操作数D和第五子操作数E，第四/第五子操作数的比特位宽k＝第四/第五操作的第二比特位宽2 N/m；其中，所述第二比特位宽/所述第一比特位宽＝2 M，m、k、N为正整数，M是小于N的任意正整数。
定点通用单元120还用于在计算模式为第一定点计算模式时，将k组第一子操作数A和第二子操作数B相乘后与上级输入端C输入的k个第三子操作数C分别累加，从定点输出端输出定点运算结果；
定点通用单元120还用于在计算模式为第二定点计算模式时，将k组第四子操作数D和第五子操作数E相乘后与上级输入端C输入的k个第三子操作数C分别累加，从定点输出端输出定点运算结果。
在计算模式为第一定点计算模式时，可将第一操作数A和第二操作数B组合为第一子操作数A 1和第二子操作数B 1、第一子操作数A 2和第二子操作数B 2，然后将第一子操作数A 1/A 2和第二子操作数B 1/B 2相乘，与第三子操作数C 1/C 2相分别累加，从定点输出端输出上述运算的结果；
在计算模式为第二定点计算模式时，可以将第一操作数A和第二操作数B拆分为第四子操作数D 1和第五子操作数E 1、第四子操作数D 2和第五子操作数E 2，然后将第四子操作数D 1/D 2和第五子操作数E 1/E 2相乘，与第三子操作数C 1/C 2相分别累加，从定点输出端输出上述运算的结果。
图7示出了本申请一个示意性实施例提供的乘累加模块的结构框图。具体的，定点通用单元120包括乘法器子单元240、加法器子单元260和定点 结果选择单元215；
乘法器子单元240的输入端与数据重组器180相连，加法器子单元260的输入端与乘法器子单元240的输出端和上级输入端C分别相连，定点结果选择单元215的输入端与加法器子单元260的输出端相连，定点结果选择单元215的输出端与输出选择单元160相连。
浮点专用单元140包括浮点加法器子单元220、移位单元205、搜索单元206和浮点结果输出单元207；
浮点加法器子单元220的输入端与数据重组器180、上级输入端C、加法器子单元260的输出端、移位单元205和搜索单元206分别相连，移位单元205的输入端与浮点加法器子单元220的输出端相连，搜索单元206的输入端与浮点加法器子单元220的输出端相连，浮点结果输出单元207与输入端与浮点加法器子单元220的输出端相连，浮点结果输出单元207的输出端与输出选择单元160相连。
可选的，数据重组器180包括k组重组输出端，k组重组输出端中的第i组重组输出端包括第一重组输出端A i和第二重组输出端B i；
定点通用单元包括
Figure PCTCN2019126829-appb-000026
个乘法器和
Figure PCTCN2019126829-appb-000027
个加法器，h为第二比特位宽的最小取值，h、X为正整数；
Figure PCTCN2019126829-appb-000028
个乘法器中的第j个乘法器的第一输入端与第f组重组输出端中的第一重组输出端A f相连，所述第j个乘法器的第二输入端与第t组重组输出端中的第二重组输出端B t相连，其中，f＝j-(t-1)*m，t＝ceil(j/m)，ceil为向上取整，i、j为正整数，且i小于或等于m。
可选的，第j个乘法器，用于将第一操作数A的第f组子操作数A f/D f与第二操作数B的第t组子操作数B t/E t相乘。
示意性的，数据重组器180包括2组重组输出端，2组重组输出端中包括第一组重组输出端的第一重组输出端A 1和第二重组输出端B 1、第二组重组输出端的第一重组输出端A 2和第二重组输出端B 2；此时，定点通用单元120包括4个乘法器和4个加法器，如图7，乘法器子单元240包括第一乘法器1、第二乘法器2、第三乘法器3和第四乘法器4，加法器子单元260包括第四加 法器1、第五加法器2、第六加法器3和第七加法器4。
在一些实施例中，定点通用单元120的结构如图7所示，上级输入端包括第一输入端C 1和第二输入端C 2；
第一乘法器1的输入端与第一重组单元输出端A 1、第二重组输出端B 1分别相连，第二乘法器2的输入端与第一重组输出端A 2、第二重组输出端B 1分别相连，第三乘法器3的输入端与第一重组输出端A 1、第二重组输出端B 2分别相连，第四乘法器4的输入端与第一重组输出端A 2、第二重组输出端B 2分别相连；
第四加法器1的输入端与第一乘法器1的输出端、第二乘法器2的输出端、分别相连，第五加法器2的输入端与第三乘法器3的输出端、第四乘法器4的输出端分别相连；第六加法器3的输入端与第四加法器1的输出端、第五加法器4的输出端、第一输入端C 1分别相连；加法器4的输入端与加法器1的输出端、加法器2的输出端、第二输入端C 2、第一输入端A、第二输入端分别相连；
定点结果选择单元的输入端与加法器3的输出端、加法器4的输出端分别相连。
可选的，上级输入端C输入的第三操作数C包括第三子操作数C 1和第三子操作数C 2；
在一些实施例中，第一乘法器1，用于将第一重组输出端A 1输出的数据与第二重组输出端B 1输出的数据相乘，得到第一乘积；第二乘法器2，用于将第一重组输出端A 2输出的数据与第二重组输出端B 1输出的数据相乘，得到第二乘积；第三乘法器3，用于将第一重组输出端A 1输出的数据与第二重组输出端B 2输出的数据相乘，得到第三乘积；第四乘法器4，用于将第一重组输出端A 2输出的数据与第二重组输出端B 2输出的数据相乘，得到第四乘积；
第四加法器1，用于将第一乘积、第二乘积累加，得到第一加法和；第五加法器2，用于将第三乘积和第四乘积相加，得到第二加法和；第六加法器3，用于将第一加法和、第三子操作数C 1、加法器4的进位值累加，得到第三加法和；加法器4，用于将第一加法和、第二加法和、第三子操作数C 2累加，得到第四加法和；
定点结果选择单元215，用于将第三加法和与第四加法和拼接在一起，得到定点运算结果。
在一些实施例中，第一乘法器1，用于将第一重组输出端A 1输出的数据与第二重组输出端B 1输出的数据相乘，得到第一乘积；第四乘法器4，用于将第一重组输出端A 2输出的数据与第二重组输出端B 2输出的数据相乘，得到第四乘积；
第四加法器3，用于将第一乘积和第三子操作数C 1累加，得到第五加法和；第七加法器4，用于将第四乘积和第三子操作数C 2累加，得到第六加法和；
定点结果选择单元215，用于将第五加法和与第六加法和拼接在一起得到定点输出结果。
综上所述，本实施例提供的包括乘累加模块的芯片通过在乘累加模块中设置定点通用单元和浮点专用单元，该浮点专用单元与定点通用单元的定点输出端相连，由定点通用单元来完成定点计算模式下的乘累加计算，由定点通用单元和浮点专用单元协同完成浮点计算模式下的乘累加计算，实现了同一个乘累加模块能够同时实现定点乘累加运算和浮点乘累加两种运算，由于定点运算单元与浮点运算单元集成在一个电路中，部分器件共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及减少了芯片在乘累加运算时的功耗。
具体的，上述乘累加模块中使用了4个乘法器和7个加法器，与相关技术方案中的实现上述两种定点计算模式与一种浮点计算模式时，使用10个乘法器和12个加法器比较，减少了5个加法器和6个乘法器。
在一些实施例中，上述任一乘累加模块可以应用于神经网络芯片中，如图8所示，是一个示例性实施例提供的包括神经网络模型的芯片结构示意图。该芯片包括若干个脉动阵列，每个脉动阵列包括X*Y个所述乘累加模块；
对于同一个所述脉动阵列，所述第i行第j列的乘累加模块的模块输出端，与所述第i+1行第j列的乘累加模块的上级输入端相连；
或者，
对于同一个所述脉动阵列，所述第i行第j列的乘累加模块的模块输出端， 与所述第i行第j+1列的乘累加模块的上级输入端相连。
其中，脉动阵列中至少一个脉动阵列的第i行第j列的乘累加模块的输入端与应用层相连，至少一个脉动阵列的第p行第q列的乘累加模块的输出端与应用层相连；至少一个脉动阵列的第p行第q列的乘累加模块的输出端是定点结果或者浮点结果的输出端，i、j、p、q为正整数。
示意性的，芯片上包括一个16*16的脉动阵列，其中，脉动阵列的第3行第2列乘累加模块的上级输入端与脉动阵列的第2行第2列乘累加模块的模块输出端相连；可选的，脉动阵列的第3行第2列乘累加模块的上级输入端还可以与脉动阵列的第3行第1列乘累加模块的模块输出端相连。
如图8，芯片上包括该神经网络模型上包括了接口单元a、片上数据存储阵列b、预处理引擎c、卷积/矩阵运算引擎d、片上指令存储h、执行单元g、控制单元f和其他引擎e。其中，卷积/矩阵运算引擎d由N层乘累加模块组成网状构成，每一层中包括至少一个乘累加模块，N为正整数。
该神经网络芯片的片上数据存储阵列b的输入端与接口单元a、预处理引擎c、卷积/矩阵运算引擎d和其他引擎e相连，输出端与预处理引擎c、卷积/矩阵运算引擎d和其他引擎e；预处理引擎c、卷积/矩阵运算引擎d和其他引擎e的输入端分别与控制单元f相连；控制单元f的输入端与执行单元g的输出端相连；执行单元g的输入端与片上指令存储h的输出端相连；片上指令存储h的输入端与接口单元a的输出端相连。
接口单元a，用于数据的输入；片上数据存储阵列b，用于中间结果的暂存；预处理引擎c，用于数据的预处理；卷积/矩阵运算引擎d，用于数据的运算；片上指令存储h，用于指令的存储；执行单元g，用于加载并执行指令；控制单元f，用于控制引擎对数据的处理；其他引擎e，用于执行其他操作。
可选的，上述乘累加模块集成在芯片上，上述芯片是CPU、GPU、FPGA、ASIC或其他AI芯片中的任意一种。
图9是本申请的一个示例性实施例提供的控制方法的流程图，该方法应用于上述图4至图8所示的任一芯片中，上述芯片中包括乘累加模块，该方法包括：
步骤301，接收第一控制信号。
乘累加模块包括模式选择端，该模式选择端用于选择定点计算模式或浮点计算模式。乘累加模块通过模式选择端接收第一控制信号，第一控制信号包括计算模式信息。比如，第一控制信号用二位二进制数表示，用“00”表示定点计算模式，“10”表示浮点计算模式。
步骤302，根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式。
乘累加模块包括定点通用单元和浮点专用单元；乘累加模块根据第一控制信号中的计算模式信息，将定点通用单元或浮点专用单元的电路导通。
当定点通用单元的电路导通时，乘累加模块处于定点计算模式；当浮点专用单元的电路导通时，乘累加模块处于浮点计算模式。
当乘累加模块处于定点计算模式时，执行步骤303；当乘累加模块处于浮点计算模式时，执行步骤305。
比如，用二进制的“00”表示定点计算模式，二进制的“10”表示浮点计算模式；当第一控制信号是“00”时，定点计算模式在乘累加模块中对应的电路导通，执行步骤303；当第一控制信号是“10”时，浮点计算模式在乘累加模块中对应的电路导通，执行步骤305。
步骤303，当计算模式处于定点计算模式时，将第一操作数A与第二操作数B相乘。
乘累加模块包括输入乘法数的第一输入端和第二输入端、输入加法数的上级输入端。当计算模式处于定点计算模式时，乘累加模块通过乘法器将从第一输入端输入的第一操作数A和从第二输入端输入的第二操作数B相乘。
步骤304，与上级乘累加模块的计算结果第三操作数C累加，得到并输出定点运算结果。
乘累加模块通过加法器将上述第一操作数A与第二操作数B的乘积与从上级输入端输入的第三操作数C累加，得到定点运算的结果；定点运算结果为最终的运算结果，输出定点运算结果。
步骤305，当计算模式处于浮点计算模式时，将第一操作数A与第二操作数B进行浮点运算中的乘法部分的计算得到第一中间结果。
浮点专用单元与定点通用单元共用乘法器，当计算模式处于浮点计算模式时，乘累加模块通过定点通用单元中的乘法器将第一操作数A与第二操作 数B中的小数部分相乘，计算得到第一中间结果。
步骤306，将第一操作数A、第二操作数B、第三操作数C和第一中间结果进行浮点运算中的加法部分的运算后，输出浮点运算结果。
乘累加模块通过浮点专用单元中的加法器将第一操作数A、第二操作数B、第三操作数C的指数部分进行加法运算，并对第三操作数C的小数部分和第一中间结果进行加法运算；乘累加模块浮点结果输出单元将指数部分和小数部分的加法运算的结果合并在一起得到并输出浮点运算结果。
综上所述，本实施例提供的控制方法，通过接收第一控制信号；根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式；当乘累加模块的计算模式处于定点计算模式时，进行定点运算，当乘累加模块的计算模式处于浮点计算模式时，进行浮点运算。该方法在一个电路中实现了定点运算与浮点运算的兼容，由于定点运算单元与浮点运算单元集成在一个电路中，乘法器共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及运算时的功耗。
当乘累加模式的计算模式为浮点计算模式时，从第一输入端A输入第一乘法数
Figure PCTCN2019126829-appb-000029
至乘累加模块，从第二输入端B输入第二乘法数
Figure PCTCN2019126829-appb-000030
至乘累加模块，从上级输入端C输入第一加法数
Figure PCTCN2019126829-appb-000031
至乘累加模块，由浮点专用单元140进行浮点运算，计算公式如下：
E＝E 1+E 2+offset，该公式为指数部分的计算公式；
M＝S 1M 1*S 2M 2+S 3M 3，该公式为小数部分的计算公式；
Figure PCTCN2019126829-appb-000032
该公式为浮点结果的计算公式；
其中，E 1是第一乘法数的指数部分，E 2是第二乘法数的指数部分，E 3是第一加法数的指数部分；S 1是第一乘法数的符号位，S 2是第二乘法数的符号位，S 3是第一加法数的符号位；M 1是第一乘法数的小数部分，M 2是第二乘法数的小数部分，M 3是第一加法数的小数部分；offset是由计算得到的小数结果产生进位导致的指数的相对偏移值。具体的，请参考图10，将图9中的步骤305至步骤306替换为步骤3061至步骤3069，对计算模式为浮点计算模式时进行详细说明，步骤如下：
步骤3061，将第一操作数A的小数部分和第二操作数B的小数部分相乘，得到第一中间结果。
对应的，第一操作数A是第一乘法数
Figure PCTCN2019126829-appb-000033
第二操作数B是第二乘法数
Figure PCTCN2019126829-appb-000034
第三操作数C是第一加法数
Figure PCTCN2019126829-appb-000035
浮点专用单元与定点通用单元共用乘法器，乘累加模块通过定点通用单元的乘法器将第一操作数
Figure PCTCN2019126829-appb-000036
的小数部分S 1M 1和第二操作数
Figure PCTCN2019126829-appb-000037
的小数部分S 2M 2相乘，得到第一中间结果S 1M 1*S 2M 2。
步骤3062，将第一操作数A的指数部分与第二操作数B的指数部分相加，得到第一指数和。
乘累加模块还通过定点通用单元中的加法器将第一操作数
Figure PCTCN2019126829-appb-000038
的指数部分E 1与第二操作数
Figure PCTCN2019126829-appb-000039
的指数部分E 2相加，得到第一指数和E 1+E 2。
步骤3063，将第一指数和与第三操作数C的指数部分的负值相加，得到第二指数和。
乘累加模块通过浮点专用单元中的加法器将第一指数和E 1+E 2与第一加法数
Figure PCTCN2019126829-appb-000040
的指数部分的负值-E 3相加，得到第二指数和E 1+E 2-E 3。
步骤3064，根据第二指数和得到移位对象和移位位数，移位对象是第一中间结果或者第三操作数C的小数部分。
乘累加模块通过移位单元对第二指数和E 1+E 2-E 3进行数据处理，得到移位对象和移位对象的移位位数。
步骤3065，根据移位位数对第一中间结果移位得到移位后的第一中间结果，或者，根据移位位数对第三操作数C的小数部分移位得到移位后的第三操作数C的小数部分。
当移位对象为第一中间结果S 1M 1*S 2M 2时，根据移位位数对第一中间结果S 1M 1*S 2M 2移位得到移位后的第一中间结果；当移位对象为第三操作数
Figure PCTCN2019126829-appb-000041
的小数部分S 3M 3时，根据移位位数对第三操作数
Figure PCTCN2019126829-appb-000042
的小数部分S 3M 3移位得到移位后的第三操作数
Figure PCTCN2019126829-appb-000043
的小数部分。
步骤3066，将移位后的第一中间结果与第三操作数C的小数部分相加，或者，将第一中间结果与移位后的第三操作数C的小数部分相加，得到小数和。
当移位对象为第一中间结果S 1M 1*S 2M 2时，将移位后的第一中间结果 S 1M 1*S 2M 2与第三操作数
Figure PCTCN2019126829-appb-000044
的小数部分S 3M 3相加；或者，当移位对象为第三操作数
Figure PCTCN2019126829-appb-000045
的小数部分S 3M 3时，将第一中间结果S 1M 1*S 2M 2与移位后的第三操作数
Figure PCTCN2019126829-appb-000046
的小数部分相加，得到小数和。
步骤3067，根据小数和得到小数结果、浮点结果的符号位以及计算得到指数的相对偏移值。
根据小数和得到小数结果S 1M 1*S 2M 2+S 3M 3、以及计算得到指数的相对偏移值offset。
乘累加模块通过搜索单元对小数和进行数据处理，得到小数结果和指数的相对偏移值offset；通过浮点结果输出单元获取小数和的符号位作为浮点结果的符号位。
步骤3068，将所述相对偏移值与所述第一指数和相加，得到浮点结果的指数结果。
乘累加模块通过加法器将指数的相对偏移值offset与第一指数和相加E 1+E 2，得到浮点结果的指数结果，并通过搜索单元将上述相加的结果更新到指数结果中，得到最终的浮点结果的指数结果E 1+E 2+offset。
步骤3069，将浮点结果的符号位、小数结果和指数结果拼接在一起得到浮点结果。
乘累加模块通过浮点结果输出单元将浮点结果的符号位、小数结果和指数结果拼接在一起得到浮点结果。
综上所述，本实施例提供的控制方法，通过接收第一控制信号；根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式；当乘累加模块的计算模式处于定点计算模式时，进行定点运算，当乘累加模块的计算模式处于浮点计算模式时，进行浮点运算。该方法在一个电路中实现了定点运算与浮点运算的兼容，由于定点运算单元与浮点运算单元集成在一个电路中，乘法器共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及运算时的功耗。
当乘累加单元的计算模式是定点计算模式时，定点计算模式包括第一定点计算模式和第二定点计算模式，请参考图11，是对定点计算模式包括第一定点计算模式和第二定点计算模式的乘累加模块进行说明，并以第一定点计 算模式为8比特位宽的定点计算模式，第二定点计算模式为16比特位宽的定点计算模式为例：
步骤401，接收第一控制信号。
乘累加模块包括模式选择端，该模式选择端用于选择乘累加模块的计算模式为第一定点计算模式、第二定点计算模式或浮点计算模式。乘累加模块通过模式选择端接收第一控制信号，第一控制信号包括计算模式信息。比如，第一控制信号用二位二进制数表示，用“00”表示第一定点计算模式，“01”表示第二定点计算模式，“10”表示浮点计算模式。
步骤402，根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式。
乘累加模块包括定点通用单元和浮点专用单元；乘累加模块根据第一控制信号中的计算模式信息，将定点通用单元或浮点专用单元的电路导通。
当定点通用单元的电路导通时，乘累加模块处于定点计算模式；当浮点专用单元的电路导通时，乘累加模块处于浮点计算模式。
示意性的，当模式选择端接收到的电信号为“00”，乘累加模块置于第一定点计算模式；当模式选择端接收到的电信号为“01”，乘累加模块置于第二定点计算模式；当模式选择端接收到的电信号为“10”，乘累加模块置于浮点计算模式。
需要说明的是，乘累加模块的计算模式的选择是依据电子设备的应用层的程序运行的需求决定的。
步骤403，当计算模式处于浮点计算模式时，将第一操作数A与第二操作数B进行浮点运算中的乘法部分的计算得到第一中间结果。
请参考图9中步骤305，在此不再加以赘述。
步骤404，将第一操作数A、第二操作数B、第三操作数C和第一中间结果进行浮点运算中的加法部分的运算后，输出浮点运算结果。
请参考图9中步骤306，在此不再加以赘述。
步骤405，在计算模式为第一定点计算模式时，将m组第一子操作数A和第二子操作数B相乘。
在计算模式为第一定点计算模式时，乘累加模块中的数据重组器将来自第一输入端的第一操作数A和来自第二输入端的第二操作数B分别重组为m 组第一子操作数A和第二子操作数B，第一/第二子操作数的比特位宽k＝第一/第二操作数的第一比特位宽2 N/m；通过乘法器将m组第一子操作数A和第二子操作数B相乘，m、N为正整数。
需要说明的是，第一定点模式下的第一比特位宽小于定点计算模式能够计算的操作数的最大比特位宽；最大比特位宽是第二比特位宽，第二比特位宽/第一比特位宽＝2 M，M是小于N的任意正整数。
步骤406，与上级输入端输入的m个第三子操作数C分别累加，从定点输出端输出定点运算结果。
乘累加模块通过加法器将上述m组第一子操作数A和第二子操作数B相乘的结果与上级输入端输入的m个第三子操作数C分别累加，最终得到定点运算结果，并通过定点结果选择单元输出定点运算结果。
示意性的，当m为2时，第三操作数C包括第三子操作数C 1和第三子操作数C 2；当计算模式为第一定点计算模式时，第一操作数A重组后包括第一子操作数A 1和第一子操作数A 2，第二操作数B重组后包括第二子操作数B 1和第二子操作数B 2；步骤405至步骤406的运算过程具体如下：
乘累加模块通过第一乘法器1将第一子操作数A 1和第二子操作数B 1相乘，得到第一乘积；通过第四乘法器4将第一子操作数A 2和第二子操作数B 2相乘，得到第四乘积；通过第四加法器1将第一乘积和第三子操作数C 1累加，得到第五加法和；通过第七加法器4将第四乘积和第三子操作数C 2累加，得到第六加法和；通过定点结果选择单元将第五加法和与第六加法和拼接在一起得到定点运算结果，并输出定点运算结果。
比如，如图12所示的数据流，第二定点计算模式的操作数的数据位宽为16bit，m为2，则第一定点计算模式的操作数的数据位宽为8bit。在第一输入端和第二输入端输入8bit的操作数1和8bit的操作数2，上级输入端输入48bit的数据3；数据1通过数据重组器重组后，将2个数据1拼接成为一个16bit的数据11，上述数11的高8位和低8位均为数据1，同理，数据2拼接成为一个16bit的数据22，数据22的高8位和低8位均为数据2；数据5则拆分为高24位和低24位；
乘法器1将数据11的高8位和数据22的高8位相乘，得到位宽16bit的第一乘积“数据1*数据2”；乘法器4将数据11的低8位和数据22的低8 位相乘，得到位宽16bit的第二乘积“数据1*数据2”；
加法器1将第一乘积与数据5的高24位累加，得到24bit的第五加法和“(数据1*数据2)+数据5的高24位”；加法器3将第四乘积与数据5的低24位累加，得到24bit的第六加法和“(数据1*数据2)+数据5的低24位”；
定点选择单元将第五加法和与第六加法和分别拼接至高24位与低24位，得到48bit的定点运算结果，并输出上述定点运算结果。
上述过程的数据流表示如下：
SIZE＝16；操作数位宽为16bit；
SUB_PART_SIZE＝8；子操作数位宽为8bit；
SUB_PART_NUMBER＝SIZE/SUB_PART_SIZE；组数为操作数位宽为16bit/子操作数位宽为8bit，分为2组；
SUB_PART_H＝RANGE(SIZE_PART_NUMBER*SUB_PART_SIZE-1,SUB_PART_SIZE)；高8位为[15:8]；
SUB_PART_L＝RANGE(SUB_PART_SIZE-1,0)；低8位为[7:0]；
A1＝unpack(A,SUB_PART_H)；A1为高8位；
A0＝unpack(A,SUB_PART_L)；A0为低8位；
B1＝unpack(B,SUB_PART_H)；B1为高8位；
B0＝unpack(B,SUB_PART_L)；B0为低8位；
C1＝C_IN_H；C1为高24位；
C0＝C_IN_L；C0为低24位；
C_OUT_H＝A1*B1+C_IN_H；C_OUT_H为高24位的计算结果；
C_OUT_L＝A0*B0+C_IN_L；C_OUT_L为低24位的计算结果。
步骤407，在计算模式为第二定点计算模式时，将m组第四子操作数D和第五子操作数E相乘。
在计算模式为第二定点计算模式时，乘累加模块中的数据重组器将第一 操作数A和第二操作数B拆分为m组第四子操作数D和第五子操作数E，第四/第五子操作数的比特位宽k＝第四/第五操作数的第二比特位宽2 N/m；通过乘法器将m组第四子操作数D和第五子操作数E相乘。
步骤408，与上级输入端输入的m个第三子操作数C分别累加，从定点输出端输出定点运算结果。
乘累加模块通过加法器将上述m组第四子操作数D和第五子操作数E相乘的结果与上级输入端输入的m个第三子操作数C分别累加，最终得到定点运算结果，并通过定点结果选择单元输出定点运算结果。
示意性的，当m为2时，第三操作数C包括第三子操作数C 1和第三子操作数C 2；当计算模式为第二定点计算模式时，第一操作数A拆分后包括第四子操作数D 1和第四子操作数D 2，第二操作数B拆分后包括第五子操作数E 1和第五子操作数E 2；步骤407至步骤408的运算过程具体如下：
乘累加模块通过第一乘法器1将第四子操作数D 1和第五子操作数E 1相乘，得到第一乘积；通过第二乘法器2将第四子操作数D 2和第五子操作数E 1相乘，得到第二乘积；通过第三乘法器3将第四子操作数D 1和第五子操作数E 2相乘，得到第三乘积；通过第四乘法器4将第四子操作数D 2和第五子操作数E 2相乘，得到第四乘积；
通过第四加法器1将第一乘积、第二乘积累加，得到第一加法和；通过第五加法器2将第三乘积和第四乘积相加，得到第二加法和；通过第六加法器3将第一加法和、第二加法和、第三子操作数C 1、加法器4的进位值累加，得到第三加法和；通过第七加法器4将第一加法和、第二加法和、第三子操作数C 2累加，得到第四加法和；通过定点结果选择单元将第三加法和与第四加法和拼接在一起，得到定点运算结果。
比如，如图13所示的数据流，第二定点计算模式的操作数的数据位宽为16bit，m为2；在第一输入端和第二输入端输入16bit的操作数3和16bit的操作数4，上级输入端输入48bit的数据3；数据1通过数据重组器拆分后，将数据1拆分为一个8bit的数据31和一个8bit的数据32，上述数据31为数据3的高8位、数据32为数据3的低8位，同理，数据4拆分为一个8bit的数据41和一个8bit的数据42，上述数据41为数据4的高8位、数据42为数据4的低8位；数据5则拆分为高24位和低24位；
乘法器1将数据31和数据41相乘，得到位宽16bit的第一乘积“数据31*数据41”；乘法器2将数据32和数据41相乘，得到位宽16bit的第二乘积“数据32*数据41”；乘法器3将数据31和数据42相乘，得到位宽16bit的第三乘积“数据31*数据42”；乘法器4将数据32和数据42相乘，得到位宽16bit的第四乘积“数据32*数据42”；
加法器1将第一乘积“数据31*数据41”、第二乘积“数据32*数据41”累加，得到位宽24bit的第一加法和“数据31*数据41+数据32*数据41”；加法器2将第三乘积“数据31*数据42”和第四乘积“数据32*数据42”相加，得到位宽16bit的第二加法和“数据31*数据42+数据32*数据42”；加法器3将第一加法和的高8位、数据5的高24位以及加法器4的进位值累加，得到位宽24bit的第三加法和，加法器4将第一加法和的低16位、第二加法和、数据5的低24位累加，得到位宽24bit第四加法和“(数据31*数据42+数据32*数据42)+(数据31*数据41+数据32*数据41)+数据5的低24位”，将位宽24bit的第三加法和通过定点结果选择单元拼接在一起输出位宽48bit的定点运算结果。
上述过程的数据流表示如下：
SIZE＝16；操作数位宽为16bit；
SUB_PART_SIZE＝8；子操作数位宽为8bit；
SUB_PART_NUMBER＝SIZE/SUB_PART_SIZE；组数为操作数位宽为16bit/子操作数位宽为8bit，分为2组；
SUB_PART_H＝RANGE(SIZE_PART_NUMBER*SUB_PART_SIZE-1,SUB_PART_SIZE)；高8位为[15:8]；
SUB_PART_L＝RANGE(SUB_PART_SIZE-1,0)；低8位为[7:0]；
A1＝unpack(A,SUB_PART_H)；A1为高8位；
A0＝unpack(A,SUB_PART_L)；A0为低8位；
B1＝unpack(B,SUB_PART_H)；B1为高8位；
B0＝unpack(B,SUB_PART_L)；B0为低8位；
C1＝C_IN_H；C1为高24位；
C0＝C_IN_L；C0为低24位；
ADD1＝shift(A1*B1,SUB_PART)+A0B1；第一乘积与第二乘积的第一加法和；
ADD2＝shift(A1*B0,SUB_PART)+A0B0；第三乘积与第四乘积的第二加法和；
ADD3＝C_IN_L+ADD2+ADD1_L；第一加法和、第二加法和与上级加法数的低24位的第四加法和；
ADD4＝carry(ADD3)+ADD1_H+C_IN_H；第一加法和、上级加法数的高24位、第三加法和的进位值的第三加法和；
C_OUT_H＝ADD4；第三加法和为高24位的计算结果；
C_OUT_L＝ADD3.第四加法和为低24位的计算结果。
综上所述，本实施例提供的控制方法，通过接收第一控制信号；根据第一控制信号，控制芯片中的乘累加模块处于对应的计算模式；当乘累加模块的计算模式处于定点计算模式时，进行定点运算，当乘累加模块的计算模式处于浮点计算模式时，进行浮点运算。该方法在一个电路中实现了定点运算与浮点运算的兼容，由于定点运算单元与浮点运算单元集成在一个电路中，乘法器共用，减少了使用的器件总数，从而减少了定点运算单元与浮点运算单元在芯片上的占用面积、以及运算时的功耗。
本实施例提供的控制方法，还通过在一个电路中支持两个高位宽的整数乘法运算的同时，兼容多组更低位宽的整数乘法运算，减少了同时支持不同位宽的整数乘法运算时电路中使用的器件的总数，减少了定点运算单元在芯片上的占用面积、以及运算时的功耗。
请参考图14，其示出了本申请一个实施例提供的电子设备的结构示意图。 该电子设备用于实施上述实施例中提供的控制方法。可选的，电子设备包括智能手机、服务器、物联网(Internet of Things，IoT)设备、云服务器、端侧设备中的至少一种，具体来讲：
电子设备500可以包括RF(Radio Frequency，射频)电路510、包括有一个或一个以上计算机可读存储介质的存储器520、输入单元530、显示单元540、传感器550、音频电路560、WiFi(wireless fidelity，无线保真)模块570、包括有一个或者一个以上处理核心的处理器580、以及电源590等部件。本领域技术人员可以理解，图14中示出的电子设备结构并不构成对电子设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。其中：
RF电路510可用于收发信息或通话过程中，信号的接收和发送，特别地，将基站的下行信息接收后，交由一个或者一个以上处理器580处理；另外，将涉及上行的数据发送给基站。通常，RF电路510包括但不限于天线、至少一个放大器、调谐器、一个或多个振荡器、用户身份模块(SIM)卡、收发信机、耦合器、LNA(Low Noise Amplifier，低噪声放大器)、双工器等。此外，RF电路510还可以通过无线通信与网络和其他设备通信。所述无线通信可以使用任一通信标准或协议，包括但不限于GSM(Global System of Mobile communication，全球移动通讯系统)、GPRS(General Packet Radio Service，通用分组无线服务)、CDMA(Code Division Multiple Access，码分多址)、WCDMA(Wideband Code Division Multiple Access,宽带码分多址)、LTE(Long Term Evolution,长期演进)、电子邮件、SMS(Short Messaging Service，短消息服务)等。
存储器520可用于存储软件程序以及模块，处理器580通过运行存储在存储器520的软件程序以及模块，从而执行各种功能应用以及数据处理。存储器520可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备500的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器520可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。相应地，存储器520还可以包括存储器控制器，以 提供处理器580和输入单元530对存储器520的访问。
输入单元530可用于接收输入的数字或字符信息，以及产生与用户设置以及功能控制有关的键盘、鼠标、操作杆、光学或者轨迹球信号输入。具体地，输入单元530可包括图像输入设备531以及其他输入设备532。图像输入设备531可以是摄像头，也可以是光电扫描设备。除了图像输入设备531，输入单元530还可以包括其他输入设备532。具体地，其他输入设备532可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。
显示单元540可用于显示由用户输入的信息或提供给用户的信息以及电子设备500的各种图形用户接口，这些图形用户接口可以由图形、文本、图标、视频和其任意组合来构成。显示单元540可包括显示面板541，可选的，可以采用LCD(Liquid Crystal Display，液晶显示器)、OLED(Organic Light-Emitting Diode,有机发光二极管)等形式来配置显示面板541。
电子设备500还可包括至少一种传感器550，比如光传感器、运动传感器以及其他传感器。具体地，光传感器可包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示面板541的亮度，接近传感器可在电子设备500移动到耳边时，关闭显示面板541和/或背光。作为运动传感器的一种，重力加速度传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别手机姿态的应用(比如横竖屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；至于电子设备500还可配置的陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
音频电路560、扬声器561，传声器562可提供用户与电子设备500之间的音频接口。音频电路560可将接收到的音频数据转换后的电信号，传输到扬声器561，由扬声器561转换为声音信号输出；另一方面，传声器562将收集的声音信号转换为电信号，由音频电路560接收后转换为音频数据，再将音频数据输出处理器580处理后，经RF电路510以发送给比如另一电子设备，或者将音频数据输出至存储器520以便进一步处理。音频电路560还可能包括耳塞插孔，以提供外设耳机与电子设备500的通信。
WiFi属于短距离无线传输技术，电子设备500通过WiFi模块570可以 帮助用户收发电子邮件、浏览网页和访问流式媒体等，它为用户提供了无线的宽带互联网访问。虽然图14示出了WiFi模块570，但是可以理解的是，其并不属于电子设备500的必须构成，完全可以根据需要在不改变发明的本质的范围内而省略。
处理器580是电子设备500的控制中心，利用各种接口和线路连接整个手机的各个部分，通过运行或执行存储在存储器520内的软件程序和/或模块，以及调用存储在存储器520内的数据，执行电子设备500的各种功能和处理数据，从而对手机进行整体监控。可选的，处理器580可包括一个或多个处理核心；优选的，处理器580可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器580中。
电子设备500还包括如上述图4至图8任一所示的包括乘累加模块的芯片582。该包括乘累加模块的芯片582可以实现如上述实施例提供的控制方法。图14给出了一种包括乘累加模块的芯片582在电子设备500中的连接方式，但包括乘累加模块的芯片582在电子设备500中的连接方法不仅限于上述一种方法，还可以与根据需要实现的功能做出适应性的连接，比如，当需要包括乘累加模块的芯片582完成图像的处理时，可以直接与图像输入设备531相连。
电子设备500还包括给各个部件供电的电源590(比如电池)，优选的，电源可以通过电源管理系统与处理器580逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。电源590还可以包括一个或一个以上的直流或交流电源、再充电系统、电源故障检测电路、电源转换器或者逆变器、电源状态指示器等任意组件。
尽管未示出，电子设备500还可以包括蓝牙模块等，在此不再赘述。
图15示出了本申请一个实施例提供的服务器的结构示意图。该服务器用于实施上述实施例中提供的控制方法。具体来讲：
所述服务器600包括中央处理单元(CPU)601、包括随机存取存储器(RAM)602和只读存储器(ROM)603的系统存储器604，以及连接系统 存储器604和中央处理单元601的系统总线605。所述服务器600还包括帮助计算机内的各个器件之间传输信息的基本输入/输出系统(I/O系统)606，和用于存储操作系统613、应用程序614和其他程序模块615的大容量存储设备607。
所述基本输入/输出系统606包括有用于显示信息的显示器608和用于用户输入信息的诸如鼠标、键盘之类的输入设备609。其中所述显示器608和输入设备609都通过连接到系统总线605的输入输出控制器610连接到中央处理单元601。所述基本输入/输出系统606还可以包括输入输出控制器610以用于接收和处理来自键盘、鼠标、或电子触控笔等多个其他设备的输入。类似地，输入输出控制器610还提供输出到显示屏、打印机或其他类型的输出设备。
所述大容量存储设备607通过连接到系统总线605的大容量存储控制器(未示出)连接到中央处理单元601。所述大容量存储设备607及其相关联的计算机可读介质为服务器600提供非易失性存储。也就是说，所述大容量存储设备607可以包括诸如硬盘或者CD-ROM驱动器之类的计算机可读介质(未示出)。
不失一般性，所述计算机可读介质可以包括计算机存储介质和通信介质。计算机存储介质包括以用于存储诸如计算机可读指令、数据结构、程序模块或其他数据等信息的任何方法或技术实现的易失性和非易失性、可移动和不可移动介质。计算机存储介质包括RAM、ROM、EPROM、EEPROM、闪存或其他固态存储其技术，CD-ROM、DVD或其他光学存储、磁带盒、磁带、磁盘存储或其他磁性存储设备。当然，本领域技术人员可知所述计算机存储介质不局限于上述几种。上述的系统存储器604和大容量存储设备607可以统称为存储器。
根据本申请的各种实施例，所述服务器600还可以通过诸如因特网等网络连接到网络上的远程计算机运行。也即服务器600可以通过连接在所述系统总线605上的网络接口单元611连接到网络612，或者说，也可以使用网络接口单元611来连接到其他类型的网络或远程计算机系统(未示出)。
所述服务器600还包括如图4至图8任一所示的包括乘累加模块的芯片616，乘累加模块616与服务器600中的其他模块通过系统总线连接。该包括 乘累加模块的芯片616可以实现如上述实施例提供的控制方法。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种包括乘累加模块的芯片，其特征在于，所述芯片中包括乘累加模块；所述乘累加模块包括：用于输入乘法数的第一输入端和第二输入端、用于输入加法数的上级输入端、用于选择定点计算模式或浮点计算模式的模式选择端和模块输出端；
    所述乘累加模块还包括：定点通用单元、浮点专用单元和输出选择单元；
    所述定点通用单元与所述第一输入端、所述第二输入端、所述上级输入端和所述模式选择端分别相连，所述定点通用单元的定点输出端分别与所述输出选择单元以及所述浮点专用单元相连；
    所述浮点专用单元与所述第一输入端、所述第二输入端、所述上级输入端、所述定点输出端和所述模式选择端分别相连，所述浮点专用单元的浮点输出端与所述输出选择单元相连；及
    所述输出选择单元，用于在所述模式选择端所指示的计算模式为定点计算模式时，将所述定点输出端与模块输出端导通；在所述计算模式为浮点计算模式时，将所述浮点输出端与所述模块输出端导通。
  2. 根据权利要求1所述的芯片，其特征在于，
    在所述计算模式为所述定点计算模式时，所述定点通用单元用于将所述第一输入端输入的第一操作数A和所述第二输入端输入的第二操作数B相乘后与所述上级输入端输入的第三操作数C累加，从所述定点输出端输出定点运算结果。
  3. 根据权利要求1所述的芯片，其特征在于，
    在所述计算模式为所述浮点计算模式时，所述定点通用单元用于对所述第一输入端输入的所述第一操作数A和所述第二输入端输入的第二操作数B进行浮点乘累加运算中的乘法部分计算，从所述定点输出端输出第一中间结果；所述浮点专用单元用于将所述第一输入端输入的所述第一操作数A、所述第二输入端输入的所述第二操作数B、所述上级输入端输入的所述第三操作数C和所述定点输出端输入的所述第一中间结果进行所述浮点乘累加运算中的加法部分运算后，从所述浮点输出端输出浮点运算结果。
  4. 根据权利要求3所述的芯片，其特征在于，所述浮点专用单元包括：加法器A、加法器B、加法器C、移位单元、搜索单元和浮点结果输出单元；
    所述加法器A的输入端与所述定点通用单元的输出端、所述上级输入端分别相连，所述加法器B的输入端与所述定点通用单元的所述定点输出端、所述上级输入端、所述移位单元的输出端分别相连，所述加法器C的输入端与所述定点通用单元的输出端、所述搜索单元的输出端分别相连；及
    所述移位单元的输入端与所述加法器A的输出端、所述加法器B的输出端分别相连，所述搜索单元的输入端与所述加法器B的输出端、所述加法器C的输出端分别相连，所述浮点结果输出单元与所述加法器B的输出端、所述搜索单元的输出端分别相连。
  5. 根据权利要求4所述的芯片，其特征在于，所述第一操作数A、所述第二操作数B和所述第三操作数C为浮点数，所述浮点数包括指数部分和小数部分；
    所述定点通用单元，用于将所述第一操作数A的小数部分和所述第二操作数B的小数部分相乘，得到所述第一中间结果；还用与将所述第一操作数A指数部分与所述第二操作数B的指数部分相加，得到第一指数和；
    所述加法器A，用于将所述第一指数和与所述第三操作数C的指数部分的负值相加，得到第二指数和；
    所述移位单元，用于根据所述第二指数和得到移位对象和移位位数，所述移位对象是所述第一中间结果或者所述第三操作数C的小数部分；当所述移位对象是所述第一中间结果时，根据所述移位位数对所述第一中间结果移位得到所述移位后的第一中间结果；或者，当所述移位对象是所述第三操作数C的小数部分时，根据所述移位位数对所述第三操作数C的小数部分移位得到所述移位后的所述第三操作数C的小数部分；
    所述加法器B，用于当所述移位对象是所述第一中间结果时，将移位后的第一中间结果与所述第三操作数C的小数部分相加得到小数和；或者，当所述移位对象是所述第三操作数C的小数部分时，将所述第一中间结果与移位后的所述第三操作数C的小数部分相加得到所述小数和；
    所述搜索单元，用于根据所述小数和得到小数结果、以及计算得到指数的相对偏移值，并从所述加法器C得到浮点结果的指数结果；
    所述加法器C，用于将所述相对偏移值与所述第一指数和相加，得到所述指数结果；及
    所述浮点结果输出单元，用于根据所述小数和的符号位确定所述浮点结果的符号位；将所述浮点结果的符号位、所述小数结果和所述指数结果拼接在一起生成所述浮点运算结果。
  6. 根据权利要求1至5任一所述的芯片，其特征在于，所述乘累加模块还包括：数据重组器；
    所述第一输入端和所述第二输入端通过所述数据重组器与所述定点通用单元相连；
    所述数据重组器，用于在所述计算模式为第一定点计算模式时，将来自所述第一输入端的第一操作数A和来自所述第二输入端的第二操作数B分别重组为m组第一子操作数A和第二子操作数B，第一/第二子操作数的比特位宽k＝第一/第二操作数的第一比特位宽2 N/m；及
    在所述计算模式为第二定点计算模式时，将所述第一操作数A和所述第二操作数B拆分为m组第四子操作数D和第五子操作数E，第四/第五子操作数的比特位宽k＝第四/第五操作数的第二比特位宽2 N/m；
    其中，所述第二比特位宽/所述第一比特位宽＝2 M，m、k、N为正整数，M是小于N的任意正整数。
  7. 根据权利要求6所述的芯片，其特征在于，
    所述定点通用单元，还用于在所述计算模式为所述第一定点计算模式时，将所述m组第一子操作数A和第二子操作数B相乘后与所述上级输入端输入的m个第三子操作数C分别累加，从所述定点输出端输出定点运算结果；及
    所述定点通用单元，还用于在所述计算模式为所述第二定点计算模式时，将所述m组第四子操作数D和第五子操作数E相乘后与所述上级输入端输入的m个第三子操作数C分别累加，从所述定点输出端输出定点运算结果。
  8. 根据权利要求6所述的芯片，其特征在于，
    所述数据重组器包括m组重组输出端，所述m组重组输出端中的第i组重组输出端包括第一重组输出端A i和第二重组输出端B i；
    所述定点通用单元包括
    Figure PCTCN2019126829-appb-100001
    个乘法器和
    Figure PCTCN2019126829-appb-100002
    个加法器，所述h为所述第二比特位宽的最小取值，h、X为正整数；及
    所述
    Figure PCTCN2019126829-appb-100003
    个乘法器中的第j个乘法器的第一输入端与第f组重组输出端中的第一重组输出端A f相连，所述第j个乘法器的第二输入端与第t组重组输出端中的第二重组输出端B t相连；
    其中，f＝j-(t-1)*m，t＝ceil(j/m)，ceil为向上取整，i、j为正整数，且i小于或等于m。
  9. 根据权利要求8所述的芯片，其特征在于，
    所述第j个乘法器，用于将所述第一操作数A的第f组子操作数A f/D f与所述第二操作数B的第t组子操作数B t/E t相乘。
  10. 根据权利要求9所述的芯片，其特征在于，
    所述数据重组器包括2组重组输出端，所述2组重组输出端中包括第一组重组输出端的第一重组输出端A 1和第二重组输出端B 1、第二组重组输出端的第一重组输出端A 2和第二重组输出端B 2；所述上级输入端包括第一输入端C 1和第二输入端C 2；
    所述定点通用单元包括乘法器1、乘法器2、乘法器3、乘法器4、加法器1、加法器2、加法器3、加法器4和定点结果选择单元；
    所述乘法器1的输入端与所述第一重组输出端A 1、所述第二重组输出端B 1分别相连，所述乘法器2的输入端与所述第一重组输出端A 2、所述第二重组输出端B 1分别相连，所述乘法器3的输入端与所述第一重组输出端A 1、所述第二重组输出端B 2分别相连，所述乘法器4的输入端与所述第一重组输出端A 2、所述第二重组输出端B 2分别相连；
    所述加法器1的输入端与所述乘法器1的输出端、所述乘法器2的输出端、分别相连，所述加法器2的输入端与所述乘法器3的输出端、所述乘法器4的输出端分别相连；所述加法器3的输入端与所述加法器1的输出端、所述加法器4的输出端、所述第一输入端C 1分别相连；所述加法器4的输入端与所述加法器1的输出端、所述加法器2的输出端、所述第二输入端C 2、所述第一输入端A、所述第二输入端分别相连；及
    所述定点结果选择单元的输入端与所述加法器3的输出端、所述加法器4的输出端分别相连。
  11. 根据权利要求10所述的方法，其特征在于，所述第三操作数C包括第三子操作数C 1和第三子操作数C 2两部分；
    所述乘法器1，用于将所述第一重组输出端A 1输出的数据与所述第二重组输出端B 1输出的数据相乘，得到第一乘积；
    所述乘法器2，用于将所述第一重组输出端A 2输出的数据与所述第二重组输出端B 1输出的数据相乘，得到第二乘积；
    所述乘法器3，用于将所述第一重组输出端A 1输出的数据与所述第二重组输出端B 2输出的数据相乘，得到第三乘积；
    所述乘法器4，用于将所述第一重组输出端A 2输出的数据与所述第二重组输出端B 2输出的数据相乘，得到第四乘积；
    所述加法器1，用于将所述第一乘积、所述第二乘积累加，得到第一加法和；
    所述加法器2，用于将所述第三乘积和所述第四乘积相加，得到第二加法和；
    所述加法器3，用于将所述第一加法和、所述第三子操作数C 1、所述加法器4的进位值累加，得到第三加法和；
    所述加法器4，用于将所述第一加法和、所述第二加法和、所述第三子操作数C 2累加，得到第四加法和；及
    所述定点结果选择单元，用于将所述第三加法和与所述第四加法和拼接在一起，得到所述定点运算结果。
  12. 根据权利要求10所述的芯片，其特征在于，所述第三操作数C包括第三子操作数C 1和第三子操作数C 2两部分；
    所述乘法器1，用于将所述第一重组输出端A 1输出的数据与所述第二重组输出端B 1输出的数据相乘，得到第一乘积；
    所述乘法器4，用于将所述第一重组输出端A 2输出的数据与所述第二重组输出端B 2输出的数据相乘，得到第四乘积；
    所述加法器3，用于将所述第一乘积和所述第三子操作数C 1累加，得到第五加法和；
    所述加法器4，用于将所述第四乘积和所述第三子操作数C 2相加，得到第六加法和；及
    所述定点结果选择单元，用于将所述第五加法和与所述第六加法和拼接在一起得到所述定点运算结果。
  13. 根据权利要求1至12任一所述的芯片，其特征在于，所述芯片包括若干个脉动阵列，每个所述脉动阵列包括X*Y个所述乘累加模块；
    对于同一个所述脉动阵列，所述第i行第j列的乘累加模块的模块输出端，与所述第i+1行第j列的乘累加模块的上级输入端相连；i、j、X、Y为正整数。
  14. 根据权利要求1至12任一所述的芯片，其特征在于，所述芯片包括若干个脉动阵列，每个所述脉动阵列包括X*Y个所述乘累加模块；
    对于同一个所述脉动阵列，所述第i行第j列的乘累加模块的模块输出端，与所述第i行第j+1列的乘累加模块的上级输入端相连，i、j、X、Y为正整数。
  15. 根据权利要求1至14任一所述的芯片，其特征在于，所述芯片是中央处理器CPU、现场可编程门阵列FPGA、专用集成电路ASIC、图形处理器GPU或人工智能AI芯片中的任意一种。
  16. 一种控制方法，所述方法应用于权利要求1至15任一所述的芯片中， 其特征在于，所述方法包括：
    接收第一控制信号；
    根据所述第一控制信号，控制所述芯片中的乘累加模块处于对应的计算模式；所述计算模式包括定点计算模式和浮点计算模式；
    当所述计算模式处于所述定点计算模式时，将第一操作数A与第二操作数B相乘，之后与上级乘累加模块的计算结果第三操作数C累加，得到并输出定点运算结果；及
    当所述计算模式处于所述浮点计算模式时，将所述第一操作数A与所述第二操作数B进行浮点乘累加运算中的乘法部分的计算得到第一中间结果，将所述第一操作数A、所述第二操作数B、所述第三操作数C和所述第一中间结果进行浮点乘累加运算中的加法部分运算后，输出浮点运算结果。
  17. 根据权利要求16所述的方法，其特征在于，所述定点计算模式包括第一定点计算模式和第二定点计算模式；所述方法应用于如所述权利要求5所述的芯片中；所述第三操作数C包括m个第三子操作数C；
    当所述计算模式为第一定点计算模式时，将所述第一操作数A和所述第二操作数B分别重组为m组第一子操作数A和第二子操作数B，第一/第二子操作数的比特位宽k＝第一/第二操作数的第一比特位宽2 N/m；及
    当所述计算模式为第二定点计算模式时，将所述第一操作数A和所述第二操作数B拆分为m组第四子操作数D和第五子操作数E，第四/第五子操作数的比特位宽k＝第四/第五操作数的第二比特位宽2 N/m；
    其中，所述第二比特位宽/所述第一比特位宽＝2M，m、k、N为正整数，M是小于N的任意正整数。
  18. 根据权利要求16所述的方法，其特征在于，所述当所述计算模式处于所述浮点计算模式时，将所述第一操作数A与所述第二操作数B进行浮点乘累加运算中的乘法部分的计算得到第一中间结果，将所述第一操作数A、所述第二操作数B、所述第三操作数C和所述第一中间结果进行浮点乘累加运算中的加法部分运算后，输出浮点运算结果包括：
    将第一操作数A的小数部分和第二操作数B的小数部分相乘，得到第一 中间结果；
    将第一操作数A的指数部分与第二操作数B的指数部分相加，得到第一指数和；
    将第一指数和与第三操作数C的指数部分的负值相加，得到第二指数和；
    根据第二指数和得到移位对象和移位位数，移位对象是第一中间结果或者第三操作数C的小数部分；
    根据移位位数对第一中间结果移位得到移位后的第一中间结果，或者，根据移位位数对第三操作数C的小数部分移位得到移位后的第三操作数C的小数部分；
    将移位后的第一中间结果与第三操作数C的小数部分相加，或者，将第一中间结果与移位后的第三操作数C的小数部分相加，得到小数和；
    根据小数和得到小数结果、浮点结果的符号位以及计算得到指数的相对偏移值；
    将所述相对偏移值与所述第一指数和相加，得到浮点结果的指数结果；及
    将浮点结果的符号位、小数结果和指数结果拼接在一起得到浮点运算结果。
  19. 一种电子设备，其特征在于，所述电子设备中包括如权利要求1至15任一所述的芯片，所述芯片用于执行如权利要求16至18中任一项所述的方法的步骤。
  20. 一种非易失性的计算机可读存储介质，存储有计算机可读指令，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求16至18中任一项所述的方法的步骤。
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