WO2020135279A1 - 时钟同步方法、装置和存储介质 - Google Patents

时钟同步方法、装置和存储介质 Download PDF

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Publication number
WO2020135279A1
WO2020135279A1 PCT/CN2019/127235 CN2019127235W WO2020135279A1 WO 2020135279 A1 WO2020135279 A1 WO 2020135279A1 CN 2019127235 W CN2019127235 W CN 2019127235W WO 2020135279 A1 WO2020135279 A1 WO 2020135279A1
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WIPO (PCT)
Prior art keywords
clock
node
deviation
master
maximum
Prior art date
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PCT/CN2019/127235
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English (en)
French (fr)
Inventor
吕京飞
刘颂
徐川
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19903548.6A priority Critical patent/EP3893427A4/en
Publication of WO2020135279A1 publication Critical patent/WO2020135279A1/zh
Priority to US17/360,059 priority patent/US11811501B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0644—External master-clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Definitions

  • the present application relates to the field of communication technology, and in particular, to a clock synchronization method, device, and storage medium.
  • the G.8275.1 protocol is a protocol defined by the International Telecommunication Union Telecommunication Standardization Branch (International Telecommunication Union-Telecommunication Standardization Sector, ITU-T) based on the IEEE 1588 protocol and suitable for telecommunication applications.
  • the G.8275.1 protocol specifies the functions of the IEEE 1588 protocol necessary for interoperability of clock nodes in a clock synchronization network.
  • a clock synchronization network that follows the G.8275.1 protocol, it usually includes at least one clock source node and multiple clocks node.
  • the clock node may be connected to one or more upstream network devices.
  • the upstream network device may be referred to as a master clock node.
  • the G.8275.1 protocol defines a master clock node selection algorithm.
  • This selection algorithm can also be called an alternative-best master clock algorithm (Alternative-Best Master Clock Algorithm, A-BMCA).
  • A-BMCA Alternative-Best Master Clock Algorithm
  • the clock node receives multiple Announce messages from the multiple master clock nodes.
  • Each Announce message carries the clock level, clock accuracy, clock variance, second priority, clock local priority, clock source node identification of the clock source node located upstream of the master clock node, and the master clock node to the upstream The hop count of the clock source node.
  • A-BMCA is used to compare the fields of the clock level, clock accuracy, clock variance, second priority, and clock local priority carried in different Announce messages received.
  • the clock level carried in different received Announce messages is less than or equal to 127. If the clock levels in different Announce messages are all less than or equal to 127, compare the number of hops from the multiple master clock nodes to the upstream clock source node, and select the master clock node corresponding to the smaller hop number to clock Synchronize. If the clock levels are all greater than 127, you can determine whether the clock source node IDs carried in the received Announce message are the same.
  • the number of hops from the multiple master clock nodes to the upstream clock source node is compared, and the master clock node corresponding to the smaller hop number is selected for clock synchronization.
  • the accuracy of the master clock node selected by the number of hops may not be high, thereby reducing the accuracy of clock synchronization.
  • the present application provides a clock synchronization method, device, and storage medium, which can solve the problem that the network device selects the master clock node with low precision in the related art, thereby reducing the accuracy of the clock synchronization performed by the network device.
  • the technical solution is as follows:
  • a clock synchronization method includes: a network device receives an Announce message from a first master clock node and an Announce message from a second master clock node, from the first master clock node
  • the Announce message carries the identifier of the first clock source node and the first cumulative value of the maximum clock deviation
  • the Announce message from the second master clock node carries the identifier of the second clock source node and the cumulative value of the second maximum clock deviation
  • the network device compares the identifier of the first clock source node with the identifier of the second clock source node; when the identifier of the first clock source node is the same as the identifier of the second clock source node,
  • the network device selects a master clock node for clock synchronization from the first master clock node and the second master clock node according to the first accumulated maximum clock deviation value and the second accumulated maximum clock deviation value
  • the network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • the network device may be a device connected with at least two master clock nodes in the clock synchronization network.
  • An Announce message is a message defined by Precision Time Protocol (PTP).
  • the identifier of the first clock source node is an identifier for uniquely indicating the first clock source node.
  • the identifier of the second clock source node is an identifier for uniquely indicating the second clock source node.
  • the first accumulated maximum clock deviation is the sum of multiple first maximum clock deviations on the path from the first clock source node to the first master clock node
  • the second accumulated maximum clock deviation is the second clock source node to the second master The sum of multiple second maximum clock deviations on the path of the clock node.
  • Calibrating the clock of the network device is to set the parameters of the clock of the network device to be the same as the parameters of the clock of the selected master clock node.
  • the parameters of the clock may be the time of the clock, the frequency of the clock, or the time and frequency of the clock.
  • the network device may first compare the identifier of the first clock source node with the identifier of the second clock source node, and when the identifier of the first clock source node is the same as the identifier of the second clock source node, It indicates that the first master clock node and the second master clock node correspond to the same clock source node. At this time, the network device selects the master clock node for clock synchronization from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value. The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • the Announce message from the first master clock node also carries the clock level of the first clock source node
  • the Announce message from the second master clock node also carries the second clock source node Clock level
  • the method further includes: the network device compares the first clock source node Is compared with the clock level of the second clock source node; when the clock level of the first clock source node is equal to the clock level of the second clock source node, the network device determines the first Whether the clock level of the clock source node is less than or equal to 127;
  • the network device comparing the identifier of the first clock source node with the identifier of the second clock source node includes: When the clock level is greater than 127, the network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the clock level of the clock source node is used to indicate the clock level of the clock source node, and the smaller the value of the clock level of the clock source node, the higher the clock level of the corresponding clock source node.
  • the clock level of the first clock source node is equal to the clock level of the second clock source node, it indicates that the clock level of the first clock source node is the same as the clock level of the second clock source node. At this time, it can be determined whether the clock level of the first clock source node is less than or equal to 127.
  • the clock level of the first clock source node is equal to the clock level of the second clock source node, it is determined whether the clock level of the first clock source node Less than or equal to 127 is to determine whether the clock level of the second clock source node is less than or equal to 127.
  • the clock level of the first clock source node is greater than 127, it indicates that the first clock source node can be used not only as a clock source node tracked by other slave clock nodes, but also as a tracking other clock source node Slave clock node.
  • the second clock source node can be used not only as a clock source node tracked by other slave clock nodes, but also as a slave clock node tracking other clock source nodes.
  • the method further includes: when the clock level of the first clock source node is less than or equal to 127, the The network device selects a master clock node for clock synchronization from the first master clock node and the second master clock node according to the first accumulated maximum clock deviation value and the second accumulated maximum clock deviation value; The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • the clock level of the first clock source node is less than or equal to 127, that is, the clock level of the second clock source node is less than or equal to 127, it means that the first clock source node can only be used as a slave clock node A clock source node that is tracked, but not a slave clock node that tracks other clock source nodes.
  • the clock level of the first clock source node is less than or equal to 127, it indicates that the second clock source node can only be used as a clock source node tracked by other slave clock nodes, but not as a slave clock node tracking other clock source nodes.
  • the plurality of first maximum clock deviations refer to the plurality of maximum clock deviations corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, respectively.
  • a second maximum clock deviation refers to a plurality of maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, respectively.
  • the plurality of clock nodes on the path from the first clock source node to the first master clock node may include the first master clock node, and exclude the first clock source node.
  • the plurality of clock nodes on the path from the second clock source node to the second master clock node may include the second master clock node and not include the second clock source node.
  • the network device selects clock synchronization from the first master clock node and the second master clock node according to the first accumulated maximum clock deviation value and the second accumulated maximum clock deviation value
  • the master clock node including: the network device comparing the first maximum clock deviation accumulated value with the second maximum clock deviation accumulated value; when the first maximum clock deviation accumulated value is less than the second maximum
  • the network device determines the first master clock node as the master clock node for clock synchronization.
  • the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value are compared.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the network device can determine the second master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the master clock node that performs clock synchronization can make the accuracy of the clock synchronization performed by the network device higher, thereby further improving the accuracy of the clock after the network device is calibrated.
  • the Announce message from the first master clock node also carries a first clock variance value
  • the Announce message from the second master clock node also carries a second clock variance value
  • the network device After comparing the first maximum clock deviation accumulated value with the second maximum clock deviation accumulated value, the method further includes: when the first maximum clock deviation accumulated value is equal to the second maximum clock deviation accumulated value , The network device compares the first clock variance value with the second clock variance value; when the first clock variance value is less than the second clock variance value, the network The device determines the first master clock node as the master clock node for clock synchronization.
  • first clock variance value refers to the square root of the sum of squares of multiple first clock deviation variance values.
  • second clock variance value refers to the square root of the sum of squares of multiple second clock deviation variance values.
  • the first clock deviation variance value refers to the variance value of multiple clock deviations corresponding to one clock node on the path from the first clock source node to the first master clock node.
  • the second clock deviation variance value refers to the variance value of multiple clock deviations corresponding to one clock node on the path from the second clock source node to the second master clock node.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the network device may determine the second master clock node as the master clock node for clock synchronization, which may make the network device perform clock synchronization with higher accuracy.
  • the plurality of first maximum clock deviations refer to the plurality of maximum clock deviations respectively corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, and the At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes in the plurality of clock nodes on the path from the first clock source node to the first master clock node
  • the plurality of second The maximum clock deviation refers to a plurality of maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, and the second clock source node to the second At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes among the multiple clock nodes on the path of the master clock node, respectively.
  • a pair of adjacent clock nodes on the path from the first clock source node to the first master clock node means that the path from the first clock source node to the first master clock node can directly perform Announce message interaction Two clock nodes.
  • a pair of adjacent clock nodes on the path from the second clock source node to the second master clock node refers to two on the path from the second clock source node to the second master clock node that can directly interact with Announce messages Clock node.
  • the network device selects clock synchronization from the first master clock node and the second master clock node according to the first accumulated maximum clock deviation value and the second accumulated maximum clock deviation value
  • the master clock node includes: the network device determines a third maximum clock deviation accumulated value and a fourth maximum clock deviation accumulated value, and the network device divides the third maximum clock deviation accumulated value from the fourth maximum clock deviation The cumulative value is compared; when the third maximum clock deviation cumulative value is less than the fourth maximum clock deviation cumulative value, the network device determines the first master clock node as the master clock node for clock synchronization.
  • the third maximum clock deviation cumulative value refers to the sum of the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device and the first maximum clock deviation cumulative value.
  • the fourth cumulative value of the maximum clock deviation refers to the sum of the cumulative value of the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device and the cumulative value of the second maximum clock deviation.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the third maximum clock deviation accumulated value is greater than the fourth maximum clock deviation accumulated value, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node.
  • the network device determines the second master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the Announce message from the first master clock node also carries a first clock variance value
  • the Announce message from the second master clock node also carries a second clock variance value
  • the first The clock variance value refers to the square root of the sum of squares of multiple first clock deviation variance values
  • the second clock variance value refers to the square root of the sum of squares of multiple second clock deviation variance values.
  • the first clock deviation variance value includes a plurality of clock deviation variance values corresponding to each clock node on the path from the first clock source node to the first master clock node, and the first clock source node A variance value of a plurality of clock deviations corresponding to a transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on the path to the first master clock node, the The multiple second clock deviation variance values include multiple clock deviation variance values corresponding to each clock node on the path from the second clock source node to the second master clock node, and the second clock A variance value of a plurality of clock deviations corresponding to the transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on the path from the source node to the second master clock node; After the network device compares the third maximum clock deviation accumulated value with the fourth maximum clock deviation accumulated value, the method further includes: when the third maximum clock deviation accumulated value is equal to the fourth maximum When the accumulated clock deviation value, the network device determines the third clock variance value and
  • the third clock variance value is the square root of the sum of squares of the variance values of multiple clock deviations corresponding to the transmission medium between the first master clock node and the network device and the first clock variance value.
  • the fourth clock variance value is the square root of the sum of squares of the variance values of multiple clock deviations corresponding to the transmission medium between the second master clock node and the network device and the second clock variance value.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the third clock variance value is greater than the fourth clock variance value, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node.
  • the network device determines the second master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • a clock synchronization device having a function to implement the behavior of the clock synchronization method in the first aspect described above.
  • the clock synchronization device includes at least one module, and the at least one module is used to implement the clock synchronization method provided in the first aspect.
  • a clock synchronization device in a third aspect, includes a processor and a memory.
  • the memory is used to store a program that supports the clock synchronization device to execute the clock synchronization method provided in the first aspect. And storing data related to the clock synchronization method described in the first aspect.
  • the processor is configured to execute the program stored in the memory.
  • the clock synchronization device may further include a communication bus for establishing a connection between the processor and the memory.
  • a computer-readable storage medium having instructions stored therein, which when executed on a computer, causes the computer to execute the clock synchronization method described in the first aspect above.
  • a computer program product containing instructions, which when executed on a computer, causes the computer to execute the clock synchronization method described in the first aspect above.
  • the network device first receives the Announce message from the first master clock node and the Announce message from the second master clock node, and the Announce message from the first master clock node Carrying the identifier of the first clock source node and the first accumulated value of the maximum clock deviation, the Announce message from the second master clock node carries the identifier of the second clock source node and the accumulated value of the second maximum clock deviation.
  • the network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the identifier of the first clock source node When the identifier of the first clock source node is the same as the identifier of the second clock source node, it indicates that the first master clock node and The second master clock node corresponds to the same clock source node. At this time, it is helpful to select a clock source from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value The master clock node with a smaller clock deviation on the path from the node to the master clock node, and then calibrate the clock of the network device according to the time information of the selected master clock node. If the clock deviation caused by the path from the clock source node to the master clock node is small, the accuracy of clock synchronization by the master clock node is higher, which in turn makes the accuracy of the clock after the network device calibration higher.
  • FIG. 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a network device according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a first clock synchronization method provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a second clock synchronization method provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a clock synchronization device provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an implementation environment provided by an embodiment of the present application.
  • the implementation environment includes satellite 101, satellite 102, and network device 103-network device 111, satellite 101, satellite 102, and network device 103-network device.
  • 111 forms a clock synchronization network.
  • the satellite 101 transmits the time information to the network device 103 through the satellite signal
  • the satellite 102 transmits the time information to the network device 109 through the satellite signal
  • the network device 103 and the network device 111 may be connected through an optical fiber and transmit the time information through the optical fiber.
  • Both the satellite 101 and the satellite 102 may be a Global Positioning System (Global Positioning System, GPS), a Global Satellite Navigation System (Global Navigation, Satellite System, GLONASS), or a BeiDou Navigation Satellite System (BeiDou Navigation Satellite System).
  • the network equipment 103-the network equipment 111 may all be an operator router (provider router), an operator edge router (provider edge router), a customer edge router (customer edge router), and so on.
  • the satellite 101 and the satellite 102 are located upstream of the clock synchronization network, and the network device 111 is located downstream of the clock synchronization network.
  • the satellite 101 can achieve clock synchronization with the network device 103 by sending a clock signal to the network device 103.
  • the satellite 102 may achieve clock synchronization with the network device 109 by sending a clock signal to the network device 109.
  • the satellite 101 may include an atomic clock.
  • the network device 103 may include a clock of a communication building timing supply system (building integrated timing, BITS), and the BITS clock includes a GPS receiver.
  • BITS building integrated timing
  • the satellite 101 can send a GPS signal to the network device 103 under the drive of an atomic clock.
  • the GPS signal may include time information with the same accuracy as the atomic clock.
  • the GPS receiver of the BITS clock in the network device 103 can synchronize the BITS clock in the network device 103 with the atomic clock in the GPS satellite according to the time information in the GPS signal.
  • clock synchronization includes time synchronization and frequency synchronization
  • the network device 103 can synchronize the time of the BITS clock in the network device 103 with the time of the atomic clock in the GPS satellite, and the network device 103 can synchronize the network device 103
  • the frequency of the BITS clock in is synchronized with the frequency of the atomic clock in the GPS satellite.
  • the network device 103 can serve as a time source node.
  • the clock synchronization between the network device 109 and the satellite 102 can be performed by the above method, and the network device 109 after clock synchronization can be used as another clock source node.
  • the network device 103 as a time source node can synchronize clocks between the network device 104 and the network device 106 and the network device 103 located downstream of the network device 103.
  • the network device 103 may send a synchronization (Sync) message to the network device 104 located downstream of the network device 103, and the Sync message records the transmission of the Sync message.
  • Time stamp 1 After receiving the Sync message, the network device 104 locally records a time stamp 2 indicating the reception time of the Sync message, and then the network device 104 sends a delay request (Delay_req) message to the network device 103.
  • Delay_req delay request
  • a time stamp 3 indicating the sending time of the Delay_req message is recorded locally.
  • the network device 103 After receiving the Delay_req message, the network device 103 locally records a time stamp 4 indicating the receiving time of the Delay_req message, and finally the network device 103 generates a delay request feedback (Delay_resp) report carrying the time stamp 4 ⁇ 104 ⁇ The text and sent to the network device 104.
  • Delay_resp delay request feedback
  • the network device 104 can obtain the timestamp 1 of the Sync message sent by the network device 103 and the timestamp 2 of the Sync message received by the network device 104, and the timestamp 3 of the Delay_req message sent by the network device 104 and the Delay_req received by the network device 103 Message time stamp 4.
  • the network device 104 can determine the frequency deviation from the network device 103 through time stamp 1 and time stamp 2, and perform frequency synchronization with the network device 103 according to the frequency deviation; and the network device 104 can pass the time stamp 1 and time The stamp 2, the time stamp 3 and the time stamp 4 determine the time deviation with the network device 103, and perform time synchronization with the network device 103 according to the time deviation, that is, clock synchronization with the network device 103 is achieved .
  • the network device 104 may serve as a master clock node to synchronize the clock between the network device 105 and the network device 104 located downstream of the network device 104, and so on.
  • the network device 111 is located downstream of the network device 105, the network device 108, and the network device 110. Therefore, the network device 105, the network device 108, and the network device 110 can all serve as the master clock node of the network device 111.
  • the network device 111 can receive three Announce messages from the network device 105, the network device 108, and the network device 110. These three Announce messages all carry the identifier of the clock source node upstream of the master clock node and the maximum value of the master clock node. The accumulated clock deviation and the number of hops from the master clock node to the upstream clock source node.
  • the Announce message sent by the network device 105 carries the identifier of the network device 103, the accumulated value of the maximum clock deviation of the network device 105, and the number of hops from the network device 105 to the network device 103
  • the Announce message sent by the network device 108 carries the network
  • the Announce message sent by the network device 110 carries the identifier of the network device 109, and the accumulated maximum clock deviation of the network device 110 Value and the number of hops from the network device 110 to the network device 109.
  • the network device 111 can select a network device that can perform clock synchronization from the network device 105, the network device 108, and the network device 110 according to the data carried in the three Announce messages, and then similarly, the network device 104 and the network The process of clock synchronization between the devices 103 to achieve clock synchronization between the network device 111 and the network device selected to perform clock synchronization.
  • FIG. 2 is a schematic structural diagram of a network device provided by an embodiment of the present application.
  • the network device may be any one of the network device 103-network device 111 shown in FIG.
  • the network device includes at least one processor 201, a communication bus 202, a memory 203, at least one communication interface 204, and a clock 205.
  • the processor 201 may be a general-purpose central processing unit (Central Processing Unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or may be one or more programs used to control the application program Implementation of integrated circuits.
  • CPU Central Processing Unit
  • ASIC application-specific integrated circuit
  • the communication bus 202 may include a path for transferring information between the aforementioned components.
  • the memory 203 may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or random access memory (RAM) or can store information and instructions
  • the other types of dynamic storage devices can also be Electrically Erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), CD-ROM (Compact Disc Read-Only Memory, CD-ROM) or other disc storage , Optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program code in the form of instructions or data structures And any other media that can be accessed by the network device, but not limited to this.
  • the memory 203 may exist independently and be connected to the processor 201 through the communication bus 202.
  • the memory 203 may also be integrated with the processor 201.
  • the communication interface 204 uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), and Wireless Local Area Networks (WLAN).
  • a transceiver uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), and Wireless Local Area Networks (WLAN).
  • RAN Radio Access Network
  • WLAN Wireless Local Area Networks
  • the clock 205 may be a BITS clock, and the BITS clock may include a GPS receiver.
  • the processor 201 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 2.
  • the network device may include multiple processors, such as the processor 201 and the processor 206 shown in FIG. 2.
  • processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU).
  • the processor here may refer to one or more devices, circuits, and/or processing cores for processing data.
  • the network device may further include an output device 207 and an input device 208 (not shown in the figure).
  • the output device 207 communicates with the processor 201 and can display information in various ways.
  • the output device 207 can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc.
  • the input device 208 communicates with the processor 201 and can receive user input in a variety of ways.
  • the input device 208 may be a mouse, a keyboard, a touch screen device, or a sensing device.
  • the above network device may be a general network device or a dedicated network device.
  • the network device may be a router, a switch, etc.
  • the embodiment of the present application does not limit the type of network device.
  • the memory 203 is used to store the program code 210 for executing the solution of the present application, and the processor 201 is used to execute the program code 210 stored in the memory 203.
  • the network device may implement the clock synchronization method provided in the embodiment of FIG. 3 below through the processor 201 and the program code 210 in the memory 203.
  • FIG. 3 is a flowchart of a first clock synchronization method provided by an embodiment of the present application. The method is applied to a network device. Referring to FIG. 3, the method includes:
  • the network device receives the notification Announce message from the first master clock node and the Announce message from the second master clock node.
  • the Announce message from the first master clock node carries the identifier of the first clock source node and the first maximum Cumulative clock deviation value
  • the Announce message from the second master clock node carries the identifier of the second clock source node and the second maximum cumulative clock deviation value.
  • the network device may be a device connected with at least two master clock nodes in the clock synchronization network.
  • it may be the network device 111 in FIG. 2.
  • the first master clock node and the second master clock node are clock nodes connected to the network device and located upstream of the network device.
  • Announce message is a message defined by PTP.
  • the identifier of the first clock source node is an identifier for uniquely indicating the first clock source node.
  • the identifier of the second clock source node is an identifier for uniquely indicating the second clock source node.
  • the first maximum clock deviation cumulative value is the sum of a plurality of first maximum clock deviations on the path from the first clock source node to the first master clock node.
  • the second maximum clock deviation cumulative value is the sum of multiple second maximum clock deviations on the path from the second clock source node to the second master clock node.
  • multiple first maximum clock deviations may refer to the first clock source node to the first master clock node. Multiple maximum clock deviations corresponding to multiple clock nodes on the path.
  • the multiple second maximum clock deviations may refer to multiple maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, respectively. That is, each clock node on the path from the first clock source node to the first master clock node corresponds to a maximum clock deviation, and the maximum clock deviation is called a first maximum clock deviation.
  • each clock node on the path from the second clock source node to the second master clock node also corresponds to a maximum clock deviation, and the maximum clock deviation is called a second maximum clock deviation.
  • the clock node may generally include multiple master communication interfaces and multiple slave communication interfaces. Multiple slave communication interfaces can respectively communicate with multiple master clock nodes according to the G.8275.1 protocol; multiple master communication interfaces can respectively communicate with multiple slave clock nodes located downstream according to the G.8275.1 protocol.
  • the following uses multiple master communication interfaces as an example for illustration.
  • the slave clock node that communicates with the master communication interface cannot communicate with the master communication interface. Clock synchronization between the clock nodes.
  • the slave clock node needs to communicate with other master communication interfaces included in the clock node, so that clock synchronization with the clock node can be achieved through other master communication interfaces.
  • the clock node will have a deviation in hop amplitude because the slave clock node communicates with other master communication interfaces. That is, when the slave clock node communicates with the original master communication interface, the accuracy of clock synchronization between the slave clock node and the clock node is higher than when the slave clock node communicates with other master communication interfaces. The accuracy of clock synchronization between the slave clock node and the clock node.
  • the clock node may not have a situation where the communication interface fails and the clock node communicating with the communication interface needs to communicate with other communication interfaces, so the deviation of the hopping amplitude is not an inevitable deviation of the clock node.
  • the clock node will inevitably generate jitter in the natural environment where it is located, resulting in jitter deviation. Furthermore, the clock node will inevitably have a static deviation due to the slow drift during use.
  • the above-mentioned clock node jump amplitude deviation, jitter deviation and static deviation are all clock node clock deviations. These three clock deviations can obtain a maximum value for evaluating the accuracy of the clock node through the detection of multiple different sampling moments before the clock node leaves the factory. For example, the clock node can obtain 100 transition amplitude deviations and 100 jitter deviations in 100 sampling moments before leaving the factory. By taking the maximum value among these 100 hopping amplitude deviations, the maximum hopping amplitude deviation can be obtained.
  • the maximum jitter deviation can be obtained.
  • the maximum static deviation can be obtained.
  • the maximum jump amplitude deviation, maximum jitter deviation and maximum static deviation can be saved in the clock node when the clock node leaves the factory.
  • the maximum clock deviation value is the sum of the maximum jump amplitude deviation, the maximum jitter deviation, and the maximum static deviation;
  • the maximum clock deviation value is the sum of the maximum jitter deviation and the maximum static deviation.
  • the maximum clock deviation corresponding to the clock node may be the sum of the maximum jump amplitude deviation, the maximum jitter deviation, and the maximum static deviation , Can also be the sum of the maximum jitter deviation and the maximum static deviation.
  • the maximum clock deviation corresponding to the clock node may be the sum of the maximum jump amplitude deviation, the maximum jitter deviation, and the maximum static deviation, It can also be the sum of the maximum jitter deviation and the maximum static deviation.
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the maximum clock deviation 104
  • the network device 105 corresponds to the maximum clock deviation 105. That is, there are two first maximum clock deviations on the path from the network device 103 to the network device 105, namely the maximum clock deviation 104 and the maximum clock deviation 105. In this way, the first maximum clock deviation accumulated value is the sum of the maximum clock deviation 104 and the maximum clock deviation 105.
  • the plurality of clock nodes on the path from the first clock source node to the first master clock node may include the first master clock node, and exclude the first clock source node.
  • the plurality of clock nodes on the path from the second clock source node to the second master clock node may include the second master clock node and not include the second clock source node.
  • the transmission medium between two adjacent clock nodes may also have a corresponding clock deviation. Therefore, the plurality of first maximum clock deviations may refer to the plurality of maximum clock deviations respectively corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, and the first clock source node to the first master At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes among multiple clock nodes on the path of the clock node, respectively.
  • the plurality of second maximum clock deviations may refer to the plurality of maximum clock deviations respectively corresponding to the plurality of clock nodes on the path from the second clock source node to the second master clock node, and the second clock source node to the second master clock At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes among multiple clock nodes on the path of the node. That is, each clock node on the path from the first clock source node to the first master clock node corresponds to a maximum clock deviation, and the transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes is also Corresponding to a maximum clock deviation, it may be called a first maximum clock deviation.
  • each clock node on the path from the second clock source node to the second master clock node corresponds to a maximum clock deviation
  • at least one pair of adjacent clock nodes corresponds to a maximum clock deviation, which may be referred to as a second maximum clock deviation.
  • a pair of adjacent clock nodes on the path from the first clock source node to the first master clock node means that the path from the first clock source node to the first master clock node can directly perform Announce message interaction Two clock nodes.
  • a pair of adjacent clock nodes on the path from the second clock source node to the second master clock node refers to two on the path from the second clock source node to the second master clock node that can directly interact with Announce messages Clock node.
  • the network device 104 and the network device 105 in FIG. 1 may be referred to as a pair of adjacent clock nodes.
  • the transmission medium between adjacent clock nodes may be an optical fiber. Since the optical fiber is affected by factors such as temperature, humidity, and pressure, the delay of clock synchronization between a pair of adjacent clock nodes may be affected. There is a clock deviation in the transmission medium between adjacent clock nodes.
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the maximum clock deviation 104
  • the network device 105 corresponds to the maximum clock deviation 105
  • the transmission medium n between the network device 104 and the network device 105 also corresponds to the maximum clock deviation n. That is, there are three first maximum clock deviations on the path from the network device 103 to the network device 105, that is, the maximum clock deviation 104, the maximum clock deviation 105, and the maximum clock deviation n.
  • the first maximum clock deviation accumulated value is the sum of the maximum clock deviation 104, the first maximum clock deviation 105, and the first maximum clock deviation n.
  • multiple first maximum clock deviations refer to multiple maximum clock deviations corresponding to multiple clock nodes on the path from the first clock source node to the first master clock node, respectively.
  • a detection instrument can be provided at the two adjacent clock nodes in advance to transmit time information in the forward and reverse directions between the two clock nodes.
  • the generated clock deviation is detected. Similar to the above clock nodes, it can be detected at multiple different sampling moments, and then the maximum value of the detected clock deviations is taken as the maximum clock deviation of the transmission medium between these two adjacent clock nodes. And save the maximum clock deviation of the transmission medium between the two adjacent clock nodes to any one of the two adjacent clock nodes.
  • S302 The network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the clock nodes in the entire clock synchronization network need to track the same clock source node, so that the clock nodes in the entire clock synchronization network correspond to the same clock source node. Therefore, First, by comparing the identifier of the first clock source node with the identifier of the second clock source node, it is determined whether the clock source nodes of the first master clock node and the second master clock node are the same.
  • the clock source nodes of the first master clock node and the second master clock node are the same, then it can be guaranteed that the clock nodes in the clock synchronization network will track the same clock source node, and then select the network that can be connected to the network through the following S303 The master clock node where the device performs clock synchronization.
  • the network device selects from the first master clock node and the second master according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value Among the clock nodes, select the main clock node for clock synchronization.
  • the master clock node for clock synchronization can be selected from the first master clock node and the second master clock node based on the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value.
  • the concepts of the first clock deviation accumulated value and the second clock deviation accumulated value are different.
  • the implementation manner of selecting the master clock node for clock synchronization from the first master clock node and the second master clock node will also be different Therefore, the selection of the master clock node will be described separately in two possible implementations.
  • the first possible implementation manner corresponds to the first case in S301 above
  • the second possible implementation manner corresponds to the second case in S301 above.
  • the first possible implementation manner the network device compares the first maximum clock deviation accumulated value with the second maximum clock deviation accumulated value. When the first maximum clock deviation accumulated value is less than the second maximum clock deviation accumulated value, the network device will The first master clock node is determined as the master clock node for clock synchronization; when the first accumulated maximum clock deviation value is greater than the second accumulated maximum clock deviation value, the network device determines the second master clock node as the master clock node for clock synchronization .
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the network device may determine the second master clock node as the master clock node for clock synchronization, which may make the network device perform clock synchronization with higher accuracy.
  • the The Announce message may also carry the hop count from the first master clock node to the first clock source node, and the Announce message from the second master clock node may also carry the hop count from the second master clock node to the second clock source node, By comparing the number of hops from the first master clock node to the first clock source node and the number of hops from the second master clock node to the second clock source node, the master clock node for the network device to perform clock synchronization can be selected.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • the second possible implementation manner the network device determines the third maximum clock deviation accumulated value and the fourth maximum clock deviation accumulated value, and compares the third maximum clock deviation accumulated value with the fourth maximum clock deviation accumulated value. When the accumulated maximum clock deviation value is less than the fourth accumulated maximum clock deviation value, the network device determines the first master clock node as the master clock node for clock synchronization; when the third accumulated maximum clock deviation value is greater than the fourth accumulated maximum clock deviation value , The network device determines the second master clock node as the master clock node for clock synchronization.
  • the third maximum accumulated clock deviation refers to the sum of the maximum accumulated clock deviation corresponding to the transmission medium between the first master clock node and the network device and the first accumulated accumulated maximum clock deviation
  • the fourth accumulated accumulated maximum clock deviation It refers to the sum of the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device and the cumulative value of the second maximum clock deviation.
  • the maximum clock deviation of the transmission medium between two adjacent clock nodes can be saved to any one of the two clock nodes. That is, the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device may be saved in the first master clock node or the network device. Similarly, the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device can be saved in the second master clock node or in the network device.
  • the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device is saved in the first master clock node
  • the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device is saved in the second In the master clock node
  • the cumulative value of the first clock deviation carried in the Announce message from the first master clock node contains the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device.
  • the accumulated value of the second clock deviation carried in the Announce message of the second master clock node includes the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device. In this case, the first maximum clock deviation accumulated value can be directly compared with the second maximum clock deviation accumulated value.
  • the network device compares the first The master clock node is determined as the master clock node for clock synchronization; when the first accumulated maximum clock deviation value is greater than the second accumulated maximum clock deviation value, the network device determines the second master clock node as the master clock node for clock synchronization.
  • the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device is saved in the network device
  • the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device is saved in the network device
  • the cumulative value of the first clock deviation carried in the Announce message from the first master clock node does not include the maximum clock deviation corresponding to the transmission medium between the first master clock node and the network device.
  • the cumulative value of the second clock deviation carried in the Announce message of the clock node does not include the maximum clock deviation corresponding to the transmission medium between the second master clock node and the network device.
  • the network device determines the first master clock node as the master clock node for clock synchronization; when the third accumulated maximum clock deviation value is greater than the fourth accumulated maximum clock deviation value, the network The device determines the second master clock node as the master clock node for clock synchronization.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the third maximum clock deviation accumulated value is greater than the fourth maximum clock deviation accumulated value, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node. In this case, the network device determines the second master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the third maximum clock deviation cumulative value will be described below by way of example:
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the maximum clock deviation 104
  • the network device 105 corresponds to the maximum clock deviation 105
  • the transmission medium n between the network device 104 and the network device 105 also corresponds to the maximum clock deviation n
  • the transmission medium m between them corresponds to the maximum clock deviation m, that is, there are four first maximum clock deviations on the path from the network device 103 to the network device 105, namely the maximum clock deviation 104, the maximum clock deviation 105, and the maximum clock deviation n and the maximum clock deviation m.
  • the first maximum clock deviation accumulated value is the sum of the maximum clock deviation 104, the first maximum clock deviation 105, and the first maximum clock deviation n
  • the third maximum clock deviation accumulated value is the maximum clock deviation m and the first maximum The sum of accumulated clock deviations.
  • the The Announce message may also carry the hop count from the first master clock node to the first clock source node, and the Announce message from the second master clock node may also carry the hop count from the second master clock node to the second clock source node, By comparing the number of hops from the first master clock node to the first clock source node and the number of hops from the second master clock node to the second clock source node, the master clock node for the network device to perform clock synchronization can be selected.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • S304 The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • calibrating the clock of the network device is to set the clock of the network device to the same clock as the clock of the selected master clock node, and the clock synchronization may include time synchronization and frequency synchronization.
  • the specific implementation manner of S304 may include: the network device and the master clock node perform communication using PTP messages according to IEEE1588-2008.
  • PTP messages include Sync messages, Delay_req messages, and Delay_resp messages.
  • Time information is carried in PTP messages.
  • the time information may be time stamp 1, time stamp 2, time stamp 3, and time stamp 4.
  • the network device can use the time information to calculate the time deviation between the network device and the master clock node.
  • the network device calibrates the time of the clock of the network device according to the time deviation.
  • the network device may use the time information to calculate the frequency deviation of the network device from the master clock node.
  • the network device calibrates the frequency of the clock of the network device according to the frequency deviation.
  • the network device can only calibrate the time.
  • the network device can only calibrate the frequency.
  • Network devices can also calibrate time and frequency.
  • For the process of the network device acquiring time information reference may be made to the description of the network device 104 acquiring time stamp 1, time stamp 2, time stamp 3, and time stamp 4 above.
  • the specific implementation of the network device calibrating the frequency of the clock of the network device according to the frequency deviation may include: the clock of the network device may include a voltage source and a crystal oscillator. The output voltage of the voltage source acts on the crystal oscillator. The higher the output voltage of the voltage source, the higher the operating frequency of the crystal oscillator.
  • the network device may include a central processing unit. The central processing unit can control the output voltage of the voltage source. Furthermore, the central processing unit can calibrate the frequency of the clock of the network device by controlling the output voltage of the voltage source. Specifically, the central processing unit may determine the voltage adjustment value 1 according to the frequency deviation.
  • the network device also includes a memory coupled to the central processing unit. The correspondence between the frequency deviation and the voltage adjustment value can be stored in the memory.
  • the central processing unit may search for the voltage adjustment value corresponding to the first frequency deviation, that is, the voltage adjustment value 1, by accessing the memory.
  • the output voltage of the voltage source is the voltage value 1.
  • the central processing unit determines the voltage adjustment value 1, it can adjust the output voltage of the voltage source to the voltage value 2 according to the voltage adjustment value 1.
  • the voltage value 2 is equal to the sum of the voltage value 1 and the voltage adjustment value 1. Therefore, if the voltage adjustment value 1 is a positive number, it means that the frequency of the clock of the network device is lower than the frequency of the master clock node.
  • the central processing unit can calibrate the clock frequency of the network device by increasing the operating frequency of the crystal oscillator. If the voltage adjustment value 1 is a negative number, it means that the frequency of the network device's clock is higher than the frequency of the master clock node.
  • the central processing unit can calibrate the clock frequency of the network device by reducing the operating frequency of the crystal oscillator.
  • the specific implementation manner of the network device calibrating the time of the clock of the network device according to the time deviation may include: the clock of the network device includes a crystal oscillator and a counter.
  • the counter may specifically be an accumulator.
  • the counter can contain a memory.
  • the value stored in the memory is equal to the current time recorded by the clock.
  • the crystal oscillator can output a pulse signal to the counter every working cycle.
  • the counter detects the rising or falling edge of the pulse signal, the counter adds the increment to the value stored in the memory to update the value stored in the memory.
  • the increment is equal to the crystal's nominal duty cycle.
  • the nominal operating frequency of a crystal oscillator may be 125 Megahertz (Mega Hertz, MHz).
  • the nominal duty cycle of the crystal can be 8 nanoseconds.
  • the central processing unit of the network device may update the value stored in the memory included in the counter according to the time deviation, thereby updating the time of the clock of the network device.
  • the clock time of the network device can be calibrated.
  • the master clock node that can perform clock synchronization with the network device can be determined according to the sizes of the identifiers of the two clock source nodes .
  • the master clock node corresponding to the clock source node with the smaller identifier is used as the master clock node for the network device to perform clock synchronization, so that the network device performs clock synchronization with higher accuracy.
  • the identifier of the first clock source node is smaller than the identifier of the second clock source node, it indicates that the accuracy of clock synchronization by the first master clock node is higher than the accuracy of clock synchronization by the second master clock node.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the identifier of the first clock source node is greater than the identifier of the second clock source node, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • the Announce message from the first master clock node may also carry the clock level of the first clock source node
  • the Announce message from the second master clock node may also carry the clock level of the second clock source node.
  • Step (1) The network device compares the clock level of the first clock source node with the clock level of the second clock source node. When the clock level of the first clock source node is equal to the clock level of the second clock source node, the network device Determine whether the clock level of the first clock source node is less than or equal to 127. When the clock level of the first clock source node is greater than 127, return to S302.
  • the clock level of the clock source node is used to indicate the clock level of the clock source node, and the smaller the value of the clock level of the clock source node, the higher the clock level of the corresponding clock source node.
  • the clock level of the first clock source node is equal to the clock level of the second clock source node, it indicates that the clock level of the first clock source node is the same as the clock level of the second clock source node. At this time, it can be determined whether the clock level of the first clock source node is less than or equal to 127.
  • the clock level of the first clock source node is equal to the clock level of the second clock source node, it is determined whether the clock level of the first clock source node Less than or equal to 127 is to determine whether the clock level of the second clock source node is less than or equal to 127.
  • the clock level of the first clock source node is greater than 127, it indicates that the first clock source node can be used not only as a clock source node tracked by other slave clock nodes, but also as a tracking other clock source node Slave clock node.
  • the network device may return to the above S302 to continue to compare the identifier of the first clock source node and the identifier of the second clock source node.
  • Step (2) When the clock level of the first clock source node is less than or equal to 127, the network device selects from the first master clock node and the second master clock according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value Among the nodes, select the master clock node for clock synchronization.
  • the clock level of the first clock source node is less than or equal to 127, that is, the clock level of the second clock source node is less than or equal to 127, it means that the first clock source node can only be used as a slave clock node A clock source node that is tracked, but not a slave clock node that tracks other clock source nodes.
  • the clock level of the first clock source node is less than or equal to 127, it indicates that the second clock source node can only be used as a clock source node tracked by other slave clock nodes, but not as a slave clock node tracking other clock source nodes.
  • the network device can select the master clock node for clock synchronization from the first master clock node and the second master clock node based on the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value, and the network device
  • the process of selecting the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value from the first master clock node and the second master clock node to select the master clock node for clock synchronization is similar to the corresponding process in S303 above, here No longer.
  • Step (3) The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • step (3) is similar to the above S304 and will not be repeated here.
  • the network device first receives the Announce message from the first master clock node and the Announce message from the second master clock node, and the Announce message from the first master clock node carries the first clock source node’s The identifier and the accumulated value of the first maximum clock deviation.
  • the Announce message from the second master clock node carries the identifier of the second clock source node and the accumulated value of the second maximum clock deviation.
  • the network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the identifier of the first clock source node When the identifier of the first clock source node is the same as the identifier of the second clock source node, it indicates that the first master clock node and The second master clock node corresponds to the same clock source node. At this time, it is helpful to select a clock source from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value The master clock node with a smaller clock deviation on the path from the node to the master clock node, and then calibrate the clock of the network device according to the time information of the selected master clock node. If the clock deviation caused by the path from the clock source node to the master clock node is small, the accuracy of clock synchronization by the master clock node is higher, which in turn makes the accuracy of the clock after the network device calibration higher.
  • FIG. 4 is a flowchart of a second clock synchronization method provided by an embodiment of the present application, and the method is applied to a network device. Referring to Figure 4, the method includes:
  • the network device receives the Announce message from the first master clock node and the Announce message from the second master clock node.
  • the Announce message from the first master clock node carries the identifier of the first clock source node and the first maximum clock Cumulative deviation value
  • the Announce message from the second master clock node carries the identifier of the second clock source node and the cumulative value of the second maximum clock deviation.
  • the network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the network device selects from the first master clock node and the second master according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value Among the clock nodes, select the main clock node for clock synchronization.
  • S401 to S403 in this embodiment is similar to the content of S301 to S303 in the foregoing embodiment.
  • specific implementation manners of S401 to S403 reference may be made to the description of S301 to S303 in the embodiment, and details are not described herein again.
  • the network device selects to perform the clock
  • the method of synchronizing the master clock node is different from that of the above embodiment, and this case will be described in detail below.
  • the Announce message from the first master clock node can also carry the first clock variance value
  • the Announce message from the second master clock node also carries the second clock variance value.
  • the first clock variance value refers to the square root of the sum of squares of multiple first clock deviation variance values
  • the second clock variance value refers to the square root of the sum of squares of multiple second clock deviation variance values.
  • the first clock deviation variance value may refer to the variance values of multiple clock deviations corresponding to one clock node on the path from the first clock source node to the first master clock node.
  • the second clock deviation variance value may refer to a path from the second clock source node to the second master clock node The variance value of multiple clock deviations corresponding to one clock node. That is, each clock node on the path from the first clock source node to the first master clock node corresponds to multiple clock deviations.
  • the variance value of the multiple clock deviations is the first clock deviation variance value.
  • Each clock node on the path from the second clock source node to the second master clock node corresponds to multiple clock deviations
  • the variance value of the multiple clock deviations is the second clock deviation variance value.
  • the multiple first clock deviation variance values correspond to the multiple clock nodes on the path from the first clock source node to the first master clock node
  • the multiple second clock deviation variance values correspond to the second clock
  • the clock deviation may be a jump amplitude deviation, a jitter deviation and a static deviation of the clock node.
  • the maximum clock deviation of the clock node that is, the maximum clock deviation of the clock node may be the sum of the maximum jump amplitude deviation, the maximum jitter deviation and the maximum static deviation, or the maximum jitter deviation and the maximum static deviation. Sum. Therefore, similarly, the first clock deviation variance value of the clock node may be the variance value of the jump amplitude deviation, jitter deviation and static deviation of the clock node, or may be the square of the jitter deviation and static deviation of the clock node Difference.
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the first clock deviation variance value 104
  • the network device 105 corresponds to the first clock deviation variance value 105.
  • the first clock variance value is the square root of the sum of the squares of the first clock deviation variance value 104 and the first clock deviation variance value 105.
  • the multiple first clock deviation variance values include the multiple clock deviation variance values corresponding to each clock node on the path from the first clock source node to the first master clock node, and the first clock source node to the first A variance value of a plurality of clock deviations corresponding to a transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on a path of a master clock node.
  • the multiple second clock deviation variance values include multiple clock deviation variance values corresponding to each clock node on the path from the second clock source node to the second master clock node, and the second clock source node to the second master A variance value of a plurality of clock deviations corresponding to a transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on the path of the clock node. That is, each clock node on the path from the first clock source node to the first master clock node corresponds to a clock deviation variance value, and transmission between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes The medium corresponds to a clock deviation variance value, which may be referred to as a first clock deviation variance value.
  • each clock node on the path from the second clock source node to the second master clock node corresponds to a clock deviation variance value
  • the transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes Corresponding to a clock deviation variance value, it may be referred to as a second clock deviation variance value.
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the first clock deviation variance value 104
  • the network device 105 corresponds to the first clock deviation variance value 105
  • the transmission medium n between the network device 104 and the network device 105 corresponds to the first clock deviation The variance value n.
  • the first clock variance value is the square root of the sum of squares of the first clock deviation variance value 104, the first clock deviation variance value 105, and the first clock deviation variance value n.
  • the concept of the first clock variance value and the second clock variance value is different in two different cases. Therefore, according to the first clock variance value and the second clock variance value, the implementation manner of selecting the master clock node for clock synchronization from the first master clock node and the second master clock node will also be different. Next, the selection of the master clock node will be described in two possible implementation modes. The first possible implementation manner corresponds to the first case of this step, and the second possible implementation manner corresponds to the second case of this step.
  • the first possible implementation manner the network device compares the first clock variance value with the second clock variance value, and when the first clock variance value is less than the second clock variance value, the network device compares the first master clock The node is determined as the master clock node for clock synchronization; when the first clock variance value is greater than the second clock variance value, the network device determines the second master clock node as the master clock node for clock synchronization.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the network device may determine the second master clock node as the master clock node for clock synchronization, which may make the network device perform clock synchronization with higher accuracy.
  • the Announce message from the first master clock node can also carry the hop count from the first master clock node to the first clock source node
  • the Announce message from the second master clock node can also carry The number of hops from the second master clock node to the second clock source node, by comparing the number of hops from the first master clock node to the first clock source node, and the number of hops from the second master clock node to the second clock source node, You can select the master clock node that the network device synchronizes with.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • the second possible implementation manner the network device determines the third clock variance value and the fourth clock variance value, and the network device compares the third clock variance value with the fourth clock variance value, when the third clock side When the difference is less than the fourth clock variance value, the network device determines the first master clock node as the master clock node for clock synchronization; when the third clock variance value is greater than the fourth clock variance value, the network device sets the second The master clock node is determined as the master clock node for clock synchronization.
  • the third clock variance value is the square root of the sum of squares of the variance values of multiple clock deviations corresponding to the transmission medium between the first master clock node and the network device and the first clock variance value.
  • the fourth clock variance value is the square root of the sum of squares of the variance values of multiple clock deviations corresponding to the transmission medium between the second master clock node and the network device and the second clock variance value.
  • the transmission medium between the first master clock node and the network device corresponds to the variance of multiple clock deviations
  • the value is saved in the first master clock node, and the variance value of the multiple clock deviations corresponding to the transmission medium between the second master clock node and the network device is saved in the second master clock node, at this time, from the first master clock
  • the first clock deviation variance value carried in the Announce message of the node is the result obtained by considering the variance values of multiple clock deviations corresponding to the transmission medium between the first master clock node and the network device, and comes from the second master
  • the second clock deviation variance value carried in the Announce message of the clock node is the result obtained by considering the variance values of multiple clock deviations corresponding to the transmission medium between the second master clock node and the network device.
  • the network device determines the second master clock node as the master clock node for clock synchronization.
  • the multiple clocks corresponding to the transmission medium between the second master clock node and the network device are saved to the network device, the multiple clocks corresponding to the transmission medium between the second master clock node and the network device The deviation variance value is saved in the network device.
  • the transmission between the first master clock node and the network device is not considered in the first clock deviation variance value carried in the Announce message from the first master clock node
  • the variance value of multiple clock deviations corresponding to the medium, the second clock deviation variance value carried in the Announce message from the second master clock node does not consider the transmission medium correspondence between the second master clock node and the network device The variance value of multiple clock deviations.
  • the network device determines the first master clock node as the master clock node for clock synchronization; when the third clock variance value is greater than the fourth clock variance value, the network device sets the second master clock The node is determined as the master clock node for clock synchronization.
  • the network device determines the first master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the third clock variance value is greater than the fourth clock variance value, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node. In this case, the network device determines the second master clock node as the master clock node for clock synchronization, which can make the network device perform clock synchronization with higher accuracy.
  • the network device 103 is the first clock source node.
  • the path from the network device 103 to the network device 105 further includes the network device 104.
  • the network device 104 corresponds to the first clock deviation variance value 104
  • the network device 105 corresponds to the first clock deviation variance value 105
  • the transmission medium n between the network device 104 and the network device 105 corresponds to the first clock deviation square
  • the difference n, the transmission medium m between the network device 105 and the network device 111 corresponds to the first clock deviation variance value m.
  • the first clock variance value is the square root of the square sum of the first clock deviation variance value 104, the first clock deviation variance value 105, and the first clock deviation variance value n
  • the third clock variance is the first The square root of the sum of squares of the one clock deviation variance value m and the first clock variance value.
  • the Announce message from the first master clock node can also carry the hop count from the first master clock node to the first clock source node
  • the Announce message from the second master clock node can also carry the The number of hops from the two main clock nodes to the second clock source node can be determined by comparing the number of hops from the first main clock node to the first clock source node and the number of hops from the second main clock node to the second clock source node Select the master clock node of the network device for clock synchronization.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • S405 The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • the master clock node that can perform clock synchronization with the network device can be determined according to the sizes of the identifiers of the two clock source nodes .
  • the master clock node corresponding to the clock source node with the smaller identifier is used as the master clock node for the network device to perform clock synchronization, so that the network device performs clock synchronization with higher accuracy.
  • the identifier of the first clock source node is smaller than the identifier of the second clock source node, it indicates that the accuracy of clock synchronization by the first master clock node is higher than the accuracy of clock synchronization by the second master clock node.
  • the network device may determine the first master clock node as the master clock node for clock synchronization.
  • the identifier of the first clock source node is greater than the identifier of the second clock source node, it indicates that the accuracy of clock synchronization by the second master clock node is higher than the accuracy of clock synchronization by the first master clock node.
  • the network device may determine the second master clock node as the master clock node for clock synchronization.
  • the Announce message from the first master clock node may also carry the clock level of the first clock source node
  • the Announce message from the second master clock node may also carry the clock level of the second clock source node.
  • a master clock node that can perform clock synchronization with the network device can also be determined through the following steps A-D.
  • Step A The network device compares the clock level of the first clock source node with the clock level of the second clock source node. When the clock level of the first clock source node is equal to the clock level of the second clock source node, the network device determines Whether the clock level of a clock source node is less than or equal to 127, and when the clock level of the first clock source node is greater than 127, return to S402.
  • Step B When the clock level of the first clock source node is less than or equal to 127, the network device selects from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value Select the master clock node for clock synchronization.
  • step A-step B in this embodiment is basically the same as the content of step (1)-step (2) in the above embodiment, and will not be repeated here.
  • Step C When the accumulated value of the first maximum clock deviation is equal to the accumulated value of the second maximum clock deviation, the network device selects from the first master clock node and the second master clock node according to the first clock variance value and the second clock variance value Select the master clock node for clock synchronization.
  • step C is similar to the above S404 and will not be repeated here.
  • Step D The network device calibrates the clock of the network device according to the time information of the selected master clock node.
  • step D is similar to the above S304 and will not be repeated here.
  • the network device first receives the Announce message from the first master clock node and the Announce message from the second master clock node, and the Announce message from the first master clock node carries the first clock source node’s The identifier, the first accumulated maximum clock deviation value and the first clock variance value, the Announce message from the second master clock node carries the identifier of the second clock source node, the second largest clock deviation accumulated value and the second clock variance value . The network device then compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the network device selects clock synchronization from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value The main clock node.
  • the network device selects from the first master clock node and the second master clock node according to the first clock variance value and the second clock variance value The master clock node for clock synchronization.
  • the network device calibrates the clock of the network device according to the time information of the selected master clock node. If the clock deviation caused by the path from the clock source node to the master clock node is small, the accuracy of clock synchronization by the master clock node is higher, which in turn makes the accuracy of the clock after the network device calibration higher.
  • FIG. 5 is a schematic structural diagram of a clock synchronization device provided by an embodiment of the present application.
  • the clock synchronization device may be implemented as part or all of a computer device by software, hardware, or a combination of the two.
  • the clock synchronization device is applied to the network device
  • the network device may be the network device shown in FIG. 2.
  • the device includes: a receiving module 501, a first comparison module 502, a selection module 503 and a first calibration module 504.
  • the receiving module 501 is used to perform the operation in S301 or the operation in S401;
  • the first comparison module 502 is used to perform the operation in S302 or the operation in S402;
  • the selection module 503 is used to perform the operation in S303 or the operation in S403;
  • the first calibration module 504 is used to perform the operation in S304.
  • the plurality of first maximum clock deviations refer to the plurality of maximum clock deviations corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, respectively.
  • a second maximum clock deviation refers to a plurality of maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, respectively.
  • the Announce message from the first master clock node also carries the clock level of the first clock source node
  • the Announce message from the second master clock node also carries the second clock source node 'S clock level
  • the device also includes:
  • a second comparison module configured to compare the clock level of the first clock source node with the clock level of the second clock source node
  • the determining module is configured to determine whether the clock level of the first clock source node is less than or equal to 127 when the clock level of the first clock source node is equal to the clock level of the second clock source node;
  • the first comparison module 502 includes:
  • the first comparison submodule is configured to compare the identifier of the first clock source node and the identifier of the second clock source node when the clock level of the first clock source node is greater than 127.
  • the device further includes:
  • the selection module 503 is further configured to, when the clock level of the first clock source node is less than or equal to 127, according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value, select from the first Select a master clock node for clock synchronization from the master clock node and the second master clock node;
  • the second calibration module is used to calibrate the clock of the clock synchronization device according to the time information of the selected master clock node.
  • the plurality of first maximum clock deviations refer to the plurality of maximum clock deviations corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, respectively.
  • a second maximum clock deviation refers to a plurality of maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, respectively.
  • the selection module 503 includes:
  • a second comparison submodule configured to compare the first maximum clock deviation accumulated value with the second maximum clock deviation accumulated value
  • the first determining submodule is configured to determine the first master clock node as the master clock node for clock synchronization when the first accumulated maximum clock deviation value is less than the second accumulated maximum clock deviation value.
  • the Announce message from the first master clock node also carries a first clock variance value
  • the Announce message from the second master clock node also carries a second clock variance value
  • the first The clock variance value refers to the square root of the sum of squares of multiple first clock deviation variance values
  • the second clock variance value refers to the square root of the sum of squares of multiple second clock deviation variance values.
  • the clock deviation variance value refers to the variance value of multiple clock deviations corresponding to one clock node on the path from the first clock source node to the first master clock node
  • the second clock deviation variance value is Refers to the variance values of multiple clock deviations corresponding to one clock node on the path from the second clock source node to the second master clock node;
  • the device also includes:
  • a third comparison module configured to compare the first clock variance value with the second clock variance value when the first maximum clock deviation cumulative value is equal to the second maximum clock deviation cumulative value
  • the first determining module is configured to determine the first master clock node as the master clock node for clock synchronization when the first clock variance value is less than the second clock variance value.
  • the plurality of first maximum clock deviations refer to the plurality of maximum clock deviations respectively corresponding to the plurality of clock nodes on the path from the first clock source node to the first master clock node, and the At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes in the plurality of clock nodes on the path from the first clock source node to the first master clock node
  • the plurality of second The maximum clock deviation refers to a plurality of maximum clock deviations corresponding to multiple clock nodes on the path from the second clock source node to the second master clock node, and the second clock source node to the second At least one maximum clock deviation corresponding to the transmission medium between at least one pair of adjacent clock nodes among the multiple clock nodes on the path of the master clock node, respectively.
  • the selection module 503 includes:
  • the second determining submodule is used to determine a third maximum clock deviation accumulated value and a fourth maximum clock deviation accumulated value, where the third maximum clock deviation accumulated value refers to the difference between the first master clock node and the clock synchronization device The sum of the maximum clock deviation corresponding to the transmission medium between the first maximum clock deviation cumulative value and the fourth maximum clock deviation cumulative value refers to the transmission between the second master clock node and the clock synchronization device The sum of the maximum clock deviation corresponding to the medium and the cumulative value of the second maximum clock deviation;
  • a third comparison submodule configured to compare the third maximum clock deviation accumulated value with the fourth maximum clock deviation accumulated value
  • the third determining submodule is configured to determine the first master clock node as a master clock node for clock synchronization when the third accumulated maximum clock deviation value is less than the fourth accumulated maximum clock deviation value.
  • the Announce message from the first master clock node also carries a first clock variance value
  • the Announce message from the second master clock node also carries a second clock variance value
  • the first The clock variance value refers to the square root of the sum of squares of multiple first clock deviation variance values
  • the second clock variance value refers to the square root of the sum of squares of multiple second clock deviation variance values.
  • the first clock deviation variance value includes a plurality of clock deviation variance values corresponding to each clock node on the path from the first clock source node to the first master clock node, and the first clock source node A variance value of a plurality of clock deviations corresponding to a transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on the path to the first master clock node, the The multiple second clock deviation variance values include multiple clock deviation variance values corresponding to each clock node on the path from the second clock source node to the second master clock node, and the second clock A variance value of a plurality of clock deviations corresponding to the transmission medium between each pair of adjacent clock nodes in at least one pair of adjacent clock nodes on the path from the source node to the second master clock node;
  • the device also includes:
  • a second determining module configured to determine a third clock variance value and a fourth clock variance value when the third maximum clock deviation cumulative value is equal to the fourth maximum clock deviation cumulative value, the third clock square The difference is the square root of the sum of the squares of the variances of the multiple clock deviations corresponding to the transmission medium between the first master clock node and the clock synchronization device, and the fourth The clock variance value is the square root of the sum of squares of the variances of multiple clock deviations corresponding to the transmission medium between the second master clock node and the clock synchronization device and the second clock variance value;
  • a fourth comparison module configured to compare the third clock variance value with the fourth clock variance value
  • the third determining module is configured to determine the first master clock node as the master clock node for clock synchronization when the third clock variance value is less than the fourth clock variance value.
  • the network device first receives the Announce message from the first master clock node and the Announce message from the second master clock node, and the Announce message from the first master clock node carries the first clock source node’s The identifier and the accumulated value of the first maximum clock deviation.
  • the Announce message from the second master clock node carries the identifier of the second clock source node and the accumulated value of the second maximum clock deviation.
  • the network device compares the identifier of the first clock source node with the identifier of the second clock source node.
  • the identifier of the first clock source node When the identifier of the first clock source node is the same as the identifier of the second clock source node, it indicates that the first master clock node and The second master clock node corresponds to the same clock source node. At this time, it is helpful to select a clock source from the first master clock node and the second master clock node according to the first maximum clock deviation accumulated value and the second maximum clock deviation accumulated value The master clock node with a smaller clock deviation on the path from the node to the master clock node, and then calibrate the clock of the network device according to the time information of the selected master clock node. If the clock deviation caused by the path from the clock source node to the master clock node is small, the accuracy of clock synchronization by the master clock node is higher, which in turn makes the accuracy of the clock after the network device calibration higher.
  • the clock synchronization device provided in the above embodiments only uses the division of the above functional modules as examples for clock synchronization. In practical applications, the above functions can be allocated by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the clock synchronization device and the clock synchronization method embodiment provided in the above embodiments belong to the same concept. For the specific implementation process, see the method embodiment, and details are not described here.
  • the computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be from a website site, computer, server or data center Transmit to another website, computer, server or data center by wired (for example: coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (for example: infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server, a data center, or the like that includes one or more available medium integrations.
  • the available media may be magnetic media (for example: floppy disk, hard disk, magnetic tape), optical media (for example: Digital Versatile Disc (DVD)) or semiconductor media (for example: Solid State Disk (SSD)) Wait.

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Abstract

本申请公开了一种时钟同步方法、装置和存储介质，属于通信技术领域。所述方法包括：网络设备先接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，当第一主时钟节点的Announce报文中携带的第一时钟源节点的标识与第二主时钟节点的Announce报文中携带的第二时钟源节点的标识相同时，从第一主时钟节点和第二主时钟节点中选择带来的时钟偏差较小的主时钟节点，再根据该主时钟节点的时间信息校准该网络设备的时钟。本申请选择时钟偏差较小的主时钟节点作为网络设备进行时钟同步的主时钟节点，使得该网络设备进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。

Description

时钟同步方法、装置和存储介质
本申请要求于2018年12月29日提交中国国家知识产权局、申请号为201811645611.6、申请名称为“时钟同步方法、装置和存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别涉及一种时钟同步方法、装置和存储介质。
背景技术
随着电信网络的不断发展，电信网络对时钟同步的精确度要求越来越高，使得越来越多的精准时钟同步协议应运而生。其中，G.8275.1协议是一种由国际电信联盟电信标准分局(International Telecommunication Union-Telecommunication Standardization Sector，ITU-T)基于IEEE 1588协议定义的适用于电信应用的协议。G.8275.1协议明确了时钟同步网络中的各时钟节点的互操作性所必需的IEEE 1588协议的功能，在遵循G.8275.1协议的时钟同步网络中，通常包括至少一个时钟源节点和多个时钟节点。对于该多个时钟节点中的任一时钟节点，该时钟节点可以与一个或多个上游网络设备连接，此时，该上游网络设备可以称为主时钟节点。对于连接有多个主时钟节点的情况，往往需要从该多个主时钟节点中选择一个主时钟节点来进行时钟同步。
G.8275.1协议定义了一种主时钟节点的选择算法。该选择算法也可以称为备选最佳主时钟算法(Alternative-Best Master Clock Algorithm，A-BMCA)。当一个时钟节点连接有多个主时钟节点时，该时钟节点会接收到分别来自该多个主时钟节点的多个通知(Announce)报文(message)。每个Announce报文中携带位于主时钟节点的上游的时钟源节点的时钟等级、时钟精度、时钟方差、第二优先级、时钟本地优先级、时钟源节点的标识，以及主时钟节点到位于上游的时钟源节点的跳数。通过A-BMCA对接收到的不同的Announce报文中携带的时钟等级、时钟精度、时钟方差、第二优先级、以及时钟本地优先级这些字段进行比较。如果一个Announce报文中携带的上述这些字段与另一个Announce报文中携带的上述这些字段分别相同，则可以判断接收到的不同的Announce报文中携带的时钟等级是否小于或等于127。如果不同的Announce报文中的时钟等级均小于或等于127，则对该多个主时钟节点到位于上游的时钟源节点的跳数进行比较，并选择对应较小跳数的主时钟节点进行时钟同步。如果时钟等级均大于127，则可以判断接收到的Announce报文中携带的时钟源节点的标识是否相同。如果相同，则对该多个主时钟节点到位于上游的时钟源节点的跳数进行比较，并选择对应较小跳数的主时钟节点进行时钟同步。然而，通过跳数选择出的主时钟节点的精确度可能并不高，从而降低了时钟同步的精确度。
发明内容
本申请提供了一种时钟同步方法、装置和存储介质，可以解决相关技术中网络设备选 择主时钟节点精度不高，从而降低网络设备进行时钟同步的精确度的问题。所述技术方案如下：
第一方面，提供了一种时钟同步方法，所述方法包括：网络设备接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自所述第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自所述第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值；所述网络设备将所述第一时钟源节点的标识与所述第二时钟源节点的标识进行比较；当所述第一时钟源节点的标识与所述第二时钟源节点的标识相同时，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；所述网络设备根据选择的主时钟节点的时间信息校准所述网络设备的时钟。
需要说明的是，网络设备可以是时钟同步网络中连接有至少两个主时钟节点的设备。Announce报文是一种由精确时钟协议(Precision Time Protocol，PTP)定义的报文。第一时钟源节点的标识是用于唯一指示第一时钟源节点的标识。第二时钟源节点的标识是用于唯一指示第二时钟源节点的标识。第一最大时钟偏差累计值是第一时钟源节点到第一主时钟节点的路径上的多个第一最大时钟偏差之和，第二最大时钟偏差累计值是第二时钟源节点到第二主时钟节点的路径上的多个第二最大时钟偏差之和。校准网络设备的时钟即是将该网络设备的时钟的参数设置为与选择的主时钟节点的时钟的参数相同。时钟的参数可以是时钟的时间、时钟的频率、或者时钟的时间以及频率。
在本申请实施例中，该网络设备可以先将第一时钟源节点的标识与第二时钟源节点的标识进行比较，当第一时钟源节点的标识与第二时钟源节点的标识相同时，表明第一主时钟节点和第二主时钟节点对应着同一个时钟源节点。此时，该网络设备再根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。该网络设备根据选择的主时钟节点的时间信息校准网络设备的时钟。
可选地，来自所述第一主时钟节点的Announce报文还携带所述第一时钟源节点的时钟等级，来自所述第二主时钟节点的Announce报文还携带所述第二时钟源节点的时钟等级；所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较之前，所述方法还包括：所述网络设备将所述第一时钟源节点的时钟等级与所述第二时钟源节点的时钟等级进行比较；当所述第一时钟源节点的时钟等级等于所述第二时钟源节点的时钟等级时，所述网络设备判断所述第一时钟源节点的时钟等级是否小于或等于127；所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较，包括：当所述第一时钟源节点的时钟等级大于127时，所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较。
需要说明的是，时钟源节点的时钟等级用于指示时钟源节点的时钟级别，且时钟源节点的时钟等级的数值越小其所对应的时钟源节点的时钟级别越高。当第一时钟源节点的时钟等级等于第二时钟源节点的时钟等级时，表明第一时钟源节点的时钟级别与第二时钟源节点的时钟级别相同。此时，可以判断第一时钟源节点的时钟等级是否小于或等于127，由于第一时钟源节点的时钟等级与第二时钟源节点的时钟等级相等，所以判断第一时钟源 节点的时钟等级是否小于或等于127也即是判断第二时钟源节点的时钟等级是否小于或等于127。在一种可能的实现方式中，当第一时钟源节点的时钟等级大于127时，表明第一时钟源节点不仅可以作为被其他从时钟节点跟踪的时钟源节点，还可以作为跟踪其他时钟源节点的从时钟节点。同理，当第二时钟源节点的时钟等级大于127时，表明第二时钟源节点不仅可以作为被其他从时钟节点跟踪的时钟源节点，还可以作为跟踪其他时钟源节点的从时钟节点。
可选地，所述网络设备判断所述第一时钟源节点的时钟等级是否小于或等于127之后，所述方法还包括：当所述第一时钟源节点的时钟等级小于或等于127时，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；所述网络设备根据选择的主时钟节点的时间信息校准所述网络设备的时钟。
需要说明的是，当第一时钟源节点的时钟等级小于或等于127时，也即第二时钟源节点的时钟等级小于或等于127时，表明第一时钟源节点只能作为被其他从时钟节点跟踪的时钟源节点，而不能作为跟踪其他时钟源节点的从时钟节点。同理，当第一时钟源节点的时钟等级小于或等于127时，表明第二时钟源节点只能作为被其他从时钟节点跟踪的时钟源节点，而不能作为跟踪其他时钟源节点的从时钟节点。
可选地，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。
需要说明的是，第一时钟源节点与第一主时钟节点之间可能存在多条路径，第一时钟源节点到第一主时钟节点的路径上的多个时钟节点可以是位于该多条路径上的多个时钟节点。类似地，第二时钟源节点与第二主时钟节点之间可能存在多条路径，第二时钟源节点到第二主时钟节点的路径上的多个时钟节点可以是指位于该多条路径上的多个时钟节点。并且，第一时钟源节点到第一主时钟节点的路径上的多个时钟节点可以包括第一主时钟节点，且不包括第一时钟源节点。类似地，第二时钟源节点到第二主时钟节点的路径上的多个时钟节点可以包括第二主时钟节点，且不包括第二时钟源节点。
可选地，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点，包括：所述网络设备将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较；当所述第一最大时钟偏差累计值小于所述第二最大时钟偏差累计值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，将第一最大时钟偏差累计值和第二最大时钟偏差累计值进行比较。当第一最大时钟偏差累计值小于第二最大时钟偏差累计值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。当第一最大时钟偏差累计值大于第二最大时钟偏差累计值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点，可以 使该网络设备进行时钟同步的精确度更高。
在本申请实施例中，时钟源节点到主时钟节点的路径上带来的时钟偏差越小，通过该主时钟节点进行时钟同步的精确度越高。所以可以将第一主时钟节点的第一最大时钟偏差累计值与第二主时钟节点的第二最大时钟偏差累计值的大小进行比较，选择其中较小的一项对应的主时钟节点作为网络设备进行时钟同步的主时钟节点可以使网络设备进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。
可选地，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述网络设备将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较之后，所述方法还包括：当所述第一最大时钟偏差累计值等于所述第二最大时钟偏差累计值时，所述网络设备将所述第一时钟方差值与所述第二时钟方差值进行比较；当所述第一时钟方差值小于所述第二时钟方差值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根。第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根。第一时钟偏差方差值是指第一时钟源节点到第一主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值。第二时钟偏差方差值是指第二时钟源节点到第二主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值。
在本申请实施例中，当第一时钟方差值小于第二时钟方差值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。类似地，当第一时钟方差值大于第二时钟方差值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
可选地，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。
需要说明的是，第一时钟源节点到第一主时钟节点的路径上的一对相邻时钟节点是指第一时钟源节点到第一主时钟节点的路径上可以直接进行Announce报文交互的两个时钟节点。类似地，第二时钟源节点到第二主时钟节点的路径上的一对相邻时钟节点是指第二时钟源节点到第二主时钟节点的路径上可以直接进行Announce报文交互的两个时钟节点。
可选地，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点，包括：所述网络设备确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，所述网络设备将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较；当所述第 三最大时钟偏差累计值小于所述第四最大时钟偏差累计值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，第三最大时钟偏差累计值是指第一主时钟节点与网络设备之间的传输介质对应的最大时钟偏差与第一最大时钟偏差累计值之和。第四最大时钟偏差累计值是指第二主时钟节点与网络设备之间的传输介质对应的最大时钟偏差与第二最大时钟偏差累计值之和。
在本申请实施例中，当第三最大时钟偏差累计值小于第四最大时钟偏差累计值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。当第三最大时钟偏差累计值大于第四最大时钟偏差累计值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
可选地，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述多个第一时钟偏差方差值包括所述第一时钟源节点到所述第一主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值，所述多个第二时钟偏差方差值包括所述第二时钟源节点到所述第二主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值；所述网络设备将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较之后，所述方法还包括：当所述第三最大时钟偏差累计值等于所述第四最大时钟偏差累计值时，所述网络设备确定第三时钟方差值和第四时钟方差值，所述网络设备将所述第三时钟方差值与所述第四时钟方差值进行比较；当所述第三时钟方差值小于所述第四时钟方差值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，第三时钟方差值是第一主时钟节点与网络设备之间的传输介质对应的多个时钟偏差的方差值与第一时钟方差值的平方和的平方根。第四时钟方差值是第二主时钟节点与网络设备之间的传输介质对应的多个时钟偏差的方差值与第二时钟方差值的平方和的平方根。
在本申请实施例中，当第三时钟方差值小于第四时钟方差值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。类似地，当第三时钟方差值大于第四时钟方差值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网 络设备进行时钟同步的精确度更高。
第二方面，提供了一种时钟同步装置，所述时钟同步装置具有实现上述第一方面中时钟同步方法行为的功能。所述时钟同步装置包括至少一个模块，所述至少一个模块用于实现上述第一方面所提供的时钟同步方法。
第三方面，提供了一种时钟同步装置，所述时钟同步装置的结构中包括处理器和存储器，所述存储器用于存储支持时钟同步装置执行上述第一方面所提供的时钟同步方法的程序，以及存储用于实现上述第一方面所述的时钟同步方法所涉及的数据。所述处理器被配置为用于执行所述存储器中存储的程序。所述时钟同步装置还可以包括通信总线，所述通信总线用于在所述处理器与所述存储器之间建立连接。
第四方面，提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面所述的时钟同步方法。
第五方面，提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面所述的时钟同步方法。
上述第二方面、第三方面、第四方面和第五方面所获得的技术效果与上述第一方面中对应的技术手段获得的技术效果近似，在这里不再赘述。
本申请提供的技术方案至少可以带来以下有益效果：网络设备先接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值。然后该网络设备再将第一时钟源节点的标识与第二时钟源节点的标识进行比较，当第一时钟源节点的标识与第二时钟源节点的标识相同时，表明第一主时钟节点和第二主时钟节点对应同一时钟源节点，此时，根据第一最大时钟偏差累计值和第二最大时钟偏差累计值有助于从第一主时钟节点和第二主时钟节点中，选择时钟源节点到主时钟节点路径上带来的时钟偏差较小的主时钟节点，再根据选择的主时钟节点的时间信息校准该网络设备的时钟。时钟源节点到主时钟节点的路径上带来的时钟偏差较小的话，通过该主时钟节点进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。
附图说明
图1是本申请实施例提供的一种实施环境的示意图。
图2是本申请实施例提供的一种网络设备的结构示意图。
图3是本申请实施例提供的第一种时钟同步方法的流程图。
图4是本申请实施例提供的第二种时钟同步方法的流程图。
图5是本申请实施例提供的一种时钟同步装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的实施方式作进一步地详细描述。
在对本申请实施例进行详细的解释说明之前，先对本申请实施例的实施环境进行介绍：
图1是本申请实施例提供的一种实施环境的示意图，参见图1，该实施环境包括卫星101、卫星102以及网络设备103-网络设备111，卫星101、卫星102以及网络设备103-网络设备111组成时钟同步网络。卫星101通过卫星信号向网络设备103传输时间信息，卫星102通过卫星信号向网络设备109传输时间信息，网络设备103-网络设备111之间可以通过光纤连接，并通过光纤传输时间信息。卫星101和卫星102均可以是全球定位系统(Global Positioning System，GPS)、全球卫星导航系统(Global Navigation Satellite System，GLONASS)或者北斗导航卫星系统(BeiDou Navigation Satellite System)等。网络设备103-网络设备111均可以是运营商路由器(provider router)、运营商边缘路由器(provider edge router)和用户边缘路由器(customer edge router)等。
其中，卫星101和卫星102位于时钟同步网络的上游，网络设备111位于时钟同步网络的下游。卫星101可以通过向网络设备103发送时钟信号来实现与网络设备103之间的时钟同步。类似地，卫星102可以通过向网络设备109发送时钟信号来实现与网络设备109之间的时钟同步。
具体地，以卫星101和网络设备103为例，当卫星101是GPS时，卫星101可以包括原子时钟(atomic clock)。网络设备103可以包含通信楼定时供给系统(building integrated timing supply，BITS)时钟，BITS时钟包括GPS接收机。卫星101可以在原子时钟的驱动下，向网络设备103发送GPS信号。该GPS信号中可以包括精度与原子时钟的精度相同的时间信息。网络设备103中的BITS时钟的GPS接收机接收到该GPS信号后，可以根据该GPS信号中的时间信息，将网络设备103中的BITS时钟与GPS卫星中的原子时钟进行时钟同步。由于时钟同步包括时间同步和频率同步，因此，具体地，网络设备103可以将网络设备103中的BITS时钟的时间与GPS卫星中的原子时钟的时间进行同步，以及网络设备103可以将网络设备103中的BITS时钟的频率与GPS卫星中的原子时钟的频率进行同步。网络设备103与卫星101进行时钟同步后，网络设备103可以作为一个时间源节点。类似地，通过上述方法可以将网络设备109与卫星102之间进行时钟同步，并将进行时钟同步后的网络设备109作为另一个时钟源节点。
网络设备103作为时间源节点，可以使位于网络设备103下游的网络设备104和网络设备106与网络设备103之间进行时钟同步。具体地，以网络设备103和网络设备104为例，网络设备103可以向位于网络设备103下游的网络设备104发送同步(Sync)报文，该Sync报文上记录有指示该Sync报文的发送时间的时间戳1。网络设备104在接收到该Sync报文的同时再在网络设备104本地记录指示该Sync报文的接收时间的时间戳2，之后网络设备104再向网络设备103发送延迟请求(Delay_req)报文，并在网络设备104本地记录指示该Delay_req报文的发送时间的时间戳3。网络设备103在接收到该Delay_req报文的同时再在网络设备103本地记录指示该Delay_req报文的接收时间的时间戳4，最后网络设备103再产生携带时间戳4的延迟请求反馈(Delay_resp)报文并发送给网络设备104。至此，网络设备104可以获取到网络设备103发送Sync报文的时间戳1和网络设备 104接收Sync报文的时间戳2，以及网络设备104发送Delay_req报文的时间戳3和网络设备103接收Delay_req报文时间戳4。网络设备104可以通过时间戳1和时间戳2确定出与网络设备103之间的频率偏差，并根据该频率偏差与网络设备103之间进行频率同步；且网络设备104可以通过时间戳1、时间戳2、时间戳3和时间戳4确定出与网络设备103之间的时间偏差，并根据该时间偏差与网络设备103之间进行时间同步，也即实现了与网络设备103之间的时钟同步。
类似地，网络设备104与网络设备103进行时钟同步后，网络设备104可以作为主时钟节点，使位于网络设备104下游的网络设备105与网络设备104之间进行时钟同步，并可以以此类推。
其中，网络设备111位于网络设备105、网络设备108以及网络设备110的下游，因此网络设备105、网络设备108以及网络设备110均可以作为网络设备111的主时钟节点。网络设备111可以接收来自网络设备105、网络设备108以及网络设备110的三个Announce报文，这三个Announce报文中都携带主时钟节点的上游的时钟源节点的标识、主时钟节点的最大时钟偏差累计值以及主时钟节点到位于上游的时钟源节点的跳数。即，网络设备105发送的Announce报文中携带网络设备103的标识、网络设备105的最大时钟偏差累计值以及网络设备105到网络设备103的跳数，网络设备108发送的Announce报文中携带网络设备103的标识、网络设备108的最大时钟偏差累计值以及网络设备108到网络设备103的跳数，网络设备110发送的Announce报文中携带网络设备109的标识、网络设备110的最大时钟偏差累计值以及网络设备110到网络设备109的跳数。网络设备111可以根据这三个Announce报文中携带的数据，从网络设备105、网络设备108以及网络设备110中选择可以进行时钟同步的网络设备，然后类似地，可以按照上述网络设备104与网络设备103之间进行时钟同步的过程，来实现网络设备111与选择进行时钟同步的网络设备之间的时钟同步。
图2是本申请实施例提供的一种网络设备的结构示意图，该网络设备可以是图1中所示的网络设备103-网络设备111中任意一个网络设备。参见图2，该网络设备包括至少一个处理器201、通信总线202、存储器203、至少一个通信接口204以及时钟205。
处理器201可以是一个通用中央处理器(Central Processing Unit，CPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)，或者可以是一个或多个用于控制本申请方案程序执行的集成电路。
通信总线202可包括一通路，用于在上述组件之间传送信息。
存储器203可以是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，也可以是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，也可以是电可擦可编程只读存储器(Electrically Erasable Programmable Read-Only Memory，EEPROM)、只读光盘(Compact Disc Read-Only Memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由网络设备存取的任何其它介质，但不限于此。存储器203可以是独立存在，并通过通信总线202与处理器201相连接。存储器203也可以和处理器201集成在一起。
通信接口204使用任何收发器一类的装置，用于与其它设备或通信网络通信，如以太网，无线接入网(Radio Access Network，RAN)、无线局域网(Wireless Local Area Networks，WLAN)等。
时钟205可以是BITS时钟，且BITS时钟可以包括GPS接收机。
在具体实现中，作为一种实施例，处理器201可以包括一个或多个CPU，如图2中所示的CPU0和CPU1。
在具体实现中，作为一种实施例，网络设备可以包括多个处理器，如图2中所示的处理器201和处理器206。这些处理器中的每一个可以是一个单核处理器(single-CPU)，也可以是一个多核处理器(multi-CPU)。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据的处理核。
在具体实现中，作为一种实施例，网络设备还可以包括输出设备207和输入设备208(图中未示出)。输出设备207和处理器201通信，可以以多种方式来显示信息。例如，输出设备207可以是液晶显示器(liquid crystal display，LCD)、发光二级管(light emitting diode，LED)显示设备、阴极射线管(cathode ray tube，CRT)显示设备或投影仪(projector)等。输入设备208和处理器201通信，可以以多种方式接收用户的输入。例如，输入设备208可以是鼠标、键盘、触摸屏设备或传感设备等。
上述的网络设备可以是一个通用网络设备或一个专用网络设备。在具体实现中，网络设备可以是路由器、交换机等，本申请实施例不限定网络设备的类型。
其中，存储器203用于存储执行本申请方案的程序代码210，处理器201用于执行存储器203中存储的程序代码210。该网络设备可以通过处理器201以及存储器203中的程序代码210，来实现下文图3实施例提供的时钟同步方法。
图3是本申请实施例提供的第一种时钟同步方法的流程图，该方法应用于网络设备。参见图3，该方法包括：
S301：网络设备接收来自第一主时钟节点的通知Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值。
需要说明的是，网络设备可以是时钟同步网络中连接有至少两个主时钟节点的设备。比如，可以为图2中的网络设备111。第一主时钟节点和第二主时钟节点是与该网络设备连接的且位于该网络设备的上游的时钟节点。Announce报文一种由PTP定义的报文。第一时钟源节点的标识是用于唯一指示第一时钟源节点的标识。第二时钟源节点的标识是用于唯一指示第二时钟源节点的标识。
另外，第一最大时钟偏差累计值是第一时钟源节点到第一主时钟节点的路径上的多个第一最大时钟偏差之和。第二最大时钟偏差累计值是第二时钟源节点到第二主时钟节点的路径上的多个第二最大时钟偏差之和。
在第一种情况中，时钟源节点到主时钟节点的路径上，可能只有时钟节点存在时钟偏差，因此，多个第一最大时钟偏差可以是指第一时钟源节点到第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。多个第二最大时钟偏差是可以是指第二时钟 源节点到第二主时钟节点的路径上的多个时钟节点都分别对应的多个最大时钟偏差。也即是，第一时钟源节点到第一主时钟节点的路径上的每个时钟节点都对应一个最大时钟偏差，该最大时钟偏差称为第一最大时钟偏差。类似地，第二时钟源节点到第二主时钟节点的路径上的每个时钟节点也都对应一个最大时钟偏差，该最大时钟偏差称为第二最大时钟偏差。
时钟节点通常可以包括多个主(Master)通信接口和多个从(Slave)通信接口。多个从通信接口可以按照G.8275.1协议分别与多个主时钟节点进行通信；多个主通信接口可以按照G.8275.1协议分别与多个位于下游的从时钟节点进行通信。下文以多个主通信接口为例进行说明，当时钟节点的多个主通信接口中的一个主通信接口出现故障时，与该主通信接口进行通信的从时钟节点无法通过该主通信接口实现与该时钟节点之间的时钟同步。此时，需要将该从时钟节点与该时钟节点包括的其他主通信接口进行通信，从而可以通过其他主通信接口实现与该时钟节点之间的时钟同步。这种情况下，该时钟节点会因为该从时钟节点与其他主通信接口进行通信而产生跳变幅度偏差。也即是，该从时钟节点与原主通信接口进行通信时，该从时钟节点与该时钟节点之间进行时钟同步的精确度，要高于该从时钟节点与其他主通信接口进行通信时，该从时钟节点与该时钟节点之间进行时钟同步的精确度。当然，时钟节点也可能不存在通信接口出现故障需要使与该通信接口进行通信的时钟节点与其他通信接口进行通信的情况，所以跳变幅度偏差不是时钟节点存在的必然偏差。另外，时钟节点在其所处的自然环境中会不可避免的因为自然环境的因素而产生抖动，从而产生抖动偏差。再者，时钟节点会在使用过程中不可避免的因存在缓慢的偏移而产生静态偏差。上述时钟节点的跳变幅度偏差、抖动偏差以及静态偏差都是时钟节点的时钟偏差。这三个时钟偏差可以在时钟节点出厂之前通过多个不同采样时刻的检测而获得一个用于评价该时钟节点的精度的最大值。例如，时钟节点在出厂之前可以在100个采样时刻中获得100个跳变幅度偏差和100个抖动偏差。取这100个跳变幅度偏差中的最大值即可以得到最大跳变幅度偏差。取这100个抖动偏差所构成的抖动偏差范围的上限与下限之间的差值的绝对值，即可得到最大抖动偏差。取这100个抖动偏差所构成的抖动偏差范围的中间值，即可得到最大静态偏差。可以在时钟节点出厂时将最大跳变幅度偏差、最大抖动偏差以及最大静态偏差保存到时钟节点中。当时钟节点的通信接口出现故障需要使与该通信接口进行通信的时钟节点与其他通信接口进行通信时，最大时钟偏差值即是最大跳变幅度偏差、最大抖动偏差以及最大静态偏差之和；当时钟节点未出现更换主通信接口的情况时，最大时钟偏差值即是最大抖动偏差以及最大静态偏差之和。
基于上述说明，对于第一时钟源节点到第一主时钟节点的路径上的每个时钟节点，该时钟节点对应的最大时钟偏差可以是最大跳变幅度偏差、最大抖动偏差以及最大静态偏差之和，也可以是最大抖动偏差以及最大静态偏差之和。类似地，对于第二时钟源节点到第二主时钟节点的路径上的每个时钟节点，该时钟节点对应的最大时钟偏差可以是最大跳变幅度偏差、最大抖动偏差以及最大静态偏差之和，也可以是最大抖动偏差以及最大静态偏差之和。
下面通过举例来对第一种情况下的第一最大时钟偏差累计值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着最大时钟偏差104，网络设备105对应着最大时钟偏差105。 也即是在网络设备103到网络设备105的路径上有2个第一最大时钟偏差，即最大时钟偏差104和最大时钟偏差105。如此，第一最大时钟偏差累计值即是最大时钟偏差104与最大时钟偏差105之和。
值得注意的是，第一时钟源节点与第一主时钟节点之间可能存在多条路径，第一时钟源节点到第一主时钟节点的路径上的多个时钟节点可以是位于该多条路径上的多个时钟节点。类似地，第二时钟源节点与第二主时钟节点之间可能存在多条路径，第二时钟源节点到第二主时钟节点的路径上的多个时钟节点可以是指位于该多条路径上的多个时钟节点。并且，第一时钟源节点到第一主时钟节点的路径上的多个时钟节点可以包括第一主时钟节点，且不包括第一时钟源节点。类似地，第二时钟源节点到第二主时钟节点的路径上的多个时钟节点可以包括第二主时钟节点，且不包括第二时钟源节点。
在第二种情况中，时钟源节点到主时钟节点的路径上，除过时钟节点存在时钟偏差之外，相邻两个时钟节点之间的传输介质也可能存在对应的时钟偏差。因此，多个第一最大时钟偏差可以是指第一时钟源节点到第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及第一时钟源节点到第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。多个第二最大时钟偏差可以是是指第二时钟源节点到第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及第二时钟源节点到第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。也即是，第一时钟源节点到第一主时钟节点的路径上的每个时钟节点对应一个最大时钟偏差，且至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质也对应一个最大时钟偏差，可以称为第一最大时钟偏差，类似地，第二时钟源节点到第二主时钟节点的路径上的每个时钟节点对应一个最大时钟偏差，至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质也对应一个最大时钟偏差，可以称为第二最大时钟偏差。
需要说明的是，第一时钟源节点到第一主时钟节点的路径上的一对相邻时钟节点是指第一时钟源节点到第一主时钟节点的路径上可以直接进行Announce报文交互的两个时钟节点。类似地，第二时钟源节点到第二主时钟节点的路径上的一对相邻时钟节点是指第二时钟源节点到第二主时钟节点的路径上可以直接进行Announce报文交互的两个时钟节点。比如，图1中的网络设备104和网络设备105可以称为一对相邻时钟节点。其中，相邻时钟节点之间的传输介质可以是光纤，由于光纤会受到温度、湿度、压力等因素的影响，因此，一对相邻时钟节点之间进行时钟同步的时延可能受到影响，进而造成相邻时钟节点之间的传输介质存在时钟偏差。
下面通过举例来对第二种情况下的第一最大时钟偏差累计值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着最大时钟偏差104，网络设备105对应着最大时钟偏差105，且网络设备104与网络设备105之间的传输介质n还对应着最大时钟偏差n。也即是，网络设备103到网络设备105的路径上有3个第一最大时钟偏差，即最大时钟偏差104、最大时钟偏差105以及最大时钟偏差n。如此，第一最大时钟偏差累计值即是最大时钟偏差104、第一最大时钟偏差105以及第一最大时钟偏差n之和。
值得注意的是，当第一时钟源节点到第一主时钟节点的路径上的多个时钟节点中每对相邻时钟节点之间的传输介质处于理想状态时，即每对相邻时钟节点之间的传输介质不会因温度、湿度、压力等因素而产生时钟偏差。这样的条件下，多个第一最大时钟偏差就是指第一时钟源节点到第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。
另外，对于一对相邻时钟节点之间的传输介质，可以事先在这两个相邻时钟节点处分别设置一个检测仪器，以对这两个时钟节点之间的传输介质正反向传输时间信息产生的时钟偏差进行检测。与上述时钟节点的类似，可以在多个不同的采样时刻进行检测，之后取检测到的时钟偏差中的最大值，作为这两个相邻时钟节点之间的传输介质的最大时钟偏差。并将这两个相邻时钟节点之间的传输介质的最大时钟偏差保存至这两个相邻时钟节点中的任一时钟节点。
S302：网络设备将第一时钟源节点的标识与第二时钟源节点的标识进行比较。
需要说明的是，在一些实施环境中，需要整个时钟同步网络中的时钟节点都跟踪同一个时钟源节点，以使得整个时钟同步网络中的时钟节点都对应着一个相同的时钟源节点，因此，先通过将第一时钟源节点的标识与第二时钟源节点的标识进行比较，来确定第一主时钟节点和第二主时钟节点的时钟源节点是否相同。如果第一主时钟节点和第二主时钟节点的时钟源节点相同，那么就可以保证该时钟同步网络中的时钟节点都会跟踪到同一个时钟源节点，然后再通过如下S303来选择可以与该网络设备进行时钟同步的主时钟节点。
S303：当第一时钟源节点的标识与第二时钟源节点的标识相同时，网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，当第一时钟源节点的标识与第二时钟源节点的标识相同时，即表明第一主时钟节点和第二主时钟节点对应着同一个时钟源节点。此时，时钟源节点不会成为影响网络设备从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点的因素。因此，可以根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
基于上述S301的描述，在两种不同的情况下，第一时钟偏差累计值和第二时钟偏差累计值的概念不同。在这种情况下，根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点的实现方式也会不同，因此，接下来也将分两种可能的实现方式分别对主时钟节点的选择进行说明。其中，第一种可能的实现方式对应上述S301中的第一种情况，第二种可能的实现方式对应上述S301中的第二种情况。
第一种可能的实现方式：网络设备将第一最大时钟偏差累计值与第二最大时钟偏差累计值进行比较，当第一最大时钟偏差累计值小于第二最大时钟偏差累计值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第一最大时钟偏差累计值大于第二最大时钟偏差累计值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，当第一最大时钟偏差累计值小于第二最大时钟偏差累计值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以 使该网络设备进行时钟同步的精确度更高。当第一最大时钟偏差累计值大于第二最大时钟偏差累计值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
值得注意的是，在第一时钟源节点的标识与第二时钟源节点的标识相同的条件下，当第一最大时钟偏差累计值等于第二最大偏差累计值时，来自第一主时钟节点的Announce报文中还可以携带第一主时钟节点到第一时钟源节点的跳数，来自第二主时钟节点Announce报文中还可以携带第二主时钟节点到第二时钟源节点的跳数，通过比较第一主时钟节点到第一时钟源节点的跳数，以及第二主时钟节点到第二时钟源节点的跳数的大小，可以选择出该网络设备进行时钟同步的主时钟节点。由于跳数值越大，主时钟节点到时钟源节点的路径上的时钟节点个数越多，而较多的时钟节点会带来更大的时钟偏差，从而导致通过该主时钟节点进行时钟同步的精确度降低。因此，当第一主时钟节点到第一时钟源节点的的跳数小于第二主时钟节点到第二时钟源节点的跳数时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当然，当第一主时钟节点到第一时钟源节点的的跳数大于第二主时钟节点到第二时钟源节点的跳数时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
第二种可能的实现方式：网络设备确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，并将第三最大时钟偏差累计值与第四最大时钟偏差累计值进行比较，当第三最大时钟偏差累计值小于第四最大时钟偏差累计值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第三最大时钟偏差累计值大于第四最大时钟偏差累计值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，第三最大时钟偏差累计值是指第一主时钟节点与网络设备之间的传输介质对应的最大时钟偏差与第一最大时钟偏差累计值之和，第四最大时钟偏差累计值是指第二主时钟节点与网络设备之间的传输介质对应的最大时钟偏差与第二最大时钟偏差累计值之和。
基于上述S301的描述，相邻两个时钟节点之间的传输介质的最大时钟偏差可以保存到这两个时钟节点中的任一时钟节点。也即是，第一主时钟节点和网络设备之间的传输介质对应的最大时钟偏差可以保存到第一主时钟节点中，也可以保存到网络设备中。同理，第二主时钟节点和网络设备之间的传输介质对应的最大时钟偏差可以保存到第二主时钟节点中，也可以保存到网络设备中。当第一主时钟节点和网络设备之间的传输介质对应的最大时钟偏差保存到第一主时钟节点中，第二主时钟节点和网络设备之间的传输介质对应的最大时钟偏差保存到第二主时钟节点中，此时，来自第一主时钟节点的Announce报文中携带的第一时钟偏差累计值中包含有第一主时钟节点和网络设备之间的传输介质对应的最大时钟偏差，来自第二主时钟节点的Announce报文中携带的第二时钟偏差累计值中包含有第二主时钟节点和网络设备之间的传输介质对应的最大时钟偏差。在这种情况下，可以直接将第一最大时钟偏差累计值与第二最大时钟偏差累计值进行比较，当第一最大时钟偏差累计值小于第二最大时钟偏差累计值时，网络设备将第一主时钟节点确定为进行时 钟同步的主时钟节点；当第一最大时钟偏差累计值大于第二最大时钟偏差累计值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
然而，当第一主时钟节点和网络设备之间的传输介质对应的最大时钟偏差保存到网络设备中，第二主时钟节点和网络设备之间的传输介质对应的最大时钟偏差保存到网络设备中，此时，来自第一主时钟节点的Announce报文中携带的第一时钟偏差累计值中就不包含第一主时钟节点和网络设备之间的传输介质对应的最大时钟偏差，来自第二主时钟节点的Announce报文中携带的第二时钟偏差累计值中就不包含第二主时钟节点和网络设备之间的传输介质对应的最大时钟偏差。在这种情况下，就需要确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，并将第三最大时钟偏差累计值与第四最大时钟偏差累计值进行比较，当第三最大时钟偏差累计值小于第四最大时钟偏差累计值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第三最大时钟偏差累计值大于第四最大时钟偏差累计值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
另外，当第三最大时钟偏差累计值小于第四最大时钟偏差累计值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。当第三最大时钟偏差累计值大于第四最大时钟偏差累计值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
下面通过举例来对第三最大时钟偏差累计值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着最大时钟偏差104，网络设备105对应着最大时钟偏差105，网络设备104与网络设备105之间的传输介质n还对应着最大时钟偏差n，网络设备105与网络设备111之间的传输介质m对应着最大时钟偏差m，也即是，网络设备103到网络设备105的路径上有4个第一最大时钟偏差，即最大时钟偏差104、最大时钟偏差105、最大时钟偏差n以及最大时钟偏差m。如此，第一最大时钟偏差累计值即是最大时钟偏差104、第一最大时钟偏差105以及第一最大时钟偏差n之和，那么第三最大时钟偏差累计值即是最大时钟偏差m与第一最大时钟偏差累计值之和。
值得注意的是，在第一时钟源节点的标识与第二时钟源节点的标识相同的条件下，当第三最大时钟偏差累计值等于第四最大偏差累计值时，来自第一主时钟节点的Announce报文中还可以携带第一主时钟节点到第一时钟源节点的跳数，来自第二主时钟节点Announce报文中还可以携带第二主时钟节点到第二时钟源节点的跳数，通过比较第一主时钟节点到第一时钟源节点的跳数，以及第二主时钟节点到第二时钟源节点的跳数的大小，可以选择出该网络设备进行时钟同步的主时钟节点。由于跳数值越大，主时钟节点到时钟源节点的路径上的时钟节点个数越多，而较多的时钟节点会带来更大的时钟偏差，从而导致通过该主时钟节点进行时钟同步的精确度降低。因此，当第一主时钟节点到第一时钟源节点的的跳数小于第二主时钟节点到第二时钟源节点的跳数时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该 网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当然，当第一主时钟节点到第一时钟源节点的的跳数大于第二主时钟节点到第二时钟源节点的跳数时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
S304：网络设备根据选择的主时钟节点的时间信息校准网络设备的时钟。
需要说明的是，校准网络设备的时钟即是将该网络设备的时钟设置为与选择的主时钟节点的时钟相同的时钟，该时钟同步可以包括时间同步和频率同步。
S304具体实现方式可以包括：网络设备和主时钟节点根据IEEE1588-2008，利用PTP报文进行通信。PTP报文包括Sync报文、Delay_req报文以及Delay_resp报文。时间信息携带在PTP报文中。时间信息可以是时间戳1、时间戳2、时间戳3以及时间戳4。网络设备可以利用时间信息，计算网络设备与主时钟节点的时间偏差。网络设备根据时间偏差，校准网络设备的时钟的时间。或者，网络设备可以利用时间信息，计算网络设备与主时钟节点的频率偏差。网络设备根据频率偏差，校准网络设备的时钟的频率。网络设备可以只校准时间。网络设备可以只校准频率。网络设备也可以校准时间以及频率。关于网络设备与主时钟节点利用PTP报文进行通信的过程，参考上文对网络设备104通过PTP报文与网络设备103进行通信的描述。关于网络设备获取时间信息的过程，可以参考上文对网络设备104获取时间戳1、时间戳2、时间戳3以及时间戳4的描述。
网络设备根据频率偏差，校准网络设备的时钟的频率的具体实现方式可以包括：网络设备的时钟可以包括电压源以及晶振。电压源的输出电压作用于晶振。电压源的输出电压越高，则晶振的工作频率越高。网络设备可以包括中央处理单元。中央处理单元可以控制电压源的输出电压。进而，中央处理单元可以通过控制电压源的输出电压，校准网络设备的时钟的频率。具体地，中央处理单元可以根据频率偏差确定电压调整值1。具体地，网络设备还包括与中央处理单元耦合的存储器。存储器中可以存储有频率偏差与电压调整值的对应关系。中央处理单元可以通过访问存储器在所述对应关系中查找与所述第一频率偏差对应的电压调整值，即电压调整值1。中央处理单元确定电压调整值1之前，电压源的输出电压为电压值1。中央处理单元确定电压调整值1之后，可以依据电压调整值1，将电压源的输出电压调整为电压值2。电压值2等于电压值1与电压调整值1的和。因此，如果电压调整值1是正数，则意味着网络设备的时钟的频率低于主时钟节点的频率。中央处理单元可以通过提高晶振的工作频率，校准网络设备的时钟的频率。如果电压调整值1是负数，则意味着网络设备的时钟的频率高于主时钟节点的频率。中央处理单元可以通过降低晶振的工作频率，校准网络设备的时钟的频率。
网络设备根据时间偏差，校准网络设备的时钟的时间的具体实现方式可以包括：网络设备的时钟包括晶振和计数器。计数器具体可以是累加器。计数器中可以包含一个存储器。存储器中保存的值等于该时钟记录的当前时间。晶振可以在每个工作周期向计数器输出一个脉冲信号。计数器检测到脉冲信号的上升沿或者下降沿时，计数器将增量与存储器中保存的值进行加法运算，从而对存储器中保存的值进行更新。增量等于晶振的标称工作周期。例如，晶振的标称工作频率可以是125兆赫兹(Mega Hertz，MHz)。相应的，晶振的标称工作周期可以是8纳秒。网络设备的中央处理单元确定时间偏差后，可以根据时间偏差对计数器包含的存储器中保存的值进行更新，从而实现了对网络设备的时钟的时间的更新。 通过上述过程，可以校准网络设备的时钟的时间。
值得注意的是，上述技术方案中，在第一时钟源节点的标识和第二时钟源节点的标识相同的情况下，进行时钟同步。然而，在第一时钟源节点的标识和第二时钟源节点的标识不相同的情况下，可以根据这两个时钟源节点的标识的大小来确定可以与该网络设备进行时钟同步的主时钟节点。由于时钟源节点的标识越小表明该时钟源节点的精度越高，也即是与该时钟源节点对应的主时钟节点进行时钟同步的精确度越高，因此，可以选择这两个时钟源节点的标识较小的时钟源节点所对应的主时钟节点作为该网络设备进行时钟同步的主时钟节点，以使该网络设备进行时钟同步的精确度更高。具体地，当第一时钟源节点的标识小于第二时钟源节点的标识时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当第一时钟源节点的标识大于第二时钟源节点的标识时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
进一步地，来自第一主时钟节点的Announce报文还可以携带第一时钟源节点的时钟等级，来自第二主时钟节点的Announce报文还可以携带第二时钟源节点的时钟等级。在S302之前，也即在比较第一时钟源节点的标识与第二时钟源节点的标识之前，还可以通过如下步骤(1)-步骤(3)来确定可以与该网络设备进行时钟同步的主时钟节点并进行时钟同步。
步骤(1)：网络设备将第一时钟源节点的时钟等级与第二时钟源节点的时钟等级进行比较，当第一时钟源节点的时钟等级等于第二时钟源节点的时钟等级时，网络设备判断第一时钟源节点的时钟等级是否小于或等于127，当第一时钟源节点的时钟等级大于127时，返回S302。
需要说明的是，时钟源节点的时钟等级用于指示时钟源节点的时钟级别，且时钟源节点的时钟等级的数值越小其所对应的时钟源节点的时钟级别越高。当第一时钟源节点的时钟等级等于第二时钟源节点的时钟等级时，表明第一时钟源节点的时钟级别与第二时钟源节点的时钟级别相同。此时，可以判断第一时钟源节点的时钟等级是否小于或等于127，由于第一时钟源节点的时钟等级与第二时钟源节点的时钟等级相等，所以判断第一时钟源节点的时钟等级是否小于或等于127也即是判断第二时钟源节点的时钟等级是否小于或等于127。在一种可能的实现方式中，当第一时钟源节点的时钟等级大于127时，表明第一时钟源节点不仅可以作为被其他从时钟节点跟踪的时钟源节点，还可以作为跟踪其他时钟源节点的从时钟节点。同理，当第二时钟源节点的时钟等级大于127时，表明第二时钟源节点不仅可以作为被其他从时钟节点跟踪的时钟源节点，还可以作为跟踪其他时钟源节点的从时钟节点。如此，该网络设备可以返回上述S302，继续进行第一时钟源节点的标识和第二时钟源节点的标识的比较。
步骤(2)：当第一时钟源节点的时钟等级小于或等于127时，网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，当第一时钟源节点的时钟等级小于或等于127时，也即第二时钟源节 点的时钟等级小于或等于127时，表明第一时钟源节点只能作为被其他从时钟节点跟踪的时钟源节点，而不能作为跟踪其他时钟源节点的从时钟节点。同理，当第一时钟源节点的时钟等级小于或等于127时，表明第二时钟源节点只能作为被其他从时钟节点跟踪的时钟源节点，而不能作为跟踪其他时钟源节点的从时钟节点。如此，该网络设备可以根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点，且该网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点的过程与上述S303中相应的过程类似，此处不再赘述。
步骤(3)：网络设备根据选择的主时钟节点的时间信息校准网络设备的时钟。
需要说明的是，步骤(3)与上述S304类似，此处不再赘述。
在本申请实施例中，网络设备先接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值。然后该网络设备再将第一时钟源节点的标识与第二时钟源节点的标识进行比较，当第一时钟源节点的标识与第二时钟源节点的标识相同时，表明第一主时钟节点和第二主时钟节点对应同一时钟源节点，此时，根据第一最大时钟偏差累计值和第二最大时钟偏差累计值有助于从第一主时钟节点和第二主时钟节点中，选择时钟源节点到主时钟节点的路径上带来的时钟偏差较小的主时钟节点，再根据选择的主时钟节点的时间信息校准该网络设备的时钟。时钟源节点到主时钟节点的路径上带来的时钟偏差较小的话，通过该主时钟节点进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。
图4为本申请实施例提供的第二种时钟同步方法的流程图，该方法应用于网络设备。参见图4，该方法包括：
S401：网络设备接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值。
S402：网络设备将第一时钟源节点的标识与第二时钟源节点的标识进行比较。
S403：当第一时钟源节点的标识与第二时钟源节点的标识相同时，网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，本实施例中S401至S403的内容与上述实施例中S301至S303的内容类似。关于S401至S403的具体实现方式，可以参考实施例对S301至S303的描述，此处不再赘述。不过对于第一最大时钟偏差累计值等于第二最大时钟偏差累计值的情况，以及第三最大时钟偏差累计值等于第四最大时钟偏差累计值的情况，在本实施例中，网络设备选择进行时钟同步的主时钟节点的方式与上述实施例的方式不相同，接下来对这种情况进行详细说明。
S404：当第一最大时钟偏差累计值等于第二最大时钟偏差累计值时，网络设备根据第 一时钟方差值和第二时钟方差值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，来自第一主时钟节点的Announce报文还可以携带第一时钟方差值，来自第二主时钟节点的Announce报文还携带第二时钟方差值。第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根。
在第一种情况中，时钟源节点到主时钟节点的路径上，可能只有时钟节点存在时钟偏差，因此，对于多个第一时钟偏差方差值中的任一第一时钟偏差方差值，这个第一时钟偏差方差值可以是指第一时钟源节点到第一主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值。同理，对于多个第二时钟偏差方差值中的任一第二时钟偏差方差值，这个第二时钟偏差方差值可以是指第二时钟源节点到第二主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值。也即是，第一时钟源节点到第一主时钟节点的路径上的每个时钟节点都对应多个时钟偏差，这多个时钟偏差的方差值即为第一时钟偏差方差值，第二时钟源节点到第二主时钟节点的路径上的每个时钟节点都对应多个时钟偏差，这多个时钟偏差的方差值即为第二时钟偏差方差值。换句话说，多个第一时钟偏差方差值与第一时钟源节点到第一主时钟节点的路径上的多个时钟节点一一对应，多个第二时钟偏差方差值与第二时钟源节点到第二主时钟节点的路径上的多个时钟节点一一对应。
由于上述实施例对时钟偏差进行过说明，时钟偏差可以是时钟节点的跳变幅度偏差、抖动偏差和静态偏差。且上述实施例对时钟节点的最大时钟偏差进行过说明，即时钟节点的最大时钟偏差可以是最大跳变幅度偏差、最大抖动偏差以及最大静态偏差之和，也可以是最大抖动偏差以及最大静态偏差之和。所以，类似地，时钟节点的第一时钟偏差方差值可以是该时钟节点的跳变幅度偏差、抖动偏差和静态偏差的方差值，也可以是该时钟节点的抖动偏差和静态偏差的方差值。
下面通过举例来对第一种情况下的第一时钟方差值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着第一时钟偏差方差值104，网络设备105对应着第一时钟偏差方差值105。如此，第一时钟方差值即是第一时钟偏差方差值104与第一时钟偏差方差值105的平方和的平方根。
在第二种情况中，时钟源节点到主时钟节点的路径上，除过时钟节点存在时钟偏差之外，相邻时钟节点之间传输介质也可能存在的时钟偏差。因此，多个第一时钟偏差方差值包括第一时钟源节点到第一主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及第一时钟源节点到第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值。多个第二时钟偏差方差值包括第二时钟源节点到第二主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及第二时钟源节点到第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值。也即是，第一时钟源节点到第一主时钟节点的路径上的每个时钟节点对应一个时钟偏差方差值，且至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应一个时 钟偏差方差值，可以称为第一时钟偏差方差值。类似地，第二时钟源节点到第二主时钟节点的路径上的每个时钟节点对应一个时钟偏差方差值，且至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应一个时钟偏差方差值，可以称为第二时钟偏差方差值。
下面通过举例来对第二种情况下的第一时钟方差值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着第一时钟偏差方差值104，网络设备105对应着第一时钟偏差方差值105，且网络设备104与网络设备105之间的传输介质n对应着第一时钟偏差方差值n。如此，第一时钟方差值即是第一时钟偏差方差值104、第一时钟偏差方差值105以及第一时钟偏差方差值n的平方和的平方根。
由于在两种不同情况下，第一时钟方差值和第二时钟方差值的概念不同。因此，根据第一时钟方差值和第二时钟方差值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点的实现方式也会不同。接下来将分两种可能的实现方式分别对主时钟节点的选择进行说明。其中，第一种可能的实现方式对应本步骤的第一种情况，第二种可能的实现方式对应本步骤的第二种情况。
第一种可能的实现方式：网络设备将第一时钟方差值与第二时钟方差值进行比较，当第一时钟方差值小于第二时钟方差值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第一时钟方差值大于第二时钟方差值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，当第一时钟方差值小于第二时钟方差值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。类似地，当第一时钟方差值大于第二时钟方差值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
值得注意的是，在第一时钟源节点的标识与第二时钟源节点的标识相同的条件下，当第一最大时钟偏差累计值等于第二最大偏差累计值，且第一时钟方差值等于第二时钟方差值时，来自第一主时钟节点的Announce报文中还可以携带第一主时钟节点到第一时钟源节点的跳数，来自第二主时钟节点Announce报文中还可以携带第二主时钟节点到第二时钟源节点的跳数，通过比较第一主时钟节点到第一时钟源节点的跳数，以及第二主时钟节点到第二时钟源节点的跳数的大小，可以选择出该网络设备进行时钟同步的主时钟节点。由于跳数值越大，主时钟节点到时钟源节点的路径上的时钟节点个数越多，而较多的时钟节点会带来更大的时钟偏差，从而导致通过该主时钟节点进行时钟同步的精确度降低。因此，当第一主时钟节点到第一时钟源节点的的跳数小于第二主时钟节点到第二时钟源节点的跳数时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当然，当第一主时钟节点到第一时钟源节点的的跳数大于第二主时钟节点到第二时钟源节点的跳数时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第 一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
第二种可能的实现方式：网络设备确定第三时钟方差值和第四时钟方差值，并网络设备将第三时钟方差值与第四时钟方差值进行比较，当第三时钟方差值小于第四时钟方差值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第三时钟方差值大于第四时钟方差值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
需要说明的是，第三时钟方差值是第一主时钟节点与网络设备之间的传输介质对应的多个时钟偏差的方差值与第一时钟方差值的平方和的平方根。第四时钟方差值是第二主时钟节点与网络设备之间的传输介质对应的多个时钟偏差的方差值与第二时钟方差值的平方和的平方根。
与上述S303中的第二种可能的实现方式类似，在本步骤的第二种可能的实现方式中，当第一主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值保存到第一主时钟节点中，第二主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值保存到第二主时钟节点中，此时，来自第一主时钟节点的Announce报文中携带的第一时钟偏差方差值即为考虑了第一主时钟节点与网络设备之间的传输介质对应的多个时钟偏差的方差值得到的结果，来自第二主时钟节点的Announce报文中携带的第二时钟偏差方差值即为考虑了第二主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值得到的结果。在这种情况下，可以直接将第一时钟偏差方差值与第二时钟偏差方差值进行比较，当第一时钟偏差方差值小于第二时钟偏差方差值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第一时钟偏差方差值大于第二时钟偏差方差值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
然而，当第一主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值保存到网络设备中，第二主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值保存到网络设备中，此时，来自第一主时钟节点的Announce报文中携带的第一时钟偏差方差值中就没有考虑第一主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值，来自第二主时钟节点的Announce报文中携带的第二时钟偏差方差值中就没有考虑第二主时钟节点和网络设备之间的传输介质对应的多个时钟偏差的方差值。在这种情况下，就需要确定第三时钟偏差方差值和第四时钟偏差方差值，并将第三时钟方差值与第四时钟方差值进行比较，当第三时钟方差值小于第四时钟方差值时，网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点；当第三时钟方差值大于第四时钟方差值时，网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点。
另外，当第三时钟方差值小于第四时钟方差值时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第一主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。类似地，当第三时钟方差值大于第四时钟方差值时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备将第二主时钟节点确定为进行时钟同步的主时钟节点，可以使该网络设备进行时钟同步的精确度更高。
下面通过举例来对第三时钟方差值进行说明：
例如，以图1中的网络设备111为例，网络设备105为第一主时钟节点，那么网络设备103即为第一时钟源节点。网络设备103到网络设备105的路径上还包括网络设备104。其中，网络设备104对应着第一时钟偏差方差值104，网络设备105对应着第一时钟偏差方差值105，网络设备104与网络设备105之间的传输介质n对应着第一时钟偏差方差值n，网络设备105与网络设备111之间的传输介质m对应着第一时钟偏差方差值m。如此，第一时钟方差值即是第一时钟偏差方差值104、第一时钟偏差方差值105以及第一时钟偏差方差值n的平方和的平方根，那么第三时钟方差即是第一时钟偏差方差值m与第一时钟方差值的平方和的平方根。
值得注意的是，在第一时钟源节点的标识与第二时钟源节点的标识相同的条件下，当第一最大时钟偏差累计值等于第二最大偏差累计值，且第三时钟方差值等于第四时钟方差值时，来自第一主时钟节点Announce报文中还可以携带第一主时钟节点到第一时钟源节点的跳数，来自第二主时钟节点Announce报文中还可以携带第二主时钟节点到第二时钟源节点的跳数，通过比较第一主时钟节点到第一时钟源节点的跳数，以及第二主时钟节点到第二时钟源节点的跳数的大小，可以选择出该网络设备进行时钟同步的主时钟节点。由于跳数值越大，主时钟节点到时钟源节点的路径上的时钟节点个数越多，而较多的时钟节点会带来更大的时钟偏差，从而导致通过该主时钟节点进行时钟同步的精确度降低。因此，当第一主时钟节点到第一时钟源节点的的跳数小于第二主时钟节点到第二时钟源节点的跳数时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当然，当第一主时钟节点到第一时钟源节点的的跳数大于第二主时钟节点到第二时钟源节点的跳数时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
S405：网络设备根据选择的主时钟节点的时间信息校准网络设备的时钟。
需要说明的是，S405的具体实现方式，可以参考实施例对S304的描述，此处不再赘述。
值得注意的是，上述技术方案中，在第一时钟源节点的标识和第二时钟源节点的标识相同的情况下，进行时钟同步。然而，在第一时钟源节点的标识和第二时钟源节点的标识不相同的情况下，可以根据这两个时钟源节点的标识的大小来确定可以与该网络设备进行时钟同步的主时钟节点。由于时钟源节点的标识越小表明该时钟源节点的精度越高，也即是与该时钟源节点对应的主时钟节点进行时钟同步的精确度越高，因此，可以选择这两个时钟源节点的标识较小的时钟源节点所对应的主时钟节点作为该网络设备进行时钟同步的主时钟节点，以使该网络设备进行时钟同步的精确度更高。具体地，当第一时钟源节点的标识小于第二时钟源节点的标识时，表明通过第一主时钟节点进行时钟同步的精确度高于通过第二主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第一主时钟节点确定为进行时钟同步的主时钟节点。当第一时钟源节点的标识大于第二时钟源节点的标识时，表明通过第二主时钟节点进行时钟同步的精确度高于通过第一主时钟节点进行时钟同步的精确度。这种情况下，该网络设备可以将第二主时钟节点确定为进行时钟同步的主时钟节点。
进一步地，来自第一主时钟节点的Announce报文还可以携带第一时钟源节点的时钟等级，来自第二主时钟节点的Announce报文还可以携带第二时钟源节点的时钟等级。在S402之前，也即在比较第一时钟源节点的标识与第二时钟源节点的标识之前，还可以通过如下步骤A-步骤D来确定可以与该网络设备进行时钟同步的主时钟节点。
步骤A：网络设备将第一时钟源节点的时钟等级与第二时钟源节点的时钟等级进行比较，当第一时钟源节点的时钟等级等于第二时钟源节点的时钟等级时，网络设备判断第一时钟源节点的时钟等级是否小于或等于127，当第一时钟源节点的时钟等级大于127时，返回S402。
步骤B：当第一时钟源节点的时钟等级小于或等于127时，网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，本实施例中步骤A-步骤B的内容与上述实施例中步骤(1)-步骤(2)的内容基本相同，此处不再赘述。
步骤C：当第一最大时钟偏差累计值等于第二最大时钟偏差累计值时，网络设备根据第一时钟方差值和第二时钟方差值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。
需要说明的是，步骤C与上述S404类似，此处不再赘述。
步骤D：网络设备根据选择的主时钟节点的时间信息校准网络设备的时钟。
需要说明的是，步骤D与上述S304类似，此处不再赘述。
在本申请实施例中，网络设备先接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识、第一最大时钟偏差累计值和第一时钟方差值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识、第二最大时钟偏差累计值和第二时钟方差值。然后该网络设备再将第一时钟源节点的标识与第二时钟源节点的标识进行比较，当第一时钟源节点的标识与第二时钟源节点的标识相同时，表明第一主时钟节点和第二主时钟节点对应同一时钟源节点，此时，网络设备根据第一最大时钟偏差累计值和第二最大时钟偏差累计值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。当第一最大时钟偏差累计值等于第二最大时钟偏差累计值时，网络设备再根据第一时钟方差值和第二时钟方差值，从第一主时钟节点和第二主时钟节点中选择进行时钟同步的主时钟节点。最后该网络设备再根据选择的主时钟节点的时间信息校准该网络设备的时钟。时钟源节点到主时钟节点的路径上带来的时钟偏差较小的话，通过该主时钟节点进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。
图5是本申请实施例提供的一种时钟同步装置的结构示意图，该时钟同步装置可以由软件、硬件或者两者的结合实现成为计算机设备的部分或者全部，该时钟同步装置应用于该网络设备中，该网络设备可以为图2所示的网络设备。参见图5，该装置包括：接收模块501、第一比较模块502、选择模块503和第一校准模块504。
接收模块501，用于执行S301中的操作或者S401中的操作；
第一比较模块502，用于用于执行S302中的操作或者S402中的操作；
选择模块503，用于执行S303中的操作或者S403中的操作；
第一校准模块504，用于执行S304中的操作。
可选地，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。
可选地，来自所述第一主时钟节点的Announce报文还携带所述第一时钟源节点的时钟等级，来自所述第二主时钟节点的Announce报文还携带所述第二时钟源节点的时钟等级；
该装置还包括：
第二比较模块，用于将所述第一时钟源节点的时钟等级与所述第二时钟源节点的时钟等级进行比较；
判断模块，用于当所述第一时钟源节点的时钟等级等于所述第二时钟源节点的时钟等级时，判断所述第一时钟源节点的时钟等级是否小于或等于127；
第一比较模块502包括：
第一比较子模块，用于当所述第一时钟源节点的时钟等级大于127时，将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较。
可选地，该装置还包括：
选择模块503，还用于当所述第一时钟源节点的时钟等级小于或等于127时，根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；
第二校准模块，用于根据选择的主时钟节点的时间信息校准所述时钟同步装置的时钟。
可选地，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。
可选地，选择模块503包括：
第二比较子模块，用于将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较；
第一确定子模块，用于当所述第一最大时钟偏差累计值小于所述第二最大时钟偏差累计值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
可选地，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述第一时钟偏差方差值是指所述第一时钟源节点到所述第一主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值，所述第二时钟偏差方差值是指所述第二时钟源节点到所述第二主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值；
该装置还包括：
第三比较模块，用于当所述第一最大时钟偏差累计值等于所述第二最大时钟偏差累计值时，将所述第一时钟方差值与所述第二时钟方差值进行比较；
第一确定模块，用于当所述第一时钟方差值小于所述第二时钟方差值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
可选地，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。
可选地，选择模块503包括：
第二确定子模块，用于确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，所述第三最大时钟偏差累计值是指所述第一主时钟节点与所述时钟同步装置之间的传输介质对应的最大时钟偏差与所述第一最大时钟偏差累计值之和，所述第四最大时钟偏差累计值是指所述第二主时钟节点与所述时钟同步装置之间的传输介质对应的最大时钟偏差与所述第二最大时钟偏差累计值之和；
第三比较子模块，用于将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较；
第三确定子模块，用于当所述第三最大时钟偏差累计值小于所述第四最大时钟偏差累计值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
可选地，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述多个第一时钟偏差方差值包括所述第一时钟源节点到所述第一主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值，所述多个第二时钟偏差方差值包括所述第二时钟源节点到所述第二主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值；
该装置还包括：
第二确定模块，用于当所述第三最大时钟偏差累计值等于所述第四最大时钟偏差累计值时，确定第三时钟方差值和第四时钟方差值，所述第三时钟方差值是所述第一主时钟节点与所述时钟同步装置之间的传输介质对应的多个时钟偏差的方差值与所述第一时钟方差值的平方和的平方根，所述第四时钟方差值是所述第二主时钟节点与所述时钟同步装置之间的传输介质对应的多个时钟偏差的方差值与所述第二时钟方差值的平方和的平方根；
第四比较模块，用于将所述第三时钟方差值与所述第四时钟方差值进行比较；
第三确定模块，用于当所述第三时钟方差值小于所述第四时钟方差值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
在本申请实施例中，网络设备先接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值。然后该网络设备再将第一时钟源节点的标识与第二时钟源节点的标识进行比较，当第一时钟源节点的标识与第二时钟源节点的标识相同时，表明第一主时钟节点和第二主时钟节点对应同一时钟源节点，此时，根据第一最大时钟偏差累计值和第二最大时钟偏差累计值有助于从第一主时钟节点和第二主时钟节点中，选择时钟源节点到主时钟节点的路径上带来的时钟偏差较小的主时钟节点，再根据选择的主时钟节点的时间信息校准该网络设备的时钟。时钟源节点到主时钟节点的路径上带来的时钟偏差较小的话，通过该主时钟节点进行时钟同步的精确度更高，进而使得该网络设备校准之后的时钟的精度更高。
需要说明的是：上述实施例提供的时钟同步装置在时钟同步时，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的时钟同步装置与时钟同步方法实施例属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意结合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络或其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如：同轴电缆、光纤、数据用户线(Digital Subscriber Line，DSL))或无线(例如：红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质，或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如：软盘、硬盘、磁带)、光介质(例如：数字通用光盘(Digital Versatile Disc，DVD))或半导体介质(例如：固态硬盘(Solid State Disk，SSD))等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种时钟同步方法，其特征在于，所述方法包括：
    网络设备接收来自第一主时钟节点的通知Announce报文和来自第二主时钟节点的Announce报文，来自所述第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自所述第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值，所述第一最大时钟偏差累计值是所述第一时钟源节点到所述第一主时钟节点的路径上的多个第一最大时钟偏差之和，所述第二最大时钟偏差累计值是所述第二时钟源节点到所述第二主时钟节点的路径上的多个第二最大时钟偏差之和；
    所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较；
    当所述第一时钟源节点的标识与所述第二时钟源节点的标识相同时，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；
    所述网络设备根据选择的主时钟节点的时间信息校准所述网络设备的时钟。
  2. 如权利要求1所述的方法，其特征在于，来自所述第一主时钟节点的Announce报文还携带所述第一时钟源节点的时钟等级，来自所述第二主时钟节点的Announce报文还携带所述第二时钟源节点的时钟等级；
    所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较之前，所述方法还包括：
    所述网络设备将所述第一时钟源节点的时钟等级与所述第二时钟源节点的时钟等级进行比较；
    当所述第一时钟源节点的时钟等级等于所述第二时钟源节点的时钟等级时，所述网络设备判断所述第一时钟源节点的时钟等级是否小于或等于127；
    所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较，包括：
    当所述第一时钟源节点的时钟等级大于127时，所述网络设备将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较。
  3. 如权利要求2所述的方法，其特征在于，所述网络设备判断所述第一时钟源节点的时钟等级是否小于或等于127之后，所述方法还包括：
    当所述第一时钟源节点的时钟等级小于或等于127时，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；
    所述网络设备根据选择的主时钟节点的时间信息校准所述网络设备的时钟。
  4. 如权利要求1-3任一所述的方法，其特征在于，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的 路径上的多个时钟节点分别对应的多个最大时钟偏差。
  5. 如权利要求4所述的方法，其特征在于，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点，包括：
    所述网络设备将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较；
    当所述第一最大时钟偏差累计值小于所述第二最大时钟偏差累计值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  6. 如权利要求5所述的方法，其特征在于，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述第一时钟偏差方差值是指所述第一时钟源节点到所述第一主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值，所述第二时钟偏差方差值是指所述第二时钟源节点到所述第二主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值；
    所述网络设备将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较之后，所述方法还包括：
    当所述第一最大时钟偏差累计值等于所述第二最大时钟偏差累计值时，所述网络设备将所述第一时钟方差值与所述第二时钟方差值进行比较；
    当所述第一时钟方差值小于所述第二时钟方差值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  7. 如权利要求1-3任一所述的方法，其特征在于，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。
  8. 如权利要求7所述的方法，其特征在于，所述网络设备根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点，包括：
    所述网络设备确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，所述第三最大时钟偏差累计值是指所述第一主时钟节点与所述网络设备之间的传输介质对应的最大时钟偏差与所述第一最大时钟偏差累计值之和，所述第四最大时钟偏差累计值是指所述第 二主时钟节点与所述网络设备之间的传输介质对应的最大时钟偏差与所述第二最大时钟偏差累计值之和；
    所述网络设备将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较；
    当所述第三最大时钟偏差累计值小于所述第四最大时钟偏差累计值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  9. 如权利要求8所述的方法，其特征在于，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述多个第一时钟偏差方差值包括所述第一时钟源节点到所述第一主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值，所述多个第二时钟偏差方差值包括所述第二时钟源节点到所述第二主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值；
    所述网络设备将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较之后，所述方法还包括：
    当所述第三最大时钟偏差累计值等于所述第四最大时钟偏差累计值时，所述网络设备确定第三时钟方差值和第四时钟方差值，所述第三时钟方差值是所述第一主时钟节点与所述网络设备之间的传输介质对应的多个时钟偏差的方差值与所述第一时钟方差值的平方和的平方根，所述第四时钟方差值是所述第二主时钟节点与所述网络设备之间的传输介质对应的多个时钟偏差的方差值与所述第二时钟方差值的平方和的平方根；
    所述网络设备将所述第三时钟方差值与所述第四时钟方差值进行比较；
    当所述第三时钟方差值小于所述第四时钟方差值时，所述网络设备将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  10. 一种时钟同步装置，其特征在于，所述装置包括：
    接收模块，用于接收来自第一主时钟节点的Announce报文和来自第二主时钟节点的Announce报文，来自所述第一主时钟节点的Announce报文携带第一时钟源节点的标识和第一最大时钟偏差累计值，来自所述第二主时钟节点的Announce报文携带第二时钟源节点的标识和第二最大时钟偏差累计值，所述第一最大时钟偏差累计值是所述第一时钟源节点到所述第一主时钟节点的路径上的多个第一最大时钟偏差之和，所述第二最大时钟偏差累计值是所述第二时钟源节点到所述第二主时钟节点的路径上的多个第二最大时钟偏差之和；
    第一比较模块，用于将所述第一时钟源节点的标识与所述第二时钟源节点的标识进行比较；
    选择模块，用于当所述第一时钟源节点的标识与所述第二时钟源节点的标识相同时，根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；
    第一校准模块，用于根据选择的主时钟节点的时间信息校准所述时钟同步装置的时钟。
  11. 如权利要求10所述的装置，其特征在于，来自所述第一主时钟节点的Announce报文还携带所述第一时钟源节点的时钟等级，来自所述第二主时钟节点的Announce报文还携带所述第二时钟源节点的时钟等级；
    所述装置还包括：
    第二比较模块，用于将所述第一时钟源节点的时钟等级与所述第二时钟源节点的时钟等级进行比较；
    判断模块，用于当所述第一时钟源节点的时钟等级等于所述第二时钟源节点的时钟等级时，判断所述第一时钟源节点的时钟等级是否小于或等于127；
    所述第一比较模块包括：
    第一比较子模块，用于当所述第一时钟源节点的时钟等级大于127时，将所述第一时钟源节点的标识和所述第二时钟源节点的标识进行比较。
  12. 如权利要求11所述的装置，其特征在于，所述装置还包括：
    所述选择模块，还用于当所述第一时钟源节点的时钟等级小于或等于127时，根据所述第一最大时钟偏差累计值和所述第二最大时钟偏差累计值，从所述第一主时钟节点和所述第二主时钟节点中选择进行时钟同步的主时钟节点；
    第二校准模块，用于根据选择的主时钟节点的时间信息校准所述时钟同步装置的时钟。
  13. 如权利要求10-12任一所述的装置，其特征在于，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差。
  14. 如权利要求13所述的装置，其特征在于，所述选择模块包括：
    第二比较子模块，用于将所述第一最大时钟偏差累计值与所述第二最大时钟偏差累计值进行比较；
    第一确定子模块，用于当所述第一最大时钟偏差累计值小于所述第二最大时钟偏差累计值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  15. 如权利要求14所述的装置，其特征在于，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述第一时钟偏差方差值是指所述第一时钟源节点到所述第一主时钟节点的路径上的一个时钟节点对应的多个时钟 偏差的方差值，所述第二时钟偏差方差值是指所述第二时钟源节点到所述第二主时钟节点的路径上的一个时钟节点对应的多个时钟偏差的方差值；
    所述装置还包括：
    第三比较模块，用于当所述第一最大时钟偏差累计值等于所述第二最大时钟偏差累计值时，将所述第一时钟方差值与所述第二时钟方差值进行比较；
    第一确定模块，用于当所述第一时钟方差值小于所述第二时钟方差值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  16. 如权利要求10-12任一所述的装置，其特征在于，所述多个第一最大时钟偏差是指所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差，所述多个第二最大时钟偏差是指所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点分别对应的多个最大时钟偏差，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点之间的传输介质分别对应的至少一个最大时钟偏差。
  17. 如权利要求16所述的装置，其特征在于，所述选择模块包括：
    第二确定子模块，用于确定第三最大时钟偏差累计值和第四最大时钟偏差累计值，所述第三最大时钟偏差累计值是指所述第一主时钟节点与所述时钟同步装置之间的传输介质对应的最大时钟偏差与所述第一最大时钟偏差累计值之和，所述第四最大时钟偏差累计值是指所述第二主时钟节点与所述时钟同步装置之间的传输介质对应的最大时钟偏差与所述第二最大时钟偏差累计值之和；
    第三比较子模块，用于将所述第三最大时钟偏差累计值与所述第四最大时钟偏差累计值进行比较；
    第三确定子模块，用于当所述第三最大时钟偏差累计值小于所述第四最大时钟偏差累计值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  18. 如权利要求17所述的装置，其特征在于，来自所述第一主时钟节点的Announce报文还携带第一时钟方差值，来自所述第二主时钟节点的Announce报文还携带第二时钟方差值，所述第一时钟方差值是指多个第一时钟偏差方差值的平方和的平方根，所述第二时钟方差值是指多个第二时钟偏差方差值的平方和的平方根，所述多个第一时钟偏差方差值包括所述第一时钟源节点到所述第一主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第一时钟源节点到所述第一主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值，所述多个第二时钟偏差方差值包括所述第二时钟源节点到所述第二主时钟节点的路径上的每个时钟节点对应的多个时钟偏差的方差值，以及所述第二时钟源节点到所述第二主时钟节点的路径上的多个时钟节点中的至少一对相邻时钟节点中每对相邻时钟节点之间的传输介质对应的多个时钟偏差的方差值；
    所述装置还包括：
    第二确定模块，用于当所述第三最大时钟偏差累计值等于所述第四最大时钟偏差累计值时，确定第三时钟方差值和第四时钟方差值，所述第三时钟方差值是所述第一主时钟节点与所述时钟同步装置之间的传输介质对应的多个时钟偏差的方差值与所述第一时钟方差值的平方和的平方根，所述第四时钟方差值是所述第二主时钟节点与所述时钟同步装置之间的传输介质对应的多个时钟偏差的方差值与所述第二时钟方差值的平方和的平方根；
    第四比较模块，用于将所述第三时钟方差值与所述第四时钟方差值进行比较；
    第三确定模块，用于当所述第三时钟方差值小于所述第四时钟方差值时，将所述第一主时钟节点确定为进行时钟同步的主时钟节点。
  19. 一种计算机可读存储介质，所述计算机可读存储介质上存储有指令，其特征在于，所述指令被处理器执行时实现权利要求1-9所述的任一项方法的步骤。
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