WO2020133646A1 - Système et procédé d'attaque de dispositif d'affichage - Google Patents

Système et procédé d'attaque de dispositif d'affichage Download PDF

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Publication number
WO2020133646A1
WO2020133646A1 PCT/CN2019/075517 CN2019075517W WO2020133646A1 WO 2020133646 A1 WO2020133646 A1 WO 2020133646A1 CN 2019075517 W CN2019075517 W CN 2019075517W WO 2020133646 A1 WO2020133646 A1 WO 2020133646A1
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WO
WIPO (PCT)
Prior art keywords
switch module
bus
sub
terminal
output terminal
Prior art date
Application number
PCT/CN2019/075517
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English (en)
Chinese (zh)
Inventor
李文芳
曹丹
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2020133646A1 publication Critical patent/WO2020133646A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display device driving system and a display device driving method.
  • LCD liquid crystal displays
  • other flat display devices have been widely used in mobile phones, TVs, and individuals due to their advantages of high image quality, power saving, thin body, and wide range of applications.
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
  • the flat panel display device generally includes a display panel and an external driving circuit.
  • the external driving circuit generally includes a control board (CB) and a system chip (SOC).
  • the control board is provided with components such as a timing controller (TCON) and a power management chip (PMIC). .
  • the control board (CB) is connected to the control board integrated circuit (I2C) bus.
  • the control board I2C bus is connected to the timing controller and the power management chip.
  • the existing power management chip does not have a storage module inside, and its working parameters ( code) is stored in the external flash memory connected to the timing controller. Because the I2C bus of the control board connects the timing controller and the power management chip, the timing controller can read the code stored in the flash memory and pass the control during operation.
  • the board I2C bus is transmitted to the power management chip for its use. In order to prevent reading errors, this process is generally carried out during the frame blanking time of the display device, and will always occupy the control board I2C bus during the process.
  • the system chip is connected to the system chip I2C bus.
  • the system chip I2C bus needs to be directly connected to the control board I2C bus, so that the system chip can use the connected system chip I2C bus and the control board I2C bus to communicate with the control board to Perform the flicker adjustment operation. Because the system chip I2C bus is directly connected to the control board I2C bus, at some moments, the signal on the system chip I2C bus and the control board I2C bus may interfere with each other, affecting the effective transmission of the signal.
  • the object of the present invention is to provide a display device driving system capable of connecting or disconnecting the first I2C bus and the second I2C bus in a time-sharing manner, thereby ensuring the effective communication between the system chip and the control board and avoiding the first I2C When the bus and the second I2C bus work independently, the signals interfere with each other.
  • Another object of the present invention is to provide a display device driving method capable of connecting or disconnecting the first I2C bus and the second I2C bus in a time-sharing manner, thereby ensuring the effective communication between the system chip and the control board When one I2C bus and the second I2C bus work independently, the signals interfere with each other.
  • the present invention first provides a display device driving system, including a system chip, a control board, a switch module, a first I2C bus, and a second I2C bus;
  • the system chip is electrically connected to the input end of the switch module via the first I2C bus
  • the control board is electrically connected to the output end of the switch module via the second I2C bus
  • the control end of the switch module is connected to the control signal
  • the switch module When the control signal is a preset first potential, the switch module electrically connects its input terminal and output terminal, thereby electrically connecting the first I2C bus and the second I2C bus; when the control signal is preset When the second potential is reached, the switch module disconnects its input end from the output end, thereby disconnecting the first I2C bus from the second I2C bus.
  • the control board includes a body and a timing controller and a power management chip provided on the body; the second I2C bus is electrically connected to the timing controller and the power management chip.
  • the first I2C bus includes a first serial data line and a first serial clock line;
  • the input terminal of the switch module includes a first input terminal and a second input terminal;
  • the first serial data line and the first The serial clock line is electrically connected to the first input terminal and the second input terminal respectively;
  • the second I2C bus includes a second serial data line and a second serial clock line; the output terminal of the switch module includes a first output terminal and a second output terminal; the second serial data line and the second The serial clock line is electrically connected to the first output terminal and the second output terminal, respectively.
  • the switch module When the control signal is the preset first potential, the switch module connects its first input terminal to the first output terminal, and connects its second input terminal to the second output terminal; when the control signal is When the second potential is set, the switch module disconnects its first input terminal from the first output terminal, and disconnects its second input terminal from the second output terminal.
  • the switch module includes a first sub-switch module and a second sub-switch module; the control terminal of the first sub-switch module and the control terminal of the second sub-switch module are the control terminals of the switch module; the first sub-switch module The input end and the output end are respectively the first input end and the first output end of the switch module; the input end and the output end of the second sub-switch module are the second input end and the second output end of the switch module, respectively.
  • the first sub-switch module When the control signal is a preset first potential, the first sub-switch module connects its input end to the output end, and the second sub-switch module connects its input end to the output end; when the control signal is preset At the second potential, the first sub-switch module disconnects its input terminal from the output terminal, and the second sub-switch module disconnects its input terminal from the output terminal.
  • the first sub-switch module includes a first field effect tube and a second field effect tube, the gate of the first field effect tube and the gate of the second field effect tube are electrically connected to control the first sub-switch module
  • the source is the input of the first sub-switch module, and the drain is electrically connected to the drain of the second field-effect transistor, and the source of the second field-effect transistor is the output of the first sub-switch module;
  • the second sub-switch module includes a third field effect tube and a fourth field effect tube.
  • the gate of the third field effect tube and the gate of the fourth field effect tube are electrically connected to control the second sub-switch module.
  • the source terminal is the input terminal of the second sub-switch module, and the drain is electrically connected to the drain of the fourth field effect transistor, and the source of the fourth field-effect transistor is the output terminal of the second sub-switch module.
  • the first FET, the second FET, the third FET and the fourth FET are all N-type FETs.
  • the preset first potential is a high potential
  • the preset second potential is a low potential
  • the invention also provides a display device driving method, which is applied to the above display device driving system, and includes:
  • the control signal is a preset first potential, and the switch module electrically connects the input end and the output end thereof, thereby electrically connecting the first I2C bus and the second I2C bus;
  • the control signal is a preset second potential, and the switch module disconnects its input terminal from the output terminal, thereby disconnecting the first I2C bus from the second I2C bus.
  • the system chip is electrically connected to the input end of the switch module via the first I2C bus
  • the control board is electrically connected to the output end of the switch module via the second I2C bus.
  • the control terminal is connected to the control signal.
  • the switch module electrically connects the input terminal and the output terminal to electrically connect the first I2C bus and the second I2C bus.
  • the switch module disconnects its input and output terminals to disconnect the first I2C bus from the second I2C bus, and can connect or disconnect the first I2C bus and the second I2C bus in a time-sharing manner.
  • the display device driving method of the present invention can connect or disconnect the first I2C bus and the second I2C bus in a time-sharing manner, thereby ensuring the effective communication between the system chip and the control board and avoiding the first I2C bus and the second I2C bus The signals interfere with each other when working alone.
  • FIG. 1 is a schematic structural diagram of a display device driving system of the present invention
  • FIG. 2 is a flowchart of a driving method of a display device of the present invention
  • FIG. 3 is a timing diagram of step S1 of the display device driving method of the present invention.
  • FIG. 4 is a timing diagram of step S2 of the display device driving method of the present invention.
  • the present invention provides a display device driving system, including a system chip 10 Control panel 20 , Switch module 30 ,the first I2C bus 40 And second I2C bus 50 .
  • the system chip 10 First I2C bus 40 With switch module 30
  • the input terminal is electrically connected to the control board 20 Second I2C bus 50 With switch module 30
  • the output of the switch is electrically connected, the switch module 30
  • the switch module 30 Connect its input and output terminals electrically, so that the first I2C bus 40 With the second I2C bus 50 Electrical connection.
  • the switch module 30 Disconnect its input from the output, so that the first I2C bus 40 With the second I2C bus 50 disconnect.
  • control board 20 Including ontology twenty one And on the body twenty one Timing controller twenty two And power management chip twenty three .
  • the second I2C bus 50 With timing controller twenty two And power management chip twenty three All are electrically connected.
  • the first I2C bus 40 Including the first serial data line SDA_S And the first serial clock line SCL_S .
  • the switch module 30 The input terminal includes a first input terminal and a second input terminal.
  • the first serial data line SDA_S And the first serial clock line SCL_S It is electrically connected to the first input terminal and the second input terminal respectively.
  • the second I2C bus 50 Includes second serial data line SDA_C And the second serial clock line SCL_C .
  • the switch module 30 The output terminal includes a first output terminal and a second output terminal.
  • the second serial data line SDA_C And the second serial clock line SCL_C They are electrically connected to the first output terminal and the second output terminal respectively.
  • the switch module 30 Connect the first input terminal to the first output terminal, and connect the second input terminal to the second output terminal.
  • the switch module 30 Disconnect its first input from the first output, and disconnect its second input from the second output.
  • the switch module 30 Including the first sub-switch module 31 And the second sub-switch module 32 .
  • the first sub-switch module 31 Control terminal and second sub-switch module 32 The control terminal is the switch module 30 Control side.
  • the first sub-switch module 31 The input terminal and output terminal are switch modules 30 The first input terminal and the first output terminal.
  • the second sub-switch module 32 The input terminal and output terminal are switch modules 30 The second input and the second output.
  • the control signal WP When it is the preset first potential, the first sub-switch module 31 Connect its input and output, the second sub-switch module 32 Connect its input and output.
  • the control signal WP When it is the preset second potential, the first sub-switch module 31 Disconnect its input and output, the second sub-switch module 32 Disconnect its input and output.
  • the first sub-switch module 31 Including the first FET Q1 FET Q2 , The first FET Q1 Grid and second field effect transistor Q2 Is electrically connected to the first sub-switch module 31
  • the control terminal of the source is the first sub-switch module 31
  • the input terminal, the drain is electrically connected to the second FET Q2
  • the drain of the second FET Q2 The source is the first sub-switch module 31 Output.
  • the second sub-switch module 32 Including third field effect transistor Q3 And fourth field effect transistor Q4 , The third FET Q3 Gate and fourth field effect transistor Q4 Is electrically connected to the second sub-switch module 32
  • the control terminal of the source is the second sub-switch module 32 Input terminal, the drain is electrically connected to the fourth field effect transistor Q4 The drain of the fourth FET Q4
  • the source is the second sub-switch module 32 Output.
  • the first field effect tube Q1 2.
  • Second Field Effect Transistor Q2 3rd field effect transistor Q3 And fourth field effect transistor Q4 All N Type field effect tube.
  • the preset first potential is a high potential
  • the preset second potential is a low potential
  • a switch module is provided by 31 , The switch module 31 The control terminal access control signal WP , The input terminal is electrically connected to the system chip 10 Electrically connected first I2C bus 40 , The output terminal is electrically connected to the control board 20 Electrically connected second I2C bus 50 , When the system chip needs to be 10 With control panel 20 When electrically connected, please refer to the picture 3 To make the control signal WP For the first potential of high potential, control the switch module 31 Connect its input and output terminals electrically, so that the first I2C bus 40 With the second I2C bus 50 Electrically connected, so that the system chip 10 And control board 20 The first one that can be electrically connected I2C bus 40 With the second I2C bus 50 Communication, this time first I2C bus 40 The first serial data line SDA_S The waveform of the voltage on the second I2C bus 50 Second serial data line SDA_C The waveform of the voltage on is consistent, the first I2C bus 40 The first serial clock
  • the second potential of the low potential controls the switch module 31 Disconnect its input from the output, so that the first I2C bus 40 With the second I2C bus 50 Disconnected, at this time the first I2C bus 40
  • the first serial data line SDA_S The waveform of the voltage on the second I2C bus 50 Second serial data line SDA_C
  • the waveforms on the voltage are independent, the first I2C bus 40
  • the first serial clock line SCL_S The waveform of the voltage on the second I2C bus 50 Second serial clock line SCL_C
  • the waveforms on the voltage are independent, the first I2C bus 40 And second I2C bus 50 Able to transmit signals independently without interfering with each other.
  • the present invention also provides a display device driving method, which is applied to the above-mentioned display device driving system and includes the following steps:
  • step S1 Please refer to the picture 1 And figure 3 ,
  • the control signal WP It is the preset first potential, specifically high potential, switch module 30 Connect its input and output terminals electrically, so that the first I2C bus 40 With the second I2C bus 50 Electrically connected, so that the system chip 10 And control board 20 The first one that can be electrically connected I2C bus 40 With the second I2C bus 50 Communication, this time first I2C bus 40
  • the first serial data line SDA_S The waveform of the voltage on the second I2C bus 50 Second serial data line SDA_C
  • the waveform of the voltage on is consistent
  • the first I2C bus 40 The first serial clock line SCL_S The waveform of the voltage on the second I2C bus 50 Second serial clock line SCL_C The waveform of the voltage on is consistent.
  • step S2 Please refer to the picture 1 And figure 4 ,
  • switch module 30 Disconnect its input from the output, so that the first I2C bus 40 With the second I2C bus 50 Disconnected, at this time the first I2C bus 40
  • the first serial data line SDA_S The waveform of the voltage on the second I2C bus 50 Second serial data line SDA_C
  • the waveforms on the voltage are independent of each other, the first I2C bus 40
  • the first serial clock line SCL_S The waveform of the voltage on the second I2C bus 50 Second serial clock line SCL_C
  • the waveforms on the voltage are independent of each other, the first I2C bus 40 And second I2C bus 50 Able to transmit signals independently without interfering with each other.
  • the system chip I2C The bus is electrically connected to the input end of the switch module, and the control board passes the second I2C
  • the bus is electrically connected to the output end of the switch module, the control end of the switch module is connected to the control signal, and when the control signal is the preset first potential, the switch module electrically connects its input end and the output end to connect the first I2C Bus and second I2C The bus is electrically connected.
  • the switch module disconnects its input end from the output end to connect the first I2C Bus and second I2C The bus is disconnected.
  • I2C Bus and second I2C The bus is connected or disconnected, so as to ensure the effective communication between the system chip and the control board, and avoid the first I2C Bus and second I2C When the bus works alone, the signals interfere with each other.
  • the display device driving method of the present invention can I2C Bus and second I2C The bus is connected or disconnected, so as to ensure the effective communication between the system chip and the control board, and avoid the first I2C Bus and second I2C When the bus works alone, the signals interfere with each other.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Système et procédé d'attaque de dispositif d'affichage. Un système (10) sur puce dans le système d'attaque de dispositif d'affichage est relié électriquement à une extrémité d'entrée d'un module (30) de commutation au moyen d'un premier bus I2C (40). Une carte (20) de commande est reliée électriquement à une extrémité de sortie du module (30) de commutation au moyen d'un second bus I2C (50). Une extrémité de commande du module (30) de commutation est reliée à un signal de commande (WP). Lorsque le signal de commande (WP) est à un premier potentiel électrique prédéfini, le module (30) de commutation connecte électriquement son extrémité d'entrée et son extrémité de sortie de façon à connecter électriquement le premier bus I2C (40) et le second bus I2C (50). Lorsque le signal de commande (WP) est à un second potentiel électrique prédéfini, le module (30) de commutation déconnecte son extrémité d'entrée et son extrémité de sortie de façon à déconnecter le premier bus I2C (40) et le second bus I2C (50). Le premier bus I2C (40) et le second bus I2C (50) peuvent être connectés ou déconnectés selon un partage de temps, assurant ainsi une communication efficace entre le système (10) sur puce et la carte (20) de commande, et évitant un brouillage mutuel de signaux lorsque le premier bus I2C (40) et le second bus I2C (50) fonctionnent séparément.
PCT/CN2019/075517 2018-12-28 2019-02-20 Système et procédé d'attaque de dispositif d'affichage WO2020133646A1 (fr)

Applications Claiming Priority (2)

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CN201811618442.7A CN109410824A (zh) 2018-12-28 2018-12-28 显示装置驱动系统及显示装置驱动方法
CN201811618442.7 2018-12-28

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WO2020133646A1 true WO2020133646A1 (fr) 2020-07-02

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CN110223652B (zh) * 2019-06-10 2021-08-24 北海惠科光电技术有限公司 时序控制器控制方法、时序控制器和驱动电路
CN110992866B (zh) * 2019-12-10 2022-12-06 Tcl华星光电技术有限公司 显示面板的驱动电路和电子设备的逻辑电路
CN112735317B (zh) * 2020-12-31 2023-03-17 绵阳惠科光电科技有限公司 控制电路和显示装置
CN112785957B (zh) * 2021-01-05 2023-02-03 Tcl华星光电技术有限公司 驱动电路、显示装置及其控制方法
CN113284452A (zh) * 2021-05-31 2021-08-20 深圳市华星光电半导体显示技术有限公司 显示装置及其控制方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050023011A (ko) * 2003-08-28 2005-03-09 삼성전자주식회사 액정 표시 장치용 구동 장치 및 방법
CN201388259Y (zh) * 2009-03-20 2010-01-20 青岛海信电器股份有限公司 一种板间连接电路及具有所述电路的液晶电视机
KR20110066735A (ko) * 2009-12-11 2011-06-17 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN104299556A (zh) * 2014-10-13 2015-01-21 深圳市华星光电技术有限公司 驱动电路及显示装置
CN106847163A (zh) * 2017-04-19 2017-06-13 惠科股份有限公司 一种显示面板控制电路、显示装置及其控制方法
CN107610664A (zh) * 2017-09-25 2018-01-19 惠科股份有限公司 一种电路板以及显示器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2730049Y (zh) * 2004-10-14 2005-09-28 海信集团有限公司 电视机iic总线上的隔离电路
CN101539900B (zh) * 2008-03-18 2011-08-24 英业达股份有限公司 解决具有相同定址地址的两i2c从属装置间产生冲突的装置
CN102194436B (zh) * 2011-04-18 2015-09-16 北京彩讯科技股份有限公司 Ddc接口隔离保护电路
CN206259950U (zh) * 2016-10-25 2017-06-16 深圳欧陆通电子有限公司 一种通信总线隔离电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050023011A (ko) * 2003-08-28 2005-03-09 삼성전자주식회사 액정 표시 장치용 구동 장치 및 방법
CN201388259Y (zh) * 2009-03-20 2010-01-20 青岛海信电器股份有限公司 一种板间连接电路及具有所述电路的液晶电视机
KR20110066735A (ko) * 2009-12-11 2011-06-17 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN104299556A (zh) * 2014-10-13 2015-01-21 深圳市华星光电技术有限公司 驱动电路及显示装置
CN106847163A (zh) * 2017-04-19 2017-06-13 惠科股份有限公司 一种显示面板控制电路、显示装置及其控制方法
CN107610664A (zh) * 2017-09-25 2018-01-19 惠科股份有限公司 一种电路板以及显示器

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