WO2020133630A1 - 显示面板的时序控制芯片的控制方法和显示面板 - Google Patents

显示面板的时序控制芯片的控制方法和显示面板 Download PDF

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Publication number
WO2020133630A1
WO2020133630A1 PCT/CN2019/073607 CN2019073607W WO2020133630A1 WO 2020133630 A1 WO2020133630 A1 WO 2020133630A1 CN 2019073607 W CN2019073607 W CN 2019073607W WO 2020133630 A1 WO2020133630 A1 WO 2020133630A1
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Prior art keywords
timing control
control chip
comparison result
enable signal
chip
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Ceased
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PCT/CN2019/073607
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English (en)
French (fr)
Inventor
张良
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HKC Co Ltd
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HKC Co Ltd
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Priority to US17/040,971 priority Critical patent/US11636815B2/en
Publication of WO2020133630A1 publication Critical patent/WO2020133630A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller

Definitions

  • the present application relates to the field of display devices, and in particular, to a method for controlling a timing control chip of a display panel and a display panel.
  • liquid crystal display which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel and a backlight module.
  • the liquid crystal panel includes a color filter substrate (Color Filter Substrate, CF Substrate, also known as a color filter substrate), a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate)
  • CF Substrate Color Filter Substrate
  • TFT Substrate thin film transistor array substrate
  • the purpose of the present application is to provide a method for controlling a timing control chip of a display panel and a display panel, to prevent the screen abnormality caused by an error in reading the initialization configuration code of the timing control chip.
  • the present application provides a method for controlling a timing control chip of a display panel, including the steps of: a pulse modulator generates a write protection level and outputs it to a write protection pin of a memory chip; a detection circuit detects a write Enter the actual level value of the protection pin; the detection circuit compares the actual level value with the write protection level, and sends the comparison result to the timing control chip; the timing control chip controls whether to read the memory chip according to the comparison result The initial configuration code stored in it.
  • the present application also provides a method for controlling a timing control chip of a display panel, including the steps of: a pulse modulator generates a write protection level and outputs it to a write protection pin of a memory chip;
  • the detection circuit detects the actual level value of the write protection pin; the detection circuit compares the actual level value with the write protection level and sends the comparison result to the timing control chip; the detection circuit outputs the corresponding value according to the comparison result Enable signal to the timing control chip; if the comparison result is that the actual level value is not equal to the write protection level, the detection circuit sends a first enable signal to the timing control chip; the timing control chip controls the off according to the first enable signal Turn on the serial bidirectional pass bus set between the timing control chip and the memory chip; the timing control chip does not output the serial bidirectional pass signal to the memory chip; restart the circuit; the detection circuit re-detects the actual level value of the write protection pin ; If the comparison result is that the actual level value is equal to the write protection level, the detection circuit sends a second enable signal to the timing control chip; the timing control chip controls the activation and setting between the timing control chip and the memory chip according to the second enable signal
  • the present application also provides a display panel, including: a memory chip, including a write protection pin, storing the initialization code of the timing control chip; a timing control chip, reading the initialization code of the timing control chip and performing initialization configuration; a serial bidirectional pass bus , Which is set between the memory chip and the timing control chip; a pulse modulator, which outputs a write protection level to the write protection pin; and a detection circuit, which is provided in the pulse modulator and detects writing The actual level value of the protection pin is compared with the write protection level, and a corresponding enable signal is output to the timing control chip according to the comparison result; the timing control chip includes a microprogram controller, the microprogram The controller receives the corresponding enable signal and controls to disconnect or enable the serial bidirectional pass-through bus provided between the memory chip and the timing control chip according to the enable signal.
  • the microprogram controller inside the timing control chip will read the initialization configuration code stored in the memory chip through the serial bidirectional bus to complete the initialization setting of the timing control chip.
  • the protection level will actually change due to interference and other conditions.
  • the level changes the initial configuration code is read, and the high error rate causes subsequent problems; and the detection circuit can detect the write protection pin If the level value is abnormal, it means that there may be an error in reading. You can tell the timing control chip not to read to avoid the problem of reading error.
  • FIG. 1 is a schematic diagram of a communication architecture according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an improved communication architecture according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of steps of a method for controlling a timing control chip according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • EEPROM Electrical Erasable Programmable Read-Only Memory
  • FIG. 1 is the communication architecture diagram of TCON and EEPROM.
  • the micro controller Microcontroller Unit; MCU
  • MCU Microcontroller Unit
  • I2C Inter-Integrated Circuit
  • Microcontroller and its peripheral equipment One serial data line SDA and one serial clock line SCL;
  • the bus reads the initialization configuration code (code) stored in the EEPROM to complete the initialization setting of TCON.
  • the EEPROM write protection signal (Write-Protection, WP) generated by the PWM IC, the normal pull-down High is 3.3V, that is to say, it should be in the write protection state under normal conditions, but the problem that is more likely to occur now is that it may be due to possible Wires or other interferences cause the WP level to be lower than 3.3V to be disabled, and the I2C bus communication is not normal, then there may be malfunctions that cause errors when reading the code stored in the EEPROM, and there is no error correction mechanism nowadays , Then there is no way to prevent this from happening.
  • WP Write-Protection
  • an embodiment of the present application discloses a method for controlling the timing control chip 120 of the display panel 100, including the steps of:
  • the pulse modulator 130 generates a write protection level and outputs it to the write protection pin 112 of the memory chip 110;
  • the detection circuit 131 detects the actual level value of the write protection pin 112;
  • the detection circuit 131 compares the actual level value with the write protection level, and sends the comparison result to the timing control chip 120;
  • the timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the comparison result.
  • the write protection level will change due to interference and other conditions.
  • the initial configuration code is read, and the high error rate causes subsequent problems; and the detection circuit 131 can detect The actual level value of the write protection pin 112, if the level value is abnormal, it means that an error may occur in reading, you can tell the timing control chip 120, do not read, to avoid the problem of reading error, Ensure that the screen is displayed normally.
  • the timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the comparison result: the detection circuit 131 outputs a corresponding enable signal to the timing control chip 120 according to the comparison result; The timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the corresponding enable signal.
  • the timing control chip 120 completes the comparison work, and controls whether to read based on the read signal and the enable signal used by itself If there is an abnormality, the timing control chip 120 will not read the wrong code, causing a screen display problem.
  • the timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the corresponding enable signal includes: if the comparison result is that the actual level value is not equal to the write protection power
  • the detection circuit 131 sends a first enable signal to the timing control chip 120; the timing control chip 120 controls to disconnect the serial bidirectional pass-through bus 140 provided between the timing control chip 120 and the memory chip 110 according to the first enable signal ;
  • the timing control chip 120 does not output a serial bidirectional pass signal to the memory chip 110.
  • the first enable signal indicates that an unexpected problem occurred in reading the code, which may be electrostatic interference, or other signal interference, and other possibilities.
  • the first enable signal tells the timing control chip 120 to be off When the I2C bus is turned on, the timing does not output the I2C signal, so the operation of reading the code of the memory chip 110 will not be performed, and the timing control chip 120 will not read the wrong code, causing screen display problems.
  • the step of the timing control chip 120 not outputting the serial bidirectional pass signal to the memory chip 110 further includes: restarting the circuit; the detection circuit 131 re-detects the actual level value of the write protection pin 112; if compared As a result, the actual level value is equal to the write protection level, and the detection circuit 131 sends a second enable signal to the timing control chip 120; the timing control chip 120 controls the enabling and setting of the timing control chip 120 and the memory chip according to the second enable signal Serial bidirectional pass bus 140 between 110; the timing control chip 120 outputs a serial bidirectional pass signal to the memory chip 110, and reads the initialization configuration code stored in the memory chip 110; the timing control chip 120 according to the read initialization configuration Code for initial configuration.
  • the second enable signal in addition to controlling the disconnection of the I2C bus, also informs the timing control chip 120 that the problem of static electricity or external signal interference needs to be eliminated by restarting the circuit or re-powering on. After the problem is eliminated, as long as the level of WP The level returns to normal, then TCON will still read the code correctly, so as to display the picture correctly.
  • an embodiment of the present application discloses a method for controlling the timing control chip 120 of the display panel 100, including the steps of:
  • the pulse modulator 130 generates a write protection level and outputs it to the write protection pin 112 of the memory chip 110;
  • the detection circuit 131 detects the actual level value of the write protection pin 112;
  • the detection circuit 131 compares the actual level value with the write protection level, and sends the comparison result to the timing control chip 120;
  • the timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the comparison result.
  • the write protection level will change due to interference and other conditions.
  • the initial configuration code is read, and the high error rate causes subsequent problems; and the detection circuit 131 can detect The actual level value of the write protection pin 112, if the level value is abnormal, it means that an error may occur in reading, you can tell the timing control chip 120, do not read, to avoid the problem of reading error, Ensure that the screen is displayed normally.
  • the timing control chip 120 controls whether to read the initial configuration code stored in the memory chip 110 according to the comparison result: the detection circuit 131 outputs a corresponding enable signal to the timing control chip according to the comparison result 120; The timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the corresponding enable signal.
  • the timing control chip 120 completes the comparison work, and controls whether to read based on the read signal and the enable signal used by itself If there is an abnormality, the timing control chip 120 will not read the wrong code, causing a screen display problem.
  • the timing control chip 120 controls whether to read the initialization configuration code stored in the memory chip 110 according to the corresponding enable signal includes: if the comparison result is that the actual level value is not equal to the write protection power
  • the detection circuit 131 sends a first enable signal to the timing control chip 120; the timing control chip 120 controls to disconnect the serial bidirectional pass-through bus 140 provided between the timing control chip 120 and the memory chip 110 according to the first enable signal ;
  • the timing control chip 120 does not output a serial bidirectional pass signal to the memory chip 110.
  • the first enable signal indicates that an unexpected problem occurred in reading the code, which may be electrostatic interference, or other signal interference, and other possibilities.
  • the first enable signal tells the timing control chip 120 to be off When the I2C bus is turned on, the timing does not output the I2C signal, so the operation of reading the code of the memory chip 110 will not be performed, and the timing control chip 120 will not read the wrong code, causing screen display problems.
  • the step of the detection circuit 131 sending a first enable signal to the timing control chip 120 includes:
  • the pulse modulator 130 sets a preset level value; if the actual level value is not equal to the write protection level value and is equal to the preset level value in the comparison result, the detection circuit 131 sends a third enable signal Give timing control chip 120.
  • the preset level value is the control output through the pulse modulation IC. When the preset level value occurs, it will indicate that there is some expected problem in the action of reading the code. It needs to be specifically eliminated before the code can be read. take.
  • the third enable signal is to check whether the code itself is correct. At this time, the circuit may not be affected by static electricity or interference signals. The reading operation itself is correct, but it may still cause problems such as abnormal screen display.
  • the third enable signal in addition to telling the timing control chip 120 not to read, also tells it that the problem is that the code itself is wrong. It is necessary to store the correct code for the memory chip 110 in order to ensure that the subsequent screen is displayed normally. After the code, the timing control chip 120 reads the correct code.
  • the detection circuit 131 sends a third enable signal to the timing control chip 120
  • the steps include: the detector 111 reads the actual calibration and information from the actual stored initial configuration code, and compares the actual calibration and information with the pre-stored standard calibration and information. If the calibration and the information are inconsistent, the initial configuration code error signal is output to the pulse modulator 130; the pulse modulator 130 controls the level value of the write protection pin to become the preset level value; the detection circuit 131 detects the preset power If the value is equal, a third enable signal is sent to the timing control chip 120.
  • the preset level value represents that the error of the code data itself has occurred.
  • a detector 111 may be added to the memory chip 110.
  • the detector 111 stores the standard calibration and information corresponding to the correct code ; Before reading the code, the detector 111 detects the actual calibration and information in the code and compares it with the standard calibration and information. If the comparison result is inconsistent, the code error signal is output to the PWM IC.
  • the IC controls the level value of the write-protect pin 112 to become a preset level value, and the detection circuit detects the preset level value and outputs a third enable signal; the third enable signal helps timing
  • the control chip 120 not only disconnects the I2C bus, but also informs that the reason for the disconnection is the error of the code data itself. After the correct code data needs to be updated, the timing control chip 120 reads the normal code and displays it normally.
  • the timing control chip 120 controls whether to read the initialization configuration code of the timing control chip 120 stored in the memory chip 110 according to the comparison result.
  • the step further includes: the detector 111 reads from the actually stored initialization configuration code Take the actual calibration and information, and compare the actual calibration and information with the pre-stored standard calibration and information; output the correct information or error information of the initial configuration code to the timing control chip 120 according to the comparison result; the timing control chip 120 is based on The correct information or error information of the initial configuration code is used to control the disconnection or enable of the serial bidirectional bus 140; when the timing control chip 120 receives the correct information of the initial configuration code, the timing control chip 120 according to the comparison result of the detection circuit 131, Control whether to read the timing control chip 120 stored in the memory chip 110 to initialize the configuration code.
  • the detector 111 is added here.
  • the detector 111 reads the actual calibration and information from the actually stored code, and compares the actual calibration and information with the pre-stored standard calibration and information; if the actual calibration and information are If the standard calibration and information are inconsistent, the code error signal is output to the timing control chip 120; if the actual calibration and information are consistent with the standard calibration and information, the code correct signal is output to the timing control chip 120; the timing control chip 120 judges first Whether the code error information or the code correct information is read. If the timing control chip 120 receives the code error information, it controls to disconnect the I2C bus between the timing control chip 120 and the memory chip 110;
  • the timing control chip 120 controls whether to read the initialization configuration code of the timing control chip 120 stored in the storage chip 110 according to the comparison result of the detection circuit 131, and directly Code correct or wrong information is sent to the timing control chip 120.
  • an embodiment of the present application discloses a method for controlling the timing control chip 120 of the display panel 100, including the steps of:
  • the pulse modulator 130 generates a write protection level and outputs it to the write protection pin 112 of the memory chip 110; the detection circuit 131 detects the actual level value of the write protection pin 112; the detection circuit 131 converts the actual level value Compare with the write protection level and send the comparison result to the timing control chip 120; the detection circuit 131 outputs the corresponding enable signal to the timing control chip 120 according to the comparison result; if the comparison result is that the actual level value is not equal to the write
  • the detection circuit 131 sends a first enable signal to the timing control chip 120; the timing control chip 120 controls to disconnect the serial bidirectional set between the timing control chip 120 and the memory chip 110 according to the first enable signal Pass-through bus 140; timing control chip 120 does not output a serial bidirectional pass signal to memory chip 110; restart the circuit; detection circuit 131 re-detects the actual level value of write protection pin 112; if the comparison result is that the actual level value is equal to Write protection level, the detection circuit 131 sends a second enable signal
  • the setting detection circuit 131 can detect the write For the actual level value of the protection pin 112, the detection circuit 131 outputs the corresponding enable signal to the timing control chip 120 according to the comparison result.
  • the comparison result is that the actual level value is not equal to the write protection level, and the detection circuit 131 issues the An enable signal is given to the timing control chip 120.
  • the first enable signal indicates that an unexpected problem has occurred in the code reading, which may be electrostatic interference, other signal interference, and other possibilities. At this time, the first The enable signal tells the timing control chip 120 to disconnect the I2C bus.
  • the detection circuit 131 sends a second enable signal to the timing control chip 120.
  • the second enable signal also informs the timing control chip 120, the problem of static electricity or external signal interference needs to be eliminated by restarting the circuit or re-powering on. After the problem is removed, as long as the level of WP returns to normal, then TCON will still read the code correctly, so as to correctly The screen is displayed.
  • the present application also provides a display panel 100, including: a memory chip 110, including a write protection pin 112, and a storage timing control chip 120 initialization code ; Timing control chip 120, read the timing control chip 120 initialization code and initialize the configuration; serial bidirectional pass bus 140, set between the memory chip 110 and the timing control chip 120; pulse modulator 130, output write protection Level to the write protection pin; the detection circuit 131, which is set in the pulse modulator 130, detects the actual level value of the write protection pin 112, compares it with the write protection level, and according to The comparison result outputs a corresponding enable signal to the timing control chip 120; the timing control chip 120 includes a microprogram controller 121, and the microprogram controller 121 receives the corresponding enable signal, and controls the disconnection or enabling settings according to the enable signal A serial bidirectional bus 140 between the memory chip 110 and the timing control chip 120.
  • a detection circuit 131 for WP level is added inside the PWM IC, and an enable signal output is sent to the TCON to make a decision to turn on or off the bus after detecting the size of the WP level, thereby preventing the occurrence of EEPROM An error occurred when reading the code.
  • the detection circuit 131 sends an enable signal output1 to the TCON to Make a decision to switch on the I2C bus, that is, the EEPROM has been in write protection at this time, no matter how the I2C signal changes, there will be no error in reading the code; if the WP level detection circuit 131 detects WP power When it is lower than the High 3.3V level; the detection circuit 131 sends an enable signal output2 to the TCON to make the decision to disconnect the I2C bus. At this time, the EEPROM write protection is invalid, and the TCON does not output the I2C signal. There will be no error in reading the code. After re-powering on, as long as the level of WP returns to normal, then TCON will still read the code correctly, so as to display the picture correctly.
  • the memory chip 110 further includes: a detector 111 storing standard calibration and information, and the detector 111 detects the actual calibration and information stored in the storage chip 110, and checks and calibrates the information and actual according to the standard The result of the comparison between the calibration and the information, output the correct information of the initial configuration code or the error information of the initial configuration code; the timing control chip 120 controls to disconnect or enable the setting on the memory chip 110 and the timing control according to the correct information of the initial configuration code or the error information of the initial configuration code A serial bidirectional bus 140 between the chips 120.
  • a detector 111 is added to the storage chip 110, and the detector 111 stores the standard calibration and information corresponding to the correct code; before reading the code, the detector 111 detects the actual calibration and information in the code, And compare with the standard calibration and information. If the comparison result is inconsistent, output code error signal to PWM IC, which controls the level value of write protection pin 112 to become the preset level value.
  • the test circuit detects the preset level value and outputs a third enable signal; in addition to helping the timing control chip 120 disconnect the I2C bus, the third enable signal also informs that the cause of the disconnection is the problem of the code data itself, After the correct code data needs to be updated, the timing control chip 120 is allowed to read the normal code and display it normally.
  • all the above detection circuits can be ordinary voltage division detection circuits or current detection circuits, and even ordinary potentiometers or current meters can realize the function of detecting the level of the corresponding pin.
  • the panel of this application may be a TN panel (full name Twisted Nematic, ie twisted nematic panel), IPS panel (In-Plane Switching), VA panel (Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology), Of course, it can also be other types of panels, just apply.
  • TN panel full name Twisted Nematic, ie twisted nematic panel
  • IPS panel In-Plane Switching
  • VA panel Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种显示面板的时序控制芯片的控制方法和显示面板，包括步骤:写入保护电平输出至写入保护引脚；检测写入保护引脚的实际电平值；根据实际电平值跟写入保护电平的比较结果，控制是否读取初始化配置编码。

Description

显示面板的时序控制芯片的控制方法和显示面板
本申请要求于2018年12月27日提交中国专利局、申请号为CN201811607004.0、发明名称为“一种显示面板的时序控制芯片的控制方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示装置领域，尤其涉及一种显示面板的时序控制芯片的控制方法和显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息,而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。现在市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，目前已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)和光罩(Mask)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。
一般在液晶面板的电路之间都会存在内阻损耗，会导致电压不稳定，从而影响信号的输出，导致画面异常，降低实验和生产效率的问题。
技术解决方案
本申请的目的在于提供一种显示面板的时序控制芯片的控制方法和显示面板，防止时序控制芯片初始化配置编码读取错误造成画面异常。
为实现上述目的，本申请提供了一种显示面板的时序控制芯片的控制方法，包括步骤:脉冲调制器产生写入保护电平并输出到存储芯片的写入保护引脚；侦测电路检测写入保护引 脚的实际电平值；侦测电路将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片；时序控制芯片根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码。
本申请还提供一种显示面板的时序控制芯片的控制方法，包括步骤:脉冲调制器产生写入保护电平并输出到存储芯片的写入保护引脚；
侦测电路检测写入保护引脚的实际电平值；侦测电路将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片；侦测电路根据比较结果输出对应的使能信号给时序控制芯片；若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片；时序控制芯片根据第一使能信号控制断开设置在时序控制芯片和存储芯片之间的串行双向通行总线；时序控制芯片不输出串行双向通行信号给存储芯片；重启电路；侦测电路重新检测写入保护引脚的实际电平值；若比较结果为实际电平值等于写入保护电平，侦测电路发出第二使能信号给时序控制芯片；时序控制芯片根据第二使能信号控制启用设置在时序控制芯片和存储芯片之间的串行双向通行总线；时序控制芯片输出串行双向通行信号给存储芯片，并读取存储在存储芯片中的初始化配置编码；时序控制芯片根据读取的初始化配置编码进行初始化配置。
本申请还提供了一种显示面板,包括：存储芯片，包括写入保护引脚，存储时序控制芯片初始化编码；时序控制芯片，读取时序控制芯片初始化编码并进行初始化配置；串行双向通行总线，设置在所述存储芯片和时序控制芯片之间；脉冲调制器，输出写入保护电平到所述写入保护引脚；以及侦测电路，设置在所述脉冲调制器内，检测写入保护引脚的实际电平值，与写入保护电平进行比较，并根据比较结果输出对应的使能信号给所述时序控制芯片；所述时序控制芯片包括微程序控制器，所述微程序控制器接收所述对应的使能信号，并根据使能信号控制断开或者启用设置在存储芯片和时序控制芯片之间的串行双向通行总线。
在刚上电时，时序控制芯片内部的微程序控制器会通过串行双向通行总线去读取存储芯片里面存储的初始化配置编码，完成时序控制芯片的初始化设定的情况来说，对于写入保护电平，实际上会因为干扰等情况会发生电平变化，发生电平变化的时候读取初始化配置编码，错误率高而造成后续问题；而侦测电路可以侦测该写入保护引脚的实际电平值，若电平值出现异常，则代表读取可能发生错误，则可以告知该时序控制芯片，不要进行读取，以避免读取错误的问题。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的 附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种通信架构的示意图；
图2是本申请实施例一种改善后的通信架构的示意图；
图3是本申请实施例一种时序控制芯片的控制方法步骤的示意图；
图4是本申请实施例一种显示面板的示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和实施例对本申请作进一步说明。
在液晶面板的驱动控制板上，有一颗可编程可擦除型存储IC(Electrically Erasable Programmable Read-Only Memory，EEPROM)，用来存储时序控制芯片(TCON)的软体编码 (code)设定，可是在实际的实验或生产过程中，经常容易发生EEPROM中存储的TCON code读取错误的情况，造成画面异常，降低了实验和生产效率。
如图1所示为TCON与EEPROM的通信架构图，在刚上电时，TCON内部的微程序控制器(Microcontroller Unit；MCU)会通过串行双向通行(Inter－Integrated Circuit，I2C)总线是连接微控制器及其外围设备。一条串行数据线SDA，一条串行时钟线SCL；)总线去读取EEPROM里面存储的初始化配置编码(code)，完成TCON的初始化设定。PWM IC产生的EEPROM写保护信号(Write-Protection，WP)，常态下拉High为3.3V，即正常状态下要处于写保护状态，可是现在比较容易出现的问题是，由于实验和生产过程中可能的线材或其他干扰，导致WP电平低于3.3V被失效，且I2C总线通信不正常，那么就有可能会出现误动作而导致读取EEPROM里面存储的code时出错，而现今并没有纠错机制，那么就无法防范这种情况的发生。
如图1至图4所示，本申请实施例公布了一种显示面板100的时序控制芯片120的控制方法，包括步骤:
S11：脉冲调制器130产生写入保护电平并输出到存储芯片110的写入保护引脚112；
S12：侦测电路131检测写入保护引脚112的实际电平值；
S13:侦测电路131将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片120；
S14：时序控制芯片120根据比较结果，控制是否读取存储芯片110里面存储的初始化配置编码。
实际上写入保护电平，会因为干扰等情况会发生电平变化，发生电平变化的时候读取初始化配置编码(code)，错误率高而造成后续问题；而侦测电路131可以侦测该写入保护引脚112的实际电平值，若电平值出现异常，则代表读取可能发生错误，则可以告知该时序控制芯片120，不要进行读取，以避免读取错误的问题，保证画面正常显示。
在一实施例中，时序控制芯片120根据比较结果，控制是否读取存储芯片110里面存储的初始化配置编码的步骤包括：侦测电路131根据比较结果输出对应的使能信号给时序控制芯片120；时序控制芯片120根据对应的使能信号，控制是否读取存储芯片110里面存储的初始化配置编码。
我们将写入保护电平与检测的实际电平值在侦测电路131处进行比较，该时序控制芯片120完成比较的工作，而根据本身进行读取和使用的使能信号来控制是否读取，如果存在异常，该时序控制芯片120也就不会读取到错误的code，造成画面显示问题。
在一实施例中，所述时序控制芯片120根据对应的使能信号，控制是否读取存储芯片110里面存储的初始化配置编码的步骤包括：若比较结果为实际电平值不等于写入保护电平， 侦测电路131发出第一使能信号给时序控制芯片120；时序控制芯片120根据第一使能信号控制断开设置在时序控制芯片120和存储芯片110之间的串行双向通行总线140；时序控制芯片120不输出串行双向通行信号给存储芯片110。
第一使能信号指示，该code读取出现了不可预期的问题，可能是静电干扰，也可能是其他信号干扰，以及其他可能，此时，该第一使能信号告知时序控制芯片120要断开I2C总线，由于时序不输出I2C信号，故而读取存储芯片110code的动作将不会实行，该时序控制芯片120也就不会读取到错误的code，造成画面显示问题。
在一实施例中，时序控制芯片120不输出串行双向通行信号给存储芯片110的步骤之后还包括：重启电路；侦测电路131重新检测写入保护引脚112的实际电平值；若比较结果为实际电平值等于写入保护电平，侦测电路131发出第二使能信号给时序控制芯片120；时序控制芯片120根据第二使能信号控制启用设置在时序控制芯片120和存储芯片110之间的串行双向通行总线140；时序控制芯片120输出串行双向通行信号给存储芯片110，并读取存储在存储芯片110中的初始化配置编码；时序控制芯片120根据读取的初始化配置编码进行初始化配置。
第二使能信号，除了控制断开I2C总线外，还告知时序控制芯片120，需要通过重启电路或者重新上电等方式来排除静电或者外部信号干扰等问题，问题排除之后，只要WP的电平准位恢复正常，那么TCON仍然会去正确地读取code，从而正确地显示画面。
作为本申请的另一实施例，如图1至图4所示，本申请实施例公布了一种显示面板100的时序控制芯片120的控制方法，包括步骤:
S11：脉冲调制器130产生写入保护电平并输出到存储芯片110的写入保护引脚112；
S12：侦测电路131检测写入保护引脚112的实际电平值；
S13:侦测电路131将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片120；
S14：时序控制芯片120根据比较结果，控制是否读取存储芯片110里面存储的初始化配置编码。
实际上写入保护电平，会因为干扰等情况会发生电平变化，发生电平变化的时候读取初始化配置编码(code)，错误率高而造成后续问题；而侦测电路131可以侦测该写入保护引脚112的实际电平值，若电平值出现异常，则代表读取可能发生错误，则可以告知该时序控制芯片120，不要进行读取，以避免读取错误的问题，保证画面正常显示。
在一实施例中，所述时序控制芯片120根据比较结果，控制是否读取存储芯片110里面存储的初始化配置编码的步骤包括：侦测电路131根据比较结果输出对应的使能信号给时序控制芯片120；时序控制芯片120根据对应的使能信号，控制是否读取存储芯片110里面存 储的初始化配置编码。
我们将写入保护电平与检测的实际电平值在侦测电路131处进行比较，该时序控制芯片120完成比较的工作，而根据本身进行读取和使用的使能信号来控制是否读取，如果存在异常，该时序控制芯片120也就不会读取到错误的code，造成画面显示问题。
在一实施例中，所述时序控制芯片120根据对应的使能信号，控制是否读取存储芯片110里面存储的初始化配置编码的步骤包括：若比较结果为实际电平值不等于写入保护电平，侦测电路131发出第一使能信号给时序控制芯片120；时序控制芯片120根据第一使能信号控制断开设置在时序控制芯片120和存储芯片110之间的串行双向通行总线140；时序控制芯片120不输出串行双向通行信号给存储芯片110。
第一使能信号指示，该code读取出现了不可预期的问题，可能是静电干扰，也可能是其他信号干扰，以及其他可能，此时，该第一使能信号告知时序控制芯片120要断开I2C总线，由于时序不输出I2C信号，故而读取存储芯片110code的动作将不会实行，该时序控制芯片120也就不会读取到错误的code，造成画面显示问题。
在一实施例中，所述若比较结果为实际电平值不等于写入保护电平，侦测电路131发出第一使能信号给时序控制芯片120的步骤包括：
所述脉冲调制器130设置预设电平值；若比较结果中，实际电平值不等于写入保护电平值，且等于预设电平值，则侦测电路131发出第三使能信号给时序控制芯片120。
预设电平值，是通过脉冲调制IC进行控制输出，该预设电平值发生时，将指示读取code的动作出现了某种预期的问题，需要针对性进行排除之后，才能进行code读取。第三使能信号在这里是检测该code本身是否是正确，此时，该电路可能并没有静电或者干扰信号的影响，读取动作本身是正确，但是仍可能造成画面显示异常等问题。第三使能信号，除了告知时序控制芯片120不要进行读取外，还告诉它问题是code本身错误，需要为存储芯片110存入正确的code，才能保证后续画面正常显示，在存入正确的code之后，该时序控制芯片120读取到正确code。
在一实施例中，所述若比较结果中，实际电平值不等于写入保护电平值，且等于预设电平值，则侦测电路131发出第三使能信号给时序控制芯片120的步骤包括：检测器111从实际存储的初始化配置编码中读取实际检校和信息，并将实际检校和信息和预存储的标准检校和信息进行对比，若实际检校和信息跟标准检校和信息不一致，则输出初始化配置编码错误信号给脉冲调制器130；脉冲调制器130控制写入保护引脚的电平值变为预设电平值；侦测电路131检测到预设电平值，则发出第三使能信号给时序控制芯片120。
该预设电平值，代表的是code数据本身错误的问题发生了，具体的，可以在存储芯片110出增加一检测器111，该检测器111存储有正确的code对应的标准检校和信息；在进行 code读取之前，该检测器111检测该code中的实际检校和信息，并与该标准检校和信息进行比对，若比对结果不一致，则输出code错误信号给PWM IC，该IC控制写入保护引脚112的电平值变为预设电平值，该侦测电路侦测到预设电平值，输出第三使能信号；该第三使能信号除了帮助时序控制芯片120断开I2C总线外，还告知断开的原因是code数据本身错误的问题，需要更新正确的code数据之后，让该时序控制芯片120读取正常的code并正常显示。
在一实施例中，所述时序控制芯片120根据比较结果，控制是否读取存储芯片110里面存储的时序控制芯片120初始化配置编码的步骤还包括：检测器111从实际存储的初始化配置编码中读取实际检校和信息，并将实际检校和信息和预存储的标准检校和信息进行对比；根据对比结果输出初始化配置编码的正确信息或错误信息给时序控制芯片120；时序控制芯片120根据初始化配置编码的正确信息或错误信息来控制断开或者启用串行双向通行总线140；时序控制芯片120接收到初始化配置编码正确信息，则所述时序控制芯片120根据侦测电路131的比较结果，控制是否读取存储芯片110里面存储的时序控制芯片120初始化配置编码。
此处增加检测器111，检测器111从实际存储的code中读取实际检校和信息，并将实际检校和信息和预存储的标准检校和信息进行对比；若实际检校和信息跟标准检校和信息不一致，则输出code错误信号给时序控制芯片120；若若实际检校和信息跟标准检校和信息一致，则输出code正确信号给时序控制芯片120；时序控制芯片120先判断读取到的是code错误信息还是code正确信息，若时序控制芯片120接收到code错误信息，则控制断开设置在时序控制芯片120和存储芯片110之间的I2C总线；
若时序控制芯片120接收到code正确信息，则所述时序控制芯片120根据侦测电路131的比较结果，控制是否读取存储芯片110里面存储的时序控制芯片120初始化配置编码(code)，直接将code正确或错误信息发送给时序控制芯片120。
作为本申请的另一实施例，如图1至图4所示，本申请实施例公布了一种显示面板100的时序控制芯片120的控制方法，包括步骤:
脉冲调制器130产生写入保护电平并输出到存储芯片110的写入保护引脚112；侦测电路131检测写入保护引脚112的实际电平值；侦测电路131将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片120；侦测电路131根据比较结果输出对应的使能信号给时序控制芯片120；若比较结果为实际电平值不等于写入保护电平，侦测电路131发出第一使能信号给时序控制芯片120；时序控制芯片120根据第一使能信号控制断开设置在时序控制芯片120和存储芯片110之间的串行双向通行总线140；时序控制芯片120不输出串行双向通行信号给存储芯片110；重启电路；侦测电路131重新检测写入保护引脚112 的实际电平值；若比较结果为实际电平值等于写入保护电平，侦测电路131发出第二使能信号给时序控制芯片120；时序控制芯片120根据第二使能信号控制启用设置在时序控制芯片120和存储芯片110之间的串行双向通行总线140；时序控制芯片120输出串行双向通行信号给存储芯片110，并读取存储在存储芯片110中的初始化配置编码；时序控制芯片120根据读取的初始化配置编码进行初始化配置。
一般情况下写入保护电平，会因为干扰等情况会发生电平变化，发生电平变化的时候读取code错误率高，会造成后续其他影响，设置侦测电路131可以侦测该写入保护引脚112的实际电平值，侦测电路131根据比较结果输出对应的使能信号给时序控制芯片120，比较结果为实际电平值不等于写入保护电平，侦测电路131发出第一使能信号给时序控制芯片120，第一使能信号指示，该code读取出现了不可预期的问题，可能是静电干扰，也可能是其他信号干扰，以及其他可能，此时，该第一使能信号告知时序控制芯片120要断开I2C总线，由于时序不输出I2C信号，故而读取存储芯片110code的动作将不会实行，该时序控制芯片120也就不会读取到错误的code，造成画面显示问题。若比较结果为实际电平值等于写入保护电平，侦测电路131发出第二使能信号给时序控制芯片120，第二使能信号，除了控制断开I2C总线外，还告知时序控制芯片120，需要通过重启电路或者重新上电等方式来排除静电或者外部信号干扰等问题，问题排除之后，只要WP的电平准位恢复正常，那么TCON仍然会去正确地读取code，从而正确地显示画面。
作为本申请的另一实施例，参考图1至图4所示，本申请还提供了一种显示面板100，包括：存储芯片110，包括写入保护引脚112，存储时序控制芯片120初始化编码；时序控制芯片120，读取时序控制芯片120初始化编码并进行初始化配置；串行双向通行总线140，设置在所述存储芯片110和时序控制芯片120之间；脉冲调制器130，输出写入保护电平到所述写入保护引脚；侦测电路131，设置在所述脉冲调制器130内，检测写入保护引脚112的实际电平值，与写入保护电平进行比较，并根据比较结果输出对应的使能信号给所述时序控制芯片120；时序控制芯片120包括微程序控制器121，微程序控制器121接收对应的使能信号，并根据使能信号控制断开或者启用设置在存储芯片110和时序控制芯片120之间的串行双向通行总线140。
在PWM IC内部增加对WP电平的侦测电路131，通过侦测到的WP电平大小后发出一使能信号output给到TCON做出接通或断开总线的决定，从而防止了出现EEPROM读取code错误的情况发生。具体的，上电后，当WP电平侦测电路131侦测到WP(写入保护)电平维持在High 3.3V准位时，由侦测电路131发出一使能信号output1给到TCON来做出接通I2C总线的决定，即此时EEPROM一直处于写保护状态，那么无论I2C信号怎么变化，都不会出现读取code错误的情况；如果WP电平侦测电路131侦测到WP电平低于High 3.3V准位的 时候；由侦测电路131发出一使能信号output2给到TCON来做出断开I2C总线的决定，即此时EEPROM写保护失效，TCON便不输出I2C信号，也就不会发生读取code错误的情况。当重新上电后，只要WP的电平准位恢复正常，那么TCON仍然会去正确地读取code，从而正确地显示画面。
在一实施例中，存储芯片110还包括：检测器111，存储有标准检校和信息，检测器111检测存储在存储芯片110中的实际检校和信息，并根据标准检校和信息和实际检校和信息的比较结果，输出初始化配置编码正确信息或初始化配置编码错误信息；时序控制芯片120根据初始化配置编码正确信息或初始化配置编码错误信息控制断开或者启用设置在存储芯片110和时序控制芯片120之间的串行双向通行总线140。
在存储芯片110处增加一检测器111，该检测器111存储有正确的code对应的标准检校和信息；在进行code读取之前，该检测器111检测该code中的实际检校和信息，并与该标准检校和信息进行比对，若比对结果不一致，则输出code错误信号给PWM IC，该IC控制写入保护引脚112的电平值变为预设电平值，该侦测电路侦测到预设电平值，输出第三使能信号；该第三使能信号除了帮助时序控制芯片120断开I2C总线外，还告知断开的原因是code数据本身错误的问题，需要更新正确的code数据之后，让该时序控制芯片120读取正常的code并正常显示。
需要说明的是，以上所有的侦测电路，可以是普通的分压检测电路或者是电流检测电路，甚至是普通的电位仪或者电流仪都可以实现检测对应引脚的电平的功能。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本发明的保护范围。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertica Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (18)

  1. 一种显示面板的时序控制芯片的控制方法，包括步骤:
    脉冲调制器产生写入保护电平并输出到存储芯片的写入保护引脚；
    侦测电路检测写入保护引脚的实际电平值；
    侦测电路将实际电平值跟写入保护电平进行比较，并输出比较结果；
    根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码。
  2. 如权利要求1所述的一种显示面板的时序控制芯片的控制方法，其中，所述根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    时序控制芯片接收比较结果；
    时序控制芯片根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码。
  3. 如权利要求2所述的一种显示面板的时序控制芯片的控制方法,其中，所述时序控制芯片根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    侦测电路根据比较结果输出对应的使能信号给时序控制芯片；
    时序控制芯片根据对应的使能信号，控制是否读取存储芯片里面存储的初始化配置编码。
  4. 如权利要求3所述的一种显示面板的时序控制芯片的控制方法,其中，所述时序控制芯片根据对应的使能信号，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片；
    时序控制芯片根据第一使能信号控制断开设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片不输出串行双向通行信号给存储芯片。
  5. 如权利要求4所述的一种显示面板的时序控制芯片的控制方法,其中，所述时序控制芯片不输出串行双向通行信号给存储芯片的步骤之后还包括：
    重启电路，重新上电；
    侦测电路重新检测写入保护引脚的实际电平值；
    若比较结果为实际电平值等于写入保护电平，侦测电路发出第二使能信号给时序控制芯片；
    时序控制芯片根据第二使能信号控制启用设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片输出串行双向通行信号给存储芯片，并读取存储在存储芯片中的初始化配 置编码；
    时序控制芯片根据读取的初始化配置编码进行初始化配置。
  6. 如权利要求1所述的一种显示面板的时序控制芯片的控制方法,其中，所述根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    侦测电路根据比较结果输出对应的使能信号给时序控制芯片；
    时序控制芯片根据对应的使能信号，控制是否读取存储芯片里面存储的初始化配置编码；
    所述时序控制芯片根据对应的使能信号，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片；
    时序控制芯片根据第一使能信号控制断开设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片不输出串行双向通行信号给存储芯片；
    重启电路，重新上电；
    侦测电路重新检测写入保护引脚的实际电平值；
    若比较结果为实际电平值等于写入保护电平，侦测电路发出第二使能信号给时序控制芯片；
    时序控制芯片根据第二使能信号控制启用设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片输出串行双向通行信号给存储芯片，并读取存储在存储芯片中的初始化配置编码；
    时序控制芯片根据读取的初始化配置编码进行初始化配置。
  7. 如权利要求2所述的一种显示面板的时序控制芯片的控制方法,其中，所述时序控制芯片根据比较结果，控制是否读取存储芯片里面存储的初始化配置编码的步骤包括：
    若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片；
    时序控制芯片根据第一使能信号控制断开设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片不输出串行双向通行信号给存储芯片；
    重启电路，重新上电；
    侦测电路重新检测写入保护引脚的实际电平值；
    若比较结果为实际电平值等于写入保护电平，侦测电路发出第二使能信号给时序控制芯片；
    时序控制芯片根据第二使能信号控制启用设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片输出串行双向通行信号给存储芯片，并读取存储在存储芯片中的初始化配置编码；
    时序控制芯片根据读取的初始化配置编码进行初始化配置。
  8. 如权利要求4所述的一种显示面板的时序控制芯片的控制方法,其中，所述若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片的步骤包括：
    所述脉冲调制器设置预设电平值；
    若比较结果中，实际电平值不等于写入保护电平值，且等于预设电平值，则侦测电路发出第三使能信号给时序控制芯片。
  9. 如权利要求8所述的一种显示面板的时序控制芯片的控制方法,其中，所述若比较结果中，实际电平值不等于写入保护电平值，且等于预设电平值，则侦测电路发出第三使能信号给时序控制芯片的步骤包括：
    检测器从实际存储的初始化配置编码中读取实际检校和信息，并将实际检校和信息和预存储的标准检校和信息进行对比；
    根据对比结果发出第三使能信号给时序控制芯片。
  10. 如权利要求9所述的一种显示面板的时序控制芯片的控制方法,其中，所述根据对比结果发出第三使能信号给时序控制芯片的步骤还包括：
    若实际检校和信息跟标准检校和信息不一致，则输出初始化配置编码错误信号给脉冲调制器；
    脉冲调制器控制写入保护引脚的电平值变为预设电平值；
    侦测电路检测到预设电平值，则发出第三使能信号给时序控制芯片。
  11. 如权利要求1所述的一种显示面板的时序控制芯片的控制方法,其中，所述时序控制芯片根据比较结果，控制是否读取存储芯片里面存储的时序控制芯片初始化配置编码的步骤还包括：
    检测器从实际存储的初始化配置编码中读取实际检校和信息，并将实际检校和信息和预存储的标准检校和信息进行对比；
    根据对比结果输出初始化配置编码的信息给时序控制芯片；
    所述时序控制芯片根据侦测电路的比较结果，控制是否读取存储芯片里面存储的时序控 制芯片初始化配置编码。
  12. 如权利要求11所述的一种显示面板的时序控制芯片的控制方法,其中，所述根据对比结果输出初始化配置编码的信息给时序控制芯片的步骤包括：
    根据对比结果输出初始化配置编码的正确信息或错误信息给时序控制芯片；
    时序控制芯片根据初始化配置编码的正确信息或错误信息来控制断开或者启用串行双向通行总线；
    若时序控制芯片接收到初始化配置编码正确信息，则所述时序控制芯片根据侦测电路的比较结果，控制是否读取存储芯片里面存储的时序控制芯片初始化配置编码。
  13. 一种显示面板的时序控制芯片的控制方法,包括步骤:
    脉冲调制器产生写入保护电平并输出到存储芯片的写入保护引脚；
    侦测电路检测写入保护引脚的实际电平值；
    侦测电路将实际电平值跟写入保护电平进行比较，并将比较结果发送给时序控制芯片；
    侦测电路根据比较结果输出对应的使能信号给时序控制芯片；
    若比较结果为实际电平值不等于写入保护电平，侦测电路发出第一使能信号给时序控制芯片；
    时序控制芯片根据第一使能信号控制断开设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片不输出串行双向通行信号给存储芯片；
    重启电路；
    侦测电路重新检测写入保护引脚的实际电平值；
    若比较结果为实际电平值等于写入保护电平，侦测电路发出第二使能信号给时序控制芯片；
    时序控制芯片根据第二使能信号控制启用设置在时序控制芯片和存储芯片之间的串行双向通行总线；
    时序控制芯片输出串行双向通行信号给存储芯片，并读取存储在存储芯片中的初始化配置编码；
    时序控制芯片根据读取的初始化配置编码进行初始化配置。
  14. 一种显示面板，包括；
    存储芯片，包括写入保护引脚，存储时序控制芯片初始化编码；
    时序控制芯片，读取时序控制芯片初始化编码并进行初始化配置；
    串行双向通行总线，设置在所述存储芯片和时序控制芯片之间；
    脉冲调制器，输出写入保护电平到所述写入保护引脚；以及
    侦测电路，设置在所述脉冲调制器内，检测写入保护引脚的实际电平值，与写入保护电平进行比较，并根据比较结果控制断开或者启用设置在存储芯片和时序控制芯片之间的串行双向通行总线。
  15. 如权利要求14所述的一种显示面板，其中，所述侦测电路输出对应的使能信号给所述时序控制芯片，所述时序控制芯片包括微程序控制器，所述微程序控制器接收所述对应的使能信号，并根据使能信号控制断开或者启用设置在存储芯片和时序控制芯片之间的串行双向通行总线。
  16. 如权利要求15所述的一种显示面板，其中，所述存储芯片还包括：
    检测器，存储有标准检校和信息，所述检测器检测存储在存储芯片中的实际检校和信息，并根据标准检校和信息和实际检校和信息的比较结果，输出初始化配置编码的信息给时序控制芯片；输出初始化配置编码正确信息或初始化配置编码错误信息；
    时序控制芯片根据接收的初始化配置编码的信息控制断开或者启用设置在存储芯片和时序控制芯片之间的串行双向通行总线。
  17. 如权利要求16所述的一种显示面板，其中，所述检测器输出初始化配置编码正确信息或初始化配置编码错误信息给所述时序控制芯片；
    所述时序控制芯片根据初始化配置编码正确信息或初始化配置编码错误信息控制断开或者启用设置在存储芯片和时序控制芯片之间的串行双向通行总线。
  18. 如权利要求17所述的一种显示面板，其中，所述显示面板还包括电源开关，所述电源开关控制所述显示面板的接通和断开。
PCT/CN2019/073607 2018-12-27 2019-01-29 显示面板的时序控制芯片的控制方法和显示面板 Ceased WO2020133630A1 (zh)

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