WO2020132981A1 - 一种电感、集成电路以及电子设备 - Google Patents

一种电感、集成电路以及电子设备 Download PDF

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Publication number
WO2020132981A1
WO2020132981A1 PCT/CN2018/124027 CN2018124027W WO2020132981A1 WO 2020132981 A1 WO2020132981 A1 WO 2020132981A1 CN 2018124027 W CN2018124027 W CN 2018124027W WO 2020132981 A1 WO2020132981 A1 WO 2020132981A1
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Prior art keywords
inductance
inductor
coil
bending
circuit
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PCT/CN2018/124027
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English (en)
French (fr)
Inventor
刘宁
邹鹏
朱靖华
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华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/124027 priority Critical patent/WO2020132981A1/zh
Priority to CN201880098675.0A priority patent/CN112840416B/zh
Publication of WO2020132981A1 publication Critical patent/WO2020132981A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H01F17/06—Fixed inductances of the signal type  with magnetic core with core substantially closed in itself, e.g. toroid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils

Definitions

  • the present application relates to the technical field of integrated circuits, in particular to an inductor, an integrated circuit and electronic equipment.
  • VRM voltage regulator module
  • the switching frequency in the traditional boost/buck circuit is low (mostly tens to hundreds of KHz, and the highest is not more than a few MHz), which requires a large inductance (tens to hundreds of uH) to reduce Ripple of small output current.
  • the larger the inductance of the inductor the larger the volume of the inductor, which is not conducive to circuit integration, and will also make the power converter larger in size, which in turn will lead to a larger electronic device.
  • the present application provides an inductance, an integrated circuit, and an electronic device to solve the problem that the existing inductance with a larger inductance has a larger volume and is not conducive to circuit integration.
  • the present application provides an inductance, the inductance comprising a coil composed of at least two inductance lines in parallel, wherein the coil is composed of one or more continuous S-shaped sections, and is directed to any section of the coil An S-shaped portion having at least a pair of bent portions of equal size and opposite bending directions.
  • the coil included in the inductor is composed of one or more continuous S-shaped parts, that is, the coil is overall S-shaped, compared with the prior art, the space occupied by the inductor in an integrated circuit can be reduced Small, conducive to circuit integration.
  • the S-shaped portion has at least one pair of the bending portions of the same size and opposite bending directions, so that the coil includes at least two parallel inductance lines Each inductance line is equal to the inner and outer times of the bending part, so that the length of the at least two inductance lines is the same, the inductance of the at least two inductance lines is the same, when the inductance is applied to multi-phase In the interleaved boost/buck circuit, the ripple of the output current of the multiphase interleaved boost/buck circuit can be reduced.
  • the at least two inductance lines have the same length and line width.
  • a magnetic shell-like structure is provided on the outside of the coil, which can further increase the inductance and mutual inductance of each inductance line in the inductance, reduce the magnetic leakage, and thus make it compare with the prior art
  • the volume of the inductor with the same inductance is smaller, which is convenient for integration.
  • the magnetic shell-like structure may be made of a magnetic film and is not in contact with the coil.
  • the direction of the hard axis of the magnetic shell-like structure is the same as the direction of the magnetic field generated in the magnetic shell-like structure after the inductor wire in the inductor is energized.
  • the magnetic shell-like structure is provided outside the two adjacent bending portions of the coil.
  • the magnetic shell-like structure is provided outside the two adjacent bending portions of the coil.
  • the present application provides an inductance including a coil composed of at least two inductor wires in parallel; wherein the coil includes at least two length extensions, at least three width extensions, and at least two For bending parts of equal size and opposite bending directions, the bending part is used to connect the adjacent length extension and the width extension; or, the coil includes at least three width extensions, and At least one pair of bending portions of equal size and opposite bending direction, the bending portion is used to connect the adjacent width extension portions.
  • the coil since the coil includes at least two length extensions, at least three width extensions, and at least two pairs of equal-sized bending portions with opposite bending directions, the bending portions are used to connect adjacent Compared with the prior art, the length extension part and the width extension part, that is, the entire coil is S-shaped, can reduce the space occupied by the inductance in the integrated circuit, which is beneficial to circuit integration.
  • the coil includes at least two pairs of bending portions of equal size and opposite bending directions, the bending portion is used to connect the adjacent length extension and width extension so that the at least two parallel inductances
  • Each inductance line in the line is equal to the number of times inside and outside of the bent portion, so that the length of the at least two inductance lines is the same, the inductance of the at least two inductance lines is the same, when the inductance is applied
  • the output current ripple of the multiphase interleaved boost/buck circuit can be reduced.
  • the coil includes at least three width extensions, and at least a pair of bending portions of equal size and opposite bending directions, the bending portion is used to connect the adjacent width extensions, that is, the entire coil
  • the shape is S-shaped, which can reduce the space occupied by the inductor in the integrated circuit, which is beneficial to circuit integration.
  • the coil includes at least one pair of bending portions of equal size and opposite bending directions, the bending portion is used to connect the adjacent width extension portions, so that each of the at least two parallel inductance lines The number of times inside and outside the bending part is equal, so that the length of the at least two inductance lines is the same, the inductance of the at least two inductance lines is the same, when the inductance is applied to the multiphase interleaved boost/ In the buck circuit, it can reduce the ripple of the output current of the multiphase interleaved boost/buck circuit.
  • the at least two inductance lines have the same length and line width.
  • a magnetic shell-like structure is provided on the outside of the coil, which can further increase the inductance and mutual inductance of each inductance line in the inductance, reduce the magnetic leakage, and thus make it compare with the prior art
  • the volume of the inductor with the same inductance is smaller, which is convenient for integration.
  • the magnetic shell-like structure may be made of a magnetic film and is not in contact with the coil.
  • the direction of the hard axis of the magnetic shell-like structure is the same as the direction of the magnetic field generated in the magnetic shell-like structure after the inductor wire in the inductor is energized.
  • the magnetic shell-like structure is provided outside the at least two length extensions.
  • the magnetic shell-like structure is provided outside the at least three width extensions.
  • the present application provides an integrated circuit that is a multiphase interleaved boost circuit or a multiphase interleaved buck circuit.
  • the multiphase interleaved boost circuit or multiphase interleaved buck circuit includes one or A plurality of inductances described in any one of the possible implementations of the first aspect or any one of the possible implementations in the second aspect.
  • the inductance used in the integrated circuit is S-shaped, the space occupied in the integrated circuit is small, which is convenient for integration.
  • the inductances of the inductance lines in the inductance are the same, the ripple of the output current of the integrated circuit is small, which can further improve the power supply reliability of the integrated circuit.
  • the present application provides an electronic device, including the integrated circuit and the processor described in any one of the possible implementation manners of the third aspect; the processor is used to control the integrated circuit The state of the switch tube.
  • the inductance used in the integrated circuit in the electronic device is S-shaped, the space occupied in the integrated circuit is convenient for integration and is beneficial to the miniaturization of the electronic device.
  • the inductances of the inductance lines in the inductance are the same, the ripple of the output current of the integrated circuit is small, which can further improve the power supply reliability of the integrated circuit.
  • FIG. 1 is a schematic structural diagram of a linear magnetic film inductor in the prior art
  • FIG. 2 is a schematic structural view of a U-shaped magnetic film inductor in the prior art
  • FIG. 3 is a schematic structural view of a U-shaped magnetic film inductor with a jump structure in the prior art
  • FIG. 4 is a schematic structural diagram of an inductor provided by an embodiment of the present application.
  • 5a is a schematic diagram of the distribution of a magnetic shell-like structure of an inductor provided by an embodiment of the present application.
  • 5b is a schematic diagram of distribution of another inductance magnetic shell-like structure provided by an embodiment of the present application.
  • 6a is a schematic diagram of an inductance line in an inductance provided by an embodiment of the present application.
  • 6b is a second schematic diagram of an inductance line in an inductance provided by an embodiment of the present application.
  • FIG. 7a is a schematic diagram of an inductance line in an inductor provided by an embodiment of the present application.
  • 7b is a second schematic diagram of an inductance line in an inductor provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a dual-phase interleaved buck circuit provided by an embodiment of the present application.
  • 11a is one of schematic diagrams of output currents of middle inductors of a two-phase interleaved buck circuit provided by an embodiment of the present application;
  • FIG. 11b is a second schematic diagram of the output current of the middle inductor in a two-phase interleaved buck circuit provided by an embodiment of the present application;
  • 11c is the third schematic diagram of the output current of the middle inductance of a two-phase interleaved buck circuit provided by an embodiment of the present application.
  • Inductors integrated in traditional integrated circuits are usually quadrilateral, octagonal, and other planar spiral structures. Since these inductors are air inductors (that is, the medium surrounding the inductor is air or other non-magnetic media), the inductance and energy density are small , Not suitable for application to power converters. In recent years, with the development of semiconductor technology and ferromagnetic materials, a magnetic film inductor has emerged.
  • the shape of the early magnetic film inductance was linear, as shown in Figure 1.
  • the inductance of the inductance wire and the coupling coefficient of the coupling inductance could be effectively improved, for example, a copper wire of about 1.5mm length
  • the inductance is only 1.5nH before the magnetic film is wrapped.
  • the inductance can be increased to more than 8nH, and the mutual inductance of this coupled inductance is higher, which can reach more than 0.8.
  • the magnetic film coupling inductance is applied to the reverse-coupled interleaved DC-DC buck circuit.
  • the magnetic film inductor is designed in a U shape to reduce the space occupied by the magnetic film inductor, as shown in FIG. 2.
  • the lengths of the inner loop inductance line and the outer loop inductance line are different, resulting in different inductances of the two inductance lines, as shown in FIG. 3. Since the inductances of the two inductance lines in the U-shaped magnetic film inductor are different, applying the magnetic film coupled inductance to the voltage conversion circuit in a staggered parallel connection will increase the current ripple at the output end, resulting in a reduction in the conversion efficiency of the voltage conversion circuit.
  • a jumper scheme can be used for the outer loop inductance line of the U-shaped magnetic film inductor ,As shown in Figure 3. Since the jumper wire needs to add a metal layer under the inductor wire, the jumper wire design structure is complicated, the process is difficult, and the thickness of the metal layer is small, the DC resistance is large, and the power consumption of the magnetic film inductor is increased. Moreover, the jumper structure cannot guarantee that the inductance of each inductance line in the U-shaped magnetic film inductor is the same.
  • the present application provides an inductor, an integrated circuit and an electronic device.
  • the present application provides an inductance 400 including a coil composed of at least two inductance lines 401 in parallel, that is, the at least two inductance lines 401 extend in the same direction
  • the intervals are distributed on the same plane, and the magnetic fluxes generated by any two adjacent inductance lines in the two inductance lines 401 are interlinked, that is to say, the at least two inductance lines 401 have magnetic coupling Or have mutual induction.
  • the coil is composed of one or more consecutive S-shaped parts, and for any S-shaped part of the coil, the S-shaped part has at least one pair of the same bending portions with the same bending direction, The number of times that the at least two inductance wires 401 are inside and outside the bent portion of the coil is equal.
  • the size of the bent portion in the S-shaped portion of the coil may be the same or different.
  • the coil includes at least two length extensions (the portion between the two adjacent bending portions in the length direction of the coil) and at least three width extensions (in the width of the coil Direction, the part to which the bending part is connected) and at least two pairs of equal-sized bending parts with opposite bending directions, the bending part is used to connect the adjacent length extension and the width extension Part, so that the at least two inductance wires 401 are located inside and outside the bending part of the coil an equal number of times.
  • the coil includes at least three width extensions, and at least a pair of bending portions of equal size and opposite bending directions, the bending portion is used to connect the adjacent width extensions, so that the at least The two inductance wires 401 are located inside and outside the bent portion of the coil the same number of times.
  • the coil included in the inductor 400 is composed of one or more continuous S-shaped parts, that is, the coil is S-shaped as a whole, compared with the prior art, the space occupied by the inductor 400 in an integrated circuit can be reduced.
  • the S-shaped portion has at least one pair of the same-sized bending portions with opposite bending directions, so that the at least two inductance wires 401 are located in the coil
  • the number of times of the inside and outside of the bending part is equal, so that the length of the at least two inductance lines 401 is the same, and the inductance of the at least two inductance lines 401 is the same. Therefore, when the inductance 400 is applied to the multiphase interleaving In the voltage/buck circuit, it can reduce the ripple of the output current of the multiphase interleaved boost/buck circuit.
  • a magnetic shell-like structure 402 may also be provided outside the coil, the magnetic shell-like structure 402 can increase the inductance and mutual inductance of the at least two inductance lines 401, and can The magnetic leakage of the at least two inductance lines 401 is reduced, so that compared with the prior art, the volume of the inductance 400 with the same inductance is smaller, which is convenient for integration.
  • the magnetic shell-like structure 402 may be made of a magnetic film and not in contact with the coil, for example, an insulating material may be filled between the magnetic shell-like structure 402 and the coil to avoid the The coil is in contact with the magnetic shell structure 402 and affects the inductance 400.
  • the at least two inductance lines 401 are usually made of wires with the same length and line width.
  • the initial permeability of the magnetic material is higher in the direction of the easy axis of the magnetic material (easy axis), but the price ratio is easily saturated, and at high frequencies (more than 10MHz), the permeability decreases seriously; in the direction of the difficult axis
  • the initial permeability of the magnetic material is slightly lower, but it is not easy to saturate, and the magnetic permeability is stable at high frequencies (10MHz to 1GHz). Therefore, when the inductor 400 is applied in a high-frequency scene, the magnetic shell The direction of the difficult axis of the structure 402 is the same as the direction of the magnetic field generated in the magnetic shell structure 402 after the two inductor wires 401 are energized. As shown in FIG. 5a or FIG. 5b, the inductance 400 in the thickness direction (Ie aa' direction) cross-sectional view.
  • the magnetic shell-like structure 402 may be disposed in the length direction of the coil, outside the portion of the coil between two adjacent bending portions, that is, outside the at least two length extensions
  • the magnetic shell-like structure is provided, as shown in FIG. 6a; or, in the width direction of the coil, the outside of the portion between the two adjacent bending portions of the coil, that is, the at least three
  • the magnetic shell-like structure is provided on the outside of the width extension, as shown in FIG. 6b.
  • a plurality of the magnetic shells may be provided outside the portion between the two adjacent bending portions of the coil Structure 402.
  • any reciprocally folded S-shaped coil that can ensure that the inductance of the at least two inductance wires is the same is applicable to the present application.
  • the coil may have one or more continuous S-shaped structures.
  • the coil shown in FIG. 7a includes two sections of S-shaped sub-coils, and the curvatures of the bent portions of the two sections of S-shaped sub-coils are different.
  • the present application also does not limit the specific shape of the bent portion in the coil.
  • the bent portion may be an arc transition (for example, FIG. 7a) or a right-angle transition (for example, FIG. 7b).
  • the present application does not limit the specific shape of the magnetic shell structure 402. Any magnetic shell-like structure 402 that can wrap the coil and is not in contact with the coil is applicable to this application.
  • the chip integrated with the inductor 400 may be a system on chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a power management chip, etc.
  • SoC system on chip
  • CPU central processing unit
  • GPU graphics processing unit
  • FIG. 8 the structure of the chip is shown in FIG. 8, the chip includes a silicon substrate, a semiconductor integrated circuit layer, a metal interconnection layer, a circuit and inductance interconnection layer, an inductance layer, and a package trace layer (such as Wafer level package (wafer level package, WLP)) and chip package pins.
  • the semiconductor integrated circuit layer is used to integrate complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS), SiGe semiconductor, GaN semiconductor and other semiconductor devices (such as field effect transistors, bipolar transistors, etc.).
  • the metal interconnection layer is used to realize interconnection between the semiconductor devices in the semiconductor integrated circuit layer.
  • the circuit and the inductor interconnection layer are used to realize the interconnection between the inductor 400 in the inductor layer and each semiconductor device in the semiconductor integrated circuit layer, for example, by routing, via, solder pillar , Copper pillars, micro bumps, solder bumps, etc., realize the interconnection between the inductor 400 in the inductor layer and each semiconductor device in the semiconductor integrated circuit layer.
  • the inductance layer is used to integrate the inductance 400.
  • the inductance 400 in the inductance layer is located on a corresponding substrate, wherein the inductance 400 may face the inductance and inductance interconnection layer, or may face The package trace layer.
  • the chip integrated with the inductor 400 can be applied to a specific device, such as a mobile phone, a computer, a notebook computer, or a tablet computer.
  • the device includes a processor and a power management chip ( power management (IC (integrated) circuit) and memory (memory), wherein the inductor 400 may be integrated in the processor and the power management chip.
  • the device may also include a camera module (Camera and Imaging processing module), a radio frequency module (RF (radio frequency module), external storage (mass storage), input/output (input/output, I/O) interface and One or more of human-interactive devices.
  • the processor may be a CPU, GPU, neural network processor (NPU) or a combination thereof; the external storage may be a hard disk, a floppy disk, or an optical disk.
  • the present application also provides an integrated circuit, the integrated circuit is a multi-phase interleaved boost circuit or a multi-phase interleaved buck circuit, the multi-phase interleaved boost circuit or the multi-phase interleaved buck circuit includes One or more inductors 400 described in any one of the possible embodiments above. Wherein, one inductance line in the inductance corresponds to one phase in the multi-phase interleaved boost circuit or the multi-phase buck circuit.
  • the integrated circuit is a two-phase interleaved boost circuit or a two-phase interleaved buck circuit.
  • the two-phase interleaved boost circuit or two-phase interleaved buck circuit One inductance 400 is included in the circuit, and two inductance lines included in the inductance 400 are respectively connected to each phase circuit in the two-phase interleaved boost circuit or two-phase interleaved buck circuit, or, if the The inductor 400 includes two inductor lines, and the integrated circuit is a four-phase interleaved boost circuit or a four-phase interleaved buck circuit.
  • the four-phase interleaved boost circuit or the four-phase interleaved buck circuit includes two In the inductor 400, the four inductor lines included in the two inductors 400 are respectively connected to each phase circuit in the four-phase interleaved boost circuit or the four-phase interleaved buck circuit.
  • the inductance includes more than two inductance lines and the number of phases of the multi-phase interleaved boost circuit or multi-phase interleaved buck circuit is greater than two phases, it is similar to the case where the above-mentioned inductance includes two inductance lines, and is no longer described here Repeat.
  • the phase-interleaved buck circuit may be an H-bridge multi-phase interleaved boost circuit or a multi-phase interleaved buck circuit.
  • the inductor 400 used in the integrated circuit is S-shaped, the space occupied in the integrated circuit is small, which is convenient for integration.
  • the inductances of the inductance lines included in the inductance 400 are the same, the ripple of the output current of the integrated circuit is small, which can improve the power supply reliability of the integrated circuit.
  • the inductor 400 used in the two-phase interleaved parallel buck circuit includes two S-shaped inductor wires as an example. The beneficial effects of integrated circuits will be described in detail.
  • the two-phase interleaved parallel buck circuit includes the inductor 400, a first diode D1, a second diode D2, a first switching transistor Q1, a second switching transistor Q2, a capacitor C1 and Resistor R1, wherein the first end of the first switch Q1 is connected to one end of the power supply S, the second end of the first switch Q1 is connected to the first end of the inductor line L1 in the inductor 400, and The cathode of the first diode D1 is connected, the anode of the first diode D1 is connected to the other end of the power source S and the first end of the capacitor C1, respectively, and the inductance line L1 in the inductor 400 Is connected to the second end of the capacitor C1, the first end of the second switch Q2 is connected to one end of the power supply S, and the second end of the second switch Q2 is connected to the inductor 400 respectively
  • the first end of the inductance line L2 in is connected to the cathode
  • the third terminal of the first switch tube Q1 and the third terminal of the second switch tube Q2 are respectively used to receive corresponding control signals (first pulse P1 and second pulse P2).
  • first pulse P1 and second pulse P2 are respectively used to receive corresponding control signals (first pulse P1 and second pulse P2).
  • the inductor line L1 and the inductor line L2 in the inductor 400 are reversely coupled.
  • the switch included in the integrated circuit in this application may be a bipolar junction transistor (BJT), a metal-oxide semiconductor field effect transistor (metal-oxide-semiconductor field-effect transistor) , MOSFET) or insulated gate bipolar transistor (IGBT) and other switches
  • BJT bipolar junction transistor
  • MOSFET metal-oxide semiconductor field effect transistor
  • IGBT insulated gate bipolar transistor
  • the multiple switch tubes included in the integrated circuit may be switches of the same type or different types of switches.
  • the second pulse P2 signal has a pulse width of 4.9ns and a period of 10ns
  • the second pulse signal is delayed by 6 ns compared to the first pulse signal, that is, the first pulse P1 and the second pulse P2
  • the phase difference is 180°
  • the inductance of the inductance line L1 in the inductor 400 is 8.04nH
  • the effective resistance is 0.05 ⁇
  • the inductance of the inductance line L2 in the inductor 400 is 8.243nH
  • the parasitic resistance is 0.05 ⁇
  • the capacitance When the capacitance value of C1 is 150nF and the resistance value of the resistor R1 is 0.5 ⁇ , the output current of the inductor 400 is as shown in FIG.
  • FIG. 11a Under the same conditions, when the inductor 400 uses an existing U-shaped magnetic film When the inductance is replaced, the output current of the U-shaped magnetic film inductor is shown in FIG. 11b. When the inductor 400 is replaced with the existing U-shaped magnetic film inductor with a jumper structure, the output current of the U-shaped magnetic film inductor is as shown in FIG. 11c.
  • 11b of the shaped magnetic film inductor output, the current ripple is larger;
  • the inductor 400 provided by the present application can effectively reduce the ripple of the output current of the multiphase interleaved boost/buck circuit.
  • the present application also provides an electronic device, the electronic device includes the integrated circuit and the controller according to any one of the above possible implementation manners, and the controller is used to control a switch in the integrated circuit The status of the tube.
  • the inductance line in the inductor 400 used in the integrated circuit in the electronic device is S-shaped, the space occupied in the integrated circuit is small, which is convenient for integration, and is also conducive to miniaturization of the electronic device.
  • the inductances of the inductance lines in the inductor 400 are the same, the ripple of the output current of the integrated circuit is small, which can improve the power supply reliability of the integrated circuit.

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Abstract

一种电感、集成电路以及电子设备，用以解决现有电感量较大的电感体积较大，不利于电路集成的问题。所述电感包括由至少两个电感线并行组成的线圈；其中，所述线圈包括包括至少两个长度延展部、至少至少三个三段平行的宽度延展部，以及至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部；或者，所述线圈包括至少三个宽度延展部，以及至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部。

Description

一种电感、集成电路以及电子设备 技术领域
本申请涉及集成电路技术领域，尤其涉及一种电感、集成电路以及电子设备。
背景技术
手机、平板电脑以及服务器等电子设备中的各元器件工作时需要的电压不完全相同，因此，电子设备通常通过电源变换器，将获得的电能转换为电子设备中的元器件工作时需要的电压，为对应的元器件供电，例如，为电子设备中的中央处理器(central processing unit，CPU)提供稳定电压的电压调节模块(voltage regulator module，VRM)就是一种典型的电源变换器。
目前，电源变换器大多数是通过多相交错并联升压(boost)/降压(buck)电路实现。但是，传统的升压/降压电路中开关频率较低(多为几十到几百KHz，最高也不过几MHz)，需要电感量较大的电感(几十到几百uH)，以减小输出电流的纹波。由于电感的电感量越大，电感的体积也越大，不利于电路集成，并且会使得电源变换器的体积也较大，进而导致电子设备的体积较大。
发明内容
本申请提供一种电感、集成电路以及电子设备，用以解决现有电感量较大的电感体积较大，不利于电路集成的问题。
第一方面，本申请提供了一种电感，所述电感包括由至少两个电感线并行组成的线圈，其中，所述线圈由连续的一段或多段S形部分组成，针对所述线圈的任意一段S形部分，该S形部分具有至少一对大小相等、折弯方向相反的折弯部。
通过上述方案，由于所述电感包括的线圈由连续的一段或多段S形部分组成，即所述线圈整体呈S形，相较于现有技术能够减少所述电感在集成电路中所占的空间小，有利于电路集成。并且，针对所述线圈中的任意一段S形部分，该S形部分具有至少一对大小相同，折弯方向相反的所述折弯部，使得所述线圈包括的至少两个并行的电感线中每个电感线处于所述折弯部内侧以及外侧的次数相等，进而使得所述至少两个电感线的长度相同，所述至少两个电感线的电感量相同，当所述电感应用于多相交错升压/降压电路中时，能够减少多相交错升压/降压电路输出电流的纹波。
一种可能的实施方式中，所述至少两个电感线的长度以及线宽相同。
一种可能的实施方式中，所述线圈的外部设置有磁性壳状结构，能够进一步提高所述电感中每个电感线的电感量以及互感系数，减少漏磁，进而使得相较于现有技术，相同电感量的所述电感的体积更小，便于集成。
一种可能的实施方式中，所述磁性壳状结构可以由磁膜制成，且与所述线圈不接触。
一种可能的实施方式中，所述磁性壳状结构的难轴方向与所述电感中电感线通电后在所述磁性壳状结构中产生的磁场方向相同。
一种可能的实施方式中，在所述线圈的长度方向上，所述线圈的相邻两个折弯部之间的外部设置有所述磁性壳状结构。
一种可能的实施方式中，在所述线圈的宽度方向上，所述线圈的相邻两个折弯部之间的外部设置有所述磁性壳状结构。
第二方面，本申请提供了一种电感，所述电感包括由至少两个电感线并行组成的线圈；其中，所述线圈包括至少两个长度延展部、至少三个宽度延展部、以及至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部；或者，所述线圈包括至少三个宽度延展部，以及至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部。
通过上述方案，由于所述线圈包括至少两个长度延展部、至少三个宽度延展部、以及至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部，即所述线圈整体呈S形，相较于现有技术能够减少所述电感在集成电路中所占的空间小，有利于电路集成。所述线圈包括至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部，使得所述至少两个并行电感线中每个电感线处于所述折弯部内侧以及外侧的次数相等，进而使得所述至少两个电感线的长度相同，所述至少两个电感线的电感量相同，当所述电感应用于多相交错升压/降压电路中时，能够减少多相交错升压/降压电路输出电流的纹波。
由于所述线圈包括至少三个宽度延展部、以及至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部，即所述线圈整体呈S形，相较于现有技术能够减少所述电感在集成电路中所占的空间小，有利于电路集成。所述线圈包括至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部，使得所述至少两个并行电感线中每个电感线处于所述折弯部内侧以及外侧的次数相等，进而使得所述至少两个电感线的长度相同，所述至少两个电感线的电感量相同，当所述电感应用于多相交错升压/降压电路中时，能够减少多相交错升压/降压电路输出电流的纹波。
一种可能的实施方式中，所述至少两个电感线的长度以及线宽相同。
一种可能的实施方式中，所述线圈的外部设置有磁性壳状结构，能够进一步提高所述电感中每个电感线的电感量以及互感系数，减少漏磁，进而使得相较于现有技术，相同电感量的所述电感的体积更小，便于集成。
一种可能的实施方式中，所述磁性壳状结构可以由磁膜制成，且与所述线圈不接触。
一种可能的实施方式中，所述磁性壳状结构的难轴方向与所述电感中电感线通电后在所述磁性壳状结构中产生的磁场方向相同。
一种可能的实施方式中，所述至少两个长度延展部的外部设置有所述磁性壳状结构。
一种可能的实施方式中，所述至少三个宽度延展部的外部设置有所述磁性壳状结构。
第三方面，本申请提供了一种集成电路，所述集成电路为多相交错升压电路或多相交错降压电路，所述多相交错升压电路或多相交错降压电路包括一个或多个上述第一方面的任意一种可能的实施方式中所述的电感或上述第二方面的任意一种可能的实施方式中所述的电感。
通过上述方案，由于所述集成电路中采用的电感为S形，在集成电路中所占的空间小，便于集成。另外，由于所述电感中电感线的电感量相同，使得所述集成电路输出电流的纹波较小，进而能够提高所述集成电路的供电可靠性。
第四方面，本申请提供了一种电子设备，包括上述第三方面的任意一种可能的实施方式中所述的集成电路以及处理器；所述处理器，用于控制所述集成电路中的开关管的状态。
通过上述方案，由于所述电子设备中的集成电路中采用的电感为S形，在集成电路中所占的空间，便于集成，有利于所述电子设备的小型化。另外，由于所述电感中电感线的电感量相同，使得所述集成电路输出电流的纹波较小，进而能够提高所述集成电路的供电可靠性。
附图说明
图1为现有技术中直线形磁膜电感的结构示意图；
图2为现有技术中U形磁膜电感的结构示意图；
图3为现有技术中具有跳结构的U形磁膜电感的结构示意图；
图4为本申请实施例提供的一种电感的结构示意图；
图5a为本申请实施例提供的一种电感的磁性壳状结构的分布示意图；
图5b为本申请实施例提供的另一种电感的磁性壳状结构的分布示意图；
图6a为本申请实施例提供的一种电感中电感线的示意图之一；
图6b为本申请实施例提供的一种电感中电感线的示意图第二；
图7a为本申请实施例提供的一种电感中电感线的示意图之一；
图7b为本申请实施例提供的一种电感中电感线的示意图第二；
图8为本申请实施例提供的一种芯片的结构示意图；
图9为本申请实施例提供的一种设备的结构示意图；
图10为本申请实施例提供的一种双相交错降压电路的结构示意图；
图11a为本申请实施例提供的一种双相交错降压电路的中电感输出电流示意图之一；
图11b为本申请实施例提供的一种双相交错降压电路的中电感输出电流示意图之二；
图11c为本申请实施例提供的一种双相交错降压电路的中电感输出电流示意图之三。
具体实施方式
传统集成电路中集成的电感通常为四边形、八边形等平面螺旋结构，由于这些电感都是空气电感(即电感周围包围的介质为空气或者为其它没有磁性的介质)，电感量以及能量密度小，不适合应用到电源变换器中。近年来，随着半导体工艺和铁磁材料的研究进展，出现了一种磁膜电感。
早期的磁膜电感的形状为直线形，如图1所示，在电感线周围包裹磁膜后，可以有效提高电感线的电感量以及耦合电感的耦合系数，例如，大概1.5mm长度的铜线电感量未包裹磁膜之前电感量只有1.5nH，当在铜线周围包裹磁膜以后，其电感量可以提高到8nH以上，并且这种耦合电感的互感系数较高，可以达到0.8以上，如果将该磁膜耦合电感应用到反向耦合交错并联的DC-DC降压电路中，单相DC-DC降压电路的稳态等效电感量可以达到8×(1+0.8)＝14.4nH，随着电感量的增大，可以进一步降低输出电流的纹波。但是，由于上述直线形磁膜电感中每个直线形电感线的驱动电路布局相距较远，占用大量空间，进而增加了集成电路的尺寸和成本，设计不灵活。
为了克服直线形磁膜电感的上述缺点，将磁膜电感设计为U字形，以减小磁膜电感占用的空间，如图2所示。但是，U形磁膜电感中内圈电感线与外圈电感线的长度不同，导致两个电感线的电感量不同，如图3所示。由于U形磁膜电感中两个电感线的电感量不同， 将该磁膜耦合电感应用到交错并联的电压转换电路中，会增加输出端的电流纹波，导致电压转换电路的转换效率降低。
为了减小U形磁膜电感中外圈电感线的长度，进而减小U形磁膜电感中两个电感线电感量的差异，可以在U形磁膜电感的外圈电感线采用跳线的方案，如图3所示。由于跳线需要在电感线下层增加金属层，导致跳线设计结构复杂，工艺难度大，且金属层厚度较小，直流电阻较大，增加磁膜电感的功耗。并且，跳线结构也无法保证U形磁膜电感中每个电感线的电感量相同。
为了克服集成电路中电感存在的上述缺陷，本申请提供了一种电感、集成电路以及电子设备。
另外，需要理解的是，在本申请的描述中，“多个”指两个或两个以上；“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
如图4所示，本申请提供了一种电感400，所述电感400包括由至少两个电感线401并行组成的线圈，即所述至少两个电感线401的延伸方向相同，且以一定的间隔分布在同一平面上，所述两个电感线401中任意两个相邻电感线所产生的磁通相互交链，也就是说，所述至少两个电感线401具有磁耦合(magnetic coupling)或者具有互感(mutual induction)。
其中，所述线圈由连续的一段或多段S形部分组成，针对所述线圈中的任意一段S形部分，该S形部分具有至少一对大小相同，折弯方向相反的所述折弯部，使得所述至少两个电感线401处于所述线圈的折弯部内侧以及外侧的次数相等。所述线圈中不同段S形部分具有的所述折弯部的大小可以相同，也可以不同。
此时，所述线圈包括至少两个长度延展部(所述线圈的长度方向上，相邻两个所述折弯部之间的部分)、至少三个宽度延展部(在所述线圈的宽度方向上，所述折弯部所连接的部分)以及至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部，使得所述至少两个电感线401处于所述线圈的折弯部内侧以及外侧的次数相等。或者，所述线圈包括至少三个宽度延展部，以及至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部，使得所述至少两个电感线401处于所述线圈的折弯部内侧以及外侧的次数相等。
由于所述电感400包括的线圈由连续的一段或多段S形部分组成，即所述线圈整体呈S形，相较于现有技术能够减少所述电感400在集成电路中所占的空间。并且，针对所述线圈中的任意一段S形部分，该S形部分具有至少一对大小相同，折弯方向相反的所述折弯部，使得所述至少两个电感线401处于所述线圈的折弯部内侧以及外侧的次数相等，进而使得所述至少两个电感线401的长度相同，所述至少两个电感线401的电感量相同，因此，当所述电感400应用于多相交错升压/降压电路中时，能够减少多相交错升压/降压电路输出电流的纹波。
进一步地，如图4所示，所述线圈的外部还可以设置有磁性壳状结构402，所述磁性壳状结构402能够增加所述至少两个电感线401的电感量以及互感系数，并且能够减少所述至少两个电感线401的漏磁，进而使得相较于现有技术，相同电感量的所述电感400的体积更小，便于集成。
具体实施中，所述磁性壳状结构402可以由磁膜制成，且与所述线圈不接触，例如，所述磁性壳状结构402与所述线圈之间可以填充绝缘材料，以避免所述所述线圈与所述所述磁性壳状结构402接触，对所述电感400造成影响。为了进一步保证所述至少两个电感线401的电感量相同，所述至少两个电感线401通常采用长度以及线宽相同的导线制成。
由于在磁性材料的易磁化轴(易轴)方向上，磁性材料的初始磁导率较高，但是比价容易饱和，而且在高频时(大于10MHz时)磁导率下降严重；在难轴方向上，磁性材料的初始磁导率稍低，但不容易饱和，而且高频时(10MHz～1GHz)磁导率稳定，因此，当所述电感400应用在高频场景下时，所述磁性壳状结构402的难轴方向与所述两个电感线401通电后在所述磁性壳状结构402中产生的磁场方向相同，如图5a或图5b中所示的所述电感400在厚度方向上(即aa’方向)的剖面图。
进一步地，所述磁性壳状结构402可以设置在所述线圈的长度方向上，所述线圈的相邻两个折弯部之间的部分的外部，即所述至少两个长度延展部的外部设置有所述磁性壳状结构，如图6a所示；或者，在所述线圈的宽度方向上，所述线圈的相邻两个折弯部之间的部分的外部，即所述至少三个宽度延展部的外部设置有所述磁性壳状结构，如图6b所示。其中，当所述线圈的相邻两个折弯部之间的距离较大时，也可以在所述线圈的相邻两个折弯部之间的部分的外部设置多个所述磁性壳状结构402。
需要说明的是，本申请并不对所述线圈的具体形状进行限定。其中，凡是能够保证所述至少两个电感线的电感量相同的往复折叠的S形线圈均适用于本申请。所述线圈可以具有一个或多个连续的S形结构。例如，如图7a所示的线圈中包括了两段S形的子线圈，这两段S形的子线圈的弯折部分的弧度不同。本申请也不对所述线圈中折弯部的具体形状进行限定，所述折弯部可以是圆弧过渡(例如图7a)，也可以是直角过渡(例如图7b)。
另外，本申请也不对所述磁性壳状结构402的具体形状进行限定。凡是能够包裹所述线圈，且不与所述线圈接触的任意形状磁性壳状结构402均适用于本申请。
具体实施中，集成有所述电感400的芯片可以是片上系统(system on chip，SoC)、中央处理器(central processing unit，CPU)、图形处理器(graphics processing unit，GPU)、电源管理芯片等芯片，所述芯片的结构如图8所示，所述芯片从下到上依次包括硅衬底、半导体集成电路层、金属互联层、电路与电感互联层、电感层、封装走线层(例如圆片级封装(wafer level package，WLP))以及芯片封装管脚。其中，所述半导体集成电路层用于集成互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)、SiGe半导体、GaN半导体等半导体器件(如场效应管、双极型晶体管等)。所述金属互联层用于实现所述半导体集成电路层中各半导体器件之间的互连。所述电路与电感互联层用于实现电感层中的电感400与半导体集成电路层中各半导体器件之间的互连，例如通过布线(routing)、通孔(via)、焊锡柱(solder pillar)、铜柱(copper pillar)、微凸点(micro bump)或焊锡凸块(solder bump)等实现电感层中的电感400与半导体集成电路层中各半导体器件之间的互连。所述电感层用于集成所述电感400，通常情况下，所述电感层中所述电感400位于相应的基板上，其中，所述电感400可以朝向所述电感与电感互联层，也可以朝向所述封装走线层。
进一步地，集成有所述电感400的芯片可以应用到具体的设备中，如手机、计算机、笔记本电脑或平板电脑，如图9所示，所述设备包括处理器(processor)、电源管理芯片(power management IC(integrated circuit))以及内存(memory)，其中，所述电感400可 以集成在所述处理器以及所述电源管理芯片中。进一步地，所述设备还可以摄像模块(Camera and Imaging processing module)、射频模块(RF(radio frequency)module)、外存(mass storage)、输入/输出(input/output，I/O)接口以及人机交互装置(human interactive device)中的一种或多种。其中，所述处理器可以是CPU、GPU、神经网络处理器(neural network processing unit，NPU)或其结合；所述外存可以是硬盘、软盘或光盘等。
基于以上实施例，本申请还提供了一种集成电路，所述集成电路为多相交错升压电路或多相交错降压电路，所述多相交错升压电路或多相交错降压电路包括一个或多个上述任意一中可能的实施方式中所述的电感400。其中，所述电感中的一个电感线对应所述多相交错升压电路或所述多相降压电路中的一相。
例如，若所述电感400中包括两个电感线，所述集成电路为两相交错升压电路或两相交错降压电路，此时，所述两相交错升压电路或两相交错降压电路中包括一个所述电感400，所述电感400中包括的两个电感线分别连接到所述两相交错升压电路或两相交错降压电路中的每相电路中，或者，若所述电感400中包括两个电感线，所述集成电路为四相交错升压电路或四相交错降压电路，此时，所述四相交错升压电路或四相交错降压电路中包括两个所述电感400，这两个电感400中包括的四个电感线分别连接到所述四相交错升压电路或四相交错降压电路中的每相电路中。当所述电感包括两个以上电感线以及所述多相交错升压电路或多相交错降压电路的相数大于两相时，与上述电感包括两个电感线的情形类似，此处不再赘述。
需要说明的是，本申请并不对对所述多相交错升压电路或多相交错降压电路中的电感、开关管等器件的具体连接方式进行限定，所述多相交错升压电路或多相交错降压电路可以是H桥多相交错升压电路或多相交错降压电路等。
通过上述方案，由于所述集成电路中采用的电感400为S形，在集成电路中所占的空间小，便于集成。另外，由于所述电感400中包括的电感线的电感量相同，使得所述集成电路输出电流的纹波较小，进而能够提高所述集成电路的供电可靠性。
下面以所述集成电路为如图7所示的两相交错并联降压电路，所述两相交错并联降压电路中采用的所述电感400包括两个S形电感线为例，对所述集成电路带来的有益效果进行详细说明。
如图10所示，所述两相交错并联降压电路包括所述电感400、第一二极管D1，第二二极管D2、第一开关管Q1、第二开关管Q2、电容C1以及电阻R1，其中，所述第一开关管Q1的第一端与电源S的一端连接，所述第一开关管Q1的第二端分别与所述电感400中的电感线L1的第一端以及所述第一二极管D1负极连接，所述第一二极管D1的正极分别与所述电源S的另一端以及所述电容C1的第一端连接，所述电感400中的电感线L1的第二端与所述电容C1的第二端连接，所述第二开关管Q2的第一端与电源S的一端连接，所述第二开关管Q2的第二端分别与所述电感400中的电感线L2的第一端以及所述第二二极管D2负极连接，所述第二二极管D2的正极分别与所述电源S的另一端以及所述电容C1的第一端连接，所述电感400中的电感线L2的第二端与所述电容C1的第二端连接，所述电阻R1与所述电容C1并联。其中，所述第一开关管Q1的第三端以及所述第二开关管Q2的第三端分别用于接收对应的控制信号(第一脉冲P1以及第二脉冲P2)，所述控制信号用于控制对应的开关管的状态(导通状态或关断状态)，所述电感400中电感线L1与电感线L2反向耦合。
需要说明的是，本申请中所述集成电路中包括的开关管可以是双极结型晶体管(bipolar junction transistor，BJT)、金属-氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)或绝缘栅双极型晶体管(insulated gate bipolar transistor，IGBT)等开关，所述集成电路中包括的多个开关管可以是相同类型的开关，也可以是不同类型的开关。
当所述第一脉冲P1为脉宽为4.9ns，周期为10ns，上升沿为0.1ns，下降沿为0.1ns的脉冲信号，所述第二脉冲P2信号为脉宽为4.9ns，周期为10ns，上升沿为0.1ns，下降沿为0.1ns的脉冲信号，且所述第二脉冲信号相较于所述第一脉冲信号延迟6ns，即所述第一脉冲P1与所述第二脉冲P2的相位相差180°，所述电感400中电感线L1的电感量为8.04nH，有效电阻为0.05Ω，所述电感400中电感线L2的电感量为8.243nH，寄生电阻为0.05Ω，所述电容C1的电容值为150nF，所述电阻R1的阻值为0.5Ω时，所述电感400的输出电流如图11a所示，在相同条件下，当所述电感400用现有的U形磁膜电感代替时，U形磁膜电感的输出电流如图11b所示，当所述电感400用现有的具有跳线结构的U形磁膜电感代替时，U形磁膜电感的输出电流如图11c所示。
由图11a可知，当所述两相交错降压电路中采用所述电感400时，所述电感400输出的电流最小值为I_out.min＝1.048A(如图11a中的m1点)，最大值I_out.max＝1.048A(如图11a中的m2点)，基本不存在纹波；由图11b可知，当所述两相交错降压电路中采用现有U形磁膜电感时，现有U形磁膜电感输出的电流最小值I_out.min＝1.033A(如图11b中的m1点)，最大值I_out.max＝1.062A(如图11b中的m2点)，电流纹波较大；由图11c可知，当所述两相交错降压电路中采用具有跳线结构的U形磁膜电感时，具有跳线结构的U形磁膜电感输出的电流最小值I_out.min＝1.043A(如图11c中的m1点)，最大值I_out.max＝1.052A(如图11c中的m2点)，电流纹波较大。可见，相较于现有技术，采用本申请所提供的电感400，能够有效减小多相交错升压/降压电路输出电流的纹波。
基于以上实施例，本申请还提供了一种电子设备，所述电子设备包括上述任意一种可能的实施方式所述的集成电路以及控制器，所述控制器用于控制所述集成电路中的开关管的状态。
通过上述方案，由于所述电子设备中的集成电路中采用的电感400中的电感线为S形，在集成电路中所占的空间小，便于集成，也有利于所述电子设备的小型化。另外，由于所述电感400中电感线的电感量相同，使得所述集成电路输出电流的纹波较小，进而能够提高所述集成电路的供电可靠性。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (11)

  1. 一种电感，其特征在于，包括由至少两个电感线并行组成的线圈；
    其中，所述线圈由连续的一段或多段S形部分组成，针对所述线圈的任意一段S形部分，该S形部分具有至少一对大小相等、折弯方向相反的折弯部。
  2. 如权利要求1所述的电感，其特征在于，所述线圈的外部设置有磁性壳状结构。
  3. 如权利要求2所述的电感，其特征在于，在所述线圈的长度方向上，所述线圈的相邻两个折弯部之间部分的外部设置有所述磁性壳状结构。
  4. 如权利要求2所述的电感，其特征在于，在所述线圈的宽度方向上，所述线圈的相邻两个折弯部之间部分的外部设置有所述磁性壳状结构。
  5. 一种电感，其特征在于，包括由至少两个电感线并行组成的线圈；
    其中，所述线圈包括至少两个长度延展部、至少三个宽度延展部，以及至少两对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述长度延展部与所述宽度延展部；或者，所述线圈包括至少三个宽度延展部，以及至少一对大小相等、折弯方向相反的折弯部，所述折弯部用于连接相邻的所述宽度延展部。
  6. 如权利要求5所述的电感，其特征在于，所述线圈的外部设置有磁性壳状结构。
  7. 如权利要求6所述的电感，其特征在于，所述至少两个长度延展部的外部设置有所述磁性壳状结构。
  8. 如权利要求6所述的电感，其特征在于，所述至少三个宽度延展部的外部设置有所述磁性壳状结构。
  9. 一种集成电路，其特征在于，所述集成电路为多相交错升压电路或多相交错降压电路，所述多相交错升压电路或多相交错降压电路包括一个或多个如权利要求1-8任意一项所述的电感。
  10. 如权利要求9所述的电路，其特征在于，所述电感中任意两个相邻电感线的同名端相反。
  11. 一种电子设备，其特征在于，包括如权利要求9或10所述的集成电路以及处理器；
    所述处理器，用于控制所述集成电路中的开关管的状态。
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