WO2020129273A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
WO2020129273A1
WO2020129273A1 PCT/JP2019/015843 JP2019015843W WO2020129273A1 WO 2020129273 A1 WO2020129273 A1 WO 2020129273A1 JP 2019015843 W JP2019015843 W JP 2019015843W WO 2020129273 A1 WO2020129273 A1 WO 2020129273A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
electrode
semiconductor element
lead frame
resin
Prior art date
Application number
PCT/JP2019/015843
Other languages
French (fr)
Japanese (ja)
Inventor
勝大 高尾
Original Assignee
アオイ電子株式会社
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Publication date
Application filed by アオイ電子株式会社 filed Critical アオイ電子株式会社
Priority to JP2019558803A priority Critical patent/JP6746808B1/en
Priority to TW108123817A priority patent/TW202025317A/en
Publication of WO2020129273A1 publication Critical patent/WO2020129273A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Definitions

  • the present invention relates to a semiconductor device and a semiconductor device manufacturing method.
  • the semiconductor element is housed with one of the electrodes provided on the semiconductor element facing the opening side of the housing of the lead frame, the other electrode is die-bonded to the lead frame, and the semiconductor element in the housing is sealed with resin.
  • a semiconductor device for surface mounting that stops. This semiconductor device is arranged such that one electrode faces a connection pad of a circuit board and is bonded to the connection pad of the circuit board with a bonding material such as solder (see Patent Document 1).
  • a semiconductor device includes at least one semiconductor element having a first electrode and a second electrode, a housing portion connected to the second electrode, and housing the at least one semiconductor element, and A terminal plate having at least one mounting terminal surface formed on the outer periphery of the housing portion, and the at least one semiconductor element housed in the housing portion of the terminal plate are sealed by exposing the first electrode. And a resin.
  • the mounting surface of the first electrode projects from the surface of the resin that seals the at least one semiconductor element.
  • it is preferable that the mounting terminal surface of the at least one mounting terminal of the terminal plate and the surface of the resin are flush with each other.
  • the semiconductor device of the first aspect it is preferable that a mounting terminal surface of the at least one mounting terminal of the terminal board is projected from the surface of the resin.
  • the at least one mounting terminal is provided on one side of the outer periphery of the accommodating portion and on an opposite side opposite to the one side, respectively. It is preferably provided.
  • the terminal plate is preferably a lead frame.
  • the accommodating portion is formed by etching the lead frame.
  • the at least one semiconductor element includes a plurality of semiconductor elements, and the plurality of semiconductor elements are accommodated in the accommodating portion of the lead frame. Is preferred.
  • the lead frame has a plurality of lead frame portions connected to each other by a connecting portion, and each of the plurality of lead frame portions includes: It is preferable to have the accommodating portion in which the at least one semiconductor element is accommodated.
  • the semiconductor element further has a third electrode, and a mounting surface of the third electrode seals the semiconductor element. It preferably protrudes from the surface of the resin.
  • the semiconductor element is a transistor, and a source electrode and a gate electrode are formed as the first electrode and the third electrode, respectively.
  • a drain electrode is preferably formed as the two electrodes.
  • the source electrode is composed of a plurality of divided source electrodes.
  • the semiconductor element has a plurality of semiconductor element regions, and each of the plurality of semiconductor element regions has the source electrode, the gate electrode, and the gate electrode. It is preferable to have the drain electrode.
  • the lead frame includes a first lead frame region and a second lead frame region which are mutually divided, A first semiconductor element and a second semiconductor element having the first electrode, the second electrode, and the third electrode, respectively, are accommodated in the accommodating portion, and the first electrode and the third semiconductor element of the first semiconductor element are accommodated. It is preferable that the electrode projects from the surface of the resin, and the back metal formed on the second electrode of the second semiconductor element projects from the surface of the resin.
  • the second electrode is electrically connected to a housing portion of a terminal plate housing a semiconductor element having a first electrode and a second electrode.
  • the semiconductor element is sealed with the resin so that the mounting surface of the first electrode projects from the surface of the resin, and the housing portion and the terminal plate formed outside the housing portion Individual semiconductor devices are obtained by cutting a connecting portion that connects a semiconductor device formation region having a mounting terminal surface and another semiconductor device formation region.
  • the surface of the resin is the mounting terminal surface of the terminal board. It is preferable that the terminal plate is sealed with the resin so as to be flush with each other.
  • the mounting terminal surface of the terminal board protrudes from the surface of the resin. Therefore, it is preferable that the terminal board is sealed with the resin.
  • FIG. 1 is an external perspective view of a semiconductor device according to the first embodiment of the present invention.
  • 2 is an external perspective view of the semiconductor device shown in FIG. 1 before resin sealing.
  • FIG. 3 is a sectional view taken along the line III-III of the semiconductor device shown in FIG. However, in FIG. 3, the top and bottom are inverted with respect to FIG. 4A is a top view of the semiconductor device shown in FIG. 2, and
  • FIG. 4B is a bottom view of the semiconductor device shown in FIG. 5A to 5E are sectional views of the semiconductor device in respective steps for explaining the example of the method for manufacturing the semiconductor device according to the first embodiment.
  • 6A to 6D are cross-sectional views of the semiconductor device in each step subsequent to FIG.
  • FIG. 7A to 7D are cross-sectional views of the semiconductor device in each step subsequent to FIG.
  • FIG. 8 is a plan view of the semiconductor device shown in FIG. 7C as seen from above.
  • FIG. 9 is a sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 10 is a bottom view showing the semiconductor device according to the third embodiment of the present invention.
  • FIG. 11 is a bottom view showing the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 12 is a bottom view showing a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 13 is a bottom view showing the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 14 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention.
  • 1 is an external perspective view of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is an external perspective view of the semiconductor device shown in FIG. 1 before resin sealing.
  • the semiconductor device 10 has a rectangular parallelepiped shape with a thickness of about 0.3 to 0.8 mm.
  • the semiconductor device 10 includes a semiconductor element 20 (see FIG. 2) such as a MOSFET (metal-oxide-semiconductor field-effect transistor), a lead frame 30 (see FIG. 2), and a resin 50.
  • the semiconductor element 20 has a gate electrode 21, two divided source electrodes 22a and 22b, and a drain electrode 24 (see FIG. 3).
  • the semiconductor element 20 is formed by stacking a gate electrode 21, divided source electrodes 22a and 22b (hereinafter, both electrodes may be collectively referred to as “source electrode 22”) and a drain electrode 24 in the thickness direction.
  • the drain electrode 24 is formed on the entire bottom surface of the semiconductor element 20 having a vertical structure.
  • the lead frame 30 has a rectangular shape having a pair of long sides and a pair of short sides in a plan view, and a housing portion 31 for housing the semiconductor element 20 and mounting terminals 33 provided in the vicinity of the four corner portions, respectively. Have. That is, a plurality (in the present embodiment, two are exemplified) of one side of the short side of the outer periphery of the housing portion 31 of the semiconductor device 10 and the opposite side facing the one side. Mounting terminals 33 are provided.
  • the lead frame 30 is electrically connected to the drain electrode 24 of the semiconductor element 20 at the bottom surface 31 a of the housing portion 31.
  • the lead frame 30 is formed of a metal such as copper or iron.
  • the semiconductor element 20 and the lead frame 30 are sealed with a resin 50 as shown in FIG. More specifically, the semiconductor element 20 is sealed by the resin 50 so that the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the two divided source electrodes 22a and 22b project from the one surface 51 of the resin 50. It The lead frame 30 is sealed with a resin 50 such that the mounting terminal surfaces 33 a, which are the surfaces of the four mounting terminals 33, are flush with the one surface 51 of the resin 50.
  • FIG. 3 is a sectional view taken along the line III-III of the semiconductor device shown in FIG. However, in FIG. 3, the top and bottom are inverted with respect to FIG. 4A is a top view of the semiconductor device shown in FIG. 2, and FIG. 4B is a bottom view of the semiconductor device shown in FIG.
  • a back metal 41 is formed on the drain electrode 24 of the semiconductor element 20, and the back metal 41 is die-bonded to the bottom surface 31 a of the housing 31 by a conductive bonding material 42 such as silver paste. Has been done. Therefore, the drain electrode 24 is electrically connected to the housing portion 31.
  • Each mounting terminal 33 is integrally formed with a side wall 32 that is formed substantially perpendicular to the bottom surface 31 a of the housing portion 31.
  • the semiconductor device 10 has a pair of side walls 32 formed integrally with each pair of the two pairs of mounting terminals 33, and the housing portion 31 has a groove provided between the pair of side walls 32. Is formed as.
  • each mounting terminal 33 has a mounting terminal body 34, a row connecting portion 35, and a column connecting portion 36, and the row connecting portion 35 and the column connecting portion 36 are respectively viewed in a plan view.
  • the mounting terminal body 34 projects in the row direction Dr and the column direction Dc.
  • the row connecting portions 35 and the column connecting portions 36 are thinner than the mounting terminal body 34.
  • the row connecting portion 35 and the column connecting portion 36 are disconnected when the individual semiconductor devices 10 are obtained from the semiconductor device assembly 100C (see FIG. 8) in which the plurality of semiconductor devices 10 are integrally formed. And has cut surfaces 35a and 36a, respectively. Therefore, the cut surfaces 35a and 36a are exposed from the resin 50 as illustrated in FIG.
  • the row direction Dr is a direction along the long side direction of the semiconductor device 10
  • the column direction Dc is a direction along the short side direction.
  • the housing portion 31 of the lead frame 30 is formed by etching from the one surface 44 (see FIG. 3) side of the lead frame 30, which is the mounting terminal surface 33a side.
  • the row connecting portion 35 and the column connecting portion 36 are formed to have a thickness smaller than that of the mounting terminal body 34 by etching the lead frame 30 from the other surface 45a side of the lead frame 30 to form the groove 47.
  • the lead frame 30 When the lead frame 30 is formed by press working, the lead frame 30 is easily deformed due to residual stress during pressing. When deformation such as warpage occurs in the lead frame 30, each connection of a circuit board (not shown) bonded to each mounting terminal surface 33a, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b. The parallelism with the pad deteriorates and the mounting accuracy decreases.
  • the housing portion 31 and the mounting terminal 33 of the lead frame 30 are formed by etching. Therefore, unlike the case of pressing, no residual stress is generated during formation, and each mounting terminal surface 33a, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b, and the circuit board. The parallelism with each connection pad can be ensured, and the mounting accuracy can be improved.
  • the resin 50 is filled in the lead frame 30 housing portion 31 and the groove 47 during molding.
  • the other surface 45a of the lead frame 30 is exposed from the resin 50 (see FIG. 4A).
  • the semiconductor element 20 and the lead frame 30 are sealed with resin 50.
  • the resin 50 ensures a state in which protection from the external environment, insulation, heat dissipation and thermal conductivity are suitable.
  • the resin 50 for example, an epoxy resin or the like is used.
  • the mounting terminal surface 33a of each mounting terminal 33 and the one surface 51 of the resin 50 are flush with each other. Further, the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are projected more than the mounting terminal surface 33 a and the one surface 51 of the resin 50.
  • the amount ⁇ h of protrusion of the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 from the one surface 51 of the resin 50 is preferably about 0.01 mm to 0.05 mm, for example. However, this numerical value is not intended to specify the protrusion amount ⁇ h in this range, but is shown only as an example.
  • the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are the one surface 51 of the resin 50 when viewed from the direction of the arrow DA in FIG. 1, that is, the direction in which the cut surface 36 a of the column connection portion 36 is the front surface. It may be any structure as long as it can be confirmed with a measuring microscope that the protrusion is not recessed.
  • the semiconductor device 10 is configured such that the mounting surface 21a of the gate electrode 21, the mounting surface 23 of the source electrode 22 and the mounting terminal surface 33a of the lead frame 30 are directed downward.
  • the mounting surface 21a of 21, the mounting surface 23 of the source electrode 22, and the mounting terminal surface 33a of the lead frame 30 are bonded to the respective connection pads of the circuit board (not shown) by a bonding material such as solder.
  • the mounting terminal surface 33a of the lead frame 30 is formed at four corners. Therefore, as compared with a structure in which one mounting terminal surface 33a is formed on each of a pair of side portions that face each other while being separated in the row direction Dr of the lead frame 30, deformation of the lead frame 30 after bonding is suppressed, and mounting is performed. The accuracy of can be improved.
  • the source electrode 22 is divided into two divided source electrodes 22a and 22b. If the structure in which the source electrode 22 is not divided but made into one is used, the amount of solder increases, and the lead frame 30 is easily deformed when the solder contracts. By dividing the source electrode 22 into the two divided source electrodes 22a and 22b, the amount of solder becomes uniform and the deformation of the lead frame 30 at the time of contraction of solder can be suppressed.
  • the mounting terminal surface 33a is exemplified as a structure divided into four, the mounting terminal surface 33a may be provided within three or five or more. When the number of mounting terminal surfaces 33a is odd, the number of mounting terminal surfaces 33a provided on one side and the other side is different. Further, the source electrode 22 may be configured as three or more divided source electrodes.
  • FIGS. 6A to 6D are diagrams.
  • 5A to 5D are cross-sectional views of the semiconductor device in each step following FIG. 5
  • FIGS. 7A to 7D are cross-sectional views of the semiconductor device in each step following FIG.
  • a manufacturing method for forming the two semiconductor devices 10 will be exemplified. However, this manufacturing method can also be applied to the case of forming one semiconductor device 10 and the case of forming three or more semiconductor devices 10.
  • a wafer 20w having two semiconductor element forming regions A1 and A2 adjacent to each other in the row direction Dr (left and right direction in FIG. 5) is prepared, and a gate electrode 21 and a source electrode 22 are provided in each semiconductor element forming region A1 and A2.
  • the drain electrode 24 is formed on the entire bottom surface of the wafer 20w.
  • the back metal 41 is formed on the drain electrode 24.
  • the back metal 41 is provided to reduce the resistance of the bottom surface of the wafer 20w.
  • the back metal 41 has a single layer structure of gold, or a multi-layer structure of titanium (lower layer), nickel (intermediate layer), gold (surface layer), and the like. You can The back metal 41 can be formed by sputtering, plating, or the like (see FIG. 5A).
  • a lead frame material 30M having two semiconductor device formation regions B1 and B2 connected to each other in the row direction Dr is prepared.
  • the lead frame material 30M is a flat plate member having a thickness of, for example, about 0.3 mm to 0.7 mm, as indicated by a chain double-dashed line L1 in FIG. 5B.
  • half-etching is performed from the one surface 44 side of the lead frame material 30M to form the accommodation portion 31.
  • the half etching for forming the accommodating portion 31 not only removes the inner region of the side wall 32 but also forms the four mounting terminals 33 illustrated in FIG. 2 in the column direction Dc (in the plane of FIG. 5). Also, the space between the mounting terminals 33 in the vertical direction) is removed. However, at this point, the row connection portion 35 and the column connection portion 36 of each mounting terminal 33 have the same thickness as the mounting terminal body 34.
  • the lead frame material 30M is half-etched from the other surface 45a side facing the one surface 44 to form the groove 47.
  • the groove 47 is formed on the four sides around each accommodation portion 31 in each of the semiconductor device formation regions B1 and B2.
  • the thickness of the row connection portion 35 and the column connection portion 36 of each mounting terminal 33 is smaller than that of the mounting terminal body 34.
  • the thickness of each of the bottom portion 45 of the accommodating portion 31, the row connecting portion 35 and the column connecting portion 36 of the mounting terminal 33 is 30 to 50 of the total thickness of the lead frame material 30M before etching. Perform it so that it becomes about %.
  • the bottom portion 45 of the housing portion 31, the row connection portion 35 and the column connection portion 36 of the mounting terminal 33 may have the same thickness or different thicknesses.
  • a back tape 62 is attached to the other surface 45a that faces the one surface 44 of the lead frame material 30M.
  • the back tape 62 is a member for preventing the resin material 50M (see FIG. 6B) from leaking to the other surface 45a side of the lead frame 30 during molding.
  • the back metal 41 formed on the bottom surface side of the wafer 20w shown in FIG. 5A is attached to the dicing tape 63 (see FIG. 5D).
  • the wafer 20w is diced at the boundary between the semiconductor element forming area A1 and the semiconductor element forming area A2 to separate the semiconductor element forming area A1 and the semiconductor element forming area A2. To do. As a result, the semiconductor element 20 is formed in each of the semiconductor element forming area A1 and the semiconductor element forming area A2. The dicing between the semiconductor element forming area A1 and the semiconductor element forming area A2 is performed up to the middle of the thickness of the dicing tape 63.
  • a conductive bonding material 42 such as a silver paste is potted on the bottom surface 31a of the accommodating portion 31 of each of the semiconductor device forming regions B1 and B2 of the lead frame material 30M.
  • each semiconductor element 20 is picked up from the dicing tape 63 by using a pick-up device or the like, and the semiconductor element 20 is inserted into the accommodating portions 31 of the semiconductor device forming regions B1 and B2 of the lead frame material 30M via the conductive bonding material 42. Die bonding is performed on the bottom surface 31a (see FIG. 6A).
  • an intermediate semiconductor device assembly 100A in which the semiconductor element 20 is die-bonded to each of the semiconductor device formation regions B1 and B2 of the lead frame material 30M is formed.
  • drain electrode 24 of the first semiconductor element 20C and the source electrode 22 of the second semiconductor element 20D are electrically connected to the lead frame region 30r, and the gate electrode 21 of the second semiconductor element 20D is It is electrically connected to the lead frame region 30s.
  • the semiconductor device 10 according to the seventh embodiment not only the first semiconductor element 20C but also the second semiconductor element 20D have the same effects (1) and (2) as those of the first embodiment. ..
  • the gate electrode 21 and the source electrode 22 in the first semiconductor element 20C are replaced with the back metal 41 and the conductive bonding material 42 or the back metal 41 formed on the drain electrode 24.
  • the same effects (3) and (4) as those of the first embodiment can be obtained.
  • the semiconductor element 20 is exemplified as the MOSFET having the gate electrode 21, the source electrode 22, and the drain electrode 24.
  • an IGBT Insulated Gate Bipolar
  • Transistor or Bipolar
  • a diode having an anode electrode and a cathode electrode can be used.
  • the lead frame 30 is exemplified as a member having a rectangular shape in a plan view.
  • the lead frame 30 may have a polygonal shape such as a triangle or a pentagonal shape in plan view.

Abstract

This semiconductor device includes: at least one semiconductor element that has a first electrode and a second electrode; a terminal plate which has an accommodating part that is connected to the second electrode and accommodates the at least one semiconductor element, and at least one mounting terminal face that is formed on an outer periphery of the accommodating part; and resin that seals the at least one semiconductor element accommodated in the accommodating part of the terminal plate with the first electrode exposed. A mounting face of the first electrode protrudes more than the surface of the resin that seals the at least one semiconductor element.

Description

半導体装置および半導体装置の製造方法Semiconductor device and method of manufacturing semiconductor device
　本発明は、半導体装置および半導体装置の製造方法に関する。 The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
　半導体素子を、半導体素子に設けられた一方の電極をリードフレームの収容部の開口側に向けた状態で収容し、他方の電極をリードフレームにダイボンディングし、収容部内の半導体素子を樹脂により封止する表面実装用の半導体装置が知られている。この半導体装置は、回路基板の接続パッドに、一方の電極を対向して配置され、はんだ等の接合材により回路基板の接続パッドに接合される（特許文献１参照）。 The semiconductor element is housed with one of the electrodes provided on the semiconductor element facing the opening side of the housing of the lead frame, the other electrode is die-bonded to the lead frame, and the semiconductor element in the housing is sealed with resin. There is known a semiconductor device for surface mounting that stops. This semiconductor device is arranged such that one electrode faces a connection pad of a circuit board and is bonded to the connection pad of the circuit board with a bonding material such as solder (see Patent Document 1).
米国特許第６，７８４，５３７号明細書US Pat. No. 6,784,537
　特許文献１に記載の半導体装置では、モールド成型により半導体素子を封止する際、上述した一方の電極の表面に樹脂バリが形成され易い。このため、はんだ等によりその電極を回路基板の接続パッドに接合する際、接合強度が低下したり、導通不良が生じたりする。 In the semiconductor device described in Patent Document 1, a resin burr is likely to be formed on the surface of one electrode described above when the semiconductor element is sealed by molding. For this reason, when the electrodes are joined to the connection pads of the circuit board by soldering or the like, the joint strength may be reduced, or conduction failure may occur.
　本発明の第１の態様によると、半導体装置は、第一電極および第二電極を有する少なくとも一つの半導体素子と、前記第二電極に接続され、前記少なくとも一つの半導体素子を収容する収容部および前記収容部の外周に形成された少なくとも一つの実装端子面を有する端子板と、前記端子板の収容部に収容された前記少なくとも一つの半導体素子を、前記第一電極を露出させて封止する樹脂とを備える。前記第一電極の実装用表面は、前記少なくとも一つの半導体素子を封止する前記樹脂の表面より突出している。
　本発明の第２の態様によると、第１の態様の半導体装置において、前記端子板の前記少なくとも一つの実装端子の実装端子面と前記樹脂の前記表面とは面一であるのが好ましい。
　本発明の第３の態様によると、第１の態様の半導体装置において、前記端子板の前記少なくとも一つの実装端子の実装端子面は前記樹脂の前記表面より突出しているのが好ましい。
　本発明の第４の態様によると、第１の態様の半導体装置において、前記少なくとも一つの実装端子は、前記収容部の前記外周のうちの一辺側および前記一辺側に対向する対向辺側にそれぞれ設けられるのが好ましい。
　本発明の第５の態様によると、第１の態様の半導体装置において、前記端子板は、リードフレームであるのが好ましい。
　本発明の第６の態様によると、第５の態様の半導体装置において、前記収容部は、前記リードフレームのエッチングにより形成されるのが好ましい。
　本発明の第７の態様によると、第５の態様の半導体装置において、前記少なくとも一つの半導体素子は複数の半導体素子を含み、前記リードフレームの前記収容部内に前記複数の半導体素子が収容されているのが好ましい。
　本発明の第８の態様によると、第５の態様の半導体装置において、前記リードフレームは連結部により相互に連結された複数のリードフレーム部を有し、前記複数のリードフレーム部の各々は、それぞれ前記少なくとも一つの半導体素子が収容された前記収容部を有するのが好ましい。
　本発明の第９の態様によると、第５の態様の半導体装置において、前記半導体素子は、第三電極をさらに有し、前記第三電極の実装用表面は、前記半導体素子を封止する前記樹脂の表面より突出しているのが好ましい。
　本発明の第１０の態様によると、第９の態様の半導体装置において、前記半導体素子はトランジスタであって、前記第一電極および前記第三電極としてソース電極およびゲート電極がそれぞれ形成され、前記第二電極としてドレイン電極が形成されるのが好ましい。
　本発明の第１１の態様によると、第１０の態様の半導体装置において、前記ソース電極は、複数の分割ソース電極により構成されるのが好ましい。
　本発明の第１２の態様によると、第１０の態様の半導体装置において、前記半導体素子は複数の半導体素子領域を有し、前記複数の半導体素子領域の各々は、前記ソース電極、前記ゲート電極および前記ドレイン電極を有するのが好ましい。
　本発明の第１３の態様によると、第９の態様の半導体装置において、前記リードフレームは、相互に分割された第１のリードフレーム領域および第２のリードフレーム領域を含み、前記リードフレームの前記収容部内に前記第一電極、前記第二電極および前記第三電極をそれぞれ有する第１の半導体素子および第２の半導体素子が収容され、前記第１の半導体素子の前記第一電極および前記第三電極は前記樹脂の表面より突出し、前記第２の半導体素子の前記第二電極上に形成されたバックメタルは前記樹脂の表面より突出しているのが好ましい。
　本発明の第１４の態様によると、半導体装置の製造方法は、第一電極および第二電極を有する半導体素子が収容される端子板の収容部へ、前記第二電極が電気的に接続されるようにボンディングし、前記第一電極の実装用表面が樹脂の表面より突出するように前記半導体素子を前記樹脂により封止し、前記収容部と前記収容部の外部に形成された前記端子板の実装端子面とを有する半導体装置形成領域と、別の前記半導体装置形成領域とを接続する連結部分を切断することにより、個々の半導体装置を得る。
　本発明の第１５の態様によると、第１４の態様による半導体装置の製造方法において、前記半導体素子を前記樹脂により封止する際、前記樹脂の前記表面が、前記端子板の前記実装端子面と面一になるように、前記端子板が前記樹脂により封止されるのが好ましい。
　本発明の第１６の態様によると、第１４の態様による半導体装置の製造方法において、前記半導体素子を前記樹脂により封止する際、前記端子板の前記実装端子面が前記樹脂の前記表面より突出するように、前記端子板が前記樹脂により封止されるのが好ましい。 According to the first aspect of the present invention, a semiconductor device includes at least one semiconductor element having a first electrode and a second electrode, a housing portion connected to the second electrode, and housing the at least one semiconductor element, and A terminal plate having at least one mounting terminal surface formed on the outer periphery of the housing portion, and the at least one semiconductor element housed in the housing portion of the terminal plate are sealed by exposing the first electrode. And a resin. The mounting surface of the first electrode projects from the surface of the resin that seals the at least one semiconductor element.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, it is preferable that the mounting terminal surface of the at least one mounting terminal of the terminal plate and the surface of the resin are flush with each other.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, it is preferable that a mounting terminal surface of the at least one mounting terminal of the terminal board is projected from the surface of the resin.
According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, the at least one mounting terminal is provided on one side of the outer periphery of the accommodating portion and on an opposite side opposite to the one side, respectively. It is preferably provided.
According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the terminal plate is preferably a lead frame.
According to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, it is preferable that the accommodating portion is formed by etching the lead frame.
According to a seventh aspect of the present invention, in the semiconductor device according to the fifth aspect, the at least one semiconductor element includes a plurality of semiconductor elements, and the plurality of semiconductor elements are accommodated in the accommodating portion of the lead frame. Is preferred.
According to an eighth aspect of the present invention, in the semiconductor device according to the fifth aspect, the lead frame has a plurality of lead frame portions connected to each other by a connecting portion, and each of the plurality of lead frame portions includes: It is preferable to have the accommodating portion in which the at least one semiconductor element is accommodated.
According to a ninth aspect of the present invention, in the semiconductor device of the fifth aspect, the semiconductor element further has a third electrode, and a mounting surface of the third electrode seals the semiconductor element. It preferably protrudes from the surface of the resin.
According to a tenth aspect of the present invention, in the semiconductor device of the ninth aspect, the semiconductor element is a transistor, and a source electrode and a gate electrode are formed as the first electrode and the third electrode, respectively. A drain electrode is preferably formed as the two electrodes.
According to an eleventh aspect of the present invention, in the semiconductor device of the tenth aspect, it is preferable that the source electrode is composed of a plurality of divided source electrodes.
According to a twelfth aspect of the present invention, in the semiconductor device of the tenth aspect, the semiconductor element has a plurality of semiconductor element regions, and each of the plurality of semiconductor element regions has the source electrode, the gate electrode, and the gate electrode. It is preferable to have the drain electrode.
According to a thirteenth aspect of the present invention, in the semiconductor device of the ninth aspect, the lead frame includes a first lead frame region and a second lead frame region which are mutually divided, A first semiconductor element and a second semiconductor element having the first electrode, the second electrode, and the third electrode, respectively, are accommodated in the accommodating portion, and the first electrode and the third semiconductor element of the first semiconductor element are accommodated. It is preferable that the electrode projects from the surface of the resin, and the back metal formed on the second electrode of the second semiconductor element projects from the surface of the resin.
According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor device, the second electrode is electrically connected to a housing portion of a terminal plate housing a semiconductor element having a first electrode and a second electrode. As described above, the semiconductor element is sealed with the resin so that the mounting surface of the first electrode projects from the surface of the resin, and the housing portion and the terminal plate formed outside the housing portion Individual semiconductor devices are obtained by cutting a connecting portion that connects a semiconductor device formation region having a mounting terminal surface and another semiconductor device formation region.
According to a fifteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the fourteenth aspect, when the semiconductor element is sealed with the resin, the surface of the resin is the mounting terminal surface of the terminal board. It is preferable that the terminal plate is sealed with the resin so as to be flush with each other.
According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourteenth aspect, when the semiconductor element is sealed with the resin, the mounting terminal surface of the terminal board protrudes from the surface of the resin. Therefore, it is preferable that the terminal board is sealed with the resin.
　本発明によれば、半導体素子の電極の実装用表面に樹脂バリが形成されるのを抑制することができる。 According to the present invention, it is possible to suppress the formation of a resin burr on the mounting surface of the electrode of the semiconductor element.
図１は、本発明の第１の実施形態による半導体装置の外観斜視図である。FIG. 1 is an external perspective view of a semiconductor device according to the first embodiment of the present invention. 図２は、図１に示された半導体装置の樹脂封止前の外観斜視図である。2 is an external perspective view of the semiconductor device shown in FIG. 1 before resin sealing. 図３は、図１に示された半導体装置のＩＩＩ－ＩＩＩ線断面図である。但し、図３では、図１に対し上下が反転されている。FIG. 3 is a sectional view taken along the line III-III of the semiconductor device shown in FIG. However, in FIG. 3, the top and bottom are inverted with respect to FIG. 図４（Ａ）は、図２に示された半導体装置の上面図であり、図４（Ｂ）は、図２に示された半導体装置の下面図である。4A is a top view of the semiconductor device shown in FIG. 2, and FIG. 4B is a bottom view of the semiconductor device shown in FIG. 図５（Ａ）～５（Ｅ）は、第１の実施形態による半導体装置の製造方法の一例を説明するための各工程における半導体装置の断面図である。5A to 5E are sectional views of the semiconductor device in respective steps for explaining the example of the method for manufacturing the semiconductor device according to the first embodiment. 図６（Ａ）～６（Ｄ）は、図５に続く各工程における半導体装置の断面図である。6A to 6D are cross-sectional views of the semiconductor device in each step subsequent to FIG. 図７（Ａ）～７（Ｄ）は、図６に続く各工程における半導体装置の断面図である。7A to 7D are cross-sectional views of the semiconductor device in each step subsequent to FIG. 図８は、図７（Ｃ）に示された半導体装置を上方からみた平面図である。FIG. 8 is a plan view of the semiconductor device shown in FIG. 7C as seen from above. 図９は、本発明の第２の実施形態による半導体装置を示す断面図である。FIG. 9 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. 図１０は、本発明の第３の実施形態による半導体装置を示す下面図である。FIG. 10 is a bottom view showing the semiconductor device according to the third embodiment of the present invention. 図１１は、本発明の第４の実施形態による半導体装置を示す下面図である。FIG. 11 is a bottom view showing the semiconductor device according to the fourth embodiment of the present invention. 図１２は、本発明の第５の実施形態による半導体装置を示す下面図である。FIG. 12 is a bottom view showing a semiconductor device according to the fifth embodiment of the present invention. 図１３は、本発明の第６の実施形態による半導体装置を示す下面図である。FIG. 13 is a bottom view showing the semiconductor device according to the sixth embodiment of the present invention. 図１４は、本発明の第７の実施形態による半導体装置を示す断面図である。FIG. 14 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention.
－第１の実施形態－
　図１～図８を参照して、本発明の第１の実施形態による半導体装置を説明する。図１は、本発明の第１の実施形態による半導体装置の外観斜視図であり、図２は、図１に示された半導体装置の樹脂封止前の外観斜視図である。半導体装置１０は、厚さが０．３～０．８ｍｍ程度の直方体形状を有する。 -First embodiment-
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 8. 1 is an external perspective view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is an external perspective view of the semiconductor device shown in FIG. 1 before resin sealing. The semiconductor device 10 has a rectangular parallelepiped shape with a thickness of about 0.3 to 0.8 mm.
　半導体装置１０は、ＭＯＳＦＥＴ（metal-oxide-semiconductor field-effect transistor）等の半導体素子２０（図２参照）と、リードフレーム３０（図２参照）と、樹脂５０とを備えている。半導体素子２０は、ゲート電極２１と、２つの分割ソース電極２２ａ、２２ｂと、ドレイン電極２４（図３参照）とを有する。半導体素子２０は、ゲート電極２１、分割ソース電極２２ａ、２２ｂ（以下、両電極を代表して「ソース電極２２」と呼ぶことがある。）およびドレイン電極２４が厚さ方向に積層して形成された縦型構造を有し、半導体素子２０の底面全面にドレイン電極２４が形成されている。 The semiconductor device 10 includes a semiconductor element 20 (see FIG. 2) such as a MOSFET (metal-oxide-semiconductor field-effect transistor), a lead frame 30 (see FIG. 2), and a resin 50. The semiconductor element 20 has a gate electrode 21, two divided source electrodes 22a and 22b, and a drain electrode 24 (see FIG. 3). The semiconductor element 20 is formed by stacking a gate electrode 21, divided source electrodes 22a and 22b (hereinafter, both electrodes may be collectively referred to as “source electrode 22”) and a drain electrode 24 in the thickness direction. The drain electrode 24 is formed on the entire bottom surface of the semiconductor element 20 having a vertical structure.
　リードフレーム３０は、平面視で、一対の長辺と一対の短辺とを有する矩形形状を有し、半導体素子２０を収容する収容部３１および４つのコーナー部近傍のそれぞれに設けられる実装端子３３を有する。すなわち、半導体装置１０の収容部３１の外周のうちの短辺の一辺側と、この一辺側に対向する対向辺側とに、それぞれ、複数（本実施形態では、２つとして例示されている）の実装端子３３が設けられている。リードフレーム３０は、収容部３１の底面３１ａで半導体素子２０のドレイン電極２４に電気的に接続されている。リードフレーム３０は、例えば、銅、鉄等の金属により形成されている。 The lead frame 30 has a rectangular shape having a pair of long sides and a pair of short sides in a plan view, and a housing portion 31 for housing the semiconductor element 20 and mounting terminals 33 provided in the vicinity of the four corner portions, respectively. Have. That is, a plurality (in the present embodiment, two are exemplified) of one side of the short side of the outer periphery of the housing portion 31 of the semiconductor device 10 and the opposite side facing the one side. Mounting terminals 33 are provided. The lead frame 30 is electrically connected to the drain electrode 24 of the semiconductor element 20 at the bottom surface 31 a of the housing portion 31. The lead frame 30 is formed of a metal such as copper or iron.
　半導体素子２０およびリードフレーム３０は、樹脂５０により図１に図示されるように封止される。より詳細には、半導体素子２０は、樹脂５０によりゲート電極２１の実装用表面２１ａおよび２つの分割ソース電極２２ａ、２２ｂの実装用表面２３が、樹脂５０の一面５１から突出するように封止される。リードフレーム３０は、樹脂５０により４つの実装端子３３のそれぞれの表面である実装端子面３３ａが樹脂５０の一面５１と面一になるように封止されている。 The semiconductor element 20 and the lead frame 30 are sealed with a resin 50 as shown in FIG. More specifically, the semiconductor element 20 is sealed by the resin 50 so that the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the two divided source electrodes 22a and 22b project from the one surface 51 of the resin 50. It The lead frame 30 is sealed with a resin 50 such that the mounting terminal surfaces 33 a, which are the surfaces of the four mounting terminals 33, are flush with the one surface 51 of the resin 50.
　図３は、図１に示された半導体装置のＩＩＩ－ＩＩＩ線断面図である。但し、図３では、図１に対し上下が反転されている。また、図４（Ａ）は、図２に示された半導体装置の上面図であり、図４（Ｂ）は、図２に示された半導体装置の下面図である。 3 is a sectional view taken along the line III-III of the semiconductor device shown in FIG. However, in FIG. 3, the top and bottom are inverted with respect to FIG. 4A is a top view of the semiconductor device shown in FIG. 2, and FIG. 4B is a bottom view of the semiconductor device shown in FIG.
　図３に図示されるように、半導体素子２０のドレイン電極２４には、バックメタル４１が形成され、バックメタル４１は、銀ペーストのような導電接合材４２により収容部３１の底面３１ａにダイボンディングされている。したがって、ドレイン電極２４は収容部３１へ電気的に接続される。各実装端子３３は収容部３１の底面３１ａにほぼ垂直に形成された側壁３２と一体的に形成されている。換言すれば、半導体装置１０は、２対の実装端子３３のそれぞれの対に一体的に形成された１対の側壁３２を有し、収容部３１は１対の側壁３２間に設けられた溝として形成されている。 As shown in FIG. 3, a back metal 41 is formed on the drain electrode 24 of the semiconductor element 20, and the back metal 41 is die-bonded to the bottom surface 31 a of the housing 31 by a conductive bonding material 42 such as silver paste. Has been done. Therefore, the drain electrode 24 is electrically connected to the housing portion 31. Each mounting terminal 33 is integrally formed with a side wall 32 that is formed substantially perpendicular to the bottom surface 31 a of the housing portion 31. In other words, the semiconductor device 10 has a pair of side walls 32 formed integrally with each pair of the two pairs of mounting terminals 33, and the housing portion 31 has a groove provided between the pair of side walls 32. Is formed as.
　図２に図示されるように、各実装端子３３は、実装端子本体３４と、行接続部３５と列接続部３６とを有し、平面視で、行接続部３５および列接続部３６がそれぞれ実装端子本体３４から行方向Ｄｒおよび列方向Ｄｃに突き出ている。行接続部３５および列接続部３６の厚さは、実装端子本体３４より薄く形成されている。詳細は後述するが、行接続部３５および列接続部３６は、複数の半導体装置１０が一体的に形成された半導体装置集合体１００Ｃ（図８参照）から個々の半導体装置１０を得るときに切断される部分であり、それぞれ、切断面３５ａおよび３６ａを有する。従って、切断面３５ａおよび３６ａは、図１に図示されるように、樹脂５０から露出している。なお、以下の説明において、行方向Ｄｒは半導体装置１０の長辺方向に沿う方向、列方向Ｄｃは短辺方向に沿う方向とする。 As illustrated in FIG. 2, each mounting terminal 33 has a mounting terminal body 34, a row connecting portion 35, and a column connecting portion 36, and the row connecting portion 35 and the column connecting portion 36 are respectively viewed in a plan view. The mounting terminal body 34 projects in the row direction Dr and the column direction Dc. The row connecting portions 35 and the column connecting portions 36 are thinner than the mounting terminal body 34. Although details will be described later, the row connecting portion 35 and the column connecting portion 36 are disconnected when the individual semiconductor devices 10 are obtained from the semiconductor device assembly 100C (see FIG. 8) in which the plurality of semiconductor devices 10 are integrally formed. And has cut surfaces 35a and 36a, respectively. Therefore, the cut surfaces 35a and 36a are exposed from the resin 50 as illustrated in FIG. In the following description, the row direction Dr is a direction along the long side direction of the semiconductor device 10, and the column direction Dc is a direction along the short side direction.
　詳細は後述するが、リードフレーム３０の収容部３１は、リードフレーム３０の、実装端子面３３ａ側である一面４４（図３参照）側からのエッチングにより形成される。また、行接続部３５および列接続部３６は、リードフレーム３０の他面４５ａ側からリードフレーム３０をエッチングして溝４７を形成することにより、実装端子本体３４の厚さより薄い厚さに形成される。 Although details will be described later, the housing portion 31 of the lead frame 30 is formed by etching from the one surface 44 (see FIG. 3) side of the lead frame 30, which is the mounting terminal surface 33a side. The row connecting portion 35 and the column connecting portion 36 are formed to have a thickness smaller than that of the mounting terminal body 34 by etching the lead frame 30 from the other surface 45a side of the lead frame 30 to form the groove 47. It
　リードフレーム３０を、プレス加工により形成する場合は、プレス時の残留応力により、リードフレーム３０には、反り等の変形が生じ易くなる。リードフレーム３０に反り等の変形が生じると、各実装端子面３３ａ、ゲート電極２１の実装用表面２１ａおよび分割ソース電極２２ａ、２２ｂの実装用表面２３と接合される不図示の回路基板の各接続パッドとの平行度が悪くなり、実装精度が低下する。 When the lead frame 30 is formed by press working, the lead frame 30 is easily deformed due to residual stress during pressing. When deformation such as warpage occurs in the lead frame 30, each connection of a circuit board (not shown) bonded to each mounting terminal surface 33a, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b. The parallelism with the pad deteriorates and the mounting accuracy decreases.
　これに対し、本実施形態では、リードフレーム３０の収容部３１および実装端子３３をエッチングにより形成する。このため、プレス加工による場合とは異なり、形成時に残留応力は発生せず、各実装端子面３３ａ、ゲート電極２１の実装用表面２１ａおよび分割ソース電極２２ａ、２２ｂの実装用表面２３と、回路基板の各接続パッドとの平行度を確保することができ、実装精度を向上することができる。 On the other hand, in the present embodiment, the housing portion 31 and the mounting terminal 33 of the lead frame 30 are formed by etching. Therefore, unlike the case of pressing, no residual stress is generated during formation, and each mounting terminal surface 33a, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b, and the circuit board. The parallelism with each connection pad can be ensured, and the mounting accuracy can be improved.
　図３、図４（Ａ）、（Ｂ）に図示されるように、モールド成型時に、リードフレーム３０収容部３１内および溝４７内に樹脂５０が充填される。リードフレーム３０の他面４５ａは、樹脂５０から露出されている（図４（Ａ）参照）。 As illustrated in FIGS. 3, 4A, and 4B, the resin 50 is filled in the lead frame 30 housing portion 31 and the groove 47 during molding. The other surface 45a of the lead frame 30 is exposed from the resin 50 (see FIG. 4A).
　上述した通り、半導体素子２０のゲート電極２１、分割ソース電極２２ａ、２２ｂ、リードフレーム３０の他面４５ａ、各実装端子３３の実装端子面３３ａおよび切断面３５ａ、３６ａ（図１参照）を除き、半導体素子２０およびリードフレーム３０は、樹脂５０により封止されている。樹脂５０により、外部環境からの保護、絶縁性、放熱性および熱伝導性が適した状態が確保される。樹脂５０として、例えば、エポキシ樹脂等が用いられる。 As described above, except for the gate electrode 21, the divided source electrodes 22a and 22b of the semiconductor element 20, the other surface 45a of the lead frame 30, the mounting terminal surface 33a of each mounting terminal 33 and the cut surfaces 35a and 36a (see FIG. 1), The semiconductor element 20 and the lead frame 30 are sealed with resin 50. The resin 50 ensures a state in which protection from the external environment, insulation, heat dissipation and thermal conductivity are suitable. As the resin 50, for example, an epoxy resin or the like is used.
　既に説明した通り、図３にも図示されるように、各実装端子３３の実装端子面３３ａと樹脂５０の一面５１とは面一である。また、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３は、実装端子面３３ａおよび樹脂５０の一面５１よりも突出している。ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３が、樹脂５０の一面５１より突出する突出量Δｈは、例えば、０．０１ｍｍ～０．０５ｍｍ程度が好ましい。但し、この数値は、突出量Δｈを、この範囲に特定することを意図するものでは無く、一例として示したに過ぎない。図１の矢印ＤＡ方向からみて、すなわち列接続部３６の切断面３６ａを正面とする方向からみて、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３が、樹脂５０の一面５１より凹んでおらず、突出していることが測定顕微鏡で確認できる構成であればよい。 As described above, as shown in FIG. 3, the mounting terminal surface 33a of each mounting terminal 33 and the one surface 51 of the resin 50 are flush with each other. Further, the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are projected more than the mounting terminal surface 33 a and the one surface 51 of the resin 50. The amount Δh of protrusion of the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 from the one surface 51 of the resin 50 is preferably about 0.01 mm to 0.05 mm, for example. However, this numerical value is not intended to specify the protrusion amount Δh in this range, but is shown only as an example. The mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are the one surface 51 of the resin 50 when viewed from the direction of the arrow DA in FIG. 1, that is, the direction in which the cut surface 36 a of the column connection portion 36 is the front surface. It may be any structure as long as it can be confirmed with a measuring microscope that the protrusion is not recessed.
　半導体装置１０は、図３に図示されるように、ゲート電極２１の実装用表面２１ａ、ソース電極２２の実装用表面２３およびリードフレーム３０の実装端子面３３ａを下方に向けた状態で、ゲート電極２１の実装用表面２１ａ、ソース電極２２の実装用表面２３およびリードフレーム３０の実装端子面３３ａが、それぞれ、不図示の回路基板の各接続パッドに、はんだ等の接合材により接合される。リードフレーム３０の実装端子面３３ａは、４つのコーナー部に形成されている。このため、リードフレーム３０の行方向Ｄｒに離間して対向する一対の側部それぞれに１つずつ実装端子面３３ａを形成する構造に比し、接合後のリードフレーム３０の変形を抑制し、実装の精度を上げることができる。 As shown in FIG. 3, the semiconductor device 10 is configured such that the mounting surface 21a of the gate electrode 21, the mounting surface 23 of the source electrode 22 and the mounting terminal surface 33a of the lead frame 30 are directed downward. The mounting surface 21a of 21, the mounting surface 23 of the source electrode 22, and the mounting terminal surface 33a of the lead frame 30 are bonded to the respective connection pads of the circuit board (not shown) by a bonding material such as solder. The mounting terminal surface 33a of the lead frame 30 is formed at four corners. Therefore, as compared with a structure in which one mounting terminal surface 33a is formed on each of a pair of side portions that face each other while being separated in the row direction Dr of the lead frame 30, deformation of the lead frame 30 after bonding is suppressed, and mounting is performed. The accuracy of can be improved.
　また、ソース電極２２は、２つの分割ソース電極２２ａ、２２ｂに分割されている。ソース電極２２を分割せず１つとする構造とすると、はんだ量が多くなり、はんだ収縮時にリードフレーム３０が変形され易くなる。ソース電極２２を２つの分割ソース電極２２ａ、２２ｂに分割することにより、はんだ量が均一となり、はんだ収縮時のリードフレーム３０の変形を抑制することができる。 Also, the source electrode 22 is divided into two divided source electrodes 22a and 22b. If the structure in which the source electrode 22 is not divided but made into one is used, the amount of solder increases, and the lead frame 30 is easily deformed when the solder contracts. By dividing the source electrode 22 into the two divided source electrodes 22a and 22b, the amount of solder becomes uniform and the deformation of the lead frame 30 at the time of contraction of solder can be suppressed.
　なお、実装端子面３３ａは、４つに分割した構造として例示したが、実装端子面３３ａは、３つ以内または５つ以上設けてもよい。実装端子面３３ａの数を奇数とする場合、一方の側部側と他方の側部側とに設ける実装端子面３３ａの数を異ならせる。また、ソース電極２２は、３つ以上の分割ソース電極として構成するようにしてもよい。 Although the mounting terminal surface 33a is exemplified as a structure divided into four, the mounting terminal surface 33a may be provided within three or five or more. When the number of mounting terminal surfaces 33a is odd, the number of mounting terminal surfaces 33a provided on one side and the other side is different. Further, the source electrode 22 may be configured as three or more divided source electrodes.
　次に、本実施形態の半導体装置１０の製造方法の一例を示す。図５（Ａ）～５（Ｅ）は、本実施形態の半導体装置の製造方法を説明するための各工程における半導体装置の断面図であり、図６（Ａ）～６（Ｄ）は、図５に続く各工程における半導体装置の断面図であり、図７（Ａ）～７（Ｄ）は、図６に続く各工程における半導体装置の断面図である。なお、以下の説明では、２つの半導体装置１０を形成する製造方法として例示する。しかし、この製造方法は、１つの半導体装置１０を形成する場合および３つ以上の半導体装置１０を形成する場合にも適用することができる。 Next, an example of a method of manufacturing the semiconductor device 10 of this embodiment will be shown. 5A to 5E are cross-sectional views of the semiconductor device in each step for explaining the method of manufacturing the semiconductor device according to the present embodiment, and FIGS. 6A to 6D are diagrams. 5A to 5D are cross-sectional views of the semiconductor device in each step following FIG. 5, and FIGS. 7A to 7D are cross-sectional views of the semiconductor device in each step following FIG. In the following description, a manufacturing method for forming the two semiconductor devices 10 will be exemplified. However, this manufacturing method can also be applied to the case of forming one semiconductor device 10 and the case of forming three or more semiconductor devices 10.
　先ず、行方向Ｄｒ（図５の左右方向）に隣接する２つの半導体素子形成領域Ａ１、Ａ２を有するウエハ２０ｗを準備し、各半導体素子形成領域Ａ１、Ａ２に、ゲート電極２１、ソース電極２２を形成する。また、ウエハ２０ｗの底面全面にドレイン電極２４を形成する。そして、ドレイン電極２４に、バックメタル４１を形成する。バックメタル４１は、ウエハ２０ｗの底面の抵抗を下げるために設けるものであり、例えば、金の一層構造としたり、チタン（下層）・ニッケル（中間層）・金（表面層）等の複数層構造としたりすることができる。バックメタル４１は、スパッタや、めっき等により形成することができる（図５（Ａ）参照）。 First, a wafer 20w having two semiconductor element forming regions A1 and A2 adjacent to each other in the row direction Dr (left and right direction in FIG. 5) is prepared, and a gate electrode 21 and a source electrode 22 are provided in each semiconductor element forming region A1 and A2. Form. Further, the drain electrode 24 is formed on the entire bottom surface of the wafer 20w. Then, the back metal 41 is formed on the drain electrode 24. The back metal 41 is provided to reduce the resistance of the bottom surface of the wafer 20w. For example, the back metal 41 has a single layer structure of gold, or a multi-layer structure of titanium (lower layer), nickel (intermediate layer), gold (surface layer), and the like. You can The back metal 41 can be formed by sputtering, plating, or the like (see FIG. 5A).
　一方、行方向Ｄｒに互いに接続された２つの半導体装置形成領域Ｂ１、Ｂ２を有するリードフレーム材３０Ｍを準備する。リードフレーム材３０Ｍは、図５（Ｂ）に二点鎖線Ｌ１で示すように、例えば、厚さ０．３ｍｍ～０．７ｍｍ程度の平坦な板状部材である。そして、リードフレーム材３０Ｍの一面４４側からハーフエッチングして、収容部３１を形成する。収容部３１を形成するためのハーフエッチングは、側壁３２の内側領域を除去するのみでなく、図２に図示される４つの実装端子３３が形成されるように、列方向Ｄｃ（図５の紙面に垂直方向）の実装端子３３間も除去する。但し、この時点では、各実装端子３３の行接続部３５および列接続部３６は、実装端子本体３４と同じ厚さを有している。 Meanwhile, a lead frame material 30M having two semiconductor device formation regions B1 and B2 connected to each other in the row direction Dr is prepared. The lead frame material 30M is a flat plate member having a thickness of, for example, about 0.3 mm to 0.7 mm, as indicated by a chain double-dashed line L1 in FIG. 5B. Then, half-etching is performed from the one surface 44 side of the lead frame material 30M to form the accommodation portion 31. The half etching for forming the accommodating portion 31 not only removes the inner region of the side wall 32 but also forms the four mounting terminals 33 illustrated in FIG. 2 in the column direction Dc (in the plane of FIG. 5). Also, the space between the mounting terminals 33 in the vertical direction) is removed. However, at this point, the row connection portion 35 and the column connection portion 36 of each mounting terminal 33 have the same thickness as the mounting terminal body 34.
　次に、リードフレーム材３０Ｍを一面４４に対向する他面４５ａ側からハーフエッチングして溝４７を形成する。図２に図示されるように、溝４７は、各半導体装置形成領域Ｂ１、Ｂ２の各収容部３１の周囲の４辺に形成する。これにより、各実装端子３３の行接続部３５および列接続部３６の厚さは、実装端子本体３４より薄くなる。この状態では、半導体装置形成領域Ｂ１および半導体装置形成領域Ｂ２の境界部側にそれぞれが有する実装端子３３の行接続部３５は互いに接続され、したがって半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ２とは一体的に連結されている。 Next, the lead frame material 30M is half-etched from the other surface 45a side facing the one surface 44 to form the groove 47. As shown in FIG. 2, the groove 47 is formed on the four sides around each accommodation portion 31 in each of the semiconductor device formation regions B1 and B2. As a result, the thickness of the row connection portion 35 and the column connection portion 36 of each mounting terminal 33 is smaller than that of the mounting terminal body 34. In this state, the row connection portions 35 of the mounting terminals 33 provided on the boundary side of the semiconductor device formation region B1 and the semiconductor device formation region B2 are connected to each other, and therefore the semiconductor device formation region B1 and the semiconductor device formation region B2 are separated from each other. They are connected together.
　リードフレーム材３０Ｍのハーフエッチングは、収容部３１の底部４５、実装端子３３の行接続部３５および列接続部３６のそれぞれの厚さが、エッチング前のリードフレーム材３０Ｍの全厚の３０～５０％程度になるように行う。収容部３１の底部４５、実装端子３３の行接続部３５および列接続部３６の厚さは、同一であってもよいし、それぞれ、異なっていてもよい。 In the half etching of the lead frame material 30M, the thickness of each of the bottom portion 45 of the accommodating portion 31, the row connecting portion 35 and the column connecting portion 36 of the mounting terminal 33 is 30 to 50 of the total thickness of the lead frame material 30M before etching. Perform it so that it becomes about %. The bottom portion 45 of the housing portion 31, the row connection portion 35 and the column connection portion 36 of the mounting terminal 33 may have the same thickness or different thicknesses.
　図５（Ｃ）に図示されるように、リードフレーム材３０Ｍの一面４４に対向する他面４５ａには、バックテープ６２を貼り付けておく。バックテープ６２は、モールド成型の際、樹脂材５０Ｍ（図６（Ｂ）参照）が、リードフレーム３０の他面４５ａ側に漏出するのを抑制するための部材である。 As illustrated in FIG. 5C, a back tape 62 is attached to the other surface 45a that faces the one surface 44 of the lead frame material 30M. The back tape 62 is a member for preventing the resin material 50M (see FIG. 6B) from leaking to the other surface 45a side of the lead frame 30 during molding.
　次に、図５（Ａ）に図示されるウエハ２０ｗの底面側に形成されたバックメタル４１をダイシングテープ６３に貼り付ける（図５（Ｄ）参照）。 Next, the back metal 41 formed on the bottom surface side of the wafer 20w shown in FIG. 5A is attached to the dicing tape 63 (see FIG. 5D).
　そして、図５（Ｅ）に図示されるように、半導体素子形成領域Ａ１と半導体素子成領域Ａ２との境界で、ウエハ２０ｗをダイシングし、半導体素子形成領域Ａ１と半導体素子形成領域Ａ２とを分離する。これにより、半導体素子形成領域Ａ１および半導体素子形成領域Ａ２には、それぞれ、半導体素子２０が形成される。半導体素子形成領域Ａ１と半導体素子形成領域Ａ２とのダイシングは、ダイシングテープ６３の厚さの中間まで行う。 Then, as shown in FIG. 5E, the wafer 20w is diced at the boundary between the semiconductor element forming area A1 and the semiconductor element forming area A2 to separate the semiconductor element forming area A1 and the semiconductor element forming area A2. To do. As a result, the semiconductor element 20 is formed in each of the semiconductor element forming area A1 and the semiconductor element forming area A2. The dicing between the semiconductor element forming area A1 and the semiconductor element forming area A2 is performed up to the middle of the thickness of the dicing tape 63.
　次に、図６（Ａ）に示すように、リードフレーム材３０Ｍの半導体装置形成領域Ｂ１、Ｂ２それぞれの収容部３１の底面３１ａに銀ペースト等の導電接合材４２をポッティングする。そして、ピックアップ装置等を用いて各半導体素子２０をダイシングテープ６３からピックアップし、半導体素子２０を、導電接合材４２を介してリードフレーム材３０Ｍの半導体装置形成領域Ｂ１、Ｂ２それぞれの収容部３１の底面３１ａにダイボンディングする（図６（Ａ）参照）。これにより、リードフレーム材３０Ｍの半導体装置形成領域Ｂ１、Ｂ２それぞれに半導体素子２０がダイボンディングされた中間半導体装置集合体１００Ａが形成される。 Next, as shown in FIG. 6A, a conductive bonding material 42 such as a silver paste is potted on the bottom surface 31a of the accommodating portion 31 of each of the semiconductor device forming regions B1 and B2 of the lead frame material 30M. Then, each semiconductor element 20 is picked up from the dicing tape 63 by using a pick-up device or the like, and the semiconductor element 20 is inserted into the accommodating portions 31 of the semiconductor device forming regions B1 and B2 of the lead frame material 30M via the conductive bonding material 42. Die bonding is performed on the bottom surface 31a (see FIG. 6A). As a result, an intermediate semiconductor device assembly 100A in which the semiconductor element 20 is die-bonded to each of the semiconductor device formation regions B1 and B2 of the lead frame material 30M is formed.
　この後、中間半導体装置集合体１００Ａを、図６（Ｂ）に図示されるように、金型７１のキャビティ内に収容して、樹脂材５０Ｍを注入する。金型７１の上型７２の内面には、中間半導体装置集合体１００Ａを収容する前に、弾性を有する離型フィルム６４を配置しておく。金型７１のキャビティ内に中間半導体装置集合体１００Ａを収容して、上型７２と下型７３を型締めすると、リードフレーム材３０Ｍの各実装端子面３３ａが離型フィルム６４の表面６４ａに当接する。また、各半導体素子２０のゲート電極２１およびソース電極２２の実装端子面３３ａより突出する部分は、離型フィルム６４内に埋没する。このため、金型７１のキャビティ内に注入された樹脂材５０Ｍが、各半導体素子２０のゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３の周縁部に漏出するのが抑制される。また、上述したように、中間半導体装置集合体１００Ａには、バックテープ６２が貼り付けられているため、樹脂材５０Ｍがリードフレーム材３０Ｍの他面４５ａ側に漏出するのが抑制される。樹脂材５０Ｍの注入により、リードフレーム材３０Ｍの収容部３１内および各溝４７内には、樹脂材５０Ｍが充填される。 Thereafter, as shown in FIG. 6B, the intermediate semiconductor device assembly 100A is housed in the cavity of the mold 71, and the resin material 50M is injected. A release film 64 having elasticity is arranged on the inner surface of the upper mold 72 of the mold 71 before housing the intermediate semiconductor device assembly 100A. When the intermediate semiconductor device assembly 100A is housed in the cavity of the mold 71 and the upper mold 72 and the lower mold 73 are clamped, each mounting terminal surface 33a of the lead frame material 30M contacts the surface 64a of the release film 64. Contact. Further, the portions of the semiconductor element 20 that project from the mounting terminal surface 33 a of the gate electrode 21 and the source electrode 22 are buried in the release film 64. Therefore, the resin material 50M injected into the cavity of the mold 71 is suppressed from leaking to the peripheral portions of the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 of each semiconductor element 20. It Further, as described above, since the back tape 62 is attached to the intermediate semiconductor device assembly 100A, the resin material 50M is prevented from leaking to the other surface 45a side of the lead frame material 30M. By injecting the resin material 50M, the resin material 50M is filled in the housing portion 31 of the lead frame material 30M and each groove 47.
　この後、金型７１内に注入された樹脂材５０Ｍを硬化して、図６（Ｃ）に図示されるように、各半導体素子２０が樹脂５０により封止された、封止済の中間半導体装置集合体１００Ｂをバックテープ６２と共に金型７１から取り出す。 Thereafter, the resin material 50M injected into the mold 71 is cured, and each semiconductor element 20 is sealed with the resin 50, as shown in FIG. 6C. The device assembly 100B is taken out from the mold 71 together with the back tape 62.
　そして、図６（Ｄ）に図示されるように、封止済の半導体装置集合体１００Ｂからバックテープ６２を除去する。 Then, as illustrated in FIG. 6D, the back tape 62 is removed from the sealed semiconductor device assembly 100B.
　次に、封止済の半導体装置集合体１００Ｂの他面４５ａに、製品番号、ロット番号等を図７（Ａ）の矢印ＤＢ方向からレーザーによりマーキングし、封止済の半導体装置集合体１００Ｂの他面４５ａをダイシングテープ６５に貼り付ける（図７（Ｂ）参照）。 Next, a product number, a lot number, etc. are marked on the other surface 45a of the sealed semiconductor device assembly 100B from the direction of the arrow DB in FIG. The other surface 45a is attached to the dicing tape 65 (see FIG. 7B).
　そして、図７（Ｃ）に図示されるように、封止済の半導体装置集合体１００Ｂの、リードフレーム材３０Ｍの各実装端子３３および樹脂５０を切断して個々の半導体装置１０とする。但し、この段階では、封止済の半導体装置集合体１００Ｂの切断は、ダイシングテープ６５の厚さの中間まで行ない、各半導体装置１０は、ダイシングテープ６５に貼り付けたままの状態としておく。 Then, as shown in FIG. 7C, each mounting terminal 33 of the lead frame material 30M and the resin 50 of the sealed semiconductor device assembly 100B are cut into individual semiconductor devices 10. However, at this stage, the sealed semiconductor device assembly 100B is cut to the middle of the thickness of the dicing tape 65, and each semiconductor device 10 is left attached to the dicing tape 65.
　図８は、図７（Ｃ）に示された半導体装置を上方からみた平面図である。但し、図８では、行方向Ｄｒおよび列方向Ｄｃそれぞれに２つずつ配列された、合計４つの半導体装置形成領域Ｂ１～Ｂ４を有する封止済の半導体装置集合体１００Ｃとして図示されている。なお、行方向Ｄｒは半導体装置形成領域Ｂ１とＢ２との並び方向、列方向Ｄｃは半導体装置形成領域Ｂ１とＢ３との並び方向である。行方向Ｄｒに隣接する半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ２との互いの行接続部３５同士が連結され、半導体装置形成領域Ｂ３と半導体装置形成領域Ｂ４との互いの行接続部３５同士が連結され、さらに、列方向Ｄｃに隣接する半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ３との互いの列接続部３６同士が連結され、半導体装置形成領域Ｂ２と半導体装置形成領域Ｂ４との互いの列接続部３６同士が連結されている。こうして互いに接続される４つの半導体装置形成領域Ｂ１～Ｂ４の全体が１つの部材としてリードフレーム材３０Ｍが形成されている。 FIG. 8 is a plan view of the semiconductor device shown in FIG. 7C as seen from above. However, in FIG. 8, it is illustrated as a sealed semiconductor device assembly 100C having a total of four semiconductor device forming regions B1 to B4, each of which is arranged in the row direction Dr and the column direction Dc. The row direction Dr is the alignment direction of the semiconductor device formation regions B1 and B2, and the column direction Dc is the alignment direction of the semiconductor device formation regions B1 and B3. Row connection parts 35 of the semiconductor device formation region B1 and the semiconductor device formation region B2 adjacent to each other in the row direction Dr are connected to each other, and row connection parts 35 of the semiconductor device formation region B3 and the semiconductor device formation region B4 are connected to each other. And the column connecting portions 36 of the semiconductor device forming region B1 and the semiconductor device forming region B3 adjacent to each other in the column direction Dc are connected to each other, and the semiconductor device forming region B2 and the semiconductor device forming region B4 are connected to each other. The column connecting portions 36 are connected to each other. The four semiconductor device forming regions B1 to B4 connected to each other in this manner form the lead frame material 30M as one member.
　図８に図示された封止済の半導体装置集合体１００Ｃを、二点鎖線に示す行切断線８１および列切断線８２で切断する。すなわち、行方向Ｄｒに隣接する半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ２、および半導体装置形成領域Ｂ３と半導体装置形成領域Ｂ４の行接続部３５同士を連結する連結部分を列切断線８２ｂで切断する。また、列方向Ｄｃに隣接する半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ３、および半導体装置形成領域Ｂ２と半導体装置形成領域Ｂ４の列接続部３６同士を連結する連結部分を行切断線８１ｂで切断する。さらに、半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ３の行接続部３５のうち、半導体装置集合体１００Ｃの行方向Ｄｒに位置する１対の短辺の一辺側に配列された行接続部３５を列切断線８２ｃで切断し、半導体装置形成領域Ｂ２と半導体装置形成領域Ｂ４の行接続部３５のうち、半導体装置集合体１００Ｃの行方向Ｄｒに位置する１対の短辺の他辺側に配列された行接続部３５を列切断線８２ａで切断する。また、半導体装置形成領域Ｂ１と半導体装置形成領域Ｂ２の列方向Ｄｃの列接続部３６のうち、半導体装置集合体１００Ｃの列方向Ｄｃに位置する１対の長辺の一辺側に配列された列接続部３６を行切断線８１ａで切断し、半導体装置形成領域Ｂ３と半導体装置形成領域Ｂ４の列方向Ｄｃの列接続部３６のうち、半導体装置集合体１００Ｃの列方向Ｄｃに位置する１対の長辺の他辺側に配列された列接続部３６を行切断線８１ｃで切断する。これにより、封止済の半導体装置集合体１００Ｃの半導体装置形成領域Ｂ１～Ｂ４がそれぞれ個々に分離され、個々の半導体装置１０が得られる。 The sealed semiconductor device assembly 100C shown in FIG. 8 is cut along a line cutting line 81 and a column cutting line 82 indicated by a chain double-dashed line. That is, the connection portions that connect the row connection portions 35 of the semiconductor device formation region B1 and the semiconductor device formation region B2, and the semiconductor device formation region B3 and the semiconductor device formation region B4 that are adjacent to each other in the row direction Dr are cut along the column cutting line 82b. To do. In addition, a connection portion that connects the column connection portions 36 of the semiconductor device formation region B1 and the semiconductor device formation region B3, and the semiconductor device formation region B2 and the semiconductor device formation region B4 that are adjacent to each other in the column direction Dc is cut along the line cutting line 81b. To do. Further, among the row connection portions 35 of the semiconductor device formation region B1 and the semiconductor device formation region B3, the row connection portions 35 arranged on one side of a pair of short sides located in the row direction Dr of the semiconductor device assembly 100C are arranged. It is cut along the column cutting line 82c and is arranged on the other side of the pair of short sides located in the row direction Dr of the semiconductor device assembly 100C among the row connection portions 35 of the semiconductor device forming region B2 and the semiconductor device forming region B4. The row connection portion 35 thus cut is cut along the column cutting line 82a. Further, among the column connection portions 36 in the column direction Dc of the semiconductor device formation region B1 and the semiconductor device formation region B2, the columns arranged on one side of the pair of long sides located in the column direction Dc of the semiconductor device assembly 100C. The connection portion 36 is cut along the row cutting line 81a, and a pair of the column connection portions 36 in the column direction Dc of the semiconductor device formation region B3 and the semiconductor device formation region B4 are located in the column direction Dc of the semiconductor device assembly 100C. The column connecting portion 36 arranged on the other side of the long side is cut along the row cutting line 81c. As a result, the semiconductor device forming regions B1 to B4 of the sealed semiconductor device aggregate 100C are individually separated, and the individual semiconductor devices 10 are obtained.
　なお、上記では、半導体装置形成領域Ｂ１～Ｂ４が２行×２列に配列された半導体装置集合体１００Ｃとして例示したが、半導体装置集合体１００Ｃは、行方向Ｄｒおよび列方向Ｄｃに、それぞれ、１以上の任意な数の半導体装置形成領域が配列されたものとすることができる。 In the above description, the semiconductor device forming regions B1 to B4 are exemplified as the semiconductor device aggregate 100C arranged in 2 rows×2 columns, but the semiconductor device aggregate 100C is arranged in the row direction Dr and the column direction Dc, respectively. Any number of semiconductor device formation regions of 1 or more may be arranged.
　このようにして、封止済の半導体装置集合体１００Ｃを個々の半導体装置１０に分離した後は、必要に応じて、個々の半導体装置１０に対してファンクションテストを行なう。そして、図７（Ｄ）に示されるように、不図示のピックアップ装置等を用いて、良品または良否の判定マーキングがされた半導体装置１０をピックアップし、所定の格納部（図示せず）に格納する。 After separating the sealed semiconductor device assembly 100C into individual semiconductor devices 10 in this manner, a function test is performed on each semiconductor device 10 as necessary. Then, as shown in FIG. 7D, a semiconductor device 10 marked with a good or bad mark is picked up by using a pickup device or the like (not shown) and stored in a predetermined storage portion (not shown). To do.
　上記第１の実施形態における半導体装置１０は、下記の効果を奏する。
（１）半導体装置１０は、ゲート電極２１またはソース電極２２ならびにドレイン電極２４を有する半導体素子２０と、ドレイン電極２４に接続され、半導体素子２０を収容する収容部３１および収容部３１の外周に形成された少なくとも一つの実装端子３３を有する端子板であるリードフレーム３０と、リードフレーム３０の収容部３１に収容された半導体素子２０を、ゲート電極２１およびソース電極２２を露出させて封止する樹脂５０とを備える。ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３は、半導体素子２０を封止する樹脂５０の一面５１より突出している。このため、実装用表面２１ａ、２３の外周縁に半導体素子２０を封止する樹脂５０が漏出してそこに樹脂５０のバリが形成されるのを抑制することができる。これにより、半導体素子２０のゲート電極２１またはソース電極２２を回路基板の接続パッドに接合する際、接合強度の低下や、導通不良の発生を防止することができる。 The semiconductor device 10 according to the first embodiment has the following effects.
(1) The semiconductor device 10 is formed on the semiconductor element 20 having the gate electrode 21 or the source electrode 22 and the drain electrode 24, and the housing portion 31 for housing the semiconductor element 20 and the outer circumference of the housing portion 31, which is connected to the drain electrode 24. A resin that seals the lead frame 30 which is a terminal plate having at least one mounted terminal 33 and the semiconductor element 20 accommodated in the accommodating portion 31 of the lead frame 30 by exposing the gate electrode 21 and the source electrode 22. And 50. The mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 project from one surface 51 of the resin 50 that seals the semiconductor element 20. Therefore, it is possible to prevent the resin 50 that seals the semiconductor element 20 from leaking to the outer peripheral edges of the mounting surfaces 21a and 23 and forming a burr of the resin 50 there. As a result, when the gate electrode 21 or the source electrode 22 of the semiconductor element 20 is bonded to the connection pad of the circuit board, it is possible to prevent a decrease in the bonding strength and the occurrence of conduction failure.
（２）半導体装置１０に含まれるリードフレーム３０に設けられた収容部３１の外周のうちの一辺側およびその一辺側に対向する対向辺側にそれぞれ、複数の実装端子３３が設けられている。このため、リードフレーム３０に設けられた収容部３１の外周のうちの一辺側および対向辺側それぞれに１つずつ実装端子３３を形成する構造に比し、各実装端子３３の実装端子面３３ａ一箇所あたりのはんだ接合面積が小さくなり、それにより、はんだ過多による基板実装時のはんだの熱収縮による応力が減少する。このため、リードフレーム３０の変形を抑制し、樹脂５０から突出しているゲート電極２１、ソース電極２２にかかる負荷を低減することができる。また、行接続部３５は実装端子本体３３より、薄く、幅を狭く形成しているため、列切断時の負荷を低減することが出来る。 (2) A plurality of mounting terminals 33 are provided on one side of the outer circumference of the housing 31 provided in the lead frame 30 included in the semiconductor device 10 and on the opposite side facing the one side. Therefore, as compared with the structure in which the mounting terminal 33 is formed on each of the one side and the opposite side of the outer periphery of the accommodating portion 31 provided in the lead frame 30, the mounting terminal surface 33 a of each mounting terminal 33 is formed. The solder joint area per location is reduced, and as a result, the stress due to thermal contraction of the solder at the time of board mounting due to excess solder is reduced. Therefore, the deformation of the lead frame 30 can be suppressed, and the load applied to the gate electrode 21 and the source electrode 22 protruding from the resin 50 can be reduced. Further, since the row connection portion 35 is formed to be thinner and narrower than the mounting terminal body 33, it is possible to reduce the load when cutting the column.
（３）本実施形態における半導体装置１０は、実装用表面２１ａ、２３がΔｈだけ樹脂５０の一面５１から突出している構造を有する。不図示の回路基板の各接続パッドに実装用表面２１ａおよび２３が接合された実装状態において、ソース電極２２を分割ソース電極２２ａ、２２ｂとしたり、リードフレーム３０の実装端子３３の数を４つにしたりして、はんだ接合部箇所を増加することにより、はんだ応力が分散された構造が得られる。このため、ゲート電極２１およびソース電極２２にかかる応力を軽減することができる。 (3) The semiconductor device 10 according to the present embodiment has a structure in which the mounting surfaces 21a and 23 project from the one surface 51 of the resin 50 by Δh. In the mounted state where the mounting surfaces 21a and 23 are joined to the respective connection pads of the circuit board (not shown), the source electrode 22 is divided source electrodes 22a and 22b, or the number of the mounting terminals 33 of the lead frame 30 is set to four. By increasing the number of solder joints, a structure in which solder stress is dispersed can be obtained. Therefore, the stress applied to the gate electrode 21 and the source electrode 22 can be reduced.
（４）半導体装置１０のリードフレーム３０の収容部３１は、エッチングにより形成される。このため、リードフレーム３０には、プレス加工により収容部が形成される場合に生じる残留応力は発生せず、各実装端子面３３ａ、実装用表面２１ａ、２３と回路基板の各接続パッドとの平行度を確保することができ、実装精度を向上することができる。 (4) The housing portion 31 of the lead frame 30 of the semiconductor device 10 is formed by etching. Therefore, no residual stress is generated in the lead frame 30 when the accommodating portion is formed by press working, and the mounting terminal surface 33a, the mounting surfaces 21a and 23, and the connection pads of the circuit board are parallel to each other. The degree of accuracy can be secured, and the mounting accuracy can be improved.
－第２の実施形態－
　図９は、本発明の第２の実施形態による半導体装置を示す断面図である。図９は、第１の実施形態の図３に相当する。第２の実施形態では、リードフレーム３０の実装端子３３の実装端子面３３ａは、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３と、面一になっている。 -Second Embodiment-
FIG. 9 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. FIG. 9 corresponds to FIG. 3 of the first embodiment. In the second embodiment, the mounting terminal surface 33a of the mounting terminal 33 of the lead frame 30 is flush with the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22.
　この第２の実施形態においても、第１の実施形態と同様、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３は、樹脂５０の一面５１より突出している。さらに実装端子３３の実装端子面３３ａも、樹脂５０の一面５１より突出している。このため、モールド成型時に、リードフレーム３０の実装端子３３の実装端子面３３ａ、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３を、離型フィルム６４内に埋没させた状態で、リードフレーム３０を樹脂５０で封止するための樹脂材５０Ｍを注入することができる。これにより、リードフレーム３０の実装端子３３の実装端子面３３ａ、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３に樹脂バリが形成されるのを抑制することができる。第２の実施形態の他の構成は、第１の実施形態と同様であり、対応する部材に同一の符号を付して説明を省略する。 Also in the second embodiment, as in the first embodiment, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are projected from one surface 51 of the resin 50. Further, the mounting terminal surface 33 a of the mounting terminal 33 also projects from the one surface 51 of the resin 50. Therefore, at the time of molding, the mounting terminal surface 33a of the mounting terminal 33 of the lead frame 30, the mounting surface 21a of the gate electrode 21, and the mounting surface 23 of the source electrode 22 are buried in the release film 64. The resin material 50M for sealing the lead frame 30 with the resin 50 can be injected. Accordingly, it is possible to suppress the formation of resin burrs on the mounting terminal surface 33a of the mounting terminal 33 of the lead frame 30, the mounting surface 21a of the gate electrode 21, and the mounting surface 23 of the source electrode 22. The other configurations of the second embodiment are similar to those of the first embodiment, and corresponding members are designated by the same reference numerals and description thereof is omitted.
　従って、第２の実施形態における半導体装置１０も、第１の実施形態と同様な効果（１）～（４）を奏する。また、第２の実施形態によれば、リードフレーム３０の実装端子３３の実装端子面３３ａにバリが形成されるのを抑制することができる。 Therefore, the semiconductor device 10 according to the second embodiment also exhibits the same effects (1) to (4) as those of the first embodiment. Further, according to the second embodiment, it is possible to suppress the formation of burrs on the mounting terminal surface 33a of the mounting terminal 33 of the lead frame 30.
－第３の実施形態－
　図１０は、本発明の第３の実施形態による半導体装置を示す下面図である。図１０は、第１の実施形態の図４（Ｂ）に相当する。第３の実施形態の半導体装置１０は、リードフレーム３０の列方向Ｄｃに互いに離間する一辺３７ａおよび一辺３７ａに対向する対向辺３７ｂのそれぞれに沿って形成された複数の側壁６６を有している。 -Third Embodiment-
FIG. 10 is a bottom view showing the semiconductor device according to the third embodiment of the present invention. FIG. 10 corresponds to FIG. 4B of the first embodiment. The semiconductor device 10 of the third embodiment has a plurality of side walls 66 formed along each of the side 37a and the facing side 37b facing the side 37a, which are separated from each other in the column direction Dc of the lead frame 30. ..
　第１の実施形態では、リードフレーム３０の収容部３１は、行方向Ｄｒに離間された一対の側壁３２間が列方向Ｄｃに延在された直線状の溝部として形成されていた。 In the first embodiment, the accommodating portion 31 of the lead frame 30 is formed as a linear groove portion that extends in the column direction Dc between the pair of side walls 32 that are separated in the row direction Dr.
　これに対し、第３の実施形態では、リードフレーム３０の収容部３１の行方向Ｄｒに延在する一辺３７ａおよび一辺３７ａに対向する対向辺３７ｂの各々に、複数（本実施形態では２つとして例示されている）の側壁６６が形成されている。一辺３７ａおよび対向辺３７ｂに設けられた複数の側壁６６は、モールド成型時に樹脂材５０Ｍが収容部３１内に注入されるように離間して設けられている。各側壁６６の端面は、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３と面一になっており、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３と共に、不図示の回路基板の接続パッドに接合される。但し、各側壁６６の端面を、回路基板の接続パッドに接合しない構造としてもよい。 On the other hand, in the third embodiment, each side 37a extending in the row direction Dr of the accommodating portion 31 of the lead frame 30 and each of the opposing sides 37b facing the side 37a have a plurality (two in this embodiment). A side wall 66 (as illustrated) is formed. The plurality of side walls 66 provided on the one side 37a and the opposite side 37b are provided so as to be spaced apart from each other so that the resin material 50M is injected into the housing portion 31 at the time of molding. The end surface of each sidewall 66 is flush with the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22, and together with the mounting surface 21 a of the gate electrode 21 and the mounting surface 23 of the source electrode 22. , Bonded to a connection pad of a circuit board (not shown). However, the end surface of each side wall 66 may not be joined to the connection pad of the circuit board.
　第３の実施形態における他の構成は、第１の実施形態と同様であり、ゲート電極２１の実装用表面２１ａおよびソース電極２２の実装用表面２３は、樹脂５０の一面５１よりも突出している。第３の実施形態のそれ以外の他の構成も第１の実施形態と同様であり、対応する部材に同一の符号を付して説明を省略する。 Other configurations in the third embodiment are similar to those in the first embodiment, and the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 are projected more than one surface 51 of the resin 50. .. The rest of the configuration of the third embodiment is similar to that of the first embodiment, and corresponding members are assigned the same reference numerals and explanations thereof are omitted.
　従って、第３の実施形態における半導体装置１０も、第１の実施形態と同様な効果（１）～（４）を奏する。また、第３の実施形態では、リードフレーム３０の収容部３１の、一辺３７ａと対向辺３７ｂとに側壁６６が設けられているため、半導体装置１０の列方向Ｄｃからの荷重や衝撃を吸収することができる。 Therefore, the semiconductor device 10 according to the third embodiment also exhibits the same effects (1) to (4) as those of the first embodiment. Further, in the third embodiment, since the side wall 66 is provided on the one side 37a and the opposite side 37b of the accommodating portion 31 of the lead frame 30, the load and impact of the semiconductor device 10 in the column direction Dc are absorbed. be able to.
－第４の実施形態－
　図１１は、本発明の第４の実施形態による半導体装置を示す下面図である。図１１は、第１の実施形態の図４（Ｂ）に相当する。図１１に示す半導体装置１０では、半導体素子２０は、ゲート電極２１Ｂ１、ソース電極２２Ｃ１およびドレイン電極２４Ａ１を有する第１の半導体素子領域２０Ａと、ゲート電極２１Ｂ２、ソース電極２２Ｃ２およびドレイン電極２４Ａ２を有する第２の半導体素子領域２０Ｂとを備えている。換言すれば、半導体素子２０は、２つの半導体素子領域を１つのディスクリート半導体チップとして形成することによって得られる。第４の実施形態においても、ゲート電極２１Ｂ１、２１Ｂ２の実装用表面２１ａ、およびソース電極２２Ｃ１、２２Ｃ２の実装用表面２３は、半導体素子２０を封止する樹脂５０の一面５１より突出している。第４の実施形態では、第１の半導体素子領域２０Ａのソース電極２２Ｃ１と、第２の半導体素子領域２０Ｂのソース電極２２Ｃ２とは、それぞれ、分割ソース電極ではなく、１つのソース電極として例示されている。但し、ソース電極２２Ｃ１、２２Ｃ２は、それぞれ、分割ソース電極としてもよい。 -Fourth Embodiment-
FIG. 11 is a bottom view showing the semiconductor device according to the fourth embodiment of the present invention. FIG. 11 corresponds to FIG. 4B of the first embodiment. In the semiconductor device 10 shown in FIG. 11, the semiconductor element 20 has a first semiconductor element region 20A having a gate electrode 21B1, a source electrode 22C1 and a drain electrode 24A1 and a first semiconductor element region 20A having a gate electrode 21B2, a source electrode 22C2 and a drain electrode 24A2. 2 semiconductor element regions 20B. In other words, the semiconductor element 20 is obtained by forming the two semiconductor element regions as one discrete semiconductor chip. Also in the fourth embodiment, the mounting surfaces 21a of the gate electrodes 21B1 and 21B2 and the mounting surfaces 23 of the source electrodes 22C1 and 22C2 project from the one surface 51 of the resin 50 that seals the semiconductor element 20. In the fourth embodiment, the source electrode 22C1 of the first semiconductor element region 20A and the source electrode 22C2 of the second semiconductor element region 20B are each exemplified as one source electrode instead of the divided source electrode. There is. However, the source electrodes 22C1 and 22C2 may be divided source electrodes, respectively.
　第４の実施形態の他の構成は、第１の実施形態と同様であり、対応する部材に同一の符号を付して説明を省略する。 The other configurations of the fourth embodiment are similar to those of the first embodiment, and corresponding members are designated by the same reference numerals and description thereof is omitted.
　従って、第４の実施形態における半導体装置１０も、第１の実施形態と同様な効果（１）～（４）を奏する。なお、第１の半導体素子領域２０Ａのドレイン電極２４Ａ１と第２の半導体素子領域２０Ｂのドレイン電極２４Ａ２を１つの共通のドレイン電極としてもよい。また、半導体素子２０は、３つ以上の半導体素子領域を有するものとしてもよい。 Therefore, the semiconductor device 10 according to the fourth embodiment also has the same effects (1) to (4) as those of the first embodiment. The drain electrode 24A1 of the first semiconductor element region 20A and the drain electrode 24A2 of the second semiconductor element region 20B may be one common drain electrode. Further, the semiconductor element 20 may have three or more semiconductor element regions.
－第５の実施形態－
　図１２は、本発明の第５の実施形態による半導体装置を示す下面図である。図１２は、第１の実施形態の図４（Ｂ）に相当する。第５の実施形態では、半導体装置１０は、リードフレーム３０の収容部３１内に、２つの半導体素子２０が収容された構造を有する。また、リードフレーム３０の実装端子３３は、半導体装置１０の一対の短辺に、それぞれ、１つずつ設けられている。２つの半導体素子２０は、行方向Ｄｒに離間して配列されており、各実装端子３３の長さは、リードフレーム３０の列方向Ｄｃの長さとほぼ同じである。 -Fifth Embodiment-
FIG. 12 is a bottom view showing a semiconductor device according to the fifth embodiment of the present invention. FIG. 12 corresponds to FIG. 4B of the first embodiment. In the fifth embodiment, the semiconductor device 10 has a structure in which two semiconductor elements 20 are housed in the housing portion 31 of the lead frame 30. Further, the mounting terminals 33 of the lead frame 30 are provided on the pair of short sides of the semiconductor device 10 one by one. The two semiconductor elements 20 are arranged separately in the row direction Dr, and the length of each mounting terminal 33 is almost the same as the length of the lead frame 30 in the column direction Dc.
　第５の実施形態においても、ゲート電極２１の実装用表面２１ａ、分割ソース電極２２ａ、２２ｂの実装用表面２３は、２つの半導体素子２０を封止する樹脂５０の一面５１より突出している。また、各リードフレーム３０の実装端子３３の実装端子面３３ａは、樹脂５０の一面５１と面一になっている。各リードフレーム３０の実装端子３３の実装端子面３３ａを、ゲート電極２１の実装用表面２１ａ、分割ソース電極２２ａ、２２ｂの実装用表面２３と面一にしてもよい。 Also in the fifth embodiment, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b project from one surface 51 of the resin 50 that seals the two semiconductor elements 20. The mounting terminal surface 33 a of the mounting terminal 33 of each lead frame 30 is flush with the one surface 51 of the resin 50. The mounting terminal surface 33a of the mounting terminal 33 of each lead frame 30 may be flush with the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b.
　第５の実施形態の他の構成は、第１の実施形態と同様であり、対応する部材に同一の符号を付して説明を省略する。 The other configurations of the fifth embodiment are similar to those of the first embodiment, and corresponding members are designated by the same reference numerals and the description thereof will be omitted.
　従って、第５の実施形態における半導体装置１０も、第１の実施形態と同様な効果（１）、（２）、（４）を奏する。また、第５の実施形態では、リードフレーム３０の実装端子３３の数は、第１の実施形態の実装端子３３の数より少ないが、ソース電極２２を分割ソース電極２２ａ、２２ｂとしているので、第１の実施形態の効果（３）に近い効果を奏する。 Therefore, the semiconductor device 10 according to the fifth embodiment also exhibits the same effects (1), (2), and (4) as those of the first embodiment. Further, in the fifth embodiment, the number of mounting terminals 33 of the lead frame 30 is smaller than that of the mounting terminals 33 of the first embodiment, but the source electrode 22 is divided source electrodes 22a and 22b. An effect close to the effect (3) of the first embodiment is achieved.
　なお、第５の実施形態において、リードフレーム３０の収容部３１内に、３つ以上の半導体素子２０が収容されるようにしてもよい。また、実装端子面３３ａは、一対の短辺に一つずつ設けられるのではなく、分割された複数の端子面が形成されるように設けられることとしても良い。 Incidentally, in the fifth embodiment, three or more semiconductor elements 20 may be housed in the housing portion 31 of the lead frame 30. Further, the mounting terminal surfaces 33a may be provided so as to form a plurality of divided terminal surfaces instead of being provided one by one on the pair of short sides.
－第６の実施形態－
　図１３は、本発明の第６の実施形態における半導体装置を示す下面図である。図１３は、第１の実施形態の図４（Ｂ）に相当する。第６の実施形態では、半導体装置１０のリードフレーム３０は、３つの半導体装置領域１０ａ、１０ｂおよび１０ｃが列連結部３８で連結されて一体化された構造を有する。３つの半導体装置領域１０ａ、１０ｂおよび１０ｃは、１つの半導体素子２０が収容された収容部３１を、それぞれ有する。 -Sixth Embodiment-
FIG. 13 is a bottom view showing a semiconductor device according to the sixth embodiment of the present invention. FIG. 13 corresponds to FIG. 4B of the first embodiment. In the sixth embodiment, the lead frame 30 of the semiconductor device 10 has a structure in which three semiconductor device regions 10a, 10b and 10c are connected by a column connecting portion 38 and integrated. Each of the three semiconductor device regions 10a, 10b, and 10c has an accommodating portion 31 in which one semiconductor element 20 is accommodated.
　半導体装置領域１０ａ、１０ｂおよび１０ｃの各々は、収容部３１をそれぞれ有するリードフレーム部３０ａ、３０ｂおよび３０ｃの各々と、収容部３１内に収容された１つの半導体素子２０とを有する。半導体素子２０は、ゲート電極２１と分割ソース電極２２ａ、２２ｂとを有する。リードフレーム３０は、実装端子３３をそれぞれ有するリードフレーム部３０ａ、３０ｂおよび３０ｃと、リードフレーム部どうしを連結する列連結部３８とを有する。列連結部３８は、リードフレーム部３０ａとリードフレーム部３０ｂとを連結し、リードフレーム部３０ｂとリードフレーム部３０ｃとを連結する。実装端子３３は、リードフレーム部３０ａ、３０ｂおよび３０ｃの各々の一対の短辺に、それぞれ、１つずつ設けられている。各実装端子３３の長さは、リードフレーム部３０ａ、３０ｂおよび３０ｃの各々の列方向Ｄｃの長さとほぼ同じである。 Each of the semiconductor device regions 10 a, 10 b, and 10 c has each of the lead frame portions 30 a, 30 b, and 30 c each having the accommodation portion 31, and one semiconductor element 20 accommodated in the accommodation portion 31. The semiconductor element 20 has a gate electrode 21 and divided source electrodes 22a and 22b. The lead frame 30 has lead frame portions 30a, 30b, and 30c each having a mounting terminal 33, and a column connecting portion 38 that connects the lead frame portions. The column connecting portion 38 connects the lead frame portion 30a and the lead frame portion 30b, and connects the lead frame portion 30b and the lead frame portion 30c. One mounting terminal 33 is provided on each of the pair of short sides of each of the lead frame portions 30a, 30b, and 30c. The length of each mounting terminal 33 is substantially the same as the length of each of the lead frame portions 30a, 30b, and 30c in the column direction Dc.
　第６の実施形態においても、ゲート電極２１の実装用表面２１ａ、分割ソース電極２２ａ、２２ｂの実装用表面２３は、各半導体素子２０を封止する樹脂５０の一面５１より突出している。また、各リードフレーム３０の実装端子３３の実装端子面３３ａは、樹脂５０の一面５１と面一になっている。各リードフレーム３０の実装端子３３の実装端子面３３ａを、ゲート電極２１の実装用表面２１ａ、分割ソース電極２２ａ、２２ｂの実装用表面２３と面一にしてもよい。 Also in the sixth embodiment, the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b project from the one surface 51 of the resin 50 that seals each semiconductor element 20. The mounting terminal surface 33 a of the mounting terminal 33 of each lead frame 30 is flush with the one surface 51 of the resin 50. The mounting terminal surface 33a of the mounting terminal 33 of each lead frame 30 may be flush with the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the divided source electrodes 22a and 22b.
　従って、第６の実施形態における半導体装置１０も、第１の実施形態と同様な効果（１）、（２）、（４）を奏する。また、第６の実施形態では、リードフレーム３０の実装端子３３の数は、第１の実施形態の実装端子３３の数より少ないが、ソース電極２２を分割ソース電極２２ａ、２２ｂとしているので、第１の実施形態の効果（３）に近い効果を奏する。 Therefore, the semiconductor device 10 according to the sixth embodiment also exhibits the same effects (1), (2), and (4) as those of the first embodiment. Further, in the sixth embodiment, the number of the mounting terminals 33 of the lead frame 30 is smaller than the number of the mounting terminals 33 of the first embodiment, but the source electrode 22 is the divided source electrodes 22a and 22b. An effect close to the effect (3) of the first embodiment is achieved.
　なお、第６の実施形態においては、半導体装置１０は、３つの半導体装置領域１０ａ、１０ｂおよび１０ｃを有する構造として例示した。しかし、半導体装置領域の数は、それら３つに限られるものではなく、２つ以上の任意の複数にすることができる。また、半導体装置領域１０ａ、１０ｂおよび１０ｃの各収容部３１内に、１つの半導体素子２０が収容される構造として例示したが、各半導体装置領域１０ａ、１０ｂおよび１０ｃの各収容部３１内に、複数の半導体素子２０が収容されるようにしてもよい。また、実装端子面３３ａは、一対の短辺に一つずつ配置されることにより構成されるのではなく、分割された複数の端子面として構成されても良い。 In addition, in the sixth embodiment, the semiconductor device 10 is illustrated as a structure having three semiconductor device regions 10a, 10b, and 10c. However, the number of semiconductor device regions is not limited to three, and can be any number of two or more. Further, the semiconductor device regions 10a, 10b, and 10c have been described as having a structure in which one semiconductor element 20 is accommodated in each accommodating portion 31 of each semiconductor device region 10a, 10b, and 10c. You may make it accommodate several semiconductor elements 20. Further, the mounting terminal surface 33a may be configured as a plurality of divided terminal surfaces instead of being configured by arranging the mounting terminal surfaces 33a one by one on a pair of short sides.
－第７の実施形態－
　図１４は、本発明の第７の実施形態における半導体装置を示す断面図である。図１４は、第１の実施形態の図３に相当する。第７の実施形態における半導体装置１０は、リードフレーム３０の収容部３１内に、第１の半導体素子２０Ｃおよび第２の半導体素子２０Ｄが収容された構造を有する。第１の半導体素子２０Ｃおよび第２の半導体素子２０Ｄはそれぞれ、ゲート電極２１とソース電極２２とドレイン電極２４とを有する。しかし、第１の半導体素子２０Ｃおよび第２の半導体素子２０Ｄは、上下が反対に向けられた状態で収容部３１内に収容されている。また、リードフレーム３０は、リードフレーム領域３０ｒとリードフレーム領域３０ｓとに分割されている。リードフレーム領域３０ｒは実装端子３３ｒと底部４５ｒとを含み、リードフレーム領域３０ｓは実装端子３３ｓと底部４５ｓとを含む。 -Seventh Embodiment-
FIG. 14 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention. FIG. 14 corresponds to FIG. 3 of the first embodiment. The semiconductor device 10 according to the seventh embodiment has a structure in which the first semiconductor element 20C and the second semiconductor element 20D are housed in the housing portion 31 of the lead frame 30. Each of the first semiconductor element 20C and the second semiconductor element 20D has a gate electrode 21, a source electrode 22 and a drain electrode 24. However, the first semiconductor element 20C and the second semiconductor element 20D are accommodated in the accommodating portion 31 in a state in which they are turned upside down. Further, the lead frame 30 is divided into a lead frame area 30r and a lead frame area 30s. The lead frame region 30r includes a mounting terminal 33r and a bottom portion 45r, and the lead frame region 30s includes a mounting terminal 33s and a bottom portion 45s.
　第１の半導体素子２０Ｃは、第１の実施形態と同様、ドレイン電極２４をリードフレーム領域３０ｒの底部４５ｒ側に向けてリードフレーム３０の収容部３１内に収容されている。第１の半導体素子２０Ｃのドレイン電極２４は、バックメタル４１を介して、導電接合材４２により、リードフレーム領域３０ｒの底部４５ｒに接合されている。第２の半導体素子２０Ｄは、ソース電極２２をリードフレーム領域３０ｒの底部４５ｒ側に向けて、かつ、ゲート電極２１をリードフレーム領域３０ｓの底部４５ｓ側に向けて、リードフレーム３０の収容部３１に収容されている。第２の半導体素子２０Ｄのソース電極２２の実装用表面２３は、リードフレーム領域３０ｒの底部４５ｒに接合されている。また、第２の半導体素子２０Ｄのゲート電極２１の実装用表面２１ａは、リードフレーム領域３０ｓの底部４５ｓに接合されている。第２の半導体素子２０Ｄのドレイン電極２４上には、バックメタル４１が形成され、バックメタル４１上には導電接合材４２が形成されている。 Similar to the first embodiment, the first semiconductor element 20C is housed in the housing part 31 of the lead frame 30 with the drain electrode 24 facing the bottom 45r side of the lead frame region 30r. The drain electrode 24 of the first semiconductor element 20C is bonded to the bottom portion 45r of the lead frame region 30r by the conductive bonding material 42 via the back metal 41. In the second semiconductor element 20D, the source electrode 22 faces the bottom portion 45r side of the lead frame region 30r, and the gate electrode 21 faces the bottom portion 45s side of the lead frame region 30s. It is housed. The mounting surface 23 of the source electrode 22 of the second semiconductor element 20D is joined to the bottom portion 45r of the lead frame region 30r. The mounting surface 21a of the gate electrode 21 of the second semiconductor element 20D is joined to the bottom portion 45s of the lead frame region 30s. A back metal 41 is formed on the drain electrode 24 of the second semiconductor element 20D, and a conductive bonding material 42 is formed on the back metal 41.
　つまり、第１の半導体素子２０Ｃのドレイン電極２４および第２の半導体素子２０Ｄのソース電極２２は、リードフレーム領域３０ｒに電気的に接続されており、第２の半導体素子２０Ｄのゲート電極２１は、リードフレーム領域３０ｓに電気的に接続されている。 That is, the drain electrode 24 of the first semiconductor element 20C and the source electrode 22 of the second semiconductor element 20D are electrically connected to the lead frame region 30r, and the gate electrode 21 of the second semiconductor element 20D is It is electrically connected to the lead frame region 30s.
　リードフレーム領域３０ｒの実装端子３３ｒの実装端子面３３ａおよびリードフレーム領域３０ｓの実装端子３３ｓの実装端子面３３ａは、樹脂５０の一面５１と面一になっている。第１の半導体素子２０Ｃのゲート電極２１の実装用表面２１ａ、およびソース電極２２の実装用表面２３は、第１の半導体素子２０Ｃおよび第２の半導体素子２０Ｄを封止する樹脂５０の一面５１より突出している。なお、リードフレーム領域３０ｒの実装端子面３３ａおよびリードフレーム領域３０ｓの実装端子面３３ａを、第１の半導体素子２０Ｃのゲート電極２１の実装用表面２１ａ、およびソース電極２２の実装用表面２３と面一にしてもよい。 The mounting terminal surface 33a of the mounting terminal 33r in the lead frame area 30r and the mounting terminal surface 33a of the mounting terminal 33s in the lead frame area 30s are flush with the one surface 51 of the resin 50. The mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 of the first semiconductor element 20C are formed from one surface 51 of the resin 50 that seals the first semiconductor element 20C and the second semiconductor element 20D. It is protruding. The mounting terminal surface 33a of the lead frame region 30r and the mounting terminal surface 33a of the lead frame region 30s are flush with the mounting surface 21a of the gate electrode 21 and the mounting surface 23 of the source electrode 22 of the first semiconductor element 20C. May be one.
　さらに、第２の半導体素子２０Ｄのドレイン電極２４上に形成されたバックメタル４１、導電接合材４２は、樹脂５０の一面５１より突出している。第２の半導体素子２０Ｄのドレイン電極２４は、バックメタル４１を介して、導電接合材４２により不図示の回路基板の接続パッドに接合される。 Further, the back metal 41 and the conductive bonding material 42 formed on the drain electrode 24 of the second semiconductor element 20D project from the one surface 51 of the resin 50. The drain electrode 24 of the second semiconductor element 20D is bonded to the connection pad of the circuit board (not shown) by the conductive bonding material 42 via the back metal 41.
　第７の実施形態における半導体装置１０をモールド成型により形成する際、第１の半導体素子２０Ｃについては、第１の実施形態と同様な状態で、金型７１内に樹脂材５０Ｍが注入される。一方、第２の半導体素子２０Ｄについては、ドレイン電極２４上にバックメタル４１および導電接合材４２を形成しておいた状態か、またはドレイン電極２４上にバックメタル４１のみを形成した状態で、金型７１内に樹脂材５０Ｍが注入される。これにより、第２の半導体素子２０Ｄのドレイン電極２４上に形成されたバックメタル４１および導電接合材４２が樹脂５０の一面５１より突出する。 When the semiconductor device 10 according to the seventh embodiment is formed by molding, the resin material 50M is injected into the mold 71 for the first semiconductor element 20C in the same state as in the first embodiment. On the other hand, with respect to the second semiconductor element 20D, when the back metal 41 and the conductive bonding material 42 are formed on the drain electrode 24, or only the back metal 41 is formed on the drain electrode 24, gold The resin material 50M is injected into the mold 71. As a result, the back metal 41 and the conductive bonding material 42 formed on the drain electrode 24 of the second semiconductor element 20D project from the one surface 51 of the resin 50.
　第７の実施形態の他の構成は、第１の実施形態と同様であり、対応する部材に同一の符号を付して説明を省略する。 The other configurations of the seventh embodiment are similar to those of the first embodiment, and corresponding members are designated by the same reference numerals and the description thereof will be omitted.
　従って、第７の実施形態における半導体装置１０は、第１の半導体素子２０Ｃのみでなく、第２の半導体素子２０Ｄについても、第１の実施形態と同様な効果（１）、（２）を奏する。但し、第２の半導体素子２０Ｄについては、第１の半導体素子２０Ｃにおけるゲート電極２１およびソース電極２２を、ドレイン電極２４上に形成されたバックメタル４１および導電接合材４２、またはバックメタル４１に読み替えるものとする。また、第７の実施形態においても、第１の実施形態と同様な効果（３）、（４）を奏する。 Therefore, in the semiconductor device 10 according to the seventh embodiment, not only the first semiconductor element 20C but also the second semiconductor element 20D have the same effects (1) and (2) as those of the first embodiment. .. However, in the second semiconductor element 20D, the gate electrode 21 and the source electrode 22 in the first semiconductor element 20C are replaced with the back metal 41 and the conductive bonding material 42 or the back metal 41 formed on the drain electrode 24. I shall. In addition, in the seventh embodiment, the same effects (3) and (4) as those of the first embodiment can be obtained.
　なお、上記各実施形態では、半導体素子２０の支持部材として端子板であるリードフレーム３０を用いた構造として例示した。しかし、リードフレーム３０に代えて、セラミック等の絶縁性基板の表面に導電パターンが形成された端子板を用いることもできる。 In each of the above embodiments, the lead frame 30 that is the terminal plate is used as the support member for the semiconductor element 20. However, instead of the lead frame 30, a terminal plate having a conductive pattern formed on the surface of an insulating substrate such as ceramic may be used.
　上記各実施形態では、半導体素子２０を、ゲート電極２１、ソース電極２２およびドレイン電極２４を有するＭＯＳＦＥＴとして例示した。しかし、半導体素子２０として、ベース電極、エミッタ電極およびコレクタ電極を有するＩＧＢＴ（Insulated Gate Bipolar
Transistor）或いはBipolar等を用いることができる。また、半導体素子２０として、アノード電極およびカソード電極を有するダイオードを用いることができる。 In each of the above-described embodiments, the semiconductor element 20 is exemplified as the MOSFET having the gate electrode 21, the source electrode 22, and the drain electrode 24. However, as the semiconductor element 20, an IGBT (Insulated Gate Bipolar) having a base electrode, an emitter electrode and a collector electrode is used.
Transistor) or Bipolar can be used. Further, as the semiconductor element 20, a diode having an anode electrode and a cathode electrode can be used.
　上記各実施形態では、半導体素子２０、２０Ａ、２０Ｂをトランジスタとして例示した。しかし、本発明は、例えば、ダイオード等のトランジスタ以外の半導体素子を用いても適用が可能である。 In each of the above embodiments, the semiconductor elements 20, 20A, 20B are exemplified as transistors. However, the present invention can be applied, for example, by using a semiconductor element other than a transistor such as a diode.
　また、本発明の他の実施形態として、リードフレーム３０の収容部３１内に、トランジスタとダイオードとが収容されて組み合わされた半導体装置１０とすることもできる。 Further, as another embodiment of the present invention, the semiconductor device 10 in which the transistor and the diode are housed and combined in the housing portion 31 of the lead frame 30 may be used.
　上記各実施形態では、リードフレーム３０は、平面視で、矩形形状を有する部材として例示した。しかし、リードフレーム３０は、平面視で、三角形や五角形以上の多辺形としてもよい。 In each of the above embodiments, the lead frame 30 is exemplified as a member having a rectangular shape in a plan view. However, the lead frame 30 may have a polygonal shape such as a triangle or a pentagonal shape in plan view.
　上記では、種々の実施形態を説明したが、本発明はこれらの内容に限定されるものではない。本発明の技術的思想の範囲内で考えられるその他の態様も本発明の範囲内に含まれる。 Although various embodiments have been described above, the present invention is not limited to these contents. Other modes that can be considered within the scope of the technical idea of the present invention are also included in the scope of the present invention.
　次の優先権基礎出願の開示内容は引用文としてここに組み込まれる。
　日本国特許出願２０１８年第２３９９８２号（２０１８年１２月２１日出願） The disclosure content of the following priority basic application is incorporated herein by reference.
Japanese patent application 2018 No. 239982 (filed on December 21, 2018)
　１０　　　半導体装置
　１０ａ、１０ｂ、１０ｃ　　半導体装置領域
　２０、２０Ｃ、２０Ｄ　　半導体素子
　２０Ａ、２０Ｂ　　　半導体素子領域
　２１、２１Ｂ１、２１Ｂ２　　　ゲート電極（第一電極または第三電極）
　２１ａ　　実装用表面
　２２、２２Ｃ１、２２Ｃ２　　　ソース電極（第一電極または第三電極）
　２２ａ、２２ｂ　　分割ソース電極
　２３　　　実装用表面
　２４、２４Ａ１、２４Ａ２　　　ドレイン電極（第二電極）
　３０　　　リードフレーム（端子板）
　３０ａ、３０ｂ、３０ｃ　　リードフレーム部
　３０ｒ、３０ｓ　　リードフレーム領域
　３１　　　収容部
　３１ａ　　底面
　３２　　　側壁
　３３、３３ｒ、３３ｓ　　　実装端子
　３３ａ　　実装端子面
　３５　　　行接続部
　３６　　　列接続部
　３８　　　列連結部
　４１　　　バックメタル
　４２　　　導電接合材
　５１　　　一面（表面）
  10 semiconductor device 10a, 10b, 10c semiconductor device region 20, 20C, 20D semiconductor element 20A, 20B semiconductor element region 21, 21B1, 21B2 gate electrode (first electrode or third electrode)
21a Mounting surface 22, 22C1, 22C2 Source electrode (first electrode or third electrode)
22a, 22b split source electrode 23 mounting surface 24, 24A1, 24A2 drain electrode (second electrode)
30 Lead frame (terminal board)
30a, 30b, 30c Lead frame part 30r, 30s Lead frame region 31 Housing part 31a Bottom surface 32 Side wall 33, 33r, 33s Mounting terminal 33a Mounting terminal surface 35 Row connecting part 36 Column connecting part 38 Column connecting part 41 Back metal 42 Conductive bonding Material 51 One side (front side)

Claims (16)

  1. 　第一電極および第二電極を有する少なくとも一つの半導体素子と、
    　前記第二電極に接続され、前記少なくとも一つの半導体素子を収容する収容部および前記収容部の外周に形成された少なくとも一つの実装端子を有する端子板と、
    　前記端子板の収容部に収容された前記少なくとも一つの半導体素子を、前記第一電極を露出させて封止する樹脂とを備え、
    　前記第一電極の実装用表面は、前記少なくとも一つの半導体素子を封止する前記樹脂の表面より突出している半導体装置。     At least one semiconductor element having a first electrode and a second electrode,
    A terminal plate connected to the second electrode and having at least one mounting terminal formed on the outer periphery of the accommodating portion that accommodates the at least one semiconductor element, and
    The at least one semiconductor element housed in the housing portion of the terminal board, and a resin for exposing and sealing the first electrode,
    A semiconductor device in which a mounting surface of the first electrode projects from a surface of the resin that seals the at least one semiconductor element.
  2. 　請求項１に記載の半導体装置において、
    　前記端子板の前記少なくとも一つの実装端子の実装端子面と前記樹脂の前記表面とは面一である半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device in which a mounting terminal surface of the at least one mounting terminal of the terminal board and the surface of the resin are flush with each other.
  3. 　請求項１に記載の半導体装置において、
    　前記端子板の前記少なくとも一つの実装端子の実装端子面は前記樹脂の前記表面より突出している半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device in which a mounting terminal surface of the at least one mounting terminal of the terminal board is projected from the surface of the resin.
  4. 　請求項１に記載の半導体装置において、
    　前記少なくとも一つの実装端子は、前記収容部の前記外周のうちの一辺側および前記一辺側に対向する対向辺側にそれぞれ設けられる半導体装置。     The semiconductor device according to claim 1,
    The at least one mounting terminal is a semiconductor device provided on one side of the outer circumference of the accommodation portion and on an opposite side facing the one side, respectively.
  5. 　請求項１に記載の半導体装置において、
    　前記端子板は、リードフレームである半導体装置。     The semiconductor device according to claim 1,
    The semiconductor device in which the terminal board is a lead frame.
  6. 　請求項５に記載の半導体装置において、
    　前記収容部は、前記リードフレームのエッチングにより形成された半導体装置。     The semiconductor device according to claim 5,
    The storage unit is a semiconductor device formed by etching the lead frame.
  7. 　請求項５に記載の半導体装置において、
    　前記少なくとも一つの半導体素子は複数の半導体素子を含み、
    　前記リードフレームの前記収容部内に前記複数の半導体素子が収容されている半導体装置。     The semiconductor device according to claim 5,
    The at least one semiconductor device includes a plurality of semiconductor devices,
    A semiconductor device in which the plurality of semiconductor elements are housed in the housing portion of the lead frame.
  8. 　請求項５に記載の半導体装置において、
    　前記リードフレームは連結部により相互に連結された複数のリードフレーム部を有し、
    　前記複数のリードフレーム部の各々は、それぞれ前記少なくとも一つの半導体素子が収容された前記収容部を有する半導体装置。     The semiconductor device according to claim 5,
    The lead frame has a plurality of lead frame parts connected to each other by a connecting part,
    A semiconductor device, wherein each of the plurality of lead frame portions has the accommodation portion in which the at least one semiconductor element is accommodated.
  9. 　請求項５に記載の半導体装置において、
    　前記半導体素子は、第三電極をさらに有し、
    　前記第三電極の実装用表面は、前記半導体素子を封止する前記樹脂の表面より突出している半導体装置。     The semiconductor device according to claim 5,
    The semiconductor element further has a third electrode,
    A semiconductor device in which a mounting surface of the third electrode projects from a surface of the resin that seals the semiconductor element.
  10. 　請求項９に記載の半導体装置において、
    　前記半導体素子はトランジスタであって、
    　前記第一電極および前記第三電極としてソース電極およびゲート電極がそれぞれ形成され、
    　前記第二電極としてドレイン電極が形成された半導体装置。     The semiconductor device according to claim 9,
    The semiconductor element is a transistor,
    A source electrode and a gate electrode are respectively formed as the first electrode and the third electrode,
    A semiconductor device having a drain electrode formed as the second electrode.
  11. 　請求項１０に記載の半導体装置において、
    　前記ソース電極は、複数の分割ソース電極により構成される半導体装置。     The semiconductor device according to claim 10,
    A semiconductor device in which the source electrode includes a plurality of divided source electrodes.
  12. 　請求項１０に記載の半導体装置において、
    　前記半導体素子は複数の半導体素子領域を有し、
    　前記複数の半導体素子領域の各々は、前記ソース電極、前記ゲート電極および前記ドレイン電極を有する、半導体装置。     The semiconductor device according to claim 10,
    The semiconductor element has a plurality of semiconductor element regions,
    A semiconductor device in which each of the plurality of semiconductor element regions has the source electrode, the gate electrode, and the drain electrode.
  13. 　請求項９に記載の半導体装置において、
    　前記リードフレームは、相互に分割された第１のリードフレーム領域および第２のリードフレーム領域を含み、
    　前記リードフレームの前記収容部内に前記第一電極、前記第二電極および前記第三電極をそれぞれ有する第１の半導体素子および第２の半導体素子が収容され、
    　前記第１の半導体素子の前記第一電極および前記第三電極は前記樹脂の表面より突出し、前記第２の半導体素子の前記第二電極上に形成されたバックメタルは前記樹脂の表面より突出している半導体装置。     The semiconductor device according to claim 9,
    The lead frame includes a first lead frame region and a second lead frame region that are divided from each other,
    A first semiconductor element and a second semiconductor element each having the first electrode, the second electrode and the third electrode are housed in the housing portion of the lead frame;
    The first electrode and the third electrode of the first semiconductor element protrude from the surface of the resin, and the back metal formed on the second electrode of the second semiconductor element protrudes from the surface of the resin. Semiconductor device.
  14. 　第一電極および第二電極を有する半導体素子が収容される端子板の収容部へ、前記第二電極が電気的に接続されるようにボンディングし、
    　前記第一電極の実装用表面が樹脂の表面より突出するように前記半導体素子を前記樹脂により封止し、
    　前記収容部と前記収容部の外部に形成された前記端子板の実装端子面とを有する半導体装置形成領域と、別の前記半導体装置形成領域とを接続する連結部分を切断することにより、個々の半導体装置を得る半導体装置の製造方法。     To a housing portion of a terminal plate in which a semiconductor element having a first electrode and a second electrode is housed, the second electrode is bonded so as to be electrically connected,
    The semiconductor element is sealed with the resin so that the mounting surface of the first electrode protrudes from the surface of the resin,
    By cutting a connecting portion that connects the semiconductor device formation region having the accommodation part and the mounting terminal surface of the terminal plate formed outside the accommodation part and another semiconductor device formation region, A method of manufacturing a semiconductor device for obtaining a semiconductor device.
  15. 　請求項１４に記載の半導体装置の製造方法において、
    　前記半導体素子を前記樹脂により封止する際、前記樹脂の前記表面が、前記端子板の前記実装端子面と面一になるように、前記端子板が前記樹脂により封止される半導体装置の製造方法。     The method of manufacturing a semiconductor device according to claim 14,
    Manufacturing of a semiconductor device in which the terminal plate is sealed with the resin so that the surface of the resin is flush with the mounting terminal surface of the terminal plate when the semiconductor element is sealed with the resin Method.
  16. 　請求項１４に記載の半導体装置の製造方法において、
    　前記半導体素子を前記樹脂により封止する際、前記端子板の前記実装端子面が前記樹脂の前記表面より突出するように、前記端子板が前記樹脂により封止される半導体装置の製造方法。
          The method of manufacturing a semiconductor device according to claim 14,
    A method of manufacturing a semiconductor device, wherein the terminal plate is sealed with the resin so that the mounting terminal surface of the terminal plate projects from the surface of the resin when the semiconductor element is sealed with the resin.
PCT/JP2019/015843 2018-12-21 2019-04-11 Semiconductor device and method for manufacturing semiconductor device WO2020129273A1 (en)

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JP2019558803A JP6746808B1 (en) 2018-12-21 2019-04-11 Semiconductor device and method of manufacturing semiconductor device
TW108123817A TW202025317A (en) 2018-12-21 2019-07-05 Semiconductor device and method for manufacturing semiconductor device

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