WO2020125792A1 - 数据输出方法及装置、存储介质及设备 - Google Patents

数据输出方法及装置、存储介质及设备 Download PDF

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Publication number
WO2020125792A1
WO2020125792A1 PCT/CN2019/127322 CN2019127322W WO2020125792A1 WO 2020125792 A1 WO2020125792 A1 WO 2020125792A1 CN 2019127322 W CN2019127322 W CN 2019127322W WO 2020125792 A1 WO2020125792 A1 WO 2020125792A1
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WIPO (PCT)
Prior art keywords
channels
data packets
read
channel
data
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PCT/CN2019/127322
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English (en)
French (fr)
Inventor
李龙龙
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深圳市中兴微电子技术有限公司
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Publication of WO2020125792A1 publication Critical patent/WO2020125792A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H04J3/065—Synchronisation among TDM nodes using timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0664—Clock or time synchronisation among packet nodes using timestamps unidirectional timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/56—Queue scheduling implementing delay-aware scheduling
    • H04L47/562—Attaching a time tag to queues

Definitions

  • the present disclosure relates to the technical field of optical transmission networks, for example, to a data output method and device, storage medium, and equipment.
  • Optical transport network (OTN) backplane switching which can integrate OTN and packet switching on the same platform, can provide operators with maximum flexibility in network design and cost optimization, and can be accessed through switching (Switch Access, SA) interface completes Time Division Multiplexing (TDM) packet exchange.
  • Switch Access SA
  • TDM Time Division Multiplexing
  • the network processor Network Processor, NP interconnection packet exchange is realized through the exchange of Ethernet packets, and the interface can only be implemented using the Interlaken interface.
  • Packet optical transmission network Packet Optical Transmission Network, POTN
  • POTN Packet Optical Transmission Network
  • PTN Packet Transport Network
  • OTN packet, TDM
  • the cross-board uses the Interlaken interface to achieve cross-connection.
  • the present disclosure provides a data output method and device, storage medium, and equipment, which can improve the reliability of data transmission.
  • an embodiment of the present disclosure provides a data output method, including:
  • the source board adds a time stamp to the original data packet, and sends the time-stamped data packets to the sink board in parallel through two channels;
  • the sink board receives the data packets in parallel on the two channels, determines the data packets written to the cache queue of each channel according to the time stamp carried by the data packets, and separates the received data packets Write to the cache queue of the two channels;
  • the sink board reads data packets from the cache queues of the two channels in parallel, and performs alignment processing on the data packets read from the cache queues of the two channels according to the time stamp carried by the data packets;
  • the sink board After successfully aligning the read data packets in the buffer queues of the two channels, the sink board outputs the data packets read from the buffer queue of any one of the two channels .
  • an embodiment of the present disclosure provides a data output device, including:
  • the source-side single-board processing module is configured to add a time stamp to the original data packet, and send the data packet with the time stamp added to the sink-side single-board processing module in parallel through two channels;
  • the sink-side single-board processing module is configured to receive the data packets in parallel on the two channels, determine the data packets written to the cache queue of each channel according to the time stamp carried by the data packets, and The data packets are respectively written into the buffer queues of the two channels; the data packets are read in parallel from the buffer queues of the two channels, and the two channels are processed according to the time stamp carried by the data packets Align the data packets read in the cache queue of the server; after aligning the read data packets in the cache queues of the two channels successfully, the packets from any one of the two channels will be cached The read data packet is output.
  • an embodiment of the present disclosure provides a computer-readable storage medium that stores one or more programs, and the one or more programs can be used by one or more processors Implementation to achieve the above method.
  • an embodiment of the present disclosure provides an apparatus, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor executing the computer The above method is implemented in the program.
  • FIG. 1 is a flowchart of a data output method according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a time stamp carried in a TDM packet according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a data output device according to an embodiment of the present disclosure.
  • Example 4 is a schematic diagram of a data output device of Example 1 of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a device according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a data output method, including:
  • Step 110 The source-side board adds a time stamp to the original data packet, and sends the time-stamped data packet to the sink-side board in parallel through two channels.
  • Step 120 The sink board receives the data packets in parallel on the two channels, determines the data packets written to the cache queue of each channel according to the time stamp carried by the data packets, and sends the received The data packets are written into the buffer queues of the two channels respectively.
  • Step 130 The sink board reads the data packets from the cache queues of the two channels in parallel, and performs a data packet read from the cache queues of the two channels according to the time stamp carried by the data packets Alignment processing.
  • Step 140 After successfully aligning the read data packets in the cache queues of the two channels (also referred to as read buffer operations of the two channels), the sink-side board will select the two channels from the two channels. The data packet read from the buffer queue of any channel is output.
  • the read cache operation may be understood as an operation of reading data packets in the cache queues of the two channels.
  • the source-side board provides a reference basis for data alignment for parallel reception of the sink-side board by adding a time stamp to the original data packet.
  • the sink board receives the data packets in parallel on the two channels, and controls the operations of the write cache and the read cache according to the time stamp carried in the data packets.
  • the working channel fails, because the data read by the two channels are consistent, it is possible to seamlessly switch the working channel and the standby channel, thus meeting the 5G fronthaul network's requirements for communication delay and reliability.
  • the data packet includes: a time division multiplexed TDM data packet
  • the time stamping the original data packet includes: adding a time stamp to the header of the TDM data packet;
  • the TDM data packet includes: a packet header and a payload; wherein, the packet header includes a 16-bit time stamp and a 16-bit overhead (Overhead, OH);
  • the two channels are both high-speed data transmission Interlaken channels; where Interlaken is a high-speed channelized interface protocol;
  • the data packet written to the cache queue of each channel is determined according to the received time stamp carried by the data packet, and the data packet is written into the cache queue of the two channels respectively Including:
  • the time stamp of the data packet received by the channel changes from the maximum value to the minimum value
  • the time when the data packet carrying the minimum time stamp is received is used as the reference time, and the reference time All previously received data packets are written to the buffer queue of the channel;
  • the performing alignment processing on the data packets read in the buffer queues of the two channels according to the time stamp carried by the data packets includes:
  • the buffer queues of the two channels are read at the same time.
  • the first n of the buffer queues read from the two channels are read
  • the time stamps carried by the data packets are the same, determine the alignment of the data packets read in the buffer queues of the two channels;
  • n can take the value 1, or 2 or 3 or other positive integer values.
  • the performing alignment processing on the data packets read in the buffer queues of the two channels according to the time stamp carried by the data packets further includes:
  • the data packets written into the cache queues of the two channels are determined according to the received timestamps carried by the data packets and the data packets are written into the cache queue of each channel respectively ,include:
  • the write cache processing of the channel is triggered.
  • the method further includes:
  • the alarm information includes at least one of the following: misalignment of the Interlaken channel, failure to de-skew, cyclic redundancy check (Cyclic Redundancy Check, CRC) check error, packet header and packet tail mismatch error, and meta frame length error.
  • CRC Cyclic Redundancy Check
  • the method further includes:
  • the sink board After the sink board outputs the data packet read from the cache queue of the first channel of the two channels, if an alarm occurs on the first channel, the The data packets read in the buffer queue of the second channel are output;
  • the method further includes:
  • the buffer queue of each channel is a first-in first-out (First Input First Output (FIFO) queue.
  • FIFO First Input First Output
  • an embodiment of the present disclosure provides a data output device, including:
  • the source-side single-board processing module 10 is set to add a time stamp to the original data packet, and send the time-stamped data packet to the sink-side single-board processing module in parallel through two channels;
  • the sink board processing module 20 is configured to receive the data packets in parallel on two channels, determine the data packets written to the cache queue of each channel according to the time stamp carried by the data packets, and transfer the received data
  • the packets are written into the cache queues of the two channels respectively; the data packets are read in parallel from the cache queues of the two channels, and the data is read from the cache queues of the two channels according to the time stamp carried by the data packets Align the data packets; after successfully aligning the read data packets in the cache queues of the two channels, output the data packets read from the cache queue of any one of the two channels .
  • the data packet includes: a time division multiplexed TDM data packet
  • the source board processing module 10 is configured to add a time stamp to the original data packet in the following manner: add a time stamp to the header of the TDM data packet;
  • the two channels are both Interlaken channels
  • the sink board processing module 20 is configured to determine the data packet written into the cache queue of each channel according to the time stamp carried by the data packet in the following manner, and The data packets are written into the buffer queues of the two channels respectively: for each channel, when the time stamp of the data packet received by the channel changes from the maximum value to the minimum value, the time for receiving the minimum value will be carried The time of the stamped data packet is used as the reference time, and all data packets received before the reference time are written into the buffer queue of the channel;
  • the sink-side single-board processing module 20 is configured to perform alignment processing on the data packets read from the cache queues of the two channels according to the time stamp carried by the data packets in the following manner : When the number of packets allowed to be read in the buffer queues of the two channels reaches or exceeds the read threshold, the buffer queues of the two channels are read at the same time. When the top n reads from the buffer queues of the two channels When the time stamps carried by the two data packets are the same, determine the alignment of the data packets read in the buffer queues of the two channels.
  • n can take the value of 1 or 2 or 3 or other positive integer values.
  • the sink-side single-board processing module 20 is further configured to perform alignment processing on the data packets read from the cache queues of the two channels according to the time stamp carried by the data packets in the following manner : When the number of packets allowed to be read in the buffer queue of one of the two channels reaches or exceeds the read threshold, and the data allowed to be read in the buffer queue of the other channel of the two channels When the number of packets is zero, it is determined that the read buffer operation of the two channels does not meet the alignment conditions;
  • the sink board processing module 20 is configured to determine the data packet written into the cache queue of each channel according to the time stamp carried by the data packet in the following manner, and The data packets are written into the buffer queues of the two channels respectively: query the alarm information of each channel; for any one of the two channels, when the alarm information of the channel is not queried, the Write buffer processing of the channel.
  • the sink board processing module 20 is further configured to query the alarm information of each channel, and if the alarm information of any channel is queried, the alarm information is processed.
  • the alarm information includes at least one of the following: misalignment of the Interlaken channel, failure to de-skew, CRC check error, mismatch between packet header and packet tail, and meta frame length error.
  • the sink board processing module 20 is further configured to output the data packet read from the cache queue of the first channel of the two channels if the first If an alarm occurs in the channel, the data packet read from the cache queue of the second channel of the two channels is output;
  • the sink board processing module 20 is further configured to re-trigger a write operation to the cache queue of the first channel after the alarm of the first channel is restored, and to the The read buffer operations of the first channel and the second channel are realigned.
  • this example provides a data output device, including: a source-side board and a sink-side board;
  • the source-side board includes: a TDM packet processing module, a first channel sending module, and a second channel Sending module;
  • the sink board includes: first channel receiving module, second channel receiving module, first alarm processing module, second alarm processing module, FIFO read-write control module, first FIFO module, second FIFO module , And package output module;
  • the TDM packet processing module is set to add a time stamp to the original TDM data packet, and distribute the time stamped TDM data packet to the first channel sending module and the second channel sending module in parallel;
  • the first channel sending module is configured to send the time stamped TDM data packet to the sink board through the first Interlaken channel;
  • the second channel sending module is configured to send the time stamped TDM data packet to the sink board through the second Interlaken channel;
  • the first channel receiving module is configured to receive TDM data packets through the first Interlaken channel, and informs the first alarm processing module to query whether there is alarm information in the first Interlaken channel;
  • the first alarm processing module is configured to process the alarm information after querying the alarm information of the first Interlaken channel and notify the FIFO read-write control module; when the alarm information of the first Interlaken channel is not queried, notify The first Interlaken channel interface of the FIFO read-write control module is normal;
  • the second channel receiving module is configured to receive the TDM data packet through the second Interlaken channel and notify the second alarm processing module to query whether there is alarm information in the second Interlaken channel;
  • the second alarm processing module is configured to process the alarm information when the alarm information of the second Interlaken channel is queried and notify the FIFO read-write control module; when the alarm information of the second Interlaken channel is not queried, notify The interface of the second Interlaken channel of the FIFO read-write control module is normal;
  • the alarm information may include at least one of the following: misalignment of the Interlaken channel, failure to offset, CRC check error, mismatch between packet header and packet tail, and meta frame length error.
  • the FIFO read and write control module is set to learn that the first Interlaken channel interface is normal, and when the timestamp of the data packet received by the first Interlaken channel changes from the maximum value to the minimum value, it will receive the minimum timestamp
  • the moment of the data packet is used as the reference moment to trigger the first FIFO module to write the buffer; and after setting to learn that the interface of the second Interlaken channel is normal, when the time stamp of the data packet received by the second Interlaken channel changes from the maximum value to the minimum value
  • the value is set, the time when the data packet carrying the minimum time stamp is received is used as the reference time to trigger the second FIFO module to write the buffer;
  • the first FIFO module is configured to write all data packets received before the reference time to the FIFO buffer queue of the first Interlaken channel;
  • the second FIFO module is configured to write all data packets received before the reference time into the FIFO buffer queue of the second Interlaken channel;
  • the FIFO read and write control module is also set to query the number of data packets allowed to be read in the FIFO buffer queue of the first Interlaken channel and the number of data packets allowed to be read in the FIFO buffer queue of the second Interlaken channel; when the two When the number of read packets allowed in the buffer queue of each Interlaken channel reaches or exceeds the read threshold, the first FIFO module and the second FIFO module are triggered to read the FIFO buffer queue at the same time; when the FIFO buffers from the two Interlaken channels When the first n packets read in the queue carry the same timestamp, the packet output module is notified to align the packets; when the number of packets allowed to be read in the buffer queue of an Interlaken channel reaches or exceeds the read threshold, the other When the number of packets allowed to be read in the buffer queue of an Interlaken channel is 0, it is determined that the read buffer operations of the two Interlaken channels do not meet the alignment conditions;
  • the packet output module is set to select the data packets read from the FIFO buffer queue of the first Interlaken channel for output after learning that the data packets read by the FIFO buffer queues of the two Interlaken channels are aligned, or select the second Interlaken channel for output The data packets read in the FIFO buffer queue are output;
  • the FIFO read and write control module is also set to select the FIFO buffer queue from the second Interlaken channel if the packet read from the FIFO buffer queue of the first Interlaken channel is selected for output.
  • the data packet read in is output; when it is learned that the first Interlaken channel alarm is recovered, the first FIFO module is retriggered to write the buffer, and the first FIFO module and the second FIFO module read the buffer and control the data packet alignment again.
  • the source board provides a reference basis for data alignment for the parallel reception of the sink board by adding a time stamp to the original data packet.
  • the sink board receives data packets in parallel on two Interlaken channels, and controls the operations of the write cache and the read cache according to the time stamp carried in the data packets.
  • the read operations of the two Interlaken channels are aligned, either channel can be used as the current working channel, and the other channel can be used as the backup channel.
  • the working channel fails, because the data read by the two channels are consistent, it is possible to seamlessly switch the working channel and the backup channel to meet the requirements of 5G fronthaul network for communication delay and reliability.
  • an embodiment of the present disclosure further provides a device, including: a memory 510, a processor 520, and a computer program stored on the memory 510 and executable on the processor 520, and the processor 520 executes the The computer program implements the method described in any of the above embodiments.
  • An embodiment of the present disclosure also provides a computer-readable storage medium that stores computer-executable instructions, and the computer-executable instructions are used to perform the method described in any of the foregoing embodiments.
  • the technical solutions of the embodiments of the present disclosure can improve the reliability of data transmission.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes volatile and nonvolatile, removable and non-removable implemented in a variety of methods or technologies for storing information such as computer readable instructions, data structures, program modules or other data In addition to the medium.
  • Computer storage media include random access memory (Random Access Memory, RAM), (Read-Only Memory, ROM), electrically erasable programmable read-only memory (Electrically, Programmable read only memory, EEPROM), flash memory or other memory technologies, CD-ROM (Compact Disc Read-Only Memory, CD-ROM), Digital Versatile Disc (DVD) or other optical disc storage, magnetic box, magnetic tape, magnetic disk storage or other magnetic storage devices, or can be used for storage A variety of other media that can be accessed by the computer as desired information.
  • Communication media typically contains computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include a variety of information delivery media.

Abstract

本文公开了一种数据输出方法及装置。所述数据输出方法包括：源端单板为原始数据包添加时间戳，并通过两个通道将添加时间戳后的数据包并行发送至宿端单板；宿端单板在两个通道并行接收数据包，根据数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的数据包分别写入两个通道的缓存队列中；宿端单板从两个通道的缓存队列中并行读取数据包，根据所述数据包携带的时间戳对两个通道的缓存队列中读取的数据包进行对齐处理；宿端单板在对读取的两个通道的缓存队列中的数据包对齐成功后，将从两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。

Description

数据输出方法及装置、存储介质及设备
本申请要求在2018年12月21日提交中国专利局、申请号为201811573811.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及光传输网技术领域，例如涉及一种数据输出方法及装置、存储介质及设备。
背景技术
光传输网(Optical Transport Network，OTN)的下背板交换，能够集OTN与分组交换于同一平台，可为运营商在网络设计和成本优化方面提供最大的灵活性，可以通过交换接入(Switch Access，SA)接口完成时分复用(Time Division Multiplexing，TDM)包交换。
网络处理器(Network Processor，NP)对接的包交换是通过以太网包的交换实现的，接口只能采用Interlaken接口实现。分组光传输网(Packet Optical Transport Network，POTN)技术是基于OTN技术上的具有分组交换和传输能力的一种技术，它是将分组传送网(Packet Transport Network，PTN)和OTN、分组、TDM、包交换等全部优势集中到同一个设备中，实现多颗粒的交换，对多种技术进行深层次的融合达到完美，其中的交叉板采用Interlaken接口实现交叉。
但是在第五代移动通信技术(5th-Generation，5G)前传网络中，对TDM包的交换传输延时性能、传输数据可靠性提出了更高的要求。
发明内容
本公开提供一种数据输出方法及装置、存储介质及设备，能够提高数据传输的可靠性。
在一实施例中，本公开实施例提供了一种数据输出方法，包括：
源端单板为原始数据包添加时间戳，并通过两个通道将添加时间戳后的数据包并行发送至宿端单板；
所述宿端单板在所述两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中；
所述宿端单板从所述两个通道的缓存队列中并行读取数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理；
所述宿端单板在对读取的所述两个通道的缓存队列中的数据包对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。
在一实施例中，本公开实施例提供了一种数据输出装置，包括：
源端单板处理模块，设置为为原始数据包添加时间戳，并通过两个通道将添加所述时间戳后的数据包并行发送至宿端单板处理模块；
所述宿端单板处理模块，设置为在所述两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中；从所述两个通道的缓存队列中并行读取所述数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理；在对读取的所述两个通道的缓存队列中的数据包对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。
在一实施例中，本公开实施例提供了一种计算机可读存储介质，所述计算机可读存储介质存储有一个或者多个程序，所述一个或者多个程序可被一个或者多个处理器执行，以实现上述的方法。
在一实施例中，本公开实施例提供了一种设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现上述的方法。
附图说明
图1为本公开实施例的一种数据输出方法流程图；
图2为本公开实施例的一种TDM包中携带时间戳的示意图；
图3为本公开实施例的一种数据输出装置示意图；
图4为本公开示例1的一种数据输出装置示意图；
图5为本公开实施例的一种设备的结构示意图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
实施例1
如图1所示，本公开实施例提供了一种数据输出方法，包括：
步骤110，源端单板为原始数据包添加时间戳，并通过两个通道将添加时间戳后的数据包并行发送至宿端单板。
步骤120，所述宿端单板在所述两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中。
步骤130，所述宿端单板从所述两个通道的缓存队列中并行读取数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理。
步骤140，所述宿端单板在对读取的所述两个通道的缓存队列中的数据包(也称为两个通道的读缓存操作)对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。
在一实施例中，读缓存操作可以理解为读取所述两个通道的缓存队列中的数据包的操作。
在上述实施方式中，源端单板通过在原始数据包中添加时间戳为宿端单板的并行接收提供了数据对齐的参考依据。宿端单板在两个通道并行接收数据包，根据所述数据包携带的时间戳对写缓存和读缓存的操作进行控制。在读缓存时，通过检查两个通道读取的数据包携带的时间戳是否相同可以判断两个通道读出的数据包是否对齐。在两个通道的读操作对齐后，任意一个通道可以作为当前的工作通道，另一个通道可以作为备用通道。当工作通道发生故障时，由于两个通道读取的数据是一致的，因此可以达到无缝切换工作通道和备用通道，从 而满足5G前传网络对通信延时和可靠性的要求。
在一种实施方式中，所述数据包包括：时分复用TDM数据包；
在一种实施方式中，所述为原始数据包添加时间戳，包括：在TDM数据包的包头添加时间戳；
其中，如图2所示，TDM数据包包括：包头和负载；其中，包头包括16比特的时间戳和16比特的开销(Overhead，OH)；
在一种实施方式中，所述两个通道均为高速数据传输Interlaken通道；其中，Interlaken是一种高速通道化的接口协议；
在一种实施方式中，所述根据接收的所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将所述数据包分别写入所述两个通道的缓存队列中，包括：
针对每一个通道，当所述通道接收到的数据包的时间戳从最大值变为最小值时，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，将在所述参考时刻之前接收的所有数据包写入该通道的缓存队列中；
在一种实施方式中，所述根据所述数据包携带的时间戳对两个通道的缓存队列中读取的数据包进行对齐处理，包括：
当两个通道的缓存队列中允许读取的数据包的数量均达到或超过读取阈值时，同时读取两个通道的缓存队列，当从两个通道的缓存队列中读取的前n个数据包携带的时间戳相同时，确定两个通道的缓存队列中读取的数据包对齐；
其中，n可以取值为1，或2或3或其他正整数数值。
在一种实施方式中，所述根据所述数据包携带的时间戳对两个通道的缓存队列中读取的数据包进行对齐处理，还包括：
当所述两个通道中的一个通道的缓存队列中允许读取的数据包的数量达到或超过读取阈值，而所述两个通道中的另一个通道的缓存队列中允许读取的数据包的数量为零时，确定两个通道的读缓存操作不满足对齐条件；
在一种实施方式中，所述根据接收的所述数据包携带的时间戳确定写入所述两个通道的缓存队列的数据包并将所述数据包分别写入每一个通道的缓存队 列中，包括：
查询每一个通道的告警信息；
对所述两个通道中的任意一个通道，在未查询到所述通道的告警信息时，触发对所述通道的写缓存处理。
在一种实施方式中，查询每一个通道的告警信息后，所述方法还包括：
在查询到任意一个通道的告警信息后，对所述告警信息进行处理；
所述告警信息包括以下至少一种：Interlaken通道未对齐、去偏移失败、循环冗余校验(Cyclic Redundancy Check，CRC)校验错误、包头和包尾不匹配错误、和元帧长度错误。
在一种实施方式中，所述方法还包括：
当宿端单板将从所述两个通道中的第一通道的缓存队列中读取的数据包进行输出后，如果所述第一通道出现告警，则将从所述两个通道中的第二通道的缓存队列中读取的数据包进行输出；
在一种实施方式中，所述方法还包括：
当所述第一通道告警恢复后，重新触发对所述第一通道的缓存队列写操作，以及对第一通道和第二通道的读缓存操作重新进行对齐处理。
在一种实施方式中，所述每一个通道的缓存队列为先入先出(First Input First Output，FIFO)队列。
实施例2
如图2所示，本公开实施例提供了一种数据输出装置，包括：
源端单板处理模块10，设置为为原始数据包添加时间戳，并通过两个通道将添加时间戳后的数据包并行发送至宿端单板处理模块；
宿端单板处理模块20，设置为在两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中；从两个通道的缓存队列中并行 读取数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理；在对读取的所述两个通道的缓存队列中的数据包对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。
在一种实施方式中，所述数据包包括：时分复用TDM数据包；
在一种实施方式中，所述源端单板处理模块10，是设置为采用以下方式为原始数据包添加时间戳：在TDM数据包的包头添加时间戳；
在一种实施方式中，所述两个通道均为Interlaken通道；
在一种实施方式中，所述宿端单板处理模块20，是设置为采用以下方式根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中：针对每一个通道，当所述通道接收到的数据包的时间戳从最大值变为最小值时，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，将在所述参考时刻之前接收的所有数据包写入该通道的缓存队列中；
在一种实施方式中，所述宿端单板处理模块20，是设置为采用以下方式根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理：当两个通道的缓存队列中允许读取的数据包的数量均达到或超过读取阈值时，同时读取两个通道的缓存队列，当从两个通道的缓存队列中读取的前n个数据包携带的时间戳相同时，确定两个通道的缓存队列中读取的数据包对齐。
其中，n可以取值为1或2或3或其他正整数数值。
在一种实施方式中，所述宿端单板处理模块20，还设置为采用以下方式根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理：当所述两个通道中的一个通道的缓存队列中允许读取的数据包的数量达到或超过读取阈值，而所述两个通道中的另一个通道的缓存队列中允许读取的数据包的数量为零时，确定两个通道的读缓存操作不满足对齐条件；
在一种实施方式中，所述宿端单板处理模块20，是设置为采用以下方式根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中：查询每一个通道的告警 信息；对所述两个通道中的任意一个通道，在未查询到所述通道的告警信息时，触发对所述通道的写缓存处理。
在一种实施方式中，所述宿端单板处理模块20，还设置为查询每一个通道的告警信息，如果查询到任意一个通道的告警信息后，则对所述告警信息进行处理。
所述告警信息包括以下至少一种：Interlaken通道未对齐、去偏移失败、CRC校验错误、包头和包尾不匹配错误、和元帧长度错误。
在一种实施方式中，所述宿端单板处理模块20，还设置为将从所述两个通道中的第一通道的缓存队列中读取的数据包进行输出后，如果所述第一通道出现告警，则将从所述两个通道中的第二通道的缓存队列中读取的数据包进行输出；
在一种实施方式中，所述所述宿端单板处理模块20，还设置为当所述第一通道告警恢复后，重新触发对所述第一通道的缓存队列写操作，以及对所述第一通道和所述第二通道的读缓存操作重新进行对齐处理。
示例1
如图4所示，本示例提供一种数据输出装置，包括：源端单板和宿端单板；所述源端单板包括：TDM包处理模块、第一通道发送模块、和第二通道发送模块；所述宿端单板包括：第一通道接收模块、第二通道接收模块、第一告警处理模块、第二告警处理模块、FIFO读写控制模块、第一FIFO模块、第二FIFO模块、和包输出模块；
所述TDM包处理模块，设置为为原始TDM数据包添加时间戳，并将添加了时间戳的TDM数据包并行分发至第一通道发送模块和第二通道发送模块；
所述第一通道发送模块，设置为将添加了时间戳的TDM数据包通过第一Interlaken通道发送至宿端单板；
所述第二通道发送模块，设置为将添加了时间戳的TDM数据包通过第二Interlaken通道发送至宿端单板；
第一通道接收模块，设置为通过第一Interlaken通道接收TDM数据包，通 知第一告警处理模块查询所述第一Interlaken通道是否存在告警信息；
第一告警处理模块，设置为当查询到第一Interlaken通道的告警信息后，对所述告警信息进行处理，并通知FIFO读写控制模块；当未查询到第一Interlaken通道的告警信息时，通知FIFO读写控制模块第一Interlaken通道接口正常；
第二通道接收模块，设置为通过第二Interlaken通道接收TDM数据包，通知第二告警处理模块查询所述第二Interlaken通道是否存在告警信息；
第二告警处理模块，设置为当查询到第二Interlaken通道的告警信息后，对所述告警信息进行处理，并通知FIFO读写控制模块；当未查询到第二Interlaken通道的告警信息时，通知FIFO读写控制模块第二Interlaken通道接口正常；
其中，所述告警信息可以包括以下至少一种：Interlaken通道未对齐、去偏移失败、CRC校验错误、包头和包尾不匹配错误、和元帧长度错误。
FIFO读写控制模块，设置为获知第一Interlaken通道接口正常后，当所述第一Interlaken通道接收到的数据包的时间戳从最大值变为最小值时，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，触发第一FIFO模块写缓存；以及设置为获知第二Interlaken通道接口正常后，当所述第二Interlaken通道接收到的数据包的时间戳从最大值变为最小值时，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，触发第二FIFO模块写缓存；
第一FIFO模块，设置为将在所述参考时刻之前接收的所有数据包写入第一Interlaken通道的FIFO缓存队列中；
第二FIFO模块，设置为将在所述参考时刻之前接收的所有数据包写入第二Interlaken通道的FIFO缓存队列中；
FIFO读写控制模块，还设置为查询第一Interlaken通道的FIFO缓存队列中允许读取的数据包的数量，以及查询第二Interlaken通道的FIFO缓存队列中允许读取的数据包的数量；当两个Interlaken通道的缓存队列中允许读取的数据包的数量均达到或超过读取阈值时，触发第一FIFO模块和第二FIFO模块同时读取FIFO缓存队列；当从两个Interlaken通道的FIFO缓存队列中读取的 前n个数据包携带的时间戳相同时，通知包输出模块数据包对齐；当一个Interlaken通道的缓存队列中允许读取的数据包的数量达到或超过读取阈值，而另一个Interlaken通道的缓存队列中允许读取的数据包的数量为0时，确定两个Interlaken通道的读缓存操作不满足对齐条件；
包输出模块，设置为在获知两个Interlaken通道的FIFO缓存队列读取的数据包对齐后，选择从第一Interlaken通道的FIFO缓存队列中读取的数据包进行输出，或者选择从第二Interlaken通道的FIFO缓存队列中读取的数据包进行输出；
FIFO读写控制模块，还设置为当选择从第一Interlaken通道的FIFO缓存队列中读取的数据包进行输出后，如果获知第一Interlaken通道出现告警，则选择从第二Interlaken通道的FIFO缓存队列中读取的数据包进行输出；当获知第一Interlaken通道告警恢复后，重新触发第一FIFO模块写缓存，以及重新控制第一FIFO模块和第二FIFO模块读缓存并进行数据包对齐处理。
在上述示例中，源端单板通过在原始数据包中添加时间戳为宿端单板的并行接收提供了数据对齐的参考依据。宿端单板在两个Interlaken通道并行接收数据包，根据所述数据包携带的时间戳对写缓存和读缓存的操作进行控制。在读缓存时，通过检查两个Interlaken通道读取的数据包携带的时间戳是否相同可以判断两个Interlaken通道读出的数据包是否对齐。当两个Interlaken通道的读操作对齐后，任意一个通道可以作为当前的工作通道，另一个通道可以作为备用通道。当工作通道发生故障时，由于两个通道读取的数据是一致的，因此可以达到无缝切换工作通道和备用通道，从而满足5G前传网络对通信延时和可靠性的要求。
如图5所示，本公开实施例还提供一种设备，包括：存储器510、处理器520及存储在存储器510上并可在处理器520上运行的计算机程序，所述处理器520执行所述计算机程序时实现上述任一实施例所述的方法。
本公开实施例还提供一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行上述任意实施例所述的方法。
本公开实施例的技术方案能够提高数据传输的可靠性。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、 系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由多个物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的多种方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括随机存取存储器(Random Access Memory，RAM)、(Read-Only Memory，ROM)、带电可擦可编程只读存储器(Electrically Erasable Programmable read only memory，EEPROM)、闪存或其他存储器技术、只读光盘(Compact Disc Read-Only Memory，CD-ROM)、数字多功能盘(Digital Versatile Disc，DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的多种其他的介质。通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括多种信息递送介质。

Claims (12)

  1. 一种数据输出方法，包括：
    源端单板为原始数据包添加时间戳，并通过两个通道将添加时间戳后的数据包并行发送至宿端单板；
    所述宿端单板在所述两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中；
    所述宿端单板从所述两个通道的缓存队列中并行读取所述数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理；
    所述宿端单板在对读取的所述两个通道的缓存队列中的数据包对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读取的数据包进行输出。
  2. 如权利要求1所述的方法，其中：
    所述根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中，包括：
    针对每一个通道，在所述通道接收到的数据包的时间戳从最大值变为最小值的情况下，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，将在所述参考时刻之前接收的所有数据包写入所述通道的缓存队列中。
  3. 如权利要求1所述的方法，其中：
    所述根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理，包括：
    在所述两个通道的缓存队列中允许读取的数据包的数量均达到或超过读取阈值的情况下，同时读取所述两个通道的缓存队列，在从所述两个通道的缓存队列中读取的前n个数据包携带的时间戳相同的情况下，确定所述两个通道的缓存队列中读取的数据包对齐。
  4. 如权利要求1所述的方法，其中：
    所述根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理，包括：
    在所述两个通道中的一个通道的缓存队列中允许读取的数据包的数量达到或超过读取阈值，而所述两个通道中的另一个通道的缓存队列中允许读取的数据包的数量为零的情况下，确定所述两个通道的读缓存操作不满足对齐条件。
  5. 如权利要求1所述的方法，其中：
    所述根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中，包括：
    查询每一个通道的告警信息；
    对所述两个通道中的任意一个通道，在未查询到所述通道的告警信息的情况下，触发对所述通道的写缓存处理。
  6. 如权利要求1所述的方法，还包括：
    在所述宿端单板将从所述两个通道中的第一通道的缓存队列中读取的数据包进行输出后，响应于所述第一通道出现告警，将从所述两个通道中的第二通道的缓存队列中读取的数据包进行输出；
    在所述第一通道告警恢复后，重新触发对所述第一通道的缓存队列写操作，以及对所述第一通道和所述第二通道的读缓存操作重新进行对齐处理。
  7. 如权利要求1-6中任一项所述的方法，其中：
    所述两个通道均为高速数据传输Interlaken通道；
    所述数据包为时分复用TDM数据包。
  8. 一种数据输出装置，包括：
    源端单板处理模块，设置为为原始数据包添加时间戳，并通过两个通道将添加所述时间戳后的数据包并行发送至宿端单板处理模块；
    所述宿端单板处理模块，设置为在所述两个通道并行接收所述数据包，根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中；从所述两个通道的缓存队列中并行读取所述数据包，根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理；在对读取的所述两个通道的缓存队列中的数据包对齐成功后，将从所述两个通道中的任意一个通道的缓存队列中读 取的数据包进行输出。
  9. 如权利要求8所述的装置，其中：
    所述宿端单板处理模块，是设置为采用以下方式根据所述数据包携带的时间戳确定写入每一个通道的缓存队列的数据包，并将接收的所述数据包分别写入所述两个通道的缓存队列中：针对每一个通道，在所述通道接收到的数据包的时间戳从最大值变为最小值的情况下，将接收携带所述最小值时间戳的数据包的时刻作为参考时刻，将在所述参考时刻之前接收的所有数据包写入所述通道的缓存队列中。
  10. 如权利要求8所述的装置，其中：
    所述宿端单板处理模块，是设置为采用以下方式根据所述数据包携带的时间戳对所述两个通道的缓存队列中读取的数据包进行对齐处理：在所述两个通道的缓存队列中允许读取的数据包的数量均达到或超过读取阈值的情况下，同时读取所述两个通道的缓存队列，在从所述两个通道的缓存队列中读取的前n个数据包携带的时间戳相同的情况下，确定所述两个通道的缓存队列中读取的数据包对齐。
  11. 一种计算机可读存储介质，所述计算机可读存储介质存储有一个或者多个程序，所述一个或者多个程序可被一个或者多个处理器执行，以实现如权利要求1至7任一项所述的方法。
  12. 一种设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现如权利要求1至7中任一项所述的方法。
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