WO2020125691A1 - 信号处理方法、装置、设备和计算机存储介质 - Google Patents

信号处理方法、装置、设备和计算机存储介质 Download PDF

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WO2020125691A1
WO2020125691A1 PCT/CN2019/126412 CN2019126412W WO2020125691A1 WO 2020125691 A1 WO2020125691 A1 WO 2020125691A1 CN 2019126412 W CN2019126412 W CN 2019126412W WO 2020125691 A1 WO2020125691 A1 WO 2020125691A1
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data
domain
clock recovery
frequency domain
frequency
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PCT/CN2019/126412
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English (en)
French (fr)
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叶晓平
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深圳市中兴微电子技术有限公司
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Priority to KR1020217017788A priority Critical patent/KR102528484B1/ko
Priority to JP2021531472A priority patent/JP7267424B2/ja
Publication of WO2020125691A1 publication Critical patent/WO2020125691A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H04B10/616—Details of the electronic signal processing in coherent optical receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03159—Arrangements for removing intersymbol interference operating in the frequency domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/61—Coherent receivers
    • H04B10/616—Details of the electronic signal processing in coherent optical receivers
    • H04B10/6164—Estimation or correction of the frequency offset between the received optical signal and the optical local oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Definitions

  • Embodiments of the present application relate to signal processing technology of a coherent optical communication system, for example, to a signal processing method, device, device, and computer storage medium.
  • clock recovery and blind equalization are both essential parts of signal processing.
  • blind equalization is usually implemented in the time domain.
  • the amount of calculation performed is large, which increases the power consumption caused by the calculation.
  • the blind equalization process in the time domain It includes two processes: equalizer filtering and equalizer coefficient update.
  • equalizer filtering and equalizer coefficient update When these two processes are implemented in the time domain, the number of complex multiplications that need to be performed is large, which results in increased operation power consumption and brings the application of blind equalization technology.
  • Certain limitations In addition, in coherent optical communication systems, clock recovery and blind equalization are two tightly coupled links. When they are designed independently, there may be repeated operations. For this reason, considering the actual application, it is necessary to jointly design an overall architecture for these two links to reduce repetitive operations, thereby reducing chip power consumption.
  • Embodiments of the present application provide a signal processing method, device, device, and computer storage medium, and perform an overall architectural design on clock recovery and blind equalization, which can implement clock recovery and blind equalization processing in the frequency domain, as well as in the time domain. Compared with the schemes in which clock recovery and blind equalization processing are implemented in each, the calculation amount and operation power consumption are reduced.
  • An embodiment of the present application provides a signal processing method, and the method includes:
  • clock recovery input data For the clock recovery input data, perform frequency domain clock recovery to obtain clock recovery output data;
  • the output data is recovered according to the clock, and blind equalization in the frequency domain is performed to obtain equalized data in the frequency domain.
  • An embodiment of the present application further provides a signal processing device, which includes: an acquisition unit, a first processing unit, and a second processing unit;
  • the acquisition unit is set to acquire clock recovery input data
  • the first processing unit is configured to recover the input data for the clock, perform frequency domain clock recovery, and obtain clock recovery output data;
  • the second processing unit is configured to recover the output data according to the clock and perform frequency-domain blind equalization processing to obtain frequency-domain equalized data.
  • An embodiment of the present application also provides a signal processing device, including: a processor and a memory configured to store a computer program that can be run on the processor; wherein, when the processor is configured to run the computer program, the foregoing Any signal processing method.
  • An embodiment of the present application further provides a computer storage medium that stores a computer program, and when the computer program is executed by a processor, any one of the foregoing signal processing methods is implemented.
  • FIG. 1 is a flowchart of a blind equalization algorithm in the related art
  • FIG. 2 is a flowchart of a signal processing method provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a signal processing method according to an embodiment of the present application.
  • FIG. 5 is a flow chart of a constant modulus algorithm (CMA) filtering provided by an embodiment of the present application
  • FIG. 6 is a flowchart of a coefficient update process provided by an embodiment of the present application.
  • FIG. 10 is a block diagram of another CMA filtering process provided by an embodiment of this application.
  • FIG. 11 is a schematic structural diagram of a signal processing device according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a hardware structure of a signal processing device provided by an embodiment of the present application.
  • FIG. 1 is a flow block diagram of a blind equalization algorithm in the related art, as shown in Figure 1. It shows that in the related art, blind equalization filtering can be realized based on an adaptive algorithm.
  • CMA The common blind equalization algorithm.
  • CMA mainly includes the following two processes: equalizer filtering and equalizer coefficient update, these two processes are performed in the time domain, and the number of complex multiplications required is large.
  • equalizer filtering and equalizer coefficient update these two processes are performed in the time domain, and the number of complex multiplications required is large.
  • clock recovery is also an indispensable link. Due to the inconsistency between the sending clock and the local clock, a certain phase error will occur. The existence of phase error cannot guarantee that each discrete signal sampling is at the optimal sampling position. When the phase error is too large, it will affect the filtering effect of blind equalization and reduce the system performance.
  • Clock recovery and blind equalization are two closely connected modules. When performing blind equalization processing, it is necessary to obtain input data based on the process of clock recovery, and perform fast-domain Fourier transform (Fast Fourier Transformation, FFT) to perform frequency-domain filtering and frequency-domain coefficient update. When performing clock recovery, it is necessary to use blind equalized frequency-domain filtered data for error extraction.
  • FFT Fast-domain Fourier transform
  • the first embodiment of the present application proposes a signal processing method, which can be applied to a coherent optical communication system.
  • FIG. 2 is a flowchart of a signal processing method provided by an embodiment of the present application. As shown in FIG. 2, the process may include:
  • Step 2010 Obtain the clock to restore the input data.
  • Step 2020 Perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data.
  • frequency domain clock recovery In this embodiment, the purpose of frequency domain clock recovery is to recover the data to the optimal sampling position. In practical applications, in classic coherent optical communication systems, clock recovery input data usually comes from dispersion compensation.
  • the data to be phase-detected can be obtained; the phase error value is extracted by phase-detecting the data to be phase-detected; the phase error value is used to interpolate the clock recovery input data, Get clock recovery output data.
  • the clock recovery input data may be subjected to FFT transformation to obtain the frequency domain clock recovery input data
  • the frequency domain clock recovery input data may be subjected to frequency domain blind equalization processing
  • the frequency domain coefficients used at the time are multiplied to obtain the data to be discriminated.
  • the frequency domain equalization data obtained last time may be used as the data to be phase-detected.
  • the Godard phase-detector may be used to phase-detect the data to be phase-detected to extract the phase error value.
  • interpolation processing can be implemented in the time domain or the frequency domain.
  • the interpolation process implemented in the time domain is to perform a finite-length unit impulse response (Finite Impulse Response (FIR) filtering) on the clock recovery input data based on the phase error value (which can be implemented using a FIR filter) to obtain clock recovery output data.
  • FIR Finite Impulse Response
  • the interpolation process implemented in the frequency domain is: FFT transform the clock recovery input data to obtain the clock recovery input data in the frequency domain; in the frequency domain, adjust the phase of the clock recovery input data in the frequency domain to obtain the clock recovery output data .
  • Step 2030 Restore the output data according to the clock, and perform blind equalization processing in the frequency domain to obtain equalized data in the frequency domain.
  • the frequency domain blind equalization input data can be obtained from the clock recovery output data; the frequency domain coefficients can be obtained; the frequency domain blind equalization input data can be multiplied by the frequency domain coefficients to obtain the frequency domain equalization data .
  • the clock recovery output data in the case where the clock recovery output data is data obtained in the time domain, the clock recovery output data may be subjected to FFT transformation to obtain frequency domain blind equalization input data.
  • the clock recovery output data is data obtained in the frequency domain
  • the output data can be recovered according to the frequency domain clock to obtain the frequency domain blind equalization input data.
  • the blind equalization algorithm used for frequency-domain blind equalization processing is not limited.
  • CMA can be used for frequency-domain blind equalization processing.
  • the input data of frequency-domain blind equalization Enter data for the frequency domain CMA.
  • the frequency domain coefficients represent the coefficients needed to perform blind equalization in the frequency domain.
  • time domain coefficients may be acquired, and the time domain coefficients are subjected to FFT transform to obtain frequency domain coefficients.
  • the time domain coefficient can be obtained according to the initial value of the time domain coefficient and the update process of the time domain coefficient, and the initial value of the time domain coefficient can be the set value.
  • the frequency domain equalized data may also be subjected to Inverse Fast Fourier Transform (Inverse Fast Fourier Transformation, IFFT) to obtain time domain equalized data.
  • Inverse Fast Fourier Transform Inverse Fast Fourier Transformation, IFFT
  • the time-domain coefficients can also be updated.
  • time-domain balanced data needs to be obtained.
  • the time-domain equalization data can be used as the basis for carrier synchronization in addition to the coefficient update.
  • the process of updating the time-domain coefficient may include: updating the time-domain coefficient according to the frequency-domain blind equalization input data and the time-domain equalization data to obtain the updated time-domain coefficient.
  • the time-domain equalized data can be error-calculated to obtain time-domain error data; the time-domain error data can be FFT-transformed to obtain frequency-domain error data; and the frequency-domain error data can be shared with the frequency-domain blind equalized input data.
  • the yoke is multiplied to obtain cross-spectral data; the time-domain coefficients are updated according to the cross-spectral data to obtain the updated time-domain coefficients.
  • the cross-spectrum data may be subjected to IFFT transformation to obtain a coefficient adjustment amount; the coefficient adjustment quantity is used to update the time-domain coefficients to obtain an update After the time domain coefficient.
  • the time domain coefficient can be updated according to the frequency domain coefficient update algorithm.
  • the time-domain coefficient may be updated once per beat, or the time-domain coefficient may be updated every few beats.
  • one beat refers to the time for performing frequency domain clock recovery and frequency domain blind equalization processing, that is, for each beat, frequency domain clock recovery and frequency domain blind equalization processing are implemented once.
  • the time-domain coefficients required for frequency-domain blind equalization processing are the updated time-domain coefficients.
  • a processor which can be an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a digital signal processor (Digital Signal Processor, DSP), a digital signal processing device (Digital Signaling Processing Device (DSPD)), Programmable Logic Device (Programmable Logic Device, PLD), Field Programmable Gate Array (Field Programmable Gate Array, FPGA), Central Processing Unit (CPU), controller, microcomputer At least one of a controller and a microprocessor.
  • ASIC Application Specific Integrated Circuit
  • DSP Digital Signal Processor
  • DSPD Digital Signaling Processing Device
  • PLD Programmable Logic Device
  • PLD Field Programmable Gate Array
  • FPGA Field Programmable Gate Array
  • CPU Central Processing Unit
  • controller microcomputer At least one of a controller and a microprocessor.
  • the signal processing method of the embodiment of the present application can realize clock recovery and blind equalization processing in the frequency domain, reducing the computational complexity in the time domain.
  • the frequency domain is implemented in a processor such as a DSP
  • the number of multipliers used by the processor can be saved, thereby reducing operation power consumption.
  • Equalization processing is a comprehensive architectural design, which reduces the repetitive operation part of each design of clock recovery and blind equalization processing.
  • FIG. 3 is a flowchart of a signal processing method provided by an embodiment of the present application.
  • FIG. Domain clock recovery get clock recovery output data.
  • the implementation method of frequency domain clock recovery has been described in the above-mentioned contents, and will not be repeated here.
  • the clock recovery output data can be used for frequency domain CMA equalization.
  • the process of frequency domain CMA equalization may include CMA filtering and coefficient update.
  • the process of coefficient update is the process of updating the time domain coefficients described above, and will not be repeated here.
  • the time-domain equalized data can be obtained through CMA filtering.
  • the time-domain equalized data can be used as the basis for coefficient update.
  • the updated time-domain coefficients obtained through coefficient update can be used as the basis for CMA filtering.
  • the process of CMA filtering may include: obtaining frequency domain CMA input data, performing FFT transformation on the updated time domain coefficients to obtain frequency domain coefficients; multiplying frequency domain CMA input data and frequency domain coefficients to obtain frequency domain balanced data; The frequency domain equalized data is subjected to IFFT transformation, and the frequency domain equalized data is transformed into the time domain to obtain time domain equalized data.
  • the signal processing process of the second embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, wherein the process of frequency domain CMA equalization includes CMA filtering and coefficient update.
  • the frequency domain clock recovery process is implemented by the frequency domain clock recovery module
  • the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module
  • the CMA filtering process is implemented by the CMA filtering submodule
  • the coefficient update process is implemented by the coefficient updating submodule.
  • the input data (clock recovery input data) that needs to be acquired when performing clock recovery in the frequency domain is time domain data with a sampling rate of 1.5 times.
  • FIG. 4 is a flowchart of a frequency domain clock recovery process provided by an embodiment of the present application. As shown in FIG. 4, the frequency domain clock recovery process may include:
  • Step 410 Frequency domain phase detection.
  • the implementation of this step is: using a Godard phase detector to formulate the phase of the multi-band frequency domain equalized data output from the CMA filter sub-module through formula (1), and extract the phase error value according to formula (2).
  • X eq, m (k), Y eq, m (k) are the m-th and k+1 multi-band frequency domain equalization data in the X polarization state and the Y polarization state, respectively, M represents the number of segments, and C represents extraction
  • M represents the number of segments, and C represents extraction
  • the clock signal of, u is the phase error value, N is an integer multiple of 4, and the superscript * indicates conjugation.
  • Step 420 Perform data segmentation, data FFT and data interpolation sequentially.
  • An implementation manner of this step may be: performing interpolation processing on multi-segment frequency domain input data by formula (3) to obtain multi-segment frequency domain interpolation data (that is, the above-mentioned clock recovery output data).
  • the multi-segment frequency domain input data is obtained by segmenting the clock recovery input data of 1.5 times the sampling rate to obtain multi-segment time domain input data with a length of 0.75N; each two adjacent time domain input data overlaps. And the number of overlapping points is not less than the number of taps of the frequency domain CMA equalization coefficient minus one; multi-segment time domain input data is subjected to 0.75N point FFT transformation to obtain multi-segment frequency domain input data.
  • the m-th and k+1th multi-segment frequency domain input data in the X polarization state and the Y polarization state are the X polarization after interpolation processing, respectively.
  • the m-th and k+1th multi-segment interpolation data in the frequency domain and Y polarization state are the m-th and k+1th multi-segment interpolation data in the frequency domain and Y polarization state.
  • FIG. 5 is a block diagram of a CMA filtering process provided by an embodiment of the present application. As shown in FIG. 5, the CMA filtering process may include:
  • Step 510 Obtain the input data of the frequency domain CMA.
  • N/4 0s are inserted in the middle of the multi-segment frequency domain interpolation data, and each data is multiplied by 4/3 to achieve the function of 1.5 times the sampling rate to 2 times the sampling rate, to obtain multi-segment frequency domain CMA input data
  • the input data of the multi-band frequency domain CMA is the input data of the frequency domain CMA.
  • Step 520 Coefficient FFT.
  • the updated time-domain coefficients output by the coefficient update sub-module are subjected to N-point FFT transformation to obtain frequency-domain coefficients.
  • Step 530 Equalization filtering.
  • X m (k) and Y m (k) are the input data of the m-th and k+1 multi-band frequency domain CMA in the X polarization state and the Y polarization state;
  • H xx (k), H xy ( k), H yx (k) and H yy (k) are the k+1th tap values of the 4 sets of frequency domain coefficients.
  • the multi-band frequency domain equalized data in the front and back half is added for aliasing processing, and the function of converting 2 times the sampling rate to 1 time is realized to obtain the multi-band frequency domain equalized data after aliasing.
  • Step 540 Data IFFT.
  • the multi-band frequency-domain equalized data after the aliasing is subjected to an N/2-point IFFT transform to obtain multi-band time-domain equalized data, and then the overlapping data in the multi-band time-domain equalized data is removed and combined, and output to the coefficient updater Modules and subsequent modules of coherent optical communication systems (such as modules that implement carrier synchronization).
  • the coefficient update sub-module takes the input and output of the CMA filter sub-module as its own input, and the coefficient update sub-module outputs the updated equalization coefficient.
  • FIG. 6 is a block diagram of a coefficient update process provided by an embodiment of the present application. As shown in FIG. 6, the coefficient update process may include:
  • Step 610 Error calculation.
  • the overlapped data value of multiple pieces of time-domain equalized data is set to 0, and then multiplied by the difference between a constant and the modulo square of the data to obtain multiple pieces of error data.
  • the number of sections used for coefficient update can be approximately Half of M.
  • Step 620 Error FFT.
  • the N/2-point FFT transformation is performed on the multi-segment error data, and then the result of the FFT transformation is copied and spliced to realize the function of 1 times the sampling rate to 2 times to obtain the multi-segment frequency domain error data.
  • Step 630 Cross-spectrum calculation.
  • the input data of the multi-segment frequency domain CMA and the multi-segment frequency domain error data are conjugated and multiplied by using formula (5) to obtain multi-segment cross-spectrum data.
  • Err x,l (k), Err y,l (k) are the m-th and k+1 multi-segment frequency domain error data in X polarization state and Y polarization state, respectively, ⁇ xx,l (k) , ⁇ xy,l (k), ⁇ yx,l (k) and ⁇ yy,l (k) are multi-segment cross-spectral data.
  • Multi-segment cross-spectrum data is accumulated in turn to obtain total cross-spectrum data.
  • Step 640 Cross-spectrum IFFT.
  • the number of taps of the time-domain coefficients is set to T, N-point IFFT transformation is performed on the total cross-spectral data, and the first T data are taken to obtain the coefficient adjustment amount.
  • Step 650 Coefficient update.
  • an iteration factor is selected, multiplied by the coefficient adjustment amount, and then added correspondingly to the current time-domain coefficient to obtain the updated time-domain coefficient.
  • the 1.5 times sampling rate data is only an exemplary implementation of clock recovery input data.
  • the embodiments of the present application do not limit the sampling rate of clock recovery input data, as long as the clock recovery input data satisfies the data sampling rate greater than 1 times Conditions are sufficient; in the frequency domain CMA equalization process, the data sampling rate is twice.
  • the signal processing process of the third embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, wherein the process of frequency domain CMA equalization includes CMA filtering and coefficient update.
  • the frequency domain clock recovery process is implemented by the frequency domain clock recovery module
  • the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module
  • the CMA filtering process is implemented by the CMA filtering submodule
  • the coefficient update process is implemented by the coefficient updating submodule.
  • the input data (clock recovery input data) that needs to be acquired when performing frequency domain clock recovery is time domain data with a sampling rate of 2 times.
  • FIG. 7 is a flowchart of another frequency domain clock recovery process provided by an embodiment of the present application. As shown in FIG. 7, the frequency domain clock recovery process may include:
  • Step 710 Frequency domain phase detection.
  • formula (1) is used to perform phase discrimination on the multi-band frequency domain equalized data output in the CMA filter sub-module, and the phase error value is extracted according to formula (2).
  • Step 720 Data interpolation and data addition and deletion processing.
  • decimal interpolation pointer u 1 is calculated according to the phase error value u, and the value is the fractional part of 2 ⁇ u.
  • a 6-tap interpolation filter coefficient is calculated from the decimal interpolation pointer.
  • the interpolated data from the current beat and the last part of the interpolated data from the last beat are merged, and the combined data is added or deleted according to the phase error value.
  • the phase error value of the previous beat is u pre , then there are three cases:
  • FIG. 8 is a block diagram of another CMA filtering process provided by an embodiment of the present application. As shown in FIG. 8, the CMA filtering process may include:
  • Step 810 Data segmentation and data FFT.
  • the input data of the frequency domain CMA equalization module is segmented into a total of M segments, each segment has a data length of 2N, and each adjacent two segments of data overlap, and the number of overlapping points is not less than the frequency domain CMA equalization coefficient The number of taps is reduced by one; then the segmentation result is divided into multi-segment time domain odd sequence input data and multi-segment time domain even sequence input data according to the parity index, and N-point FFT transformation is performed to obtain multi-segment frequency domain odd sequence input data and multi-segment frequency Input data for domain even sequence.
  • Step 820 Coefficient FFT.
  • the time domain coefficients output by the coefficient update submodule are divided into time domain odd sequence coefficients and time domain even sequence coefficients according to the parity index, and N-point FFT transform is performed to obtain frequency domain odd sequence coefficients and frequency domain even sequence coefficients. .
  • Step 830 Equalization filtering.
  • multi-segment frequency domain odd sequence input data and multi-segment frequency domain even sequence input data are multiplied with frequency-domain odd sequence coefficients and frequency-domain even sequence coefficients respectively through formula (7) to obtain multi-segment frequency domain balanced data, Realize equalization filtering function.
  • H xx,e (k), H xy,e (k), H yx,e (k) and H yy,e (k) are the kth +1 odd sequence coefficients in frequency domain
  • H xx,o (k), H xy,o (k), H yx,o (k) and H yy,o (k) are the k+1th frequency domain even Sequence coefficients
  • X m,e (k), Y m,e (k) are the m-th k+1 multi-band frequency domain odd sequence input data in the X polarization state and the Y polarization state
  • X m,o ( k), Y m, o (k) are the input data of the m-th k+1 multi-band frequency domain even sequence in the X polarization state and the Y polarization state, respectively.
  • Step 840 Data IFFT.
  • Multi-segment frequency-domain equalization data is subjected to N-point IFFT transformation to obtain multi-segment time-domain equalization data; the overlapping data in the multi-segment time-domain equalization data is removed and combined in the natural order of the index, which is output to the coefficient update sub-module and the coherent optical communication system. Subsequent modules (such as modules that implement carrier synchronization).
  • the coefficient update sub-module takes the input and output of the CMA filter sub-module as its own input, and the coefficient update sub-module outputs the updated equalization coefficient.
  • the flow of coefficient update may include:
  • Step A10 Error calculation.
  • step 610 The implementation of this step is the same as the implementation of step 610, and will not be repeated here.
  • Step A20 Error FFT.
  • N-point FFT transformation is performed on the multi-segment error data to obtain multi-segment frequency domain error data.
  • Step A30 Cross-spectrum calculation.
  • the multi-segment frequency domain odd sequence input data and the multi-segment frequency domain even sequence input data are multiplied by the multi-segment frequency domain error data using formula (8) to obtain multi-segment cross-spectrum data.
  • X e,l (k), Ye,l (k) are the k+1 multi-band frequency domain odd sequence input data in X polarization state and Y polarization state
  • X o,l (k), Y o,l (k) are the input data of the k+1 multi-segment frequency domain odd sequence in X polarization state and Y polarization state
  • ⁇ yy,o,l (k) is the k+1th multi-segment cross-spectral data of the lth segment
  • l is the number of segments used in the coefficient update.
  • Multi-segment cross-spectrum data is accumulated in turn to obtain total cross-spectrum data.
  • Step A40 Cross-spectrum IFFT.
  • step 640 The implementation of this step is the same as the implementation of step 640, and will not be repeated here.
  • Step A50 coefficient update.
  • an iterative factor is selected and multiplied by the coefficient adjustment amount; then the results are added to the corresponding current time-domain odd sequence coefficients and time-domain even sequence coefficients to obtain the updated time-domain odd sequence coefficients and Time-domain even-sequence coefficients; sort and combine the updated time-domain odd-sequence coefficients and time-domain even-sequence coefficients according to the indexed natural sequence to obtain the updated time-domain coefficients.
  • the signal processing process of the fourth embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, wherein the process of frequency domain CMA equalization includes CMA filtering and coefficient update.
  • the frequency domain clock recovery process is implemented by the frequency domain clock recovery module
  • the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module
  • the CMA filtering process is implemented by the CMA filtering submodule
  • the coefficient update process is implemented by the coefficient updating submodule.
  • FIG. 9 is a flowchart of another frequency domain clock recovery process provided by an embodiment of the present application. As shown in FIG. 9, the frequency domain clock recovery process may include:
  • Step 910 Data segmentation, data FFT, pre-filtering and frequency domain phase detection.
  • a Godard phase discriminator is used to discriminate the phase to be discriminated by the formula (1), and the phase error value is obtained according to the formula (2).
  • the way to acquire the phase-to-be-identified data is: first divide the clock recovery input data into segments, each segment is of length N, and perform FFT transformation on the segmented data to obtain multi-segment frequency domain input data, and then multiply the multi-segment frequency domain input data.
  • the frequency domain coefficients obtained by the frequency domain CMA equalization module realize the pre-filtering operation, and then obtain the data to be phase-detected.
  • Step 920 Data interpolation.
  • the multi-segment frequency domain input data is interpolated through formula (9) to obtain the multi-segment frequency domain interpolation data (that is, the aforementioned clock recovery output data), and the multi-segment frequency domain interpolation data is output to the frequency domain CMA equalization module .
  • FIG. 10 is a block diagram of another CMA filtering process provided by an embodiment of the present application. As shown in FIG. 10, the CMA filtering process may include:
  • Step 10010 coefficient FFT.
  • the input data of the frequency domain CMA is obtained, that is, the multi-segment frequency domain interpolation data is obtained.
  • Step 10020 Equalization filtering.
  • the input data of the multi-band frequency domain CMA and the frequency domain coefficients are multiplied by formula (4) to obtain multi-band frequency domain equalized data to realize the equalization filtering function.
  • Step 10030 Data IFFT.
  • the multi-segment frequency-domain equalization data is subjected to N-point IFFT transformation to obtain multi-segment time-domain equalization data; the overlapping data in the multi-segment time-domain equalization data is removed and combined, and output to the coefficient update sub-module and the follow-up of the coherent optical communication system Modules (such as modules that implement carrier synchronization).
  • the coefficient update sub-module takes the input and output of the CMA filter sub-module as its own input, and the coefficient update sub-module outputs the updated equalization coefficient.
  • the flow of coefficient update may include:
  • Step B10 Error calculation.
  • step 610 The implementation of this step is the same as the implementation of step 610, and will not be repeated here.
  • Step B20 Error FFT.
  • N-point FFT transformation is performed on the multi-segment error data to obtain multi-segment frequency domain error data.
  • Step B30 Cross-spectrum calculation.
  • the input data of the multi-segment frequency domain CMA and the multi-segment frequency domain error data are conjugated and multiplied by using formula (5) to obtain multi-segment cross-spectrum data.
  • Multi-segment cross-spectrum data is accumulated in turn to obtain total cross-spectrum data.
  • Step B40 Cross-spectrum IFFT.
  • the number of taps of the time-domain coefficients is set to T, N-point IFFT transformation is performed on the total cross-spectral data, and the first T data are taken to obtain the coefficient adjustment amount.
  • Step B50 coefficient update.
  • an iteration factor is selected, multiplied by the coefficient adjustment amount, and then added correspondingly to the current time-domain coefficient to obtain the updated time-domain coefficient.
  • the frequency domain CMA equalization method in the embodiment of the present application is different from the CMA algorithm in the related art.
  • the CMA filtering process and coefficient updating process can use FFT transform to transform the data into the frequency domain, and then directly in the frequency domain Multiply.
  • Implementing CMA equalization in the frequency domain reduces the computational complexity when implementing in the time domain.
  • Table 1 is a comparison table of the number of complex multiplications of the CMA time-frequency domain equalization method in multiple modes. Referring to Table 1, the number of complex multiplications required by the frequency-domain CMA method is indeed less than the time-domain CMA scheme, which saves about 50%. Computing resources, therefore, applying the chip of the embodiment of the present application can save computing power consumption.
  • the fifth embodiment of the present application proposes a signal processing apparatus, which can be applied to a coherent optical communication system.
  • FIG. 11 is a schematic structural diagram of a signal processing device according to an embodiment of the present application.
  • the device includes an acquisition unit 1101, a first processing unit 1102, and a second processing unit 1103, where the acquisition unit 1101 Is set to obtain clock recovery input data; the first processing unit 1102 is set to perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data; the second processing unit 1103 is set to recover according to the clock Output data and perform blind equalization in the frequency domain to obtain frequency-domain equalized data.
  • the first processing unit 1102 is configured to acquire data to be phase-detected; by phase-identifying the data to be phase-detected, a phase error value is extracted; using the phase error value pair
  • the clock recovery input data is interpolated to obtain the clock recovery output data.
  • the first processing unit 1102 is configured to acquire the data to be phase-detected by transforming the clock recovery input data into the frequency domain to obtain the clock recovery input data in the frequency domain Multiplying the frequency-domain clock recovery input data by the frequency-domain coefficients used in the frequency-domain blind equalization process to obtain the data to be phase-identified; or, using the frequency-domain equalization data obtained last time as the phase-to-be-identified The data.
  • the first processing unit 1102 is configured to interpolate the clock recovery input data by using the phase error value as follows to obtain clock recovery output data: in the time domain, according to the The phase error value performs a finite-length unit impulse response FIR filtering on the clock recovery input data to obtain clock recovery output data; or, transforms the clock recovery input data into the frequency domain to obtain clock recovery input data in the frequency domain; In the frequency domain, the clock recovery input data in the frequency domain is phase-adjusted to obtain clock recovery output data.
  • the second processing unit 1103 is configured to obtain frequency domain blind equalization input data according to the clock recovery output data; obtain frequency domain coefficients; and combine the frequency domain blind equalization input data with the frequency The domain coefficients are multiplied to obtain the frequency domain equalized data.
  • the second processing unit 1103 is configured to obtain frequency-domain blind equalization input data according to the clock recovery output data in the following manner: the clock recovery output data is data obtained in the time domain In the case of, by converting the clock recovery output data into the frequency domain, the frequency domain blind equalization input data is obtained; in the case where the clock recovery output data is data obtained in the frequency domain, the frequency domain The clock recovery output data is the frequency domain blind equalization input data.
  • the second processing unit 1103 is configured to acquire frequency domain coefficients by acquiring time domain coefficients, transforming the time domain coefficients to the frequency domain, and obtaining the frequency domain coefficients.
  • the second processing unit 1103 is further configured to transform the frequency-domain equalized data to the time domain after obtaining the frequency-domain equalized data to obtain time-domain equalized data.
  • the second processing unit 1103 is further configured to update the time-domain coefficients according to the frequency-domain blind equalization input data and the time-domain equalization data to obtain the updated time-domain coefficients.
  • the second processing unit 1103 is configured to update the time-domain coefficients according to the frequency-domain blind equalization input data and the time-domain equalization data in the following manner to obtain the updated Time domain coefficient: perform error calculation on time domain equalized data to obtain time domain error data; transform the time domain error data to frequency domain to obtain frequency domain error data; blind the frequency domain error data from the frequency domain
  • the equalized input data is conjugated and multiplied to obtain cross-spectrum data; the time-domain coefficients are updated according to the cross-spectrum data to obtain the updated time-domain coefficients.
  • the second processing unit 1103 is configured to update the time-domain coefficients according to the cross-spectrum data in the following manner to obtain updated time-domain coefficients: transform the cross-spectrum data Go to the time domain to obtain the coefficient adjustment amount; use the coefficient adjustment amount to update the time domain coefficient to obtain the updated time domain coefficient.
  • the acquisition unit 1101, the first processing unit 1102, and the second processing unit 1103 may be implemented by a CPU, a microprocessor (MPU), a DSP, an FPGA, etc. in a coherent optical communication system.
  • MPU microprocessor
  • DSP digital signal processor
  • FPGA field-programmable gate array
  • multiple functional modules in this embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or software function modules.
  • the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • Parts can be embodied in the form of software products, which are stored in a storage medium and include multiple instructions to make a computer device (which can be a personal computer, server, or network device, etc.) or processor (processor ) Perform all or part of the steps of the method described in this embodiment.
  • the aforementioned storage media include: Universal Serial Bus (Universal Serial Bus, U disk), mobile hard disk, read only memory (Read Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk Or a variety of media such as optical discs that can store program codes.
  • the computer program instructions corresponding to a signal processing method in this embodiment may be stored on storage media such as optical disks, hard disks, U disks, etc.
  • storage media such as optical disks, hard disks, U disks, etc.
  • the apparatus may include: a memory 121 and a processor 122; wherein, the memory 121 is configured as Store a computer program and data; the processor 122 is configured to execute the computer program stored in the memory to implement any signal processing method of the foregoing embodiment.
  • the above-mentioned memory 121 may be volatile memory (volatile memory), such as RAM; or non-volatile memory (non-volatile memory), such as ROM, flash memory (flash memory), hard disk (Hard Disk) Drive (HDD) or Solid-State Drive (SSD); or a combination of the above types of memory, and provides instructions and data to the processor 122.
  • volatile memory such as RAM
  • non-volatile memory non-volatile memory
  • ROM read-only memory
  • flash memory flash memory
  • HDD hard disk
  • SSD Solid-State Drive
  • the processor 122 may be at least one of ASIC, DSP, DSPD, PLD, FPGA, CPU, controller, microcontroller, and microprocessor.
  • ASIC application specific integrated circuit
  • DSP digital signal processor
  • DSPD digital signal processor
  • PLD PLD
  • FPGA field-programmable gate array
  • CPU central processing unit
  • controller microcontroller
  • microprocessor microprocessor
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer usable program code.
  • a computer usable storage media including but not limited to disk storage and optical storage, etc.
  • These computer program instructions may also be stored in a computer readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, the instructions
  • the device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and/or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device
  • the instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and/or block diagrams.

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Abstract

本文公开了一种信号处理方法、装置、设备和计算机存储介质，该方法包括：获取时钟恢复输入数据；针对所述时钟恢复输入数据，进行频域时钟恢复，得到时钟恢复输出数据；根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。

Description

信号处理方法、装置、设备和计算机存储介质
本申请要求在2018年12月18日提交中国专利局、申请号为201811549215.3的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及相干光通信系统的信号处理技术，例如涉及一种信号处理方法、装置、设备和计算机存储介质。
背景技术
在相干光通信系统中，时钟恢复和盲均衡都是信号处理的必不可少的环节。在相关技术中，通常在时域中实现盲均衡，在时域中实现盲均衡时，所进行的运算量较大，增加了运算带来的功耗，例如，时域中的盲均衡处理过程包括均衡器滤波和均衡器系数更新两个过程，这两个过程在时域中实现时，所需进行的复乘个数较多，导致增加了运算功耗，为盲均衡技术的应用带来一定的局限性。另外，在相干光通信系统中，时钟恢复和盲均衡是两个紧密耦合的环节，当它们独自设计时，可能会存在重复的操作。为此，考虑到实际的应用，需要对这两个环节联合设计一个整体的架构，减少重复操作，从而降低芯片功耗。
发明内容
本申请实施例提供了一种信号处理方法、装置、设备和计算机存储介质，对时钟恢复和盲均衡进行一个整体的架构设计，能够在频域中实现时钟恢复和盲均衡处理，与在时域中各自实现时钟恢复和盲均衡处理的方案相比，降低了运算量和运算功耗。
本申请实施例提供了一种信号处理方法，所述方法包括：
获取时钟恢复输入数据；
针对所述时钟恢复输入数据，进行频域时钟恢复，得到时钟恢复输出数据；
根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
本申请实施例还提供了一种信号处理装置，所述装置包括：获取单元、第一处理单元和第二处理单元；
获取单元，设置为获取时钟恢复输入数据；
第一处理单元，设置为针对所述时钟恢复输入数据，进行频域时钟恢复， 得到时钟恢复输出数据；
第二处理单元，设置为根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
本申请实施例还提供了一种信号处理设备，包括：处理器和设置为存储能够在处理器上运行的计算机程序的存储器；其中，所述处理器设置为运行所述计算机程序时，执行上述任意一种信号处理方法。
本申请实施例还提供了一种计算机存储介质，存储有计算机程序，该计算机程序被处理器执行时实现上述任意一种信号处理方法。
附图说明
图1为相关技术中一种盲均衡算法的流程框图；
图2为本申请实施例提供的一种信号处理方法的流程图；
图3为本申请实施例提供的一种信号处理方法的流程框图；
图4为本申请实施例提供的一种频域时钟恢复的流程框图；
图5为本申请实施例提供的一种恒模算法(Constant Modulus Algorithm，CMA)滤波的流程框图；
图6为本申请实施例提供的一种系数更新的流程框图；
图7为本申请实施例提供的另一种频域时钟恢复的流程框图；
图8为本申请实施例提供的另一种CMA滤波的流程框图；
图9为本申请实施例提供的另一种频域时钟恢复的流程框图；
图10为本申请实施例提供的另一种CMA滤波的流程框图；
图11为本申请实施例提供的一种信号处理装置的组成结构示意图；
图12为本申请实施例提供的一种信号处理设备的硬件结构示意图。
具体实施方式
以下结合附图及实施例，对本申请进行说明。此处所描述的实施例仅仅用以解释本申请，并不用于限定本申请。
在相干光通信系统中，两个相互垂直的偏振模在光纤传输时由于光纤椭圆度、压力等原因造成传输速度不相同，会呈现双折射效应，从而引起偏振模色散(Polarization Mode Dispersion，PMD)，导致接收端误码率增大，降低通信系统性能。
为了补偿偏振模色散，以及匹配时变或未知信道的特征，通常采用自适应的均衡方法，及时更新均衡器系数，来提高信号的跟踪能力，增强补偿效果。盲均衡算法作为自适应均衡方法的其中一种，因不需要额外训练序列和提高信道利用率的优点而被广泛运用；图1为相关技术中一种盲均衡算法的流程框图，如图1所示，相关技术中，可以基于自适应算法实现盲均衡滤波。
常见的盲均衡算法为CMA，在CMA提出后，大量学者对该算法进行改进或运用。相关技术中，CMA主要包括以下两个过程：均衡器滤波和均衡器系数更新，这两个过程都在时域进行，所需进行的复乘个数多，实际应用中，通过芯片实现CMA时，会增大芯片的运算功耗，因而，有一定的局限性。
此外在相干光通信系统中，时钟恢复也是一个必不可少的环节。由于发送端时钟和本地时钟不一致，会产生一定的相位误差。相位误差的存在无法保证每次离散信号采样都在最佳采样位置上，当相位误差过大时会影响盲均衡的滤波效果，降低系统性能。时钟恢复和盲均衡是两个紧密相连的模块。进行盲均衡处理时需要基于时钟恢复的过程获取输入数据，并通过快速傅里叶变换(Fast Fourier Transformation，FFT)，进行频域滤波和频域系数更新。进行时钟恢复时，需要使用盲均衡频域滤波后的数据进行误差提取。当实现时钟恢复和盲均衡的两模块独自设计时，两个模块可能会存在重复的处理过程。为此，考虑到实际的应用，需要对这两个模块联合设计一个整体的架构，以减少两模块独自设计时存在的重复处理过程，从而降低进行运算的芯片的功耗。
基于上述记载的内容，提出以下实施例。
第一实施例
本申请第一实施例提出了一种信号处理方法，可以应用于相干光通信系统中。
图2为本申请实施例提供的一种信号处理方法的流程图，如图2所示，该流程可以包括：
步骤2010：获取时钟恢复输入数据。
步骤2020：针对所述时钟恢复输入数据，进行频域时钟恢复，得到时钟恢复输出数据。
本实施例中，进行频域时钟恢复的目的在于将数据恢复到最佳采样位置上。实际应用中，在经典的相干光通信系统中，时钟恢复输入数据通常来自色散补偿。
对于本步骤的实现方式，示例性地，可以获取待鉴相的数据；通过对待鉴相的数据进行鉴相，提取出相位误差值；利用该相位误差值对时钟恢复输入数据进行内插处理，得到时钟恢复输出数据。
对于获取待鉴相的数据的实现方式，在一个示例中，可以将时钟恢复输入数据进行FFT变换，得到频域的时钟恢复输入数据，将频域的时钟恢复输入数据与进行频域盲均衡处理时使用的频域系数相乘，得到待鉴相的数据。
对于获取待鉴相的数据的实现方式，在另一个示例中，可以将上一次得到的频域均衡数据作为所述待鉴相的数据。
作为一种实现方式，在获取待鉴相的数据后，可以利用Godard鉴相器对待鉴相的数据进行鉴相，以提取出相位误差值。
对于内插处理的实现方式，可以在时域或频域实现。
在时域实现的内插处理过程为：根据相位误差值对时钟恢复输入数据进行有限长单位冲激响应(Finite Impulse Response，FIR)滤波(可以利用FIR滤波器实现)，得到时钟恢复输出数据。
在频域实现的内插处理过程为：将时钟恢复输入数据进行FFT变换，得到频域的时钟恢复输入数据；在频域，对频域的时钟恢复输入数据进行相位调整，得到时钟恢复输出数据。
步骤2030：根据时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
对于本步骤的实现方式，在一个示例中，可以根据时钟恢复输出数据得到频域盲均衡输入数据；获取频域系数；将频域盲均衡输入数据与频域系数相乘，得到频域均衡数据。
本申请实施例中，在时钟恢复输出数据为在时域得出的数据的情况下，可以通过将时钟恢复输出数据进行FFT变换，得到频域盲均衡输入数据。
在时钟恢复输出数据为在频域得出的数据的情况下，可以根据频域的时钟恢复输出数据，得到所述频域盲均衡输入数据。
实际应用中，并不对进行频域盲均衡处理使用的盲均衡算法进行限定，例如，可以采用CMA进行频域盲均衡处理，在采用CMA进行频域盲均衡处理时，频域盲均衡输入数据记为频域CMA输入数据。
一实施例中，频域系数表示进行频域盲均衡处理所需使用的系数。对于获取频域系数的实现方式，示例性地，可以获取时域系数，将时域系数进行FFT变换，得到频域系数。时域系数可以根据时域系数的初始值和时域系数的更新 流程获得，时域系数的初始值可以是设定值。
一实施例中，在得到频域均衡数据后，还可以将频域均衡数据进行逆向快速傅里叶变换(Inverse Fast Fourier Transformation，IFFT)，得到时域均衡数据。
本申请实施例中，还可以对时域系数进行更新，在对时域系数进行更新时，需要获取时域均衡数据。实际应用中，在经典的相干光通信系统中，时域均衡数据除了用于实现系数更新外，还可以作为载波同步的依据。
作为一种实现方式，对时域系数进行更新的过程可以包括：根据频域盲均衡输入数据和时域均衡数据，对时域系数进行更新，得到更新后的时域系数。
一实施例中，可以对时域均衡数据进行误差计算，得到时域误差数据；将时域误差数据进行FFT变换，得到频域误差数据；将频域误差数据与频域盲均衡输入数据进行共轭相乘，得到互谱数据；根据互谱数据对时域系数进行更新，得到更新后的时域系数。
对于根据所述互谱数据对所述时域系数进行更新的实现方式，示例性地，可以将互谱数据进行IFFT变换，得到系数调整量；使用系数调整量对时域系数进行更新，得到更新后的时域系数。实际应用中，在得到系数调整量后，可以按照频域系数更新算法，对时域系数进行更新。
本实施例中，可以每拍对时域系数进行一次更新，也可以每隔几拍更新一次时域系数。本实施例中，一拍指的是进行一次频域时钟恢复和频域盲均衡处理的时间，即，每一拍，就实现一次频域时钟恢复和频域盲均衡处理。
实际应用中，在每次更新时域系数后，频域盲均衡处理所需要获取的时域系数为更新后的时域系数。
实际应用中，上述步骤2010至步骤2030可以由处理器实现，上述处理器可以为特定用途集成电路(Application Specific Integrated Circuit，ASIC)、数字信号处理器(Digital Signal Processor，DSP)、数字信号处理装置(Digital Signal Processing Device，DSPD)、可编程逻辑装置(Programmable Logic Device，PLD)、现场可编程门阵列(Field Programmable Gate Array，FPGA)、中央处理器(Central Processing Unit，CPU)、控制器、微控制器、微处理器中的至少一种。
与相关技术相比，采用本申请实施例的信号处理方法，可以在频域实现时钟恢复和盲均衡处理，减少了在时域实现的计算复杂度，当在处理器如DSP中实现频域的时钟恢复和盲均衡处理时，与在时域实现的频域的时钟恢复和盲均衡处理过程相比，可以节省处理器使用的乘法器个数，从而降低运算功耗，通过对时钟恢复和盲均衡处理进行综合的架构设计，减少了时钟恢复和盲均衡处理各自设计存在的重复操作部分。
基于上述记载的内容，下面通过图3对本申请实施例的实现流程进行直观地说明；图3为本申请实施例提供的一种信号处理方法的流程框图，如图3所示，可以首先进行频域时钟恢复，得到时钟恢复输出数据。频域时钟恢复的实现方式已经在上述记载的内容中作出说明，这里不再赘述。
在得到时钟恢复输出数据后，可以利用时钟恢复输出数据进行频域CMA均衡，频域CMA均衡的过程可以包括CMA滤波和系数更新。系数更新的过程为上述记载的时域系数更新的过程，这里不再赘述。通过CMA滤波可以得到时域均衡数据，该时域均衡数据可以作为系数更新的依据，通过系数更新得到的更新后的时域系数可以用作CMA滤波的依据。
CMA滤波的过程可以包括：获取频域CMA输入数据，对更新后的时域系数进行FFT变换，得到频域系数；将频域CMA输入数据与频域系数相乘，得到频域均衡数据；对频域均衡数据进行IFFT变换，将频域均衡数据变换到时域，得到时域均衡数据。
第二实施例
为了能够体现本申请的目的，在本申请第一实施例的基础上，进行举例说明。
本申请第二实施例的信号处理过程包括频域时钟恢复和频域CMA均衡两个过程，其中，频域CMA均衡的过程包括CMA滤波和系数更新。频域时钟恢复过程由频域时钟恢复模块实现，频域CMA均衡过程由频域CMA均衡模块实现，CMA滤波过程由CMA滤波子模块实现，系数更新过程由系数更新子模块实现。
本申请第二实施例中，进行频域时钟恢复时所需获取的输入数据(时钟恢复输入数据)为1.5倍采样率的时域数据。
图4为本申请实施例提供的一种频域时钟恢复的流程框图，如图4所示，频域时钟恢复的流程可以包括：
步骤410：频域鉴相。
本步骤的实现方式为：利用Godard鉴相器通过公式(1)对CMA滤波子模块中输出的多段频域均衡数据进行鉴相，并根据公式(2)提取相位误差值。
Figure PCTCN2019126412-appb-000001
Figure PCTCN2019126412-appb-000002
其中，X eq,m(k)、Y eq,m(k)分别是X偏振态、Y偏振态下的第m段、第k+1个多段频域均衡数据，M表示段数，C表示提取的时钟信号，u为相位误差值，N为4的整数倍，上标*表示共轭。
步骤420：依次进行数据分段、数据FFT和数据内插。
本步骤的一种实现方式可以为：通过公式(3)对多段频域输入数据进行内插处理，得到多段频域插值数据(即上述时钟恢复输出数据)。多段频域输入数据通过如下方式得到：将1.5倍采样率的时钟恢复输入数据进行分段，得到每段长度为0.75N的多段时域输入数据；每相邻两段时域输入数据有重叠，且重叠点数不少于频域CMA均衡系数的抽头个数减一；将多段时域输入数据进行0.75N点FFT变换，得到多段频域输入数据。
Figure PCTCN2019126412-appb-000003
Figure PCTCN2019126412-appb-000004
其中，
Figure PCTCN2019126412-appb-000005
分别为X偏振态、Y偏振态下的第m段、第k+1个多段频域输入数据，X cr,m(k)、Y cr,m(k)分别为内插处理后的X偏振态、Y偏振态下的第m段、第k+1个多段频域插值数据。
图5为本申请实施例提供的一种CMA滤波的流程框图，如图5所示，CMA滤波的流程可以包括：
步骤510：获取频域CMA的输入数据。
一实施例中，在多段频域插值数据的中间位置插入N/4个0、每个数据乘以4/3，实现1.5倍采样率转2倍采样率的功能，得到多段频域CMA输入数据，这里的多段频域CMA输入数据为上述频域CMA的输入数据。
步骤520：系数FFT。
一实施例中，将系数更新子模块输出的更新后的时域系数进行N点FFT变换，得到频域系数。
步骤530：均衡滤波。
通过公式(4)，将多段频域CMA的输入数据和频域系数各自相乘，得到多段频域均衡数据，实现均衡滤波功能。
X eq,m(k)＝X m(k)·H xx(k)+Y m(k)·H xy(k)
Y eq,m(k)＝X m(k)·H yx(k)+Y m(k)·H yy(k),k＝0,1,...,N-1   (4)
其中，X m(k)、Y m(k)分别是X偏振态、Y偏振态下的第m段、第k+1个多段频域CMA的输入数据；H xx(k)、H xy(k)、H yx(k)和H yy(k)是4组频域系数的第k+1个抽头值。
将前后半段的多段频域均衡数据相加进行混叠处理，实现2倍采样率转1倍的功能，得到混叠后的多段频域均衡数据。
步骤540：数据IFFT。
一实施例中，将混叠后的多段频域均衡数据进行N/2点IFFT变换，得到多段时域均衡数据，再剔除多段时域均衡数据中的重叠数据并进行组合，输出给系数更新子模块及相干光通信系统的后续模块(例如实现载波同步的模块)。
本申请实施例中，系数更新子模块将CMA滤波子模块的输入和输出作为自身的输入，系数更新子模块输出更新后的均衡系数。
图6为本申请实施例提供的一种系数更新的流程框图，如图6所示，系数更新的流程可以包括：
步骤610：误差计算。
一实施例中，对多段时域均衡数据的重叠数据值置0，再乘以一常数与该数据模平方的差，得到多段误差数据，为减少计算量，用于系数更新的段数可约为M的一半。
步骤620：误差FFT。
一实施例中，对多段误差数据进行N/2点FFT变换，再对FFT变换的结果进行复制并拼接，实现1倍采样率转2倍的功能，得到多段频域误差数据。
步骤630：互谱计算。
一实施例中，利用公式(5)，将多段频域CMA的输入数据与多段频域误差数据共轭相乘，得到多段互谱数据。
Figure PCTCN2019126412-appb-000006
Figure PCTCN2019126412-appb-000007
Figure PCTCN2019126412-appb-000008
Figure PCTCN2019126412-appb-000009
其中，Err x,l(k)、Err y,l(k)分别为X偏振态、Y偏振态下的第m段、第k+1个多段频域误差数据，Γ xx,l(k)、Γ xy,l(k)、Γ yx,l(k)和Γ yy,l(k)为多段互谱数据。
对多段互谱数据依次进行多段累加，得到总互谱数据。
步骤640：互谱IFFT。
一实施例中，设时域系数的抽头个数为T，对总互谱数据进行N点IFFT变换，并取前T个数据，得到系数调整量。
步骤650：系数更新。
一实施例中，选择一迭代因子，分别与系数调整量相乘，再与当前时域系数对应相加，得到更新后的时域系数。
1.5倍采样率的数据仅仅是时钟恢复输入数据的一种示例性的实现方式，本申请实施例并不对时钟恢复输入数据的采样率进行限定，只要时钟恢复输入数据满足数据采样率大于1倍的条件即可；在频域CMA均衡过程中，数据的采样率为2倍。
第三实施例
为了能够体现本申请的目的，在本申请第一实施例的基础上，进行举例说明。
本申请第三实施例的信号处理过程包括频域时钟恢复和频域CMA均衡两个过程，其中，频域CMA均衡的过程包括CMA滤波和系数更新。频域时钟恢复过程由频域时钟恢复模块实现，频域CMA均衡过程由频域CMA均衡模块实现，CMA滤波过程由CMA滤波子模块实现，系数更新过程由系数更新子模块实现。
本申请第三实施例中，进行频域时钟恢复时所需获取的输入数据(时钟恢复输入数据)为2倍采样率的时域数据。
图7为本申请实施例提供的另一种频域时钟恢复的流程框图，如图7所示，频域时钟恢复的流程可以包括：
步骤710：频域鉴相。
一实施例中，使用公式(1)，对CMA滤波子模块中输出的多段频域均衡数据进行鉴相，并根据公式(2)提取相位误差值。
步骤720：数据内插以及数据增删处理。
一实施例中，根据相位误差值u计算小数插值指针u 1，且该值为2·u的小数部分。
根据公式(6)，由小数插值指针计算6抽头的插值滤波器系数。
Figure PCTCN2019126412-appb-000010
将至少一拍前的时钟恢复输入数据与其之后一拍时钟恢复输入数据的前8个数据进行拼接，得到拼接数据；对拼接数据与插值滤波器h卷积在时域实现数据内插，得到插值数据(即上述时钟恢复输出数据)。
当前拍得到的插值数据与上一拍得到的插值数据末尾部分进行合并，并根据相位误差值对合并数据进行增删处理，记上一拍的相位误差值为u pre，则有以下三种情况：
1)当u＞0.5,u pre＜0.5,u-u pre＞0.5时，直接输出合并数据给频域CMA均衡模块。
2)当u＜0.5,u pre＞0.5,u-u pre＞0.5时，删除合并数据的开头2个数据并输出给频域CMA均衡模块。
3)在不满足以上情况1)和情况2)时(除去情况1)和情况2)外的其余情况)，则删除合并数据的开头1个数据并给频域CMA均衡模块。
图8为本申请实施例提供的另一种CMA滤波的流程框图，如图8所示，CMA滤波的流程可以包括：
步骤810：数据分段及数据FFT。
一实施例中，对频域CMA均衡模块的输入数据进行分段，共M段，每段数据长度为2N，每相邻两段数据有重叠，且重叠点数不少于频域CMA均衡系数的抽头个数减一；再将其分段结果按奇偶索引分成多段时域奇序列输入数据 和多段时域偶序列输入数据，并进行N点FFT变换，得到多段频域奇序列输入数据和多段频域偶序列输入数据。
步骤820：系数FFT。
一实施例中，将系数更新子模块输出的时域系数按奇偶索引分成时域奇序列系数和时域偶序列系数，并进行N点FFT变换，得到频域奇序列系数和频域偶序列系数。
步骤830：均衡滤波。
一实施例中，通过公式(7)，将多段频域奇序列输入数据、多段频域偶序列输入数据与频域奇序列系数、频域偶序列系数分别相乘，得到多段频域均衡数据，实现均衡滤波功能。
X eq,m(k)＝X m,e(k)·H xx,e(k)+Y m,e(k)·H xy,e(k)
+X m,o(k)·H xx,o(k)+Y m,o(k)·H xy,o(k)
Y eq,m(k)＝X m,e(k)·H yx,e(k)+Y m,e(k)·H yy,e(k)     (7)
+X m,o(k)·H yx,o(k)+Y m,o(k)·H yy,o(k)
其中，k＝0,1,..,N-1，H xx,e(k)、H xy,e(k)、H yx,e(k)和H yy,e(k)分别为第k+1个频域奇序列系数，H xx,o(k)、H xy,o(k)、H yx,o(k)和H yy,o(k)分别为第k+1个频域偶序列系数；X m,e(k)、Y m,e(k)分别为X偏振态、Y偏振态下的第m段第k+1个多段频域奇序列输入数据，X m,o(k)、Y m,o(k)分别为X偏振态、Y偏振态下的第m段第k+1个多段频域偶序列输入数据。
步骤840：数据IFFT。
将多段频域均衡数据进行N点IFFT变换，得到多段时域均衡数据；剔除多段时域均衡数据中的重叠数据并按索引的自然顺序进行组合，输出给系数更新子模块及相干光通信系统的后续模块(例如实现载波同步的模块)。
本申请实施例中，系数更新子模块将CMA滤波子模块的输入和输出作为自身的输入，系数更新子模块输出更新后的均衡系数。
本申请第三实施例中，参照图6，系数更新的流程可以包括：
步骤A10：误差计算。
本步骤的实现方式与步骤610的实现方式相同，这里不再赘述。
步骤A20：误差FFT。
一实施例中，对多段误差数据进行N点FFT变换，得到多段频域误差数据。
步骤A30：互谱计算。
一实施例中，利用公式(8)，将多段频域奇序列输入数据、多段频域偶序列输入数据与多段频域误差数据共轭相乘，得到多段互谱数据。
Figure PCTCN2019126412-appb-000011
其中，X e,l(k)、Y e,l(k)分别为X偏振态、Y偏振态下的第k+1个多段频域奇序列输入数据，X o,l(k)、Y o,l(k)分别为X偏振态、Y偏振态下的第k+1个多段频域奇序列输入数据，Γ xx,e,l(k)、Γ xx,o,l(k)、Γ xy,e,l(k)、Γ xy,o,l(k)、Γ yx,e,l(k)、Γ yx,o,l(k)、Γ yy,e,l(k)和Γ yy,o,l(k)为第l段第k+1个多段互谱数据，l为系数更新中的使用段数。
对多段互谱数据依次进行多段累加，得到总互谱数据。
步骤A40：互谱IFFT。
本步骤的实现方式与步骤640的实现方式相同，这里不再赘述。
步骤A50：系数更新。
一实施例中，选择一迭代因子，分别与系数调整量相乘；再将结果与各自对应的当前时域奇序列系数、时域偶序列系数相加，得到更新后的时域奇序列系数和时域偶序列系数；按索引的自然序列对更新后的时域奇序列系数和时域偶序列系数进行排序组合，得到更新后的时域系数。
第四实施例
为了能够体现本申请的目的，在本申请第一实施例的基础上，进行举例说明。
本申请第四实施例的信号处理过程包括频域时钟恢复和频域CMA均衡两个过程，其中，频域CMA均衡的过程包括CMA滤波和系数更新。频域时钟恢复过程由频域时钟恢复模块实现，频域CMA均衡过程由频域CMA均衡模块实现，CMA滤波过程由CMA滤波子模块实现，系数更新过程由系数更新子模块实现。
图9为本申请实施例提供的另一种频域时钟恢复的流程框图，如图9所示，频域时钟恢复的流程可以包括：
步骤910：数据分段、数据FFT、预滤波和频域鉴相。
一实施例中，使用Godard鉴相器通过公式(1)对待鉴相数据进行鉴相，并根据公式(2)得到相位误差值。待鉴相数据的获取方式为：先将时钟恢复输入数据进行分段，每段长度为N，并对分段数据进行FFT变换得到多段频域输入数据，然后对该多段频域输入数据乘以频域CMA均衡模块得到的频域系数实现预滤波操作，进而得到待鉴相数据。
步骤920：数据内插。
一实施例中，通过公式(9)对多段频域输入数据进行内插处理，得到多段频域插值数据(即上述时钟恢复输出数据)，并将多段频域插值数据输出给频域CMA均衡模块。
Figure PCTCN2019126412-appb-000012
Figure PCTCN2019126412-appb-000013
图10为本申请实施例提供的另一种CMA滤波的流程框图，如图10所示，CMA滤波的流程可以包括：
步骤10010：系数FFT。
一实施例中，获取频域CMA的输入数据，即，获取多段频域插值数据。将系数更新子模块输出的更新后的时域系数进行N点FFT变换，得到频域系数。
步骤10020：均衡滤波。
一实施例中，通过公式(4)，将多段频域CMA的输入数据和频域系数各自相乘，得到多段频域均衡数据，实现均衡滤波功能。
步骤10030：数据IFFT。
一实施例中，将多段频域均衡数据进行N点IFFT变换，得到多段时域均衡数据；剔除多段时域均衡数据中的重叠数据并组合，输出给系数更新子模块及相干光通信系统的后续模块(例如实现载波同步的模块)。
本申请实施例中，系数更新子模块将CMA滤波子模块的输入和输出作为自身的输入，系数更新子模块输出更新后的均衡系数。
本申请第四实施例中，参照图6，系数更新的流程可以包括：
步骤B10：误差计算。
本步骤的实现方式与步骤610的实现方式相同，这里不再赘述。
步骤B20：误差FFT。
一实施例中，对多段误差数据进行N点FFT变换，得到多段频域误差数据。
步骤B30：互谱计算。
一实施例中，利用公式(5)，将多段频域CMA的输入数据与多段频域误差数据共轭相乘，得到多段互谱数据。对多段互谱数据依次进行多段累加，得到总互谱数据。
步骤B40：互谱IFFT。
一实施例中，设时域系数的抽头个数为T，对总互谱数据进行N点IFFT变换，并取前T个数据，得到系数调整量。
步骤B50：系数更新。
一实施例中，选择一迭代因子，分别与系数调整量相乘，再与当前时域系数对应相加，得到更新后的时域系数。
本申请实施例的频域CMA均衡方法，不同于相关技术中的CMA算法，在本申请实施例中，CMA滤波过程和系数更新过程可以利用FFT变换将数据变换到频域，进而在频域直接相乘的方式实现。在频域实现CMA均衡减少了在时域实现时的计算复杂度。
表1为多种模式下CMA时频域均衡方法的复乘个数对比表，参照表1，频域CMA方法所需的复乘个数确实比时域CMA方案更少，约节省50％的运算资源，因此，应用本申请实施例的芯片可以节省运算功耗。
表1
Figure PCTCN2019126412-appb-000014
Figure PCTCN2019126412-appb-000015
第五实施例
在本申请前述实施例提出的信号处理方法的基础上，本申请第五实施例提出了一种信号处理装置，可以应用于相干光通信系统中。
图11为本申请实施例提供的一种信号处理装置的组成结构示意图，如图11所示，所述装置包括获取单元1101、第一处理单元1102和第二处理单元1103，其中，获取单元1101，设置为获取时钟恢复输入数据；第一处理单元1102，设置为针对所述时钟恢复输入数据，进行频域时钟恢复，得到时钟恢复输出数据；第二处理单元1103，设置为根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
在一实施方式中，所述第一处理单元1102，是设置为获取待鉴相的数据；通过对所述待鉴相的数据进行鉴相，提取出相位误差值；利用所述相位误差值对时钟恢复输入数据进行内插处理，得到时钟恢复输出数据。
在一实施方式中，所述第一处理单元1102，是设置为通过如下方式获取待鉴相的数据：将所述时钟恢复输入数据变换至频域，得到频域的时钟恢复输入数据，将所述频域的时钟恢复输入数据与进行频域盲均衡处理时使用的频域系数相乘，得到所述待鉴相的数据；或者，将上一次得到的频域均衡数据作为所述待鉴相的数据。
在一实施方式中，所述第一处理单元1102，是设置为通过如下方式利用所述相位误差值对所述时钟恢复输入数据进行内插处理，得到时钟恢复输出数据：在时域，根据所述相位误差值对所述时钟恢复输入数据进行有限长单位冲激响应FIR滤波，得到时钟恢复输出数据；或者，将所述时钟恢复输入数据变换至频域，得到频域的时钟恢复输入数据；在频域，通过所述频域的时钟恢复输入数据进行相位调整，得到时钟恢复输出数据。
在一实施方式中，所述第二处理单元1103，是设置为根据所述时钟恢复输 出数据得到频域盲均衡输入数据；获取频域系数；将所述频域盲均衡输入数据与所述频域系数相乘，得到所述频域均衡数据。
在一实施方式中，所述第二处理单元1103，是设置为通过如下方式根据所述时钟恢复输出数据得到频域盲均衡输入数据：在所述时钟恢复输出数据为在时域得出的数据的情况下，通过将所述时钟恢复输出数据变换至频域，得到所述频域盲均衡输入数据；在所述时钟恢复输出数据为在频域得出的数据的情况下，所述频域的时钟恢复输出数据即所述频域盲均衡输入数据。
在一实施方式中，所述第二处理单元1103，是设置为通过如下方式获取频域系数：获取时域系数，将所述时域系数变换至频域，得到所述频域系数。
在一实施方式中，所述第二处理单元1103，还设置为在得到频域均衡数据后，将所述频域均衡数据变换至时域，得到时域均衡数据。
在一实施方式中，所述第二处理单元1103，还设置为根据所述频域盲均衡输入数据和时域均衡数据，对时域系数进行更新，得到更新后的时域系数。
在一实施方式中，所述第二处理单元1103，是设置为通过如下方式根据所述频域盲均衡输入数据和所述时域均衡数据，对所述时域系数进行更新，得到更新后的时域系数：对时域均衡数据进行误差计算，得到时域误差数据；将所述时域误差数据变换至频域，得到频域误差数据；将所述频域误差数据与所述频域盲均衡输入数据进行共轭相乘，得到互谱数据；根据所述互谱数据对所述时域系数进行更新，得到更新后的时域系数。
在一实施方式中，所述第二处理单元1103，是设置为通过如下方式根据所述互谱数据对所述时域系数进行更新，得到更新后的时域系数：将所述互谱数据变换至时域，得到系数调整量；使用所述系数调整量对时域系数进行更新，得到更新后的时域系数。
实际应用中，上述获取单元1101、第一处理单元1102和第二处理单元1103均可由位于相干光通信系统中的CPU、微处理器(Micro Processor Unit，MPU)、DSP、FPGA等实现。
另外，在本实施例中的多个功能模块可以集成在一个处理单元中，也可以是每个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
所述集成的单元如果以软件功能模块的形式实现并非作为独立的产品进行销售或使用时，可以存储在一个计算机可读取存储介质中，基于这样的理解，本实施例的技术方案的全部或部分可以以软件产品的形式体现出来，该计算机 软件产品存储在一个存储介质中，包括多个指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或processor(处理器)执行本实施例所述方法的全部或部分步骤。而前述的存储介质包括：通用串行总线盘(Universal Serial Bus盘，U盘)、移动硬盘、只读存储器(Read Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等多种可以存储程序代码的介质。
本实施例中的一种信号处理方法对应的计算机程序指令可以被存储在光盘，硬盘，U盘等存储介质上，当存储介质中的与一种信号处理方法对应的计算机程序指令被一电子设备读取或被执行时，实现前述实施例的任意一种信号处理方法的步骤。
基于前述实施例相同的技术构思，参见图12，示出了本申请实施例提供的一种信号处理设备120，该装置可以包括：存储器121和处理器122；其中，所述存储器121，设置为存储计算机程序和数据；所述处理器122，设置为执行所述存储器中存储的计算机程序，以实现前述实施例的任意一种信号处理方法。
在实际应用中，上述存储器121可以是易失性存储器(volatile memory)，例如RAM；或者非易失性存储器(non-volatile memory)，例如ROM，快闪存储器(flash memory)，硬盘(Hard Disk Drive，HDD)或固态硬盘(Solid-State Drive，SSD)；或者上述种类的存储器的组合，并向处理器122提供指令和数据。
上述处理器122可以为ASIC、DSP、DSPD、PLD、FPGA、CPU、控制器、微控制器、微处理器中的至少一种。对于不同的设备，设置为实现上述处理器功能的电子器件还可以为其它，本申请实施例不作限定。
本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本申请的实施例而已，并非用于限定本申请的保护范围。

Claims (14)

  1. 一种信号处理方法，包括：
    获取时钟恢复输入数据；
    对所述时钟恢复输入数据进行频域时钟恢复，得到时钟恢复输出数据；
    根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
  2. 根据权利要求1所述的方法，其中，所述对所述时钟恢复输入数据进行频域时钟恢复，得到时钟恢复输出数据，包括：
    获取待鉴相的数据；
    对所述待鉴相的数据进行鉴相，以从所述待鉴相的数据提取出相位误差值；
    利用所述相位误差值对所述时钟恢复输入数据进行内插处理，得到时钟恢复输出数据。
  3. 根据权利要求2所述的方法，其中，所述获取待鉴相的数据，包括：
    将所述时钟恢复输入数据变换至频域，得到频域的时钟恢复输入数据，将所述频域的时钟恢复输入数据与用于频域盲均衡处理的频域系数相乘，得到所述待鉴相的数据；
    或者，将上一次得到的频域均衡数据作为所述待鉴相的数据。
  4. 根据权利要求2或3所述的方法，其中，所述利用所述相位误差值对所述时钟恢复输入数据进行内插处理，得到时钟恢复输出数据，包括：
    在时域，根据所述相位误差值对所述时钟恢复输入数据进行有限长单位冲激响应FIR滤波，得到时钟恢复输出数据；
    或者，将所述时钟恢复输入数据变换至频域，得到频域的时钟恢复输入数据；在频域，通过所述相位误差值对所述频域的时钟恢复输入数据进行相位调整，得到时钟恢复输出数据。
  5. 根据权利要求1-4中任一项所述的方法，其中，所述根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据，包括：
    根据所述时钟恢复输出数据得到频域盲均衡输入数据；
    获取频域系数；
    将所述频域盲均衡输入数据与所述频域系数相乘，得到所述频域均衡数据。
  6. 根据权利要求5所述的方法，其中，所述根据所述时钟恢复输出数据得到频域盲均衡输入数据，包括：
    在所述时钟恢复输出数据为在时域得出的数据的情况下，通过将所述时钟 恢复输出数据变换至频域，得到所述频域盲均衡输入数据；
    在所述时钟恢复输出数据为在频域得出的数据的情况下，根据所述频域的时钟恢复输出数据，得到所述频域盲均衡输入数据。
  7. 根据权利要求5或6所述的方法，其中，所述获取频域系数，包括：
    获取时域系数，将所述时域系数变换至频域，得到所述频域系数。
  8. 根据权利要求7所述的方法，在所述得到频域均衡数据之后，还包括：
    将所述频域均衡数据变换至时域，得到时域均衡数据。
  9. 根据权利要求8所述的方法，在所述得到时域均衡数据之后，还包括：
    根据所述频域盲均衡输入数据和所述时域均衡数据，对所述时域系数进行更新，得到更新后的时域系数。
  10. 根据权利要求9所述的方法，其中，所述根据所述频域盲均衡输入数据和所述时域均衡数据，对所述时域系数进行更新，得到更新后的时域系数，包括：
    对所述时域均衡数据进行误差计算，得到时域误差数据；
    将所述时域误差数据变换至频域，得到频域误差数据；
    将所述频域误差数据与所述频域盲均衡输入数据进行共轭相乘，得到互谱数据；
    根据所述互谱数据对所述时域系数进行更新，得到更新后的时域系数。
  11. 根据权利要求10所述的方法，其中，所述根据所述互谱数据对所述时域系数进行更新，得到更新后的时域系数，包括：
    将所述互谱数据变换至时域，得到系数调整量；
    使用所述系数调整量对所述时域系数进行更新，得到更新后的时域系数。
  12. 一种信号处理装置，包括：
    获取单元，设置为获取时钟恢复输入数据；
    第一处理单元，设置为对所述时钟恢复输入数据进行频域时钟恢复，得到时钟恢复输出数据；
    第二处理单元，设置为根据所述时钟恢复输出数据，进行频域盲均衡处理，得到频域均衡数据。
  13. 一种信号处理设备，包括：处理器和设置为存储在所述处理器上运行的计算机程序的存储器；其中，所述处理器设置为运行所述计算机程序时，执 行权利要求1至11任一项所述的信号处理方法。
  14. 一种计算机存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现权利要求1至11任一项所述的信号处理方法。
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