WO2020125191A1 - 一种高动态范围的宽频对数检波器 - Google Patents

一种高动态范围的宽频对数检波器 Download PDF

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Publication number
WO2020125191A1
WO2020125191A1 PCT/CN2019/112623 CN2019112623W WO2020125191A1 WO 2020125191 A1 WO2020125191 A1 WO 2020125191A1 CN 2019112623 W CN2019112623 W CN 2019112623W WO 2020125191 A1 WO2020125191 A1 WO 2020125191A1
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Prior art keywords
transistor
emitter
base
collector
resistor
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PCT/CN2019/112623
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English (en)
French (fr)
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吴建军
司梦娇
张颖
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南京米乐为微电子科技有限公司
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Priority to US17/298,859 priority Critical patent/US11909361B2/en
Publication of WO2020125191A1 publication Critical patent/WO2020125191A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/083—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]

Definitions

  • the invention relates to a detector, in particular to a wide-frequency logarithmic detector with high dynamic range.
  • Logarithmic detectors are widely used in radar, electronic reconnaissance, communication and telemetry systems, and are important devices that affect the dynamic range of signals received by the system.
  • the logarithmic detector in the prior art is shown in FIG. 1 and is composed of a multi-stage limiting amplifier, a detection unit, and a current summing and driving unit.
  • the limiting amplifier is amplified in stages, and the output of each stage of the limiting amplifier passes through the detection unit After detection, it is sent to the current summation and drive circuit, and finally the current summation and drive circuit outputs the final detection signal.
  • the detection sensitivity of the entire detector is low and the detection dynamic range is small.
  • the object of the invention is to provide a wide-frequency logarithmic detector with a high dynamic range, which can solve the problems of low detection sensitivity and small detection dynamic range of the detector in the prior art.
  • the high-dynamic-range wide-band log detector includes a low-noise amplifier, a compensation detection unit, a current summing and driving unit, an N -level limiting amplifier and an N -level detection unit, N ⁇ 2;
  • the input of the level limiting amplifier is connected to the output of the low noise amplifier.
  • the input of the low noise amplifier is used as the input of the entire detector.
  • the input of the low noise amplifier is also connected to the input of the compensation detection unit and the output of the compensation detection unit.
  • the output terminal of the i - th limiter amplifier is connected to the input terminal of the i- +1th limiter amplifier and the input terminal of the i - th detector unit respectively, 1 ⁇ i ⁇ N -1 , and a driving unit connected to a current summing input of i-th stage output of the detection means, detection means connected to the N-th stage output terminal of the input of limiting amplifier stage N, stage N-th output terminal is connected to a current demand detection unit
  • the input terminal of the sum drive unit, the current summation and the output terminal of the drive unit serve as the output terminal of the entire detector.
  • the low-noise amplifier includes a twenty-fourth transistor M24, an emitter of the twenty-fourth transistor M24 is grounded through a second inductor L2, and a base of the twenty-fourth transistor M24 is connected to the tenth One end of the resistor R10 and one end of the eleventh resistor R11, the base of the twenty-fourth transistor M24 also serves as the input terminal of the low-noise amplifier, the other end of the tenth resistor R10 is grounded through the voltage source Vb1, and the eleventh resistor The other end of R11 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to the collector of the twenty-fourth transistor M24 and one end of the first inductor L1, the other end of the first inductor L1 passes through the tenth
  • the second resistor R12 is connected to the fourth power supply voltage VCC4. In this way, the low-noise amplifier can achieve a working frequency band of 1-18GHz and a 1dB compression point of 3
  • circuit structure of the compensation detection unit and the detection unit are the same.
  • the circuit structure of the compensation detection unit includes a seventeenth transistor M17 and an eighteenth transistor M18.
  • the bases of the seventeenth transistor M17 and the eighteenth transistor M18 are both used as The input terminal of the compensation detection unit, the phase of the base input signal of the seventeenth transistor M17 and the base input signal of the eighteenth transistor M18 are 180 degrees out of phase, and the emitter of the seventeenth transistor M17 Grounded by the sixth current source Ib6, the emitter of the eighteenth transistor M18 is grounded by the eighth current source Ib8, and the collector of the seventeenth transistor M17 is connected to the emitter of the eleventh transistor M11, the first The base of the eleventh transistor M11, the collector of the twelfth transistor M12 and the collector of the eighteenth transistor M18, the collector of the eleventh transistor M11 and the twelfth transistor M12 , The emitter of the thirteenth transistor M13, the emitter of the fourteenth transistor M14, the collector of the ninth transistor M9, and the collector of
  • the circuit structure of the N -level limiting amplifier is the same, and the circuit structure of the limiting amplifier includes a first transistor M1 and a second transistor M2, a base electrode of the first transistor M1 and a second transistor
  • the base of M2 is used as the input terminal of the limiting amplifier
  • the phase of the base input signal of the first transistor M1 and the phase of the base input signal of the second transistor M2 are 180 degrees out of phase
  • the emitter of the second transistor M2 is grounded through the fourth current source Ib4
  • the collector of the first transistor M1 is connected to the base and the third transistor M3 respectively
  • the emitter of the fifth transistor M5 and the base of the seventh transistor M7, the collector of the second transistor M2 are respectively connected to the emitter of the sixth transistor M6, the base of the eighth transistor M8 and
  • the base of the fourth transistor M4, the base of the fifth transistor M5 are respectively connected to the collector of the third transistor M3 and one end
  • the emitter of the transistor M3 is grounded through the third current source Ib3, the emitter of the seventh transistor M7 is grounded through the first current source Ib1, and the emitter of the eighth transistor M8 is grounded through the fifth current source Ib5, The emitter of the seventh transistor M7 and the emitter of the eighth transistor M8 both serve as the output terminal of the limiting amplifier.
  • the current summing and driving unit includes a first field effect transistor F1 and a third field effect transistor F3, and the gate of the first field effect transistor F1 is connected to the gate of the second field effect transistor F2 and the first field effect, respectively
  • the drain of the tube F1, the collector of the twenty-third transistor M23 and the gate of the fifth field effect tube F5, the gate of the third field effect tube F3 are connected to the gate of the fourth field effect tube F4 and the third
  • the drain of the three field effect transistor F3, the drain of the third field effect transistor F3 is used as the input terminal of the current summing and driving unit, and the drain of the fourth field effect transistor F4 is respectively connected to the non-inverting input terminal of the operational amplifier OP1, the ninth One end of the resistor R9 and the drain of the second field effect transistor F2, the inverting input terminal of the operational amplifier OP1 is connected to the output terminal of the operational amplifier OP1, the ground terminal of the operational amplifier OP1 is grounded, and the offset terminal of the operational amplifier OP1 is connected
  • the N is a multiple of 3
  • a DC compensation circuit is provided between the 3 j +1 stage limiting amplifier and the 3 j +3 stage limiting amplifier, and the DC voltage of the 3 j +3 stage limiting amplifier
  • the DC compensation circuit amplifies the DC voltage and outputs it to the 3 j +1 stage limiting amplifier. This can reduce the DC voltage fluctuation of the limiting amplifier within the operating bandwidth, thereby improving the frequency flatness of the entire detector.
  • the circuit structure of the 3 j +1 stage limiting amplifier and the 3 j +3 stage limiting amplifier are the same; the 3 j +1 stage limiting amplifier includes the twenty-fifth transistor M25 and the twentieth
  • the base of the six-transistor M26, the base of the twenty-fifth triode M25 and the base of the twenty-sixth triode M26 are used as the input terminal of the 3 j +1 level limiting amplifier, and the twenty-fifth triode
  • the phase of the base input signal of the tube M25 and the base input signal of the twenty-sixth transistor M26 are 180 degrees out of phase.
  • the emitter of the twenty-fifth transistor M25 is grounded through the thirteenth current source Ib13.
  • the emitter of the twenty-six transistor M26 is grounded through the fifteenth current source Ib15, and the collector of the twenty-fifth transistor M25 is connected to the base of the twenty-seventh transistor M27 and the twenty-ninth triode respectively
  • the emitter of the tube M29 and the base of the thirty-first transistor M31, the collector of the twenty-sixth transistor M26 are respectively connected to the emitter of the thirty-third transistor M30, and the thirty-second transistor M32
  • the base of the 28th transistor M28, the base of the 29th transistor M29 are connected to the collector of the 27th transistor M27 and one end of the thirteenth resistor R13, respectively
  • the base of the transistor 33 is connected to the collector of the thirty-first transistor M31 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the first The collector of the twenty-ninth transistor M29, the collector of the thirty-third transistor M30, the collector of the thirty
  • the collector of the 27th transistor M27 is also connected to the end of the fifteenth resistor R15.
  • the collector of the transistor M28 is also connected to one end of the sixteenth resistor R16, the other end of the fifteenth resistor R15 and the other end of the sixteenth resistor R16 are both connected to the input end of the DC compensation circuit; the third j +2 level limit
  • the amplitude amplifier includes a first triode M1 and a second triode M2.
  • the base of the first triode M1 and the base of the second triode M2 both serve as the input terminal of the 3 j +2 stage limiting amplifier ,
  • the phase of the base input signal of the first transistor M1 and the phase of the base input signal of the second transistor M2 are 180 degrees out of phase, and the emitter of the first transistor M1 is grounded through the second current source Ib2.
  • the emitter of the second transistor M2 is grounded through the fourth current source Ib4, and the collector of the first transistor M1 is connected to the base of the third transistor M3 and the fifth transistor M5 respectively
  • the emitter and the base of the seventh transistor M7, the collector of the second transistor M2 are respectively connected to the emitter of the sixth transistor M6, the base of the eighth transistor M8 and the fourth transistor M4
  • the base of the fifth transistor M5 is connected to the collector of the third transistor M3 and one end of the first resistor R1, and the base of the sixth transistor M6 is connected to the fourth transistor M4
  • the collector of the tube M7 and the collector of the eighth transistor M8 both input the first supply voltage VCC1, the emitter of the third transistor M3 is connected to the emitter of the fourth transistor M4, and the emitter of the third transistor M3
  • the DC compensation circuit includes a 33rd transistor M33, the base of the 33rd transistor M33 is used as the input terminal of the DC compensation circuit, and the collector of the 33rd transistor M33 is connected to the 17th resistor At one end of R17, the collector of the 33rd transistor M33 also inputs the sixth supply voltage VCC6, and the other end of the 17th resistor R17 is connected to the collector of the 34th transistor M34 and the 35th
  • the base of the transistor M35, the collector of the 35th transistor M35 is used as the output terminal of the DC compensation circuit
  • the base of the 34th transistor M34 is connected to the emitter of the 33rd transistor M33
  • the emitter of the thirty-third transistor M33 is grounded through the seventeenth current source Ib17
  • the emitter of the thirty-fourth transistor M34 is grounded through the eighteenth current source Ib18
  • the emitter of the thirty-fifth transistor M35 The pole is grounded through the nineteenth current source Ib19.
  • the temperature compensation circuit the output terminal of the temperature compensation circuit is connected to the current summing and driving unit;
  • the temperature compensation circuit includes a sixth field effect transistor F6, and the gate of the sixth field effect transistor F6 is respectively connected to the gate of the seventh field effect transistor F7 Electrode, the gate of the eighth FET F8 and the output of the second operational amplifier OP2, the source of the sixth FET F6, the source of the seventh FET F7 and the source of the eighth FET F8 Both input the seventh supply voltage VCC7, the drain of the eighth field effect transistor F8 is used as the output terminal of the temperature compensation circuit, and the drain of the sixth field effect transistor F6 is connected to the non-inverting input terminal and the thirty-sixth of the second operational amplifier OP2, respectively
  • the base of the transistor M36 and the collector of the thirty-sixth transistor M36, and the drain of the seventh field effect transistor F7 are connected to the inverting input terminal of the second operational amplifier OP2 and one end of the eighteenth resistor R18, The other end of
  • the invention discloses a wide-frequency logarithmic detector with high dynamic range.
  • a low-noise amplifier in front of the first-stage limiting amplifier, the detection sensitivity of the entire detector is improved; through the combination of a low-noise amplifier and a compensation detection unit, The detection dynamic range of the entire detector is expanded.
  • Figure 1 is a block diagram of the circuit structure of the detector in the prior art
  • FIG. 2 is a block diagram of a circuit structure of a detector in a specific embodiment of the present invention.
  • 3 is a detection output curve after removing the low-noise amplifier and the compensation detection unit in the specific embodiment of the present invention
  • Example 5 is a circuit diagram of Example 1 of a limiting amplifier in a specific embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a compensation detection unit in a specific embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a current summing and driving unit in a specific embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a low-noise amplifier in a specific embodiment of the present invention.
  • FIG. 9 is a circuit diagram of the 3 j +1 stage limiting amplifier in Example 2 of the limiting amplifier in the specific embodiment of the present invention.
  • FIG. 10 is a circuit diagram of a DC compensation circuit in a specific embodiment of the present invention.
  • FIG. 11 is a circuit diagram of a temperature compensation circuit in a specific embodiment of the present invention.
  • the specific embodiment discloses a wide dynamic logarithmic detector with high dynamic range, as shown in FIG. 2, which includes a low noise amplifier, a compensation detection unit, a current summing and driving unit, an N -level limiting amplifier and an N -level detection unit , N ⁇ 2.
  • the input of the first-stage limiting amplifier is connected to the output of the low-noise amplifier.
  • the input of the low-noise amplifier is used as the input of the entire detector.
  • the input of the low-noise amplifier is also connected to the input of the compensation detection unit to compensate the detection
  • the output of the unit is connected to the current summation and the input of the drive unit.
  • the output of the i - th limiting amplifier is connected to the input of the i + 1st limiting amplifier and the input of the i - th detecting unit, 1 ⁇ i ⁇ N -1, and the driving current summing means connected to an input of i-th stage output of the detection means, the output terminal of the first N-stage limiting amplifier stage is connected to the N-th detection means input, an output stage of the detection unit N The terminal is connected to the input terminal of the current summing and driving unit, and the output terminal of the current summing and driving unit is used as the output terminal of the entire detector.
  • the present invention uses a combination of a low-noise amplifier and a compensation detection unit is that although the low-noise amplifier can improve the detection sensitivity, the upper and lower limits of the detection dynamic range are both lowered, that is, the detection dynamic range cannot be extended.
  • the compensation detection unit will work when the input signal power is relatively high, so that the shortcomings of the low-noise amplifier that cannot detect the high-power signal can be compensated, which can expand the detection dynamic range. Therefore, the combination of a low-noise amplifier and a compensation detection unit can not only improve the detection sensitivity, but also expand the detection dynamic range.
  • the low noise amplifier includes a twenty-fourth transistor M24. As shown in FIG. 8, the emitter of the twenty-fourth transistor M24 is grounded through a second inductor L2, and the bases of the twenty-fourth transistor M24 are respectively connected One end of the tenth resistor R10 and one end of the eleventh resistor R11, the base of the twenty-fourth transistor M24 also serves as the input terminal of the low noise amplifier, the other end of the tenth resistor R10 is grounded through the voltage source Vb1, the tenth The other end of a resistor R11 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to the collector of the twenty-fourth transistor M24 and one end of the first inductor L1, the other end of the first inductor L1 passes The twelfth resistor R12 is connected to the fourth supply voltage VCC4.
  • the voltage source Vb1 provides a voltage bias for the twenty-fourth transistor M24 through the tenth resistor R10.
  • the first capacitor C1 and the eleventh resistor R11 are feedback elements, which mainly adjust the gain of the low noise amplifier.
  • the twelfth resistor R12 and the first inductor L1 are load elements for increasing the high-frequency gain of the low-noise amplifier, and the second inductor L2 is the winding equivalent inductance of the low-noise amplifier.
  • the circuit structure of the compensation detection unit and the detection unit is the same.
  • the circuit structure of the compensation detection unit includes the seventeenth transistor M17 and the eighteenth transistor M18. As shown in FIG. 6, the base of the seventeenth transistor M17 and the base of the eighteenth transistor M18 Both are used as the input terminal of the compensation detection unit.
  • the phase of the base input signal of the seventeenth transistor M17 and the base input signal of the eighteenth transistor M18 are 180 degrees out of phase.
  • the emitter is grounded through the sixth current source Ib6, the emitter of the eighteenth transistor M18 is grounded through the eighth current source Ib8, and the collector of the seventeenth transistor M17 is connected to the emitter of the eleventh transistor M11 respectively ,
  • the emitter of the tube M12, the emitter of the thirteenth transistor M13, the emitter of the fourteenth transistor M14, the collector of the ninth transistor M9 and the collector of the thirteenth transistor M10 are all input Two supply voltage VCC2, the base of the eleventh transistor M11 is also connected to the base of the ninth transistor M9, the base of the twelfth transistor M12 is connected to the base of the thirteenth transistor M13,
  • the nonlinearity of the seventeenth transistor M17 and the eighteenth transistor M18 is used to make the output current and the input power have a logarithmic linear relationship.
  • the output current of the fifteenth transistor M15 and the sixteenth transistor M16 is the DC output of the input signal, which passes through the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14
  • the current mirror makes the output current of the eleventh transistor M11 minus the DC component of the input signal.
  • the ninth transistor M9, the thirteenth transistor M10, the nineteenth transistor M19, the twenty-third transistor M20, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 constitute a current mirror, which can be The current required for the mirror output.
  • the circuit structure of the N -level limiting amplifier is the same.
  • the circuit structure of the limiting amplifier includes a first transistor M1 and a second transistor M2. As shown in FIG. 5, the base of the first transistor M1 And the base of the second transistor M2 are used as the input terminal of the limiting amplifier, the phase of the base input signal of the first transistor M1 and the phase of the base input signal of the second transistor M2 are 180 degrees out of phase ,
  • the emitter of the first transistor M1 is grounded through the second current source Ib2, the emitter of the second transistor M2 is grounded through the fourth current source Ib4, and the collectors of the first transistor M1 are respectively connected to the third triode
  • the base of the transistor M3, the emitter of the fifth transistor M5 and the base of the seventh transistor M7, and the collector of the second transistor M2 are respectively connected to the emitter of the sixth transistor M6, the eighth three
  • the base of the transistor M8 and the base of the fourth transistor M4, the base of the fifth transistor M5 are respectively connected to the collector of
  • Figure 5 is a symmetrical circuit, which can be analyzed from the left side.
  • the first transistor M1, the third transistor M3, the fifth transistor M5 and the first resistor R1 form a limiting amplifier unit, and the fifth transistor is used.
  • the feedback of tube M5 reaches the function of limiting amplification.
  • the seventh transistor M7 is an emitter follower, which can reduce the output resistance and improve the capacity of the circuit with load.
  • N is a multiple of 3, and a DC compensation circuit is provided between the 3 j +1 stage limiting amplifier and the 3 j +3 stage limiting amplifier, and the DC of the 3 j +3 stage limiting amplifier The voltage is used as the input signal of the DC compensation circuit.
  • the DC compensation circuit amplifies the DC voltage and outputs it to the 3 j +1 stage limiting amplifier. This can reduce the DC voltage fluctuation of the limiting amplifier within the operating bandwidth, thereby improving the frequency flatness of the entire detector.
  • the circuit structure of the 3 j +1 level limiting amplifier and the 3 j +3 level limiting amplifier are the same.
  • the 3 j +1 stage limiting amplifier includes the twenty-fifth transistor M25 and the twenty-sixth transistor M26, the base of the twenty-fifth transistor M25 and the twenty-sixth
  • the base of the transistor M26 is used as the input terminal of the 3 j +1 stage limiting amplifier, the phase of the base input signal of the twenty-fifth transistor M25 and the base input of the twenty-sixth transistor M26
  • the phases of the signals differ by 180 degrees.
  • the emitter of the 25th transistor M25 is grounded through the thirteenth current source Ib13, and the emitter of the 26th transistor M26 is grounded through the fifteenth current source Ib15.
  • the collector of the five transistor M25 is connected to the base of the twenty-seventh transistor M27, the emitter of the twenty-ninth transistor M29 and the base of the thirty-first transistor M31, respectively.
  • the collector of the transistor M26 is connected to the emitter of the 33rd transistor M30, the base of the 32nd transistor M32 and the base of the 28th transistor M28, and the 29th triode
  • the base of the tube M29 is respectively connected to the collector of the twenty-seventh transistor M27 and one end of the thirteenth resistor R13
  • the base of the thirty-third transistor M30 is respectively connected to the collector of the thirty-first transistor M31 And one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the collector of the twenty-ninth triode M29, the collector of the thirty-third triode M30
  • the collector of the thirty-first transistor M31 and the collector of the thirty-second transistor M32 both input the fifth power supply voltage VCC5, and the emitter of the twenty-seven transistor M27 is connected to the twenty-eight transistor
  • the emitter of M28, the emitter of the twenty-seven transistor M27 is grounded through the fourteenth current
  • the third j +2 stage limiting amplifier adopts the structure of FIG. 5 and includes the first transistor M1 and the second transistor M2, the base of the first transistor M1 and the base of the second transistor M2 are both As the input terminal of the 3 j +2 stage limiting amplifier, the phase of the base input signal of the first transistor M1 and the phase of the base input signal of the second transistor M2 are 180 degrees out of phase.
  • the emitter of M1 is grounded through the second current source Ib2, the emitter of the second transistor M2 is grounded through the fourth current source Ib4, and the collector of the first transistor M1 is connected to the base of the third transistor M3,
  • the emitter of the fifth transistor M5 and the base of the seventh transistor M7, and the collector of the second transistor M2 are respectively connected to the emitter of the sixth transistor M6 and the base of the eighth transistor M8
  • the base of the fifth transistor M5 is connected to the collector of the third transistor M3 and one end of the first resistor R1, and the base of the sixth transistor M6 is connected respectively
  • the collector, the collector of the seventh transistor M7 and the collector of the eighth transistor M8 all input the first supply voltage VCC1, the emitter of the third transistor M3 is connected to the emitter of the fourth transistor M
  • the circuit structure of the 3 j +3 level limiting amplifier and the circuit structure of the 3 j +2 level limiting amplifier differ only in the fifteenth resistor R15 and the sixteenth resistor R16, and the others are the same.
  • the fifteenth resistor R15 and the sixteenth resistor R16 in the 3 j +3 stage limiting amplifier are used to extract the DC voltage Vdc.
  • the DC voltage Vdc is amplified by the DC compensation circuit and then input to the 3 j +1 stage limiting amplifier. DC voltage.
  • the fifteenth resistor R15 and the sixteenth resistor R16 in the 3 j +1 level limiting amplifier are used to receive the amplified DC voltage Vdc.
  • the transistors M33-M35, current sources I17-I19 and the seventeenth resistor R17 together form a DC voltage amplifying circuit.
  • the DC compensation circuit includes the 33rd transistor M33.
  • the base of the 33rd transistor M33 is used as the input terminal of the DC compensation circuit, and the 33rd transistor
  • the collector of M33 is connected to one end of the seventeenth resistor R17, the collector of the 33rd transistor M33 also inputs the sixth supply voltage VCC6, and the other end of the 17th resistor R17 is connected to the 34th transistor M34, respectively And the base of the 35th transistor M35.
  • the collector of the 35th transistor M35 serves as the output of the DC compensation circuit.
  • the base of the 34th transistor M34 is connected to the 30th The emitter of the transistor M33, the emitter of the 33rd transistor M33 is grounded through the seventeenth current source Ib17, and the emitter of the 34th transistor M34 is grounded through the eighteenth current source Ib18, The emitter of the thirty-five transistor M35 is grounded through the nineteenth current source Ib19.
  • the current summing and driving unit includes a first FET F1 and a third FET F3.
  • the gate of the first FET F1 is connected to the gate of the second FET F2 and the first The drain of the field effect transistor F1, the collector of the twenty-third transistor M23 and the gate of the fifth field effect transistor F5, the gate of the third field effect transistor F3 are respectively connected to the gate of the fourth field effect transistor F4
  • the drain of the third field effect transistor F3 is used as the input terminal of the current summing and driving unit
  • the drain of the fourth field effect transistor F4 is connected to the non-inverting input terminal of the operational amplifier OP1,
  • One end of the ninth resistor R9 and the drain of the second field effect transistor F2 the inverting input terminal of the operational amplifier OP1 is connected to the output terminal of the operational amplifier OP1, the ground terminal of the operational amplifier OP1 is grounded, and the offset terminal of the operational amplifier OP1 is connected to the The drain of the five field effect
  • the base of the twenty-third transistor M23 is also grounded through a seventh resistor R7.
  • the emitter of the twenty-first transistor M21 is grounded through a sixth resistor R6, and the collector of the twenty-first transistor M21 is connected to the base of the twenty-second transistor M22 and the eleventh current source Ib11, respectively.
  • the third power supply voltage VCC3 is input to both the electrode and the source of the fifth field effect transistor F5.
  • the twenty-third transistor M23, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 form a current mirror, and the current forms a voltage on the ninth resistor R9, and this voltage is obtained through the operational amplifier OP1 The desired output voltage.
  • the detector also includes a temperature compensation circuit.
  • the output of the temperature compensation circuit is connected to the other end of the current summation and eleventh current source Ib11 in the drive unit.
  • the temperature compensation circuit includes a sixth field effect transistor F6, the gate of the sixth field effect transistor F6 is connected to the gate of the seventh field effect transistor F7, the gate of the eighth field effect transistor F8 and the second The output of the operational amplifier OP2, the source of the sixth FET F6, the source of the seventh FET F7, and the source of the eighth FET F8 all input the seventh supply voltage VCC7, the eighth FET F8 The drain of is used as the output of the temperature compensation circuit.
  • the drain of the sixth field effect transistor F6 is connected to the non-inverting input terminal of the second operational amplifier OP2, the base of the 36th transistor M36 and the 36th triode
  • the collector of the tube M36, the drain of the seventh field effect tube F7 are respectively connected to the inverting input terminal of the second operational amplifier OP2 and one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 are respectively connected to the thirty-seventh
  • the collector of the transistor M37 and the base of the 37th transistor M37, the emitter of the 36th transistor M36 and the emitter of the 37th transistor M37 are both grounded.
  • the sixth field effect transistor F6, the seventh field effect transistor F7, the thirty-sixth transistor M36, the thirty-seventh transistor M37 and the eighteenth resistor R18 together form an offset proportional to the temperature
  • the current sources that is, the currents of the sixth FET F6 and the seventh FET F7 are currents proportional to the temperature.
  • the second operational amplifier OP2 is added to clamp the drain voltages of the sixth field effect transistor F6 and the seventh field effect transistor F7 at the same voltage, so that the accuracy and stability of the bias current source will be better.
  • the seventh field effect tube F7 and the eighth field effect tube F8 form a mirror current source structure.
  • the currents of the seventh field effect tube F7 and the eighth field effect tube F8 are equivalent, so that the output current of the temperature compensation circuit is a proportional to the temperature After connecting the current summing and driving unit, it can compensate the influence of temperature change on the current summing and driving unit. This makes the current summing and driving unit work in the temperature range of -40°C ⁇ 85°C. The working performance is consistent, so that the working range of the entire detector is widened, which is suitable for extreme working environments.
  • the operating frequency of the low-noise amplifier is 1-18GHz.
  • its gain characteristic curve is flat, and the flatness is within ⁇ 1.5dB, which ensures that the working bandwidth of the overall detector is not affected; the noise figure is less than 5dB, which ensures the detection circuit Sensitivity; high linearity, the output 1dB compression point OP1dB can reach 3dBm, when the input signal power is high, the power signal can enter the post stage without compression.
  • the compensation detection unit works when the output power of the low-noise amplifier is greater than 3dBm, and its working frequency band is still 1-18GHz, so that the output can be compensated when the input power is large, and its detection range is (-20dBm, 5dBm).
  • the detection output curve after removing the low noise amplifier and the compensation detection unit is shown in Fig. 3, and the detection output curve after adding the low noise amplifier and the compensation detection unit is shown in Fig. 4. It can be seen that the dynamic range of detection in Figure 3 is -55dBm ⁇ 3dBm, and the dynamic range of detection in Figure 4 is -70 dBm ⁇ 3 dBm, which means that the dynamic range of detection after the addition of a low noise amplifier and a compensation detection unit has been extended by 15dBm. The above detection dynamic range only considers the linear range.
  • the working frequency band of the detector after adding the low noise amplifier and the compensation detection unit is 1 ⁇ 18GHz
  • the detection linearity ⁇ 1.5dB the frequency flatness ⁇ 1.5dB
  • the detection output rise time is 5ns
  • the detection output fall time It is 15ns
  • the power consumption is 190mA@3.3V
  • the slope of the detection output curve is 15mV/dBm.

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Abstract

本发明公开了一种高动态范围的宽频对数检波器，包括低噪声放大器、补偿检波单元、电流求和及驱动单元、 N级限幅放大器和 N级检波单元。本发明通过在第一级限幅放大器前面加入低噪声放大器，提高了整个检波器的检波灵敏度；通过低噪声放大器和补偿检波单元的组合，扩大了整个检波器的检波动态范围。

Description

一种高动态范围的宽频对数检波器 技术领域
本发明涉及检波器，特别是涉及一种高动态范围的宽频对数检波器。
 背景技术
对数检波器广泛应用于雷达、电子侦察、通信和遥测等系统中，是影响系统接收信号动态范围的重要器件。现有技术中的对数检波器如图1所示，由多级限幅放大器、检波单元和电流求和及驱动单元构成，限幅放大器逐级放大，每级限幅放大器的输出经检波单元检波后送入电流求和及驱动电路，最后由电流求和及驱动电路输出最终的检波信号。然而，现有技术中由于限幅放大器的噪声系数较大，会导致整个检波器的检波灵敏度较低，检波动态范围较小。
 技术问题
发明目的：本发明的目的是提供一种高动态范围的宽频对数检波器，能够解决现有技术中存在的检波器检波灵敏度较低、检波动态范围较小的问题。
 技术解决方案
本发明所述的高动态范围的宽频对数检波器，包括低噪声放大器、补偿检波单元、电流求和及驱动单元、 N级限幅放大器和 N级检波单元， N≥2；其中，第一级限幅放大器的输入端连接低噪声放大器的输出端，低噪声放大器的输入端作为整个检波器的输入端，低噪声放大器的输入端还连接补偿检波单元的输入端，补偿检波单元的输出端连接电流求和及驱动单元的输入端，第 i级限幅放大器的输出端分别连接第 i+1级限幅放大器的输入端和第 i级检波单元的输入端，1≤ i≤ N-1，第 i级检波单元的输出端连接电流求和及驱动单元的输入端，第 N级限幅放大器的输出端连接第 N级检波单元的输入端，第 N级检波单元的输出端连接电流求和及驱动单元的输入端，电流求和及驱动单元的输出端作为整个检波器的输出端。
进一步，所述低噪声放大器包括第二十四三极管M24，第二十四三极管M24的发射极通过第二电感L2接地，第二十四三极管M24的基极分别连接第十电阻R10的一端和第十一电阻R11的一端，第二十四三极管M24的基极还作为低噪声放大器的输入端，第十电阻R10的另一端通过电压源Vb1接地，第十一电阻R11的另一端连接第一电容C1的一端，第一电容C1的另一端分别连接第二十四三极管M24的集电极和第一电感L1的一端，第一电感L1的另一端通过第十二电阻R12连接第四供电电压VCC4。这样低噪声放大器能够实现1-18GHz的工作频带，3dBm的输出1dB压缩点，能够实现很好的线性度。
进一步，所述补偿检波单元和检波单元的电路结构相同。
进一步，所述补偿检波单元的电路结构包括第十七三极管M17和第十八三极管M18，第十七三极管M17的基极和第十八三极管M18的基极均作为补偿检波单元的输入端，第十七三极管M17的基极输入信号的相位和第十八三极管M18的基极输入信号的相位相差180度，第十七三极管M17的发射极通过第六电流源Ib6接地，第十八三极管M18的发射极通过第八电流源Ib8接地，第十七三极管M17的集电极分别连接第十一三极管M11的发射极、第十一三极管M11的基极、第十二三极管M12的集电极和第十八三极管M18的集电极，第十一三极管M11的集电极、第十二三极管M12的发射极、第十三三极管M13的发射极、第十四三极管M14的发射极、第九三极管M9的集电极和第十三极管M10的集电极均输入第二供电电压VCC2，第十一三极管M11的基极还连接第九三极管M9的基极，第十二三极管M12的基极分别连接第十三三极管M13的基极、第十三三极管M13的集电极、第十四三极管M14的基极、第十四三极管M14的集电极、第十五三极管M15的集电极和第十六三极管M16的集电极，第十五三极管M15的基极连接第十六三极管M16的基极，第十五三极管M15的发射极连接第十六三极管M16的发射极，第十五三极管M15的发射极还通过第七电流源Ib7接地，第九三极管M9的发射极连接第三电阻R3的一端，第三电阻R3的另一端分别连接第十九三极管M19的集电极和第十三极管M10的基极，第十九三极管M19的发射极通过第四电阻R4接地，第十九三极管M19的基极分别连接第十三极管M10的发射极和第二十三极管M20的基极，第十九三极管M19的基极还通过第九电流源Ib9接地，第二十三极管M20的发射极通过第五电阻R5接地，第二十三极管M20的集电极连接第十电流源Ib10的一端，第十电流源Ib10的另一端作为补偿检波单元的输出端。
进一步，所述 N级限幅放大器的电路结构相同，限幅放大器的电路结构包括第一三极管M1和第二三极管M2，第一三极管M1的基极和第二三极管M2的基极均作为限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为限幅放大器的输出端。
进一步，所述电流求和及驱动单元包括第一场效应管F1和第三场效应管F3，第一场效应管F1的栅极分别连接第二场效应管F2的栅极、第一场效应管F1的漏极、第二十三三极管M23的集电极和第五场效应管F5的栅极，第三场效应管F3的栅极分别连接第四场效应管F4的栅极和第三场效应管F3的漏极，第三场效应管F3的漏极作为电流求和及驱动单元的输入端，第四场效应管F4的漏极分别连接运算放大器OP1的同相输入端、第九电阻R9的一端和第二场效应管F2的漏极，运算放大器OP1的反相输入端连接运算放大器OP1的输出端，运算放大器OP1的接地端接地，运算放大器OP1的偏置端连接第五场效应管F5的漏极，运算放大器OP1的输出端作为电流求和及驱动单元的输出端，第二十三三极管M23的发射极通过第八电阻R8接地，第二十三三极管M23的基极分别连接第二十二三极管M22的发射极和第二十一三极管M21的基极，第二十三三极管M23的基极还通过第七电阻R7接地，第二十一三极管M21的发射极通过第六电阻R6接地，第二十一三极管M21的集电极分别连接第二十二三极管M22的基极和第十一电流源Ib11的一端，第十一电流源Ib11的另一端连接外置电流源，第二十二三极管M22的集电极、第一场效应管F1的源极、第二场效应管F2的源极、第三场效应管F3的源极、第四场效应管F4的源极和第五场效应管F5的源极均输入第三供电电压VCC3。
进一步，所述 N为3的倍数，第3 j+1级限幅放大器和第3 j+3级限幅放大器之间设有直流补偿电路，，第3 j+3级限幅放大器的直流电压作为直流补偿电路的输入信号，直流补偿电路将直流电压放大后输出至第3 j+1级限幅放大器。这样能够使得限幅放大器在工作带宽内的直流电压波动减弱，从而提高整个检波器的频率平坦度。
进一步，所述第3 j+1级限幅放大器和第3 j+3级限幅放大器的电路结构相同；第3 j+1级限幅放大器包括第二十五三极管M25和第二十六三极管M26，第二十五三极管M25的基极和第二十六三极管M26的基极均作为第3 j+1级限幅放大器的输入端，第二十五三极管M25的基极输入信号的相位和第二十六三极管M26的基极输入信号的相位相差180度，第二十五三极管M25的发射极通过第十三电流源Ib13接地，第二十六三极管M26的发射极通过第十五电流源Ib15接地，第二十五三极管M25的集电极分别连接第二十七三极管M27的基极、第二十九三极管M29的发射极和第三十一三极管M31的基极，第二十六三极管M26的集电极分别连接第三十三极管M30的发射极、第三十二三极管M32的基极和第二十八三极管M28的基极，第二十九三极管M29的基极分别连接第二十七三极管M27的集电极和第十三电阻R13的一端，第三十三极管M30的基极分别连接第三十一三极管M31的集电极和第十四电阻R14的一端，第十三电阻R13的另一端、第十四电阻R14的另一端、第二十九三极管M29的集电极、第三十三极管M30的集电极、第三十一三极管M31的集电极和第三十二三极管M32的集电极均输入第五供电电压VCC5，第二十七三极管M27的发射极连接第二十八三极管M28的发射极，第二十七三极管M27的发射极通过第十四电流源Ib14接地，第三十一三极管M31的发射极通过第十二电流源Ib12接地，第三十二三极管M32的发射极通过第十六电流源Ib16接地，第三十一三极管M31的发射极和第三十二三极管M32的发射极均作为第3 j+1级限幅放大器的输出端，第二十七三极管M27的集电极还连接第十五电阻R15的一端，第二十八三极管M28的集电极还连接第十六电阻R16的一端，第十五电阻R15的另一端和第十六电阻R16的另一端均连接直流补偿电路的输入端；第3 j+2级限幅放大器包括第一三极管M1和第二三极管M2，第一三极管M1的基极和第二三极管M2的基极均作为第3 j+2级限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为第3 j+2级限幅放大器的输出端。
进一步，直流补偿电路包括第三十三三极管M33，第三十三三极管M33的基极作为直流补偿电路的输入端，第三十三三极管M33的集电极连接第十七电阻R17的一端，第三十三三极管M33的集电极还输入第六供电电压VCC6，第十七电阻R17的另一端分别连接第三十四三极管M34的集电极和第三十五三极管M35的基极，第三十五三极管M35的集电极作为直流补偿电路的输出端，第三十四三极管M34的基极连接第三十三三极管M33的发射极，第三十三三极管M33的发射极通过第十七电流源Ib17接地，第三十四三极管M34的发射极通过第十八电流源Ib18接地，第三十五三极管M35的发射极通过第十九电流源Ib19接地。
进一步，温度补偿电路，温度补偿电路的输出端连接电流求和及驱动单元；温度补偿电路包括第六场效应管F6，第六场效应管F6的栅极分别连接第七场效应管F7的栅极、第八场效应管F8的栅极和第二运算放大器OP2的输出端，第六场效应管F6的源极、第七场效应管F7的源极和第八场效应管F8的源极均输入第七供电电压VCC7，第八场效应管F8的漏极作为温度补偿电路的输出端，第六场效应管F6的漏极分别连接第二运算放大器OP2的同相输入端、第三十六三极管M36的基极和第三十六三极管M36的集电极，第七场效应管F7的漏极分别连接第二运算放大器OP2的反相输入端和第十八电阻R18的一端，第十八电阻R18的另一端分别连接第三十七三极管M37的集电极和第三十七三极管M37的基极，第三十六三极管M36的发射极和第三十七三极管M37的发射极均接地。这样使得电流求和及驱动单元在高低温变化时的工作状态和工作性能一致，从而使得整个检波器的工作范围拓宽，适用于极端工作环境。
 有益效果
本发明公开了一种高动态范围的宽频对数检波器，通过在第一级限幅放大器前面加入低噪声放大器，提高了整个检波器的检波灵敏度；通过低噪声放大器和补偿检波单元的组合，扩大了整个检波器的检波动态范围。
 附图说明
图1为现有技术中检波器的电路结构框图；
图2为本发明具体实施方式中检波器的电路结构框图；
图3为本发明具体实施方式中去掉低噪声放大器和补偿检波单元之后的检波输出曲线；
图4为本发明具体实施方式中加上低噪声放大器和补偿检波单元之后的检波输出曲线；
图5为本发明具体实施方式中限幅放大器的实施例1的电路图；
图6为本发明具体实施方式中补偿检波单元的电路图；
图7为本发明具体实施方式中电流求和及驱动单元的电路图；
图8为本发明具体实施方式中低噪声放大器的电路图；
图9为本发明具体实施方式中限幅放大器的实施例2中第3 j+1级限幅放大器的电路图；
图10为本发明具体实施方式中直流补偿电路的电路图；
图11为本发明具体实施方式中温度补偿电路的电路图。
 本发明的实施方式
本具体实施方式公开了一种高动态范围的宽频对数检波器，如图2所示，包括低噪声放大器、补偿检波单元、电流求和及驱动单元、 N级限幅放大器和 N级检波单元， N≥2。其中，第一级限幅放大器的输入端连接低噪声放大器的输出端，低噪声放大器的输入端作为整个检波器的输入端，低噪声放大器的输入端还连接补偿检波单元的输入端，补偿检波单元的输出端连接电流求和及驱动单元的输入端，第 i级限幅放大器的输出端分别连接第 i+1级限幅放大器的输入端和第 i级检波单元的输入端，1≤ i≤ N-1，第 i级检波单元的输出端连接电流求和及驱动单元的输入端，第 N级限幅放大器的输出端连接第 N级检波单元的输入端，第 N级检波单元的输出端连接电流求和及驱动单元的输入端，电流求和及驱动单元的输出端作为整个检波器的输出端。图2中的限幅放大器有六级， N=6。
本发明之所以采用低噪声放大器和补偿检波单元的组合，是因为仅用低噪声放大器虽然能提高检波灵敏度，但是检波动态范围的上限和下限都会下偏，也即检波动态范围得不到扩展。然而加入了补偿检波单元之后，补偿检波单元会在输入信号功率比较高的时候起作用，这样就能补偿低噪声放大器无法检测高功率信号的缺点，从而能够拓展检波动态范围。因此，采用低噪声放大器和补偿检波单元的组合，既能够提高检波灵敏度，又能够拓展检波动态范围。
低噪声放大器包括第二十四三极管M24，如图8所示，第二十四三极管M24的发射极通过第二电感L2接地，第二十四三极管M24的基极分别连接第十电阻R10的一端和第十一电阻R11的一端，第二十四三极管M24的基极还作为低噪声放大器的输入端，第十电阻R10的另一端通过电压源Vb1接地，第十一电阻R11的另一端连接第一电容C1的一端，第一电容C1的另一端分别连接第二十四三极管M24的集电极和第一电感L1的一端，第一电感L1的另一端通过第十二电阻R12连接第四供电电压VCC4。其中，电压源Vb1通过第十电阻R10为第二十四三极管M24提供电压偏置。第一电容C1和第十一电阻R11是反馈元件，主要调节低噪声放大器的增益。第十二电阻R12和第一电感L1是负载元件，用于提高低噪声放大器的高频增益，第二电感L2是低噪声放大器的绕线等效电感。
补偿检波单元和检波单元的电路结构相同。补偿检波单元的电路结构包括第十七三极管M17和第十八三极管M18，如图6所示，第十七三极管M17的基极和第十八三极管M18的基极均作为补偿检波单元的输入端，第十七三极管M17的基极输入信号的相位和第十八三极管M18的基极输入信号的相位相差180度，第十七三极管M17的发射极通过第六电流源Ib6接地，第十八三极管M18的发射极通过第八电流源Ib8接地，第十七三极管M17的集电极分别连接第十一三极管M11的发射极、第十一三极管M11的基极、第十二三极管M12的集电极和第十八三极管M18的集电极，第十一三极管M11的集电极、第十二三极管M12的发射极、第十三三极管M13的发射极、第十四三极管M14的发射极、第九三极管M9的集电极和第十三极管M10的集电极均输入第二供电电压VCC2，第十一三极管M11的基极还连接第九三极管M9的基极，第十二三极管M12的基极分别连接第十三三极管M13的基极、第十三三极管M13的集电极、第十四三极管M14的基极、第十四三极管M14的集电极、第十五三极管M15的集电极和第十六三极管M16的集电极，第十五三极管M15的基极连接第十六三极管M16的基极，第十五三极管M15的发射极连接第十六三极管M16的发射极，第十五三极管M15的发射极还通过第七电流源Ib7接地，第九三极管M9的发射极连接第三电阻R3的一端，第三电阻R3的另一端分别连接第十九三极管M19的集电极和第十三极管M10的基极，第十九三极管M19的发射极通过第四电阻R4接地，第十九三极管M19的基极分别连接第十三极管M10的发射极和第二十三极管M20的基极，第十九三极管M19的基极还通过第九电流源Ib9接地，第二十三极管M20的发射极通过第五电阻R5接地，第二十三极管M20的集电极连接第十电流源Ib10的一端，第十电流源Ib10的另一端作为补偿检波单元的输出端。图6中，利用第十七三极管M17和第十八三极管M18的非线性，使得输出电流和输入功率呈对数线性关系。第十五三极管M15和第十六三极管M16的输出电流为输入信号的直流输出，通过第十二三极管M12、第十三三极管M13和第十四三极管M14的电流镜，使得第十一三极管M11的输出电流减去了输入信号的直流分量。第九三极管M9、第十三极管M10、第十九三极管M19、第二十三极管M20、第三电阻R3、第四电阻R4和第五电阻R5构成一个电流镜，可以镜像输出所需的电流。
限幅放大器有两个实施例，分别如下。
实施例1：
实施例1中， N级限幅放大器的电路结构相同，限幅放大器的电路结构包括第一三极管M1和第二三极管M2，如图5所示，第一三极管M1的基极和第二三极管M2的基极均作为限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为限幅放大器的输出端。图5是个对称电路，可以从左半边分析，第一三极管M1、第三三极管M3、第五三极管M5和第一电阻R1构成了一个限幅放大单元，利用第五三极管M5的反馈达到限幅放大的功能。第七三极管M7是射极跟随器，可以降低输出电阻，提高电路带负载的能力。
实施例2：
实施例2中， N为3的倍数，第3 j+1级限幅放大器和第3 j+3级限幅放大器之间设有直流补偿电路，，第3 j+3级限幅放大器的直流电压作为直流补偿电路的输入信号，直流补偿电路将直流电压放大后输出至第3 j+1级限幅放大器。这样能够使得限幅放大器在工作带宽内的直流电压波动减弱，从而提高整个检波器的频率平坦度。
第3 j+1级限幅放大器和第3 j+3级限幅放大器的电路结构相同。如图9所示，第3 j+1级限幅放大器包括第二十五三极管M25和第二十六三极管M26，第二十五三极管M25的基极和第二十六三极管M26的基极均作为第3 j+1级限幅放大器的输入端，第二十五三极管M25的基极输入信号的相位和第二十六三极管M26的基极输入信号的相位相差180度，第二十五三极管M25的发射极通过第十三电流源Ib13接地，第二十六三极管M26的发射极通过第十五电流源Ib15接地，第二十五三极管M25的集电极分别连接第二十七三极管M27的基极、第二十九三极管M29的发射极和第三十一三极管M31的基极，第二十六三极管M26的集电极分别连接第三十三极管M30的发射极、第三十二三极管M32的基极和第二十八三极管M28的基极，第二十九三极管M29的基极分别连接第二十七三极管M27的集电极和第十三电阻R13的一端，第三十三极管M30的基极分别连接第三十一三极管M31的集电极和第十四电阻R14的一端，第十三电阻R13的另一端、第十四电阻R14的另一端、第二十九三极管M29的集电极、第三十三极管M30的集电极、第三十一三极管M31的集电极和第三十二三极管M32的集电极均输入第五供电电压VCC5，第二十七三极管M27的发射极连接第二十八三极管M28的发射极，第二十七三极管M27的发射极通过第十四电流源Ib14接地，第三十一三极管M31的发射极通过第十二电流源Ib12接地，第三十二三极管M32的发射极通过第十六电流源Ib16接地，第三十一三极管M31的发射极和第三十二三极管M32的发射极均作为第3 j+1级限幅放大器的输出端，第二十七三极管M27的集电极还连接第十五电阻R15的一端，第二十八三极管M28的集电极还连接第十六电阻R16的一端，第十五电阻R15的另一端和第十六电阻R16的另一端均连接直流补偿电路的输入端。第3 j+2级限幅放大器采用图5的结构，包括第一三极管M1和第二三极管M2，第一三极管M1的基极和第二三极管M2的基极均作为第3 j+2级限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为第3 j+2级限幅放大器的输出端。
可见，第3 j+3级限幅放大器的电路结构和第3 j+2级限幅放大器的电路结构只有第十五电阻R15和第十六电阻R16不同，其他都相同。第3 j+3级限幅放大器中第十五电阻R15和第十六电阻R16用来提取直流电压Vdc，直流电压Vdc经过直流补偿电路放大后输入第3 j+1级限幅放大器，补偿了直流电压。第3 j+1级限幅放大器中第十五电阻R15和第十六电阻R16用来接收放大后的直流电压Vdc。如图10所示，三极管M33-M35、电流源I17-I19以及第十七电阻R17共同组成了一个直流电压放大电路。
实施例2中，直流补偿电路包括第三十三三极管M33，如图10所示，第三十三三极管M33的基极作为直流补偿电路的输入端，第三十三三极管M33的集电极连接第十七电阻R17的一端，第三十三三极管M33的集电极还输入第六供电电压VCC6，第十七电阻R17的另一端分别连接第三十四三极管M34的集电极和第三十五三极管M35的基极，第三十五三极管M35的集电极作为直流补偿电路的输出端，第三十四三极管M34的基极连接第三十三三极管M33的发射极，第三十三三极管M33的发射极通过第十七电流源Ib17接地，第三十四三极管M34的发射极通过第十八电流源Ib18接地，第三十五三极管M35的发射极通过第十九电流源Ib19接地。
电流求和及驱动单元包括第一场效应管F1和第三场效应管F3，如图7所示，第一场效应管F1的栅极分别连接第二场效应管F2的栅极、第一场效应管F1的漏极、第二十三三极管M23的集电极和第五场效应管F5的栅极，第三场效应管F3的栅极分别连接第四场效应管F4的栅极和第三场效应管F3的漏极，第三场效应管F3的漏极作为电流求和及驱动单元的输入端，第四场效应管F4的漏极分别连接运算放大器OP1的同相输入端、第九电阻R9的一端和第二场效应管F2的漏极，运算放大器OP1的反相输入端连接运算放大器OP1的输出端，运算放大器OP1的接地端接地，运算放大器OP1的偏置端连接第五场效应管F5的漏极，运算放大器OP1的输出端作为电流求和及驱动单元的输出端，第二十三三极管M23的发射极通过第八电阻R8接地，第二十三三极管M23的基极分别连接第二十二三极管M22的发射极和第二十一三极管M21的基极，第二十三三极管M23的基极还通过第七电阻R7接地，第二十一三极管M21的发射极通过第六电阻R6接地，第二十一三极管M21的集电极分别连接第二十二三极管M22的基极和第十一电流源Ib11的一端。没有温度补偿电路时，第十一电流源Ib11的另一端连接外置电流源；有温度补偿电路时，第十一电流源Ib11的另一端连接温度补偿电路的输出端。第二十二三极管M22的集电极、第一场效应管F1的源极、第二场效应管F2的源极、第三场效应管F3的源极、第四场效应管F4的源极和第五场效应管F5的源极均输入第三供电电压VCC3。图7中，第一场效应管F1、第二场效应管F2、第三场效应管F3、第四场效应管F4、第二十一三极管M21、第二十二三极管M22、第二十三三极管M23、第六电阻R6、第七电阻R7、第八电阻R8和第九电阻R9构成一个电流镜，电流在第九电阻R9上形成电压，这个电压通过运算放大器OP1得到想要的输出电压。
此外，检波器还包括温度补偿电路，温度补偿电路的输出端连接电流求和及驱动单元中第十一电流源Ib11的另一端。如图11所示，温度补偿电路包括第六场效应管F6，第六场效应管F6的栅极分别连接第七场效应管F7的栅极、第八场效应管F8的栅极和第二运算放大器OP2的输出端，第六场效应管F6的源极、第七场效应管F7的源极和第八场效应管F8的源极均输入第七供电电压VCC7，第八场效应管F8的漏极作为温度补偿电路的输出端，第六场效应管F6的漏极分别连接第二运算放大器OP2的同相输入端、第三十六三极管M36的基极和第三十六三极管M36的集电极，第七场效应管F7的漏极分别连接第二运算放大器OP2的反相输入端和第十八电阻R18的一端，第十八电阻R18的另一端分别连接第三十七三极管M37的集电极和第三十七三极管M37的基极，第三十六三极管M36的发射极和第三十七三极管M37的发射极均接地。其中，第六场效应管F6、第七场效应管F7、第三十六三极管M36、第三十七三极管M37以及第十八电阻R18共同组成了一个和温度成正比的偏置电流源，即第六场效应管F6和第七场效应管F7的电流是和温度成正比的电流。第二运算放大器OP2的加入是为了将第六场效应管F6和第七场效应管F7的漏极电压钳制在同一电压下，这样偏置电流源的精度和稳定度就会更好。第七场效应管F7和第八场效应管F8组成镜像电流源结构，第七场效应管F7和第八场效应管F8的电流相当，从而使得温度补偿电路的输出电流就是一个和温度成正比的电流，接入电流求和及驱动单元之后就能补偿温度变化对于电流求和及驱动单元的影响，这样使得电流求和及驱动单元在-40℃~85℃的温度范围内的工作状态和工作性能一致，从而使得整个检波器的工作范围拓宽，适用于极端工作环境。
低噪声放大器工作频段为1-18GHz，在工作频段内，其增益特性曲线平坦，平坦度在±1.5dB以内，保证不影响整体检波器的工作带宽；噪声系数带内小于5dB，保证检波电路的灵敏度；线性度高，输出1dB压缩点OP1dB可以达到3dBm，在输入信号功率较高时，功率信号可以无压缩的进入后级。补偿检波单元在低噪声放大器的输出功率大于3dBm时起作用，其工作频段依然时1-18GHz，这样就可以在输入功率较大时补偿输出，其检波范围为（-20dBm，5dBm）。去掉低噪声放大器和补偿检波单元之后的检波输出曲线如图3所示，加了低噪声放大器和补偿检波单元之后的检波输出曲线如图4所示。可见，图3中的检波动态范围为-55dBm~3dBm，图4中的检波动态范围为-70 dBm ~3 dBm，也即加了低噪声放大器和补偿检波单元之后的检波动态范围扩展了15dBm。以上检波动态范围都只考虑线性范围。此外，加了低噪声放大器和补偿检波单元之后的检波器的工作频段为1~18GHz，检波线性度≤±1.5dB，频率平坦度≤±1.5dB，检波输出上升时间为5ns，检波输出下降时间为15ns，功耗为190mA@3.3V，检波输出曲线斜率为15mV/dBm。

Claims (10)

  1. 一种高动态范围的宽频对数检波器，其特征在于：包括低噪声放大器、补偿检波单元、电流求和及驱动单元、 N级限幅放大器和 N级检波单元， N≥2；其中，第一级限幅放大器的输入端连接低噪声放大器的输出端，低噪声放大器的输入端作为整个检波器的输入端，低噪声放大器的输入端还连接补偿检波单元的输入端，补偿检波单元的输出端连接电流求和及驱动单元的输入端，第 i级限幅放大器的输出端分别连接第 i+1级限幅放大器的输入端和第 i级检波单元的输入端，1≤ i≤ N-1，第 i级检波单元的输出端连接电流求和及驱动单元的输入端，第 N级限幅放大器的输出端连接第 N级检波单元的输入端，第 N级检波单元的输出端连接电流求和及驱动单元的输入端，电流求和及驱动单元的输出端作为整个检波器的输出端。
  2. 根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：所述低噪声放大器包括第二十四三极管M24，第二十四三极管M24的发射极通过第二电感L2接地，第二十四三极管M24的基极分别连接第十电阻R10的一端和第十一电阻R11的一端，第二十四三极管M24的基极还作为低噪声放大器的输入端，第十电阻R10的另一端通过电压源Vb1接地，第十一电阻R11的另一端连接第一电容C1的一端，第一电容C1的另一端分别连接第二十四三极管M24的集电极和第一电感L1的一端，第一电感L1的另一端通过第十二电阻R12连接第四供电电压VCC4。
  3. 根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：所述补偿检波单元和检波单元的电路结构相同。
  4. 根据权利要求3所述的高动态范围的宽频对数检波器，其特征在于：所述补偿检波单元的电路结构包括第十七三极管M17和第十八三极管M18，第十七三极管M17的基极和第十八三极管M18的基极均作为补偿检波单元的输入端，第十七三极管M17的基极输入信号的相位和第十八三极管M18的基极输入信号的相位相差180度，第十七三极管M17的发射极通过第六电流源Ib6接地，第十八三极管M18的发射极通过第八电流源Ib8接地，第十七三极管M17的集电极分别连接第十一三极管M11的发射极、第十一三极管M11的基极、第十二三极管M12的集电极和第十八三极管M18的集电极，第十一三极管M11的集电极、第十二三极管M12的发射极、第十三三极管M13的发射极、第十四三极管M14的发射极、第九三极管M9的集电极和第十三极管M10的集电极均输入第二供电电压VCC2，第十一三极管M11的基极还连接第九三极管M9的基极，第十二三极管M12的基极分别连接第十三三极管M13的基极、第十三三极管M13的集电极、第十四三极管M14的基极、第十四三极管M14的集电极、第十五三极管M15的集电极和第十六三极管M16的集电极，第十五三极管M15的基极连接第十六三极管M16的基极，第十五三极管M15的发射极连接第十六三极管M16的发射极，第十五三极管M15的发射极还通过第七电流源Ib7接地，第九三极管M9的发射极连接第三电阻R3的一端，第三电阻R3的另一端分别连接第十九三极管M19的集电极和第十三极管M10的基极，第十九三极管M19的发射极通过第四电阻R4接地，第十九三极管M19的基极分别连接第十三极管M10的发射极和第二十三极管M20的基极，第十九三极管M19的基极还通过第九电流源Ib9接地，第二十三极管M20的发射极通过第五电阻R5接地，第二十三极管M20的集电极连接第十电流源Ib10的一端，第十电流源Ib10的另一端作为补偿检波单元的输出端。
  5. 根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：所述 N级限幅放大器的电路结构相同，限幅放大器的电路结构包括第一三极管M1和第二三极管M2，第一三极管M1的基极和第二三极管M2的基极均作为限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为限幅放大器的输出端。
  6. 根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：所述电流求和及驱动单元包括第一场效应管F1和第三场效应管F3，第一场效应管F1的栅极分别连接第二场效应管F2的栅极、第一场效应管F1的漏极、第二十三三极管M23的集电极和第五场效应管F5的栅极，第三场效应管F3的栅极分别连接第四场效应管F4的栅极和第三场效应管F3的漏极，第三场效应管F3的漏极作为电流求和及驱动单元的输入端，第四场效应管F4的漏极分别连接运算放大器OP1的同相输入端、第九电阻R9的一端和第二场效应管F2的漏极，运算放大器OP1的反相输入端连接运算放大器OP1的输出端，运算放大器OP1的接地端接地，运算放大器OP1的偏置端连接第五场效应管F5的漏极，运算放大器OP1的输出端作为电流求和及驱动单元的输出端，第二十三三极管M23的发射极通过第八电阻R8接地，第二十三三极管M23的基极分别连接第二十二三极管M22的发射极和第二十一三极管M21的基极，第二十三三极管M23的基极还通过第七电阻R7接地，第二十一三极管M21的发射极通过第六电阻R6接地，第二十一三极管M21的集电极分别连接第二十二三极管M22的基极和第十一电流源Ib11的一端，第十一电流源Ib11的另一端连接外置电流源，第二十二三极管M22的集电极、第一场效应管F1的源极、第二场效应管F2的源极、第三场效应管F3的源极、第四场效应管F4的源极和第五场效应管F5的源极均输入第三供电电压VCC3。
  7. 根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：所述 N为3的倍数，第3 j+1级限幅放大器和第3 j+3级限幅放大器之间设有直流补偿电路，，第3 j+3级限幅放大器的直流电压作为直流补偿电路的输入信号，直流补偿电路将直流电压放大后输出至第3 j+1级限幅放大器。
  8. 根据权利要求7所述的高动态范围的宽频对数检波器，其特征在于：所述第3 j+1级限幅放大器和第3 j+3级限幅放大器的电路结构相同；第3 j+1级限幅放大器包括第二十五三极管M25和第二十六三极管M26，第二十五三极管M25的基极和第二十六三极管M26的基极均作为第3 j+1级限幅放大器的输入端，第二十五三极管M25的基极输入信号的相位和第二十六三极管M26的基极输入信号的相位相差180度，第二十五三极管M25的发射极通过第十三电流源Ib13接地，第二十六三极管M26的发射极通过第十五电流源Ib15接地，第二十五三极管M25的集电极分别连接第二十七三极管M27的基极、第二十九三极管M29的发射极和第三十一三极管M31的基极，第二十六三极管M26的集电极分别连接第三十三极管M30的发射极、第三十二三极管M32的基极和第二十八三极管M28的基极，第二十九三极管M29的基极分别连接第二十七三极管M27的集电极和第十三电阻R13的一端，第三十三极管M30的基极分别连接第三十一三极管M31的集电极和第十四电阻R14的一端，第十三电阻R13的另一端、第十四电阻R14的另一端、第二十九三极管M29的集电极、第三十三极管M30的集电极、第三十一三极管M31的集电极和第三十二三极管M32的集电极均输入第五供电电压VCC5，第二十七三极管M27的发射极连接第二十八三极管M28的发射极，第二十七三极管M27的发射极通过第十四电流源Ib14接地，第三十一三极管M31的发射极通过第十二电流源Ib12接地，第三十二三极管M32的发射极通过第十六电流源Ib16接地，第三十一三极管M31的发射极和第三十二三极管M32的发射极均作为第3 j+1级限幅放大器的输出端，第二十七三极管M27的集电极还连接第十五电阻R15的一端，第二十八三极管M28的集电极还连接第十六电阻R16的一端，第十五电阻R15的另一端和第十六电阻R16的另一端均连接直流补偿电路的输入端；第3 j+2级限幅放大器包括第一三极管M1和第二三极管M2，第一三极管M1的基极和第二三极管M2的基极均作为第3 j+2级限幅放大器的输入端，第一三极管M1的基极输入信号的相位和第二三极管M2的基极输入信号的相位相差180度，第一三极管M1的发射极通过第二电流源Ib2接地，第二三极管M2的发射极通过第四电流源Ib4接地，第一三极管M1的集电极分别连接第三三极管M3的基极、第五三极管M5的发射极和第七三极管M7的基极，第二三极管M2的集电极分别连接第六三极管M6的发射极、第八三极管M8的基极和第四三极管M4的基极，第五三极管M5的基极分别连接第三三极管M3的集电极和第一电阻R1的一端，第六三极管M6的基极分别连接第四三极管M4的集电极和第二电阻R2的一端，第一电阻R1的另一端、第二电阻R2的另一端、第五三极管M5的集电极、第六三极管M6的集电极、第七三极管M7的集电极和第八三极管M8的集电极均输入第一供电电压VCC1，第三三极管M3的发射极连接第四三极管M4的发射极，第三三极管M3的发射极通过第三电流源Ib3接地，第七三极管M7的发射极通过第一电流源Ib1接地，第八三极管M8的发射极通过第五电流源Ib5接地，第七三极管M7的发射极和第八三极管M8的发射极均作为第3 j+2级限幅放大器的输出端。
  9. 根据权利要求7所述的高动态范围的宽频对数检波器，其特征在于：所述直流补偿电路包括第三十三三极管M33，第三十三三极管M33的基极作为直流补偿电路的输入端，第三十三三极管M33的集电极连接第十七电阻R17的一端，第三十三三极管M33的集电极还输入第六供电电压VCC6，第十七电阻R17的另一端分别连接第三十四三极管M34的集电极和第三十五三极管M35的基极，第三十五三极管M35的集电极作为直流补偿电路的输出端，第三十四三极管M34的基极连接第三十三三极管M33的发射极，第三十三三极管M33的发射极通过第十七电流源Ib17接地，第三十四三极管M34的发射极通过第十八电流源Ib18接地，第三十五三极管M35的发射极通过第十九电流源Ib19接地。
  10. 、根据权利要求1所述的高动态范围的宽频对数检波器，其特征在于：还包括温度补偿电路，温度补偿电路的输出端连接电流求和及驱动单元；温度补偿电路包括第六场效应管F6，第六场效应管F6的栅极分别连接第七场效应管F7的栅极、第八场效应管F8的栅极和第二运算放大器OP2的输出端，第六场效应管F6的源极、第七场效应管F7的源极和第八场效应管F8的源极均输入第七供电电压VCC7，第八场效应管F8的漏极作为温度补偿电路的输出端，第六场效应管F6的漏极分别连接第二运算放大器OP2的同相输入端、第三十六三极管M36的基极和第三十六三极管M36的集电极，第七场效应管F7的漏极分别连接第二运算放大器OP2的反相输入端和第十八电阻R18的一端，第十八电阻R18的另一端分别连接第三十七三极管M37的集电极和第三十七三极管M37的基极，第三十六三极管M36的发射极和第三十七三极管M37的发射极均接地。
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