WO2020119821A1 - 延时抖动补偿方法、装置及计算机存储介质 - Google Patents

延时抖动补偿方法、装置及计算机存储介质 Download PDF

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WO2020119821A1
WO2020119821A1 PCT/CN2019/125589 CN2019125589W WO2020119821A1 WO 2020119821 A1 WO2020119821 A1 WO 2020119821A1 CN 2019125589 W CN2019125589 W CN 2019125589W WO 2020119821 A1 WO2020119821 A1 WO 2020119821A1
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data
amount
accumulation amount
current
timestamp
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PCT/CN2019/125589
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English (en)
French (fr)
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陈思思
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深圳市中兴微电子技术有限公司
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Priority to US17/312,437 priority Critical patent/US20220021513A1/en
Priority to EP19897382.8A priority patent/EP3883152A4/en
Publication of WO2020119821A1 publication Critical patent/WO2020119821A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/067—Details of the timestamp structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/087—Jitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/10—Active monitoring, e.g. heartbeat, ping or trace-route
    • H04L43/106—Active monitoring, e.g. heartbeat, ping or trace-route using time related information in packets, e.g. by adding timestamps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/28—Timers or timing mechanisms used in protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the present disclosure relates to the field of communication networks, for example, to a method, device and computer storage medium for delay and jitter compensation.
  • the 1588 time synchronization technology has been widely used in communication networks.
  • the basic function of the precision clock synchronization protocol (IEEE 1588 Precision, Clock Synchronization Protocol, 1588 protocol) of the network measurement and control system is to keep the most accurate clock in the distributed network synchronized with other clocks.
  • the 1588 protocol defines a Precision Time Protocol (PTP).
  • PTP can time-synchronize clocks in sensors, actuators, and other terminal devices in standard Ethernet or other distributed bus systems that use multicast technology. .
  • the dynamic jitter of the path delay is relatively large, which affects the calculation of the time deviation, and when the path delay jitter reaches a certain level, it is difficult to achieve time synchronization, and the accuracy of time synchronization is relatively low.
  • Embodiments of the present disclosure provide a method and device for compensating delay jitter and a computer storage medium to solve at least one problem in the related art, and solve the problem of relatively large path delay dynamic jitter and affecting the calculation of time deviation.
  • an embodiment of the present disclosure provides a method for delay jitter compensation.
  • the method includes:
  • the timestamp compensation component determines the current delay jitter of the data link layer according to the latest recorded data accumulation amount and a fixed value of the data accumulation amount, where the fixed value of the data accumulation amount indicates that there is no delay jitter in the data link layer The value of the cumulative amount of data;
  • the timestamp compensation component obtains an initial timestamp recorded by the protocol layer, compensates the initial timestamp according to the current delay jitter of the data link layer, and obtains a compensation timestamp, the compensation timestamp is the initial timestamp Timestamp after compensation.
  • an embodiment of the present disclosure provides a delay jitter compensation device.
  • the device includes:
  • the determining unit is configured to determine the current delay jitter of the data link layer according to the latest recorded data accumulation amount and a fixed value of the data accumulation amount, where the fixed value of the data accumulation amount indicates that there is no delay in the data link layer The value of the accumulated amount of jitter data;
  • the compensation unit is configured to obtain an initial timestamp recorded by the protocol layer, and compensate the initial timestamp according to the current delay jitter of the data link layer to obtain the compensation timestamp, the compensation timestamp is to compensate the initial timestamp Time stamp.
  • an embodiment of the present disclosure provides a delay jitter compensation device, the device including a network interface, a memory, and a processor; wherein,
  • the network interface is configured to implement connection and communication between components
  • the memory is configured to store a computer program that can run on the processor
  • the processor is configured to execute the method when running the computer program.
  • an embodiment of the present disclosure provides a computer storage medium that stores a computer program, and when the computer program is executed by at least one processor, any one of the methods is implemented.
  • FIG. 1 is a schematic diagram of an implementation process of a method for compensating a delay jitter provided by an embodiment of the present disclosure
  • 2a is a schematic diagram of an implementation process of another method for delay and jitter compensation according to an embodiment of the present disclosure
  • 2b is a schematic diagram of an implementation process of another method for delay and jitter compensation according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a delay jitter compensation device provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of time synchronization of a 1588 master-slave clock device according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of another delay jitter compensation device provided by an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a delay and jitter compensation provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a hardware structure of a delay and jitter compensation device provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of an implementation process of a delay jitter compensation method provided by an embodiment of the present disclosure. As shown in FIG. 1, the method includes steps 1010 to 1020.
  • Step 1010 The timestamp compensation component determines the current delay jitter of the data link layer according to the latest recorded data accumulation amount and a fixed value of the data accumulation amount, where the fixed value of the data accumulation amount indicates that there is no data link layer The value of the accumulated data of delay jitter.
  • the timestamp compensation component before the timestamp compensation component determines the current delay jitter of the data link layer according to the latest recorded data accumulation amount and the fixed value of the data accumulation amount, the timestamp compensation component receives the data link The current time data accumulation amount sent by the road layer, and the current time data accumulation amount is recorded as the data accumulation amount.
  • the timestamp compensation component obtains the maximum and minimum values of the accumulated data amount in the current period according to the accumulated amount of multiple data recorded in the current period.
  • the period may be a preset length of time, for example, the period of time may be 1 second, 2 seconds, and so on.
  • the timestamp compensation component calculates a fixed value of the data accumulation amount according to the maximum value and the minimum value of the data accumulation amount in the current period, for example, calculates an average value of the maximum value and the minimum value of the data accumulation amount in the current period, to obtain a data link
  • There is no accumulated data of delay jitter in the layer that is, a fixed value of the accumulated data.
  • the fixed value of the data accumulation amount corresponds to different periods, and the fixed value of the data accumulation amount obtained in different periods may be the same or different.
  • the first fixed value of the data accumulation amount will be used to determine the delay jitter of the data link layer in the next cycle.
  • the fixed value of the data accumulation amount obtained by the timestamp compensation component is the data accumulation amount without delay jitter in the data link layer.
  • the latest recorded data accumulation amount may have the data accumulation amount of delay jitter.
  • the timestamp compensation component can be based on the data The fixed value of the accumulated amount and the latest recorded data accumulated amount determine the current delay jitter of the data link layer.
  • the data link layer before the timestamp compensation component receives the current data accumulation amount sent by the data link layer, the data link layer will obtain the current data write amount and the current time data read amount, and also obtain the previous Time data accumulation amount, according to the current time data writing amount, current time data reading amount and the previous time data accumulation amount, the current time data accumulation amount is obtained, wherein the data writing amount is based on the data link layer
  • the data write enable and the data bus bit width of the input interface of the data link layer are calculated.
  • the amount of data read is based on the data read enable of the data link layer and the data bus bit width of the output interface of the data link layer. It is calculated from the expansion or contraction coefficient of the data flow rate from the input interface to the output interface of the data link layer at the current moment.
  • the data link layer sends the current data amount according to the current data write amount, the current time data read amount, and the previous time data accumulation amount, after obtaining the current time data accumulation amount
  • the time data accumulation amount reaches the timestamp compensation component; the timestamp compensation component receives the current time data accumulation amount, and records the current time data accumulation amount as the data accumulation amount.
  • the data link layer also records the current data accumulation amount, so that the latest recorded current time data accumulation amount is used as the data accumulation amount of the previous time of the next time, and is used in calculating the current time data accumulation amount of the next time, and
  • the current time data accumulation amount is sent to the timestamp compensation component, so that the timestamp compensation component determines the maximum value and the minimum value of the data accumulation amount in the current period.
  • Step 1020 The timestamp compensation component obtains an initial timestamp recorded by the protocol layer, compensates the initial timestamp according to the current delay jitter of the data link layer, and obtains a compensation timestamp.
  • the initial timestamp is the timestamp after compensation.
  • the initial timestamp recorded by the protocol layer may be the timestamp of the PTP packet sent by the protocol layer or the timestamp of the PTP packet received by the protocol layer, where the PTP packet is defined by the 1588 protocol to indicate the completion of time synchronization Packet.
  • the timestamp compensation component may compensate the initial timestamp according to the current delay jitter of the data link layer to obtain the timestamp after compensating the initial timestamp, The compensation timestamp.
  • the 1588 time calculation is directly used by the initial time stamp, which will affect the calculation of the time deviation; if the initial time stamp recorded by the protocol layer is compensated, The 1588 time calculation is performed by using the compensation timestamp.
  • the delay jitter can be automatically offset, which makes the calculation of the time deviation more accurate and improves the accuracy of time synchronization.
  • the timestamp compensation component determines the current delay jitter of the data link layer according to the latest recorded data accumulation amount and the fixed value of the data accumulation amount, and compensates the initial timestamp according to the current delay jitter of the data link layer To obtain the compensation timestamp, use the compensation timestamp to perform 1588 time calculation. In the process of calculating the time deviation, it can automatically offset the delay jitter, making the time deviation calculation more accurate and improving the time accuracy.
  • FIG. 2a is a schematic diagram of an implementation process of another method for delay jitter compensation provided by an embodiment of the present disclosure. As shown in FIG. 2a, the method is applied to a sending device and includes steps. 201a to step 207a.
  • Step 201a The protocol layer in the sending device records a first initial time stamp for sending a PTP packet.
  • the PTP packet is a data packet defined by the 1588 protocol to indicate completion of time synchronization.
  • the first initial time stamp indicates that the PTP packet is sent. Moment.
  • the protocol layer in the sending device records that the first initial timestamp for sending the PTP packet is tx_time, where the PTP packet is a data packet defined by the 1588 protocol to indicate completion of time synchronization, and the PTP packet is accompanied by other
  • the data stream enters the data link layer in the sending device.
  • Step 202a The data link layer in the sending device acquires the first current time data write amount and the first current time data read amount.
  • the data link layer in the sending device is regarded as a virtual cache, that is, data is written on the input interface of the data link layer, and data is read on the output interface of the data link layer.
  • the input interface of the data link layer is the write clock.
  • the layer's cache write operation; when en_w1 0, it means that the data link layer has no cache write operation this time, and the data bus bit width of the input interface is bit_w1, then the first current data write amount is calculated, that is, en_w1 *bit_w1.
  • the output interface of the data link layer is the read clock.
  • the effective signal of the data is the read enable en_r1
  • the bit width of the data bus of the output interface is bit_r1
  • the first current data read is calculated
  • the output is en_r1*bit_r1*c_r_w1
  • c_r_w1 represents the expansion or contraction coefficient of the data flow rate from the input interface to the output interface of the data link layer at the current moment
  • the expansion or contraction coefficient represents the data after passing through the data link layer
  • Step 203a The data link layer in the sending device acquires the first previous moment data accumulation amount, and according to the data link layer in the sending device, the first current time data write amount, the first current time data read amount, and the first The data accumulation amount at the previous moment obtains the first data accumulation amount at the current moment.
  • the data accumulation amount at the first previous moment acquired by the data link layer in the sending device is bit_sum1
  • the first current The time data read amount en_r1*bit_r1*c_r_w1 calculate the first current time data accumulation amount tx_bit_sum is bit_sum1+en_w1*bit_w1-en_r1*bit_r1*c_r_w1.
  • Step 204a The data link layer in the sending device records the first current time data accumulation amount, and sends the first current time data accumulation amount to the first timestamp compensation component.
  • the first current time data accumulation amount is recorded, so that the latest recorded first current time data accumulation amount is used as the next
  • the data accumulation amount at the first previous time of the time is used in calculating the data accumulation amount at the first current time of the next time
  • the first current time data accumulation amount is sent to the first timestamp compensation component, so that the first timestamp
  • the compensation component determines the maximum and minimum values of the data accumulation in the current cycle.
  • Step 205a The first timestamp compensation component receives the first current time data accumulation amount sent by the data link layer in the sending device, and records the first current time data accumulation amount as the first data accumulation amount.
  • Step 206a The first timestamp compensation component determines the current delay jitter of the data link layer in the sending device according to the latest recorded first data accumulation amount and the first fixed value of the data accumulation amount.
  • a fixed value indicates the amount of accumulated data without delay jitter in the sending device.
  • the first timestamp compensation component obtains the maximum and minimum values of the accumulated data amount in the current period according to the accumulated amount of data recorded in the current period, and the length of the period can be 1 second, 2 seconds, etc. Time length, when the period of time is 2 seconds, the first timestamp compensation component will obtain the maximum and minimum value of the current data accumulation amount in the current 2 seconds according to the data accumulation amount recorded in the current 2 seconds every 2 seconds .
  • the first timestamp compensation component can calculate the first fixed value of the data accumulation amount according to the maximum and minimum values of the data accumulation amount in the current period, for example, the first fixed value of the data accumulation amount can be the data accumulation in the current period
  • the average value of the maximum value and the minimum value of the amount can also be calculated according to the cumulative amount of data recorded in the current period, using the integration algorithm (integration method in mathematics) to calculate the first fixed value of the cumulative amount of data, the first fixed amount of accumulated data
  • the value indicates the amount of accumulated data without delay jitter in the transmitting device.
  • the first fixed value of the data accumulation amount corresponds to different periods, and the first fixed value of the data accumulation amount obtained in different periods may be the same or different.
  • the first fixed value of the data accumulation amount will be used to determine the delay jitter of the data link layer in the transmitting device in the next cycle.
  • the first timestamp compensation component determines the first fixed value of the data accumulation amount in the previous period, it may be based on the latest recorded first data accumulation amount and the first fixed value of the data accumulation amount determined in the previous period Value to determine the current delay jitter of the data link layer in the sending device.
  • tx_bit_sum-tx_constant_bit_sum can represent the waterline jitter of the data link layer of the sending device
  • (tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit can represent the data link of the sending device Delay jitter of the road layer, where tx_compensate_unit represents the conversion unit from the accumulated amount of data to time.
  • Step 207a The first timestamp compensation component obtains the first initial timestamp of the transmitted PTP packet recorded by the protocol layer in the sending device, and compensates the first initial timestamp according to the current delay jitter of the data link layer in the sending device to obtain A first compensation timestamp, the first compensation timestamp is a timestamp after the first initial timestamp is compensated.
  • the first timestamp compensation component obtains the first initial timestamp sent by the protocol layer in the sending device to send the PTP packet to send is tx_time, when (tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit is greater than 0, it means that the sending device The data link layer of the data is written faster than the data read.
  • the first initial timestamp tx_time makes the first compensation timestamp (the timestamp after the first initial timestamp is compensated) later than the first initial timestamp tx_time, the first compensation timestamp is tx_time+(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit,
  • the first compensation timestamp is the timestamp actually participating in the 1588 time calculation.
  • the delay jitter can be automatically offset.
  • FIG. 2b is a schematic diagram of an implementation process of another method for delay jitter compensation provided by an embodiment of the present disclosure. As shown in FIG. 2b, the method is applied to a receiving device, including: Step 201b to step 207b.
  • Step 201b The data link layer in the receiving device acquires the data writing amount at the second current time and the data reading amount at the second current time.
  • the data stream is transmitted to the transmission medium between the transmission device and the reception device through the data link layer and the physical interface layer in the transmission device, it is also transmitted through the transmission medium and the physical interface layer of the reception device To the data link layer of the receiving device, so that the data link layer in the receiving device can acquire the data writing amount and the data reading amount at the second current time.
  • the data link layer in the receiving device is regarded as a virtual cache, that is, data is written on the input interface of the data link layer, and data is read on the output interface of the data link layer.
  • the input interface of the data link layer is the write clock.
  • the output interface of the data link layer is the read clock. After the data link layer reads the data, the effective signal of the data is read enable en_r2, and the data bus of the output interface has a bit width of bit_r2.
  • the output is en_r2*bit_r2*c_r_w2, where c_r_w2 represents the expansion or contraction coefficient of the data flow rate from the input interface to the output interface of the data link layer at the current moment, and the expansion or contraction coefficient represents the data after passing through the data link layer The ratio of the total amount to the total amount of data before passing through the data link layer.
  • Step 202b The data link layer in the receiving device acquires the data accumulation amount at the second previous time, and according to the data write amount at the second current time, the data read amount at the second current time, and the second at the data link layer in the receiving device The accumulated amount of data at the previous moment obtains the accumulated amount of data at the second current moment.
  • the second current The time data read amount en_r2*bit_r2*c_r_w2 is calculated as bit_sum2+en_w2*bit_w2-en_r2*bit_r2*c_r_w2.
  • Step 203b The data link layer in the receiving device records the second current time data accumulation amount, and sends the second current time data accumulation amount to the second timestamp compensation component.
  • the second current time data accumulation amount is recorded, so that the latest recorded second current time data accumulation amount is used as the next
  • the data accumulation amount at the second previous time of the time is used in calculating the data accumulation amount at the second current time of the next time
  • the data accumulation amount at the second current time is sent to the second timestamp compensation component, so that the second timestamp
  • the compensation component determines the maximum and minimum values of the data accumulation in the current cycle.
  • Step 204b The second timestamp compensation component receives the second current time data accumulation amount sent by the data link layer in the receiving device, and records the second current time data accumulation amount as the second data accumulation amount.
  • Step 205b The second timestamp compensation component determines the current delay jitter of the data link layer in the receiving device according to the newly recorded second data accumulation amount and the second fixed value of the data accumulation amount.
  • the two fixed values indicate the accumulated amount of data without delay jitter in the receiving device.
  • the second timestamp compensation component obtains the maximum and minimum values of the accumulated data amount in the current period according to the accumulated amount of multiple data recorded in the current period.
  • the length of the period can be 1 second, 2 seconds, etc. Time length, when the time length of the cycle is 2 seconds, the second timestamp compensation component will obtain the maximum and minimum value of the current data accumulation amount in the current 2 seconds according to the data accumulation amount recorded in the current 2 seconds every 2 seconds .
  • the second timestamp compensation component can calculate the second fixed value of the data accumulation amount according to the maximum and minimum values of the data accumulation amount in the current period, for example, the second fixed value of the data accumulation amount can be the data accumulation in the current period
  • the average value of the maximum value and the minimum value of the amount can also be calculated according to the cumulative amount of data recorded in the current period, using the integration algorithm (integration method in mathematics) to calculate the second fixed value of the cumulative amount of data, the second fixed amount of the cumulative amount of data
  • the value indicates the accumulated amount of data without delay jitter in the receiving device.
  • the second fixed value of the data accumulation amount corresponds to different periods, and the second fixed value of the data accumulation amount obtained in different periods may be the same or different.
  • the second fixed value of the data accumulation amount will be used to determine the delay jitter of the data link layer in the receiving device in the next cycle.
  • the second timestamp compensation component determines the second fixed value of the data accumulation amount in the previous period, it may be based on the newly recorded second data accumulation amount and the second fixed value of the data accumulation amount determined in the previous period Value to determine the current delay jitter of the data link layer in the receiving device.
  • rx_bit_sum-rx_constant_bit_sum can represent the waterline jitter of the data link layer of the receiving device
  • (rx_bit_sum-rx_constant_bit_sum))*rx_compensate_unit can represent the data of the receiving device Delay jitter of the link layer, where rx_compensate_unit represents the conversion unit from the accumulated amount of data to time.
  • Step 206b The protocol layer in the receiving device records the second initial time stamp of receiving the PTP packet, where the second initial time stamp indicates the time when the PTP packet is received.
  • the PTP packet after the protocol layer in the sending device sends the PTP packet, the PTP packet will be transmitted to the transmission medium between the sending device and the receiving device through the data link layer and the physical interface layer in the sending device, and will also be transmitted.
  • the medium, the physical interface layer of the receiving device, and the data link layer of the receiving device are transmitted to the protocol layer of the receiving device, so that the protocol layer of the receiving device receives the PTP packet.
  • the protocol layer in the receiving device records that the second initial time stamp of receiving the PTP packet is rx_time.
  • Step 207b The second timestamp compensation component obtains the second initial timestamp recorded by the protocol layer in the receiving device and sent by the received PTP packet, and compensates the second initial timestamp according to the current delay jitter of the data link layer in the receiving device, A second compensation timestamp is obtained, and the second compensation timestamp is a timestamp after compensating the second initial timestamp.
  • the second timestamp compensation component obtains the second initial timestamp of the received PTP packet recorded by the protocol layer in the receiving device as rx_time.
  • rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit is greater than 0, it indicates that the receiving device Data reading at the data link layer is faster than data writing.
  • the second initial timestamp rx_time makes the second compensation timestamp (the timestamp after the second initial timestamp is compensated) earlier than the second initial timestamp tx_time, the second compensation timestamp is rx_time-(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit , Where the second compensation timestamp is the timestamp actually participating in the 1588 time calculation.
  • the delay jitter can be automatically offset.
  • the path delay from the protocol layer in the sending device to the protocol layer in the receiving device is calculated using the first initial timestamp and the second initial timestamp.
  • Delay rx_time-tx_time tx_delay_constant+tx_delay_jitter+rx_delay_constant+rx_delay_jitter, where tx_delay_constant is the delay constant part of the sending device, that is, the fixed value of the data link layer delay in the sending device, tx_delay_jitter is the delay jitter part of the sending device, rx_delay_constant is the delay constant part of the receiving device, that is, the fixed delay value of the data link layer in the receiving device, and rx_delay_jitter is the delay jitter part of the receiving device.
  • tx_delay_jittert and rx_delay_jitter will affect the calculation of time deviation, thereby reducing the accuracy of
  • the path delay calculation formula is as shown in equation (1):
  • the 1588 master clock device in the 1588 protocol includes a sending device and a receiving device
  • the 1588 slave clock device also includes a sending device and a receiving device.
  • the sending device in the 1588 master clock device performs the above delay jitter compensation method to obtain the first compensation timestamp
  • 1588 performs the above delay jitter compensation method from the receiving device in the clock device to obtain the second compensation time Time stamp
  • 1588 slave transmission device in the clock device performs the above-mentioned delay jitter compensation method to obtain the third compensation time stamp
  • 1588 master clock device reception device performs the above-mentioned delay jitter compensation method to obtain the fourth compensation time stamp.
  • the first compensation timestamp, the second compensation timestamp, the third compensation timestamp, and the fourth compensation timestamp are used to synchronize the time between the master and slave clock devices, so that the path in the sending device and the receiving device The delay tends to be a fixed value, improving the timing accuracy of the master and slave clock devices.
  • the Media Access Control (MAC) layer of Ethernet is selected as the protocol layer in the embodiment of the present disclosure.
  • the physical coding sublayer (Physical Coding Sublayer, PCS) and physical medium connection (Physical Medium Attachment, PMA) sublayer serve as the data link layer in the embodiments of the present disclosure, and the serializer/deserializer (SERDES)
  • the He optical module serves as the physical interface layer in the embodiments of the present disclosure.
  • the MAC layer in the 10GE sending device records the first initial timestamp for sending the PTP packet.
  • the PCS and PMA sublayers transmit Ethernet service data to obtain the accumulated data amount at the first previous moment, based on the data write amount at the first current moment, the data readout amount at the first current moment, and the accumulated data amount at the first previous moment, to obtain The first current data accumulation amount.
  • the first timestamp compensation component obtains the first current time data accumulation amount sent by the PCS and PMA sublayers in the 10GE sending device, records the first current time data accumulation amount as the first data accumulation amount, based on the latest recorded first data
  • the accumulated amount and the first fixed value of the accumulated amount of data determine the current delay jitter of the PCS and PMA sublayers in the 10GE sending device
  • the MAC layer records the first initial timestamp of the transmitted PTP packet according to the current delay jitter compensation to obtain First compensation timestamp.
  • the SERDES and optical module in the 10GE transmission device converts the logical digital signals transmitted by the PCS and PMA sublayers into optical signals, and transmits the optical signals to the optical fiber.
  • the optical fiber transmits the optical signal to the SERDES and optical module in the 10GE receiving device.
  • the SERDES and optical modules in the 10GE receiving device convert the optical signals transmitted by the optical fiber into logical digital signals, and transmit the logical digital signals to the PCS and PMA sublayers in the 10GE receiving device.
  • the PCS and PMA sublayers obtain the second previous time data accumulation amount, and obtain the second current time data accumulation amount according to the second current time data writing amount, the second current time data reading amount, and the second previous time data accumulation amount the amount.
  • the second timestamp compensation component obtains the second current time data accumulation amount sent by the PCS and PMA sublayers in the 10GE receiving device, and records the second current time data accumulation amount as the second data accumulation amount, based on the newly recorded second data
  • the accumulated amount and the second fixed value of the accumulated amount of data determine the current delay jitter of the PCS and PMA sublayers in the 10GE receiving device.
  • the MAC layer in the 10GE receiving device records the second initial time stamp of the received PTP packet.
  • the second timestamp compensation component obtains the second initial timestamp, compensates the second initial timestamp according to the current delay jitter of the PCS and PMA sublayers in the 10GE receiving device, and obtains the second compensation timestamp. Therefore, when the time offset is calculated using the compensated timestamp, the delay jitter can be automatically offset, so that the path delay in the 10GE transmitting device and the 10GE receiving device tends to a fixed value, thereby improving the accuracy of time synchronization.
  • FIG. 6 is a schematic structural diagram of a delay jitter compensation provided by an embodiment of the present disclosure.
  • the delay jitter compensation device 600 includes: a determination unit 601 and compensation unit 602.
  • the determining unit 601 is configured to determine the current delay jitter of the data link layer according to the latest recorded data accumulation amount and a fixed value of the data accumulation amount, where the fixed value of the data accumulation amount indicates that there is no delay in the data link layer The amount of data accumulated when jittering;
  • the compensation unit 602 is configured to obtain the initial timestamp recorded by the protocol layer, and compensate the initial timestamp according to the current delay jitter of the data link layer to obtain the compensation timestamp.
  • the compensation timestamp is performed on the initial timestamp. Timestamp after compensation.
  • the device 600 may further include:
  • the recording unit 603 is configured to receive the current data accumulation amount sent by the data link layer, and record the current time data accumulation amount as the data accumulation amount.
  • the recording unit 603 is further configured to obtain the maximum value and the minimum value of the data accumulation amount in the current period according to a plurality of data accumulation amounts recorded in the current period; according to the data accumulation amount in the current period The maximum and minimum values are used to calculate the fixed value of the data accumulation.
  • the determination unit 601, the compensation unit 602, and the recording unit 603 may be located in the timestamp compensation component in the foregoing technical solution description.
  • the device 600 may further include:
  • the obtaining unit 604 is configured to obtain the data writing amount and the data reading amount of the current time at the data link layer; the data link layer obtains the data accumulation amount at the previous time; the data link layer according to the current time The amount of data written, the amount of data read at the current time, and the amount of accumulated data at the previous time are obtained as the amount of accumulated data at the current time.
  • the device 600 may further include:
  • the sending unit 605 is configured to send the current data accumulation amount to the timestamp compensation component by the data link layer.
  • the acquiring unit 604 and the sending unit 605 may be located at the data link layer in the above technical solution.
  • the delay jitter compensation device is provided in the sending device and/or the receiving device.
  • the multiple components in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software function module.
  • the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it may be stored in a computer-readable storage medium, and the technical solutions of the embodiments of the present disclosure may be embodied in the form of software products
  • the computer software product is stored in a storage medium and includes multiple instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) or processor (processor) to execute the embodiments of the present disclosure All or part of the method.
  • the aforementioned storage media include: Universal Serial Bus flash disk (Universal Serial Bus flash disk, U disk), mobile hard disk, read only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), Various media that can store program codes, such as magnetic disks or optical disks.
  • an embodiment of the present disclosure provides a computer storage medium that stores a computer program, and when the computer program is executed by at least one processor, the method described in the foregoing embodiment is implemented.
  • FIG. 7 it shows a hardware structure of a delay and jitter compensation apparatus 700 provided by an embodiment of the present disclosure, including: a network interface 701, a memory 702 and a processor 703; multiple components are coupled together through a bus system 704.
  • the bus system 704 is configured to implement connection and communication between these components.
  • the bus system 704 also includes a power bus, a control bus, and a status signal bus.
  • various buses are marked as the bus system 704. among them,
  • the network interface 701 is set to receive and send signals during the process of sending and receiving information with other external network elements;
  • the memory 702 is configured to store a computer program that can run on the processor 703;
  • the processor 703 is configured to execute: when running the computer program:
  • the timestamp compensation component determines the current delay jitter of the data link layer according to the latest recorded data accumulation amount and a fixed value of the data accumulation amount, where the fixed value of the data accumulation amount indicates that there is no delay jitter in the data link layer
  • the cumulative amount of data
  • the timestamp compensation component obtains an initial timestamp recorded by the protocol layer, compensates the initial timestamp according to the current delay jitter of the data link layer, and obtains a compensation timestamp, the compensation timestamp is the initial timestamp Timestamp after compensation.
  • the processor 703 is further configured to execute:
  • the timestamp compensation component receives the current data accumulation amount sent by the data link layer, and records the current time data accumulation amount as the data accumulation amount.
  • the processor 703 is further configured to execute:
  • the timestamp compensation component obtains the maximum value and the minimum value of the data accumulation amount in the current period according to the multiple data accumulation amounts recorded in the current period;
  • the timestamp compensation component obtains a fixed value of the data accumulation amount according to the maximum value and the minimum value of the data accumulation amount in the current period.
  • the processor 703 is further configured to execute:
  • the data link layer obtains the current data write amount and current data read amount
  • the data link layer obtains the data accumulation amount at the previous time, and obtains the data accumulation amount at the current time according to the data writing amount at the current time, the data reading amount at the current time, and the data accumulation amount at the previous time.
  • the processor 703 is further configured to execute:
  • the data link layer sends the current data accumulation amount to the timestamp compensation component
  • the timestamp compensation component records the current data accumulation amount of the data link layer as the data accumulation amount.
  • the memory 702 in the embodiments of the present disclosure may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electronically Erasable programmable read only memory (Electrically, EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDRSDRAM
  • enhanced SDRAM ESDRAM
  • Sync synchronous connection dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory
  • Direct Rambus RAM Direct Rambus RAM
  • the processor 703 may be an integrated circuit chip with signal processing capabilities. In the implementation process, multiple steps of the above method may be completed by an integrated logic circuit of hardware in the processor 703 or instructions in the form of software.
  • the foregoing processor 703 may be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an existing programmable gate array (Field Programmable Gate Array, FPGA), or other Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Multiple methods, steps, and logical block diagrams disclosed in the embodiments of the present disclosure may be implemented or executed.
  • the general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the method disclosed in conjunction with the embodiments of the present disclosure may be directly embodied and executed by a hardware decoding processor, or may be executed and completed by a combination of hardware and software modules in the decoding processor.
  • the software module may be located in a storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, and a register.
  • the storage medium is located in the memory 702, and the processor 703 reads the information in the memory 702 and completes the above method in combination with its hardware.
  • the terms “include”, “include” or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device that includes a series of elements includes not only those elements , And also include other elements that are not explicitly listed, or include elements inherent to this process, method, article, or device. Without more restrictions, the element defined by the sentence "include one" does not exclude that there are other identical elements in the process, method, article or device that includes the element.
  • the disclosed method and device may be implemented in other ways.
  • the terminal embodiments described above are only schematic.
  • the division of the units is only a division of logical functions.
  • there may be other divisions for example, multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the displayed or discussed multiple components are coupled to each other, or directly coupled, or the communication connection may be through some interfaces, and the indirect coupling or communication connection of the device or unit may be electrical, mechanical, or other Form.

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Abstract

本公开实施例公开了一种延时抖动补偿方法、装置及计算机存储介质，方法包括：时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值；所述时戳补偿组件获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿所述初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。

Description

延时抖动补偿方法、装置及计算机存储介质
本申请要求在2018年12月14日提交中国专利局、申请号为201811533615.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及通信网络领域，例如涉及一种延时抖动补偿方法、装置及计算机存储介质。
背景技术
近年来，1588时间同步技术在通信网络中得到广泛应用。网络测量和控制系统的精密时钟同步协议(IEEE 1588 Precision Clock Synchronization Protocol，1588协议)的基本功能是使分布式网络内的最精确时钟与其他时钟保持同步。1588协议定义了一种精确时间协议(Precision Time Protocol，PTP)，PTP可以对标准以太网或其他采用多播技术的分布式总线系统中的传感器、执行器以及其他终端设备中的时钟进行时间同步。
在应用1588协议时，路径延时的动态抖动比较大，影响时间偏差的计算，而且当路径延时抖动达到一定程度时，很难达到时间同步，对时的精度也比较低。
发明内容
本公开实施例为解决相关技术中存在的至少一个问题而提供一种延时抖动补偿方法、装置及计算机存储介质，解决路径延时动态抖动比较大，影响时间偏差的计算的问题。
在一实施例中，本公开实施例提供一种延时抖动补偿方法，所述方法包括：
时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值；
所述时戳补偿组件获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿所述初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
在一实施例中，本公开实施例提供一种延时抖动补偿装置，所述装置包括：
确定单元，设置为根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值；
补偿单元，设置为获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
在一实施例中，本公开实施例提供一种延时抖动补偿装置，所述装置包括网络接口、存储器和处理器；其中，
所述网络接口，配置为实现组件之间的连接通信；
所述存储器，配置为存储能够在所述处理器上运行的计算机程序；
所述处理器，配置为在运行所述计算机程序时，执行所述方法。
在一实施例中，本公开实施例提供一种计算机存储介质，所述计算机存储介质存储有计算机程序，当所述计算机程序被至少一个处理器执行时实现所述任一方法。
附图说明
图1为本公开实施例提供的一种延时抖动补偿方法的实现流程示意图；
图2a为本公开实施例提供的另一种延时抖动补偿方法的实现流程示意图；
图2b为本公开实施例提供的另一种延时抖动补偿方法的实现流程示意图；
图3为本公开实施例提供的一种延时抖动补偿装置示意图；
图4为本公开实施例提供的一种1588主从时钟设备对时示意图；
图5为本公开实施例提供的另一种延时抖动补偿装置示意图
图6为本公开实施例提供的一种延时抖动补偿的结构示意图；
图7为本公开实施例提供的一种延时抖动补偿装置的硬件结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对公开的技术方案进行描述。以下实施例用于说明本公开，但不用来限制本公开的范围。
本公开实施例提供的一种延时抖动补偿方法，图1为本公开实施例提供的一种延时抖动补偿方法的实现流程示意图，如图1所示，该方法包括步骤1010 至步骤1020。
步骤1010、时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值。
在一实施例中，在所述时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动之前,所述时戳补偿组件会接收数据链路层发送的当前时刻数据累积量，并将所述当前时刻数据累积量记录为数据累积量。
在一实施例中，时戳补偿组件会根据当前周期内记录的多个数据累积量，获得当前周期内数据累积量的最大值和最小值。其中，所述周期可以是预设的时间长度，例如周期的时间长度可以是1秒、2秒等时间长度。时戳补偿组件根据所述当前周期内数据累积量的最大值和最小值，计算数据累积量的固定值，例如计算当前周期内数据累积量的最大值和最小值的平均值，获得数据链路层中没有延时抖动的数据累积量，即数据累积量的固定值。数据累积量的固定值与不同周期相对应，不同周期内得到的数据累积量的固定值可能相同、也可能不同。数据累积量的第一固定值将在下一周期用于确定数据链路层的延时抖动。
时戳补偿组件获得的数据累积量的固定值为数据链路层中没有延时抖动的数据累积量，最新记录的数据累积量可能有延时抖动的数据累积量，时戳补偿组件可以根据数据累积量的固定值以及最新记录的数据累积量，确定出数据链路层当前的延时抖动。
在一实施例中，在时戳补偿组件接收数据链路层发送的当前时刻数据累积量之前，数据链路层会获取当前时刻数据写入量和当前时刻数据读出量，还会获取前一时刻数据累积量，根据所述当前时刻数据写入量、当前时刻数据读出量以及前一时刻数据累积量，获得当前时刻数据累积量，其中，数据的写入量是根据数据链路层的数据写使能和数据链路层的输入接口的数据总线位宽计算得到的，数据的读出量是根据数据链路层的数据读使能、数据链路层的输出接口的数据总线位宽和当前时刻数据链路层的输入接口到输出接口中数据流速率的膨胀或收缩系数计算得到的。
在一实施例中，数据链路层根据所述当前时刻数据写入量、当前时刻数据读出量以及前一时刻数据累积量，获得当前时刻数据累积量后，数据链路层发送所述当前时刻数据累积量至所述时戳补偿组件；时戳补偿组件接收到当前时刻数据累积量，并将当前时刻数据累积量记录为数据累积量。数据链路层还会记录当前时刻数据累积量，以便将最新记录的当前时刻数据累积量作为下一时刻的前一时刻数据累积量，在计算下一时刻的当前时刻数据累积量中使用，并 将当前时刻数据累积量发送至时戳补偿组件，以便时戳补偿组件确定当前周期内数据累积量的最大值和最小值。
步骤1020、所述时戳补偿组件获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿所述初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
在一实施例中，协议层记录的初始时戳可以是协议层发送PTP包的时戳，也可以是协议层接收PTP包的时戳，其中PTP包是1588协议定义的用于指示完成时间同步的数据包。
时戳补偿组件获取了协议层记录的初始时戳后，可以根据所述数据链路层当前的延时抖动补偿所述初始时戳，来获得对所述初始时戳进行补偿后的时戳，即补偿时戳。当数据链路层当前有延时抖动，若不补偿协议层记录的初始时戳，直接利用初始时戳进行1588对时计算，会影响时间偏差的计算；若补偿协议层记录的初始时戳，利用补偿时戳进行1588对时计算，在计算时间偏差的过程中，可以自动抵消延时抖动，使得时间偏差的计算更加精确，提高对时精度。
本公开实施例，时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，并根据数据链路层当前的延时抖动补偿初始时戳，得到补偿时戳，利用补偿时戳进行1588对时计算，在计算时间偏差的过程中，可以自动抵消延时抖动，使得时间偏差的计算更加精确，提高对时精度。
本公开实施例提供一种延时抖动补偿方法，图2a为本公开实施例提供的另一种延时抖动补偿方法的实现流程示意图，如图2a所示，该方法应用于发送装置，包括步骤201a至步骤207a。
步骤201a、发送装置中的协议层记录发送PTP包的第一初始时戳，所述PTP包为1588协议定义的用于指示完成时间同步的数据包，所述第一初始时戳表示发送PTP包的时刻。
在一实施例中，发送装置中的协议层记录发送PTP包的第一初始时戳为tx_time，其中所述PTP包是1588协议定义的用于指示完成时间同步的数据包，该PTP包伴随其他数据流进入发送装置中的数据链路层。
步骤202a、发送装置中的数据链路层获取第一当前时刻数据写入量和第一当前时刻数据读出量。
在一实施例中，将发送装置中的数据链路层视为虚拟缓存，即在数据链路层的输入接口写入数据，在数据链路层的输出接口读出数据。数据链路层的输入接口为写时钟，当数据链路层写入数据后，该数据的有效信号为写使能en_w1， en_w1＝1或en_w1＝0，当en_w1＝1时，表示数据链路层此次缓存写入操作；当en_w1＝0时，表示数据链路层此次没有缓存写入操作，输入接口的数据总线位宽为bit_w1，则计算第一当前时刻数据写入量，即en_w1*bit_w1。数据链路层的输出接口为读时钟，当数据链路层读出数据后，该数据的有效信号为读使能en_r1，输出接口的数据总线位宽为bit_r1，则计算第一当前时刻数据读出量，即en_r1*bit_r1*c_r_w1，其中c_r_w1表示当前时刻数据链路层的输入接口到输出接口中数据流速率的膨胀或收缩系数，所述膨胀或收缩系数表示经过数据链路层后的数据总量与经过数据链路层前的数据总量的比值。
步骤203a、发送装置中的数据链路层获取第一前一时刻数据累积量，根据发送装置中的数据链路层第一当前时刻数据写入量、第一当前时刻数据读出量以及第一前一时刻数据累积量，获得第一当前时刻数据累积量。
在一实施例中，若发送装置中的数据链路层获取到的第一前一时刻数据累积量为bit_sum1，则根据数据链路层第一当前时刻数据写入量en_w1*bit_w1、第一当前时刻数据读出量en_r1*bit_r1*c_r_w1，计算第一当前时刻数据累积量tx_bit_sum为bit_sum1+en_w1*bit_w1-en_r1*bit_r1*c_r_w1。
步骤204a、发送装置中的数据链路层记录第一当前时刻数据累积量，并将第一当前时刻数据累积量发送至第一时戳补偿组件。
在一实施例中，发送装置中的数据链路层获得了第一当前时刻数据累积量后，会记录第一当前时刻数据累积量，以便将最新记录的第一当前时刻数据累积量作为下一时刻的第一前一时刻数据累积量，在计算下一时刻的第一当前时刻数据累积量中使用，并将第一当前时刻数据累积量发送至第一时戳补偿组件，以便第一时戳补偿组件确定当前周期内数据累积量的最大值和最小值。
步骤205a、第一时戳补偿组件接收发送装置中的数据链路层发送的第一当前时刻数据累积量，将第一当前时刻数据累积量记录为第一数据累积量。
步骤206a、第一时戳补偿组件根据最新记录的第一数据累积量以及数据累积量的第一固定值，确定发送装置中的数据链路层当前的延时抖动，所述数据累积量的第一固定值表示发送装置中没有延时抖动的数据累积量。
在一实施例中，第一时戳补偿组件根据当前周期内记录的多个数据累积量，获得当前周期内数据累积量的最大值和最小值，周期的时间长度可以是1秒、2秒等时间长度，当周期的时间长度为2秒时，第一时戳补偿组件每隔2秒就会根据当前2秒内记录的数据累积量，获得当前2秒内数据累积量的最大值和最小值。
另外，第一时戳补偿组件可以根据当前周期内数据累积量的最大值和最小 值，计算数据累积量的第一固定值，如，数据累积量的第一固定值可以为当前周期内数据累积量的最大值和最小值的平均值，还可以根据当前周期内记录的数据累积量，利用积分算法(数学中的积分方法)计算数据累积量的第一固定值，数据累积量的第一固定值表示发送装置中没有延时抖动的数据累积量。数据累积量的第一固定值与不同周期相对应，不同周期内得到的数据累积量的第一固定值可能相同、也可能不同。数据累积量的第一固定值将在下一周期用于确定发送装置中的数据链路层的延时抖动。
在一实施例中，第一时戳补偿组件在上一周期确定数据累积量的第一固定值后，可以根据最新记录的第一数据累积量以及上一周期确定的数据累积量的第一固定值，确定发送装置中的数据链路层当前的延时抖动。如果数据累积量的第一固定值为tx_constant_bit_sum(固定水线)，则tx_bit_sum-tx_constant_bit_sum可以表示发送装置的数据链路层的水线抖动，(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit就可以表示发送装置的数据链路层的延时抖动，其中tx_compensate_unit表示数据累积量到时间的换算单位。当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit大于0时，表示发送装置的数据链路层有延时抖动、并且延时增大；当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit小于0时，表示发送装置的数据链路层有延时抖动、但延时减小；当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit等于0时，表示发送装置的数据链路层没有延时抖动、延时不变，发送装置的数据链路层的延时为固定值。
步骤207a、第一时戳补偿组件获取发送装置中的协议层记录的发送PTP包的第一初始时戳，根据发送装置中的数据链路层当前的延时抖动补偿第一初始时戳，获得第一补偿时戳，所述第一补偿时戳为对第一初始时戳进行补偿后的时戳。
在一实施例中，第一时戳补偿组件获取发送装置中的协议层记录的发送PTP包发送的第一初始时戳为tx_time，当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit大于0时，说明发送装置中的数据链路层的数据写入比数据读出快，为了减小写入的速率，即使得数据写入和数据读出一样快，可以根据发送装置中的数据链路层的延时抖动补偿第一初始时戳tx_time，使得第一补偿时戳(第一初始时戳进行补偿后的时戳)晚于第一初始时戳tx_time，第一补偿时戳为tx_time+(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit，其中第一补偿时戳为实际参与1588对时计算的时戳，采用第一补偿时戳计算时间偏差时，可以自动抵消延时抖动。
本公开实施例提供另一种延时抖动补偿方法，图2b为本公开实施例提供的另一种延时抖动补偿方法的实现流程示意图，如图2b所示，该方法应用于接收装置，包括步骤201b至步骤207b。
步骤201b、接收装置中的数据链路层获取第二当前时刻数据写入量和第二当前时刻数据读出量。
这里，如图3所示，数据流经过发送装置中的数据链路层、物理接口层传输至发送装置与接收装置之间的传输介质后，还会经过传输介质、接收装置的物理接口层传输至接收装置的数据链路层，从而接收装置中的数据链路层可以获取第二当前时刻数据写入量和第二当前时刻数据读出量。
在一实施例中，将接收装置中的数据链路层视为虚拟缓存，即在数据链路层的输入接口写入数据，在数据链路层的输出接口读出数据。数据链路层的输入接口为写时钟，当数据链路层写入数据后，该数据的有效信号为写使能en_w2，en_w2＝1或en_w2＝0，当en_w2＝1时，表示数据链路层此次缓存写入操作；当en_w2＝0时，表示数据链路层此次没有缓存写入操作，输入接口的数据总线位宽为bit_w2，则计算第二当前时刻数据写入量，即en_w2*bit_w2。数据链路层的输出接口为读时钟，当数据链路层读出数据后，该数据的有效信号为读使能en_r2，输出接口的数据总线位宽为bit_r2，则计算第二当前时刻数据读出量，即en_r2*bit_r2*c_r_w2，其中c_r_w2表示当前时刻数据链路层的输入接口到输出接口中数据流速率的膨胀或收缩系数，所述膨胀或收缩系数表示经过数据链路层后的数据总量与经过数据链路层前的数据总量的比值。
步骤202b、接收装置中的数据链路层获取第二前一时刻数据累积量，根据接收装置中的数据链路层第二当前时刻数据写入量、第二当前时刻数据读出量以及第二前一时刻数据累积量，获得第二当前时刻数据累积量。
在一实施例中，若接收装置中的数据链路层获取到的第二前一时刻数据累积量为bit_sum2，则根据数据链路层第二当前时刻数据写入量en_w2*bit_w2、第二当前时刻数据读出量en_r2*bit_r2*c_r_w2，计算第二当前时刻数据累积量rx_bit_sum为bit_sum2+en_w2*bit_w2-en_r2*bit_r2*c_r_w2。
步骤203b、接收装置中的数据链路层记录第二当前时刻数据累积量，并将第二当前时刻数据累积量发送至第二时戳补偿组件。
在一实施例中，接收装置中的数据链路层获得了第二当前时刻数据累积量后，会记录第二当前时刻数据累积量，以便将最新记录的第二当前时刻数据累积量作为下一时刻的第二前一时刻数据累积量，在计算下一时刻的第二当前时刻数据累积量中使用，并将第二当前时刻数据累积量发送至第二时戳补偿组件， 以便第二时戳补偿组件确定当前周期内数据累积量的最大值和最小值。
步骤204b、第二时戳补偿组件接收接收装置中的数据链路层发送的第二当前时刻数据累积量，将第二当前时刻数据累积量记录为第二数据累积量。
步骤205b、第二时戳补偿组件根据最新记录的第二数据累积量以及数据累积量的第二固定值，确定接收装置中的数据链路层当前的延时抖动，所述数据累积量的第二固定值表示接收装置中没有延时抖动的数据累积量。
在一实施例中，第二时戳补偿组件根据当前周期内记录的多个数据累积量，获得当前周期内数据累积量的最大值和最小值，周期的时间长度可以是1秒、2秒等时间长度，当周期的时间长度为2秒时，第二时戳补偿组件每隔2秒就会根据当前2秒内记录的数据累积量，获得当前2秒内数据累积量的最大值和最小值。
另外，第二时戳补偿组件可以根据当前周期内数据累积量的最大值和最小值，计算数据累积量的第二固定值，如，数据累积量的第二固定值可以为当前周期内数据累积量的最大值和最小值的平均值，还可以根据当前周期内记录的数据累积量，利用积分算法(数学中的积分方法)计算数据累积量的第二固定值，数据累积量的第二固定值表示接收装置中没有延时抖动的数据累积量。数据累积量的第二固定值与不同周期相对应，不同周期内得到的数据累积量的第二固定值可能相同、也可能不同。数据累积量的第二固定值将在下一周期用于确定接收装置中的数据链路层的延时抖动。
在一实施例中，第二时戳补偿组件在上一周期确定数据累积量的第二固定值后，可以根据最新记录的第二数据累积量以及上一周期确定的数据累积量的第二固定值，确定接收装置中的数据链路层当前的延时抖动。如果数据累积量的第二固定值为rx_constant_bit_sum(固定水线)，则rx_bit_sum-rx_constant_bit_sum可以表示接收装置的数据链路层的水线抖动，(rx_bit_sum-rx_constant_bit_sum))*rx_compensate_unit就可以表示接收装置的数据链路层的延时抖动，其中rx_compensate_unit表示数据累积量到时间的换算单位。当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit大于0时，表示接收装置的数据链路层有延时抖动、并且延时增大；当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit小于0时，表示接收装置的数据链路层有延时抖动、但延时减小；当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit等于0时，表示接收装置的数据链路层没有延时抖动、延时不变，接收装置的数据链路层的延时为固定值。
步骤206b、接收装置中的协议层记录接收PTP包的第二初始时戳，所述第 二初始时戳表示接收PTP包的时刻。
在一实施例中，发送装置中的协议层发送PTP包后，PTP包会经过发送装置中的数据链路层、物理接口层传输至发送装置与接收装置之间的传输介质，还会经过传输介质、接收装置的物理接口层、接收装置的数据链路层传输至接收装置的协议层，从而接收装置的协议层接收PTP包。这里，接收装置中的协议层记录接收PTP包的第二初始时戳为rx_time。
步骤207b、第二时戳补偿组件获取接收装置中的协议层记录的接收PTP包发送的第二初始时戳，根据接收装置中的数据链路层当前的延时抖动补偿第二初始时戳，获得第二补偿时戳，所述第二补偿时戳为对第二初始时戳进行补偿后的时戳。
在一实施例中，第二时戳补偿组件获取接收装置中的协议层记录的接收PTP包的第二初始时戳为rx_time，当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit大于0时，说明接收装置中的数据链路层的数据读出比数据写入快，为了减小数据读出的速率，即使得数据写入和数据读出一样快，可以根据接收装置中的数据链路层的延时抖动补偿第二初始时戳rx_time，使得第二补偿时戳(第二初始时戳进行补偿后的时戳)早于第二初始时戳tx_time，第二补偿时戳为rx_time-(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit，其中第二补偿时戳为实际参与1588对时计算的时戳，采用第二补偿时戳计算时间偏差时，可以自动抵消延时抖动。
在一实施例中，在1588协议对时计算中，从发送装置中的协议层到接收装置中的协议层的路径延时，若采用第一初始时戳和第二初始时戳计算，则路径延时rx_time-tx_time＝tx_delay_constant+tx_delay_jitter+rx_delay_constant+rx_delay_jitter，其中tx_delay_constant为发送装置的延时常量部分、即发送装置中的数据链路层的延时固定值，tx_delay_jitter为发送装置的延时抖动部分，rx_delay_constant为接收装置的延时常量部分、即接收装置中的数据链路层的延时固定值，rx_delay_jitter为接收装置的延时抖动部分。根据1588协议，tx_delay_jittert和rx_delay_jitter会影响时间偏差的计算，从而降低对时精度。
若采用第一补偿时戳和第二补偿时戳计算，则路径延时的计算公式如式(1)：
Figure PCTCN2019125589-appb-000001
由式(1)可知，当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit为正数时，表示发送装置有延时抖动、并且延时增大，即tx_delay_jitter为正数，当(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit为负数时，表示发送装置有延时抖动、但延时减小，即tx_delay_jitter为负数，(tx_bit_sum-tx_constant_bit_sum)*tx_compensate_unit和tx_delay_jitter相减可以动态抵消发送装置的延时抖动。当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit为正数时，表示接收装置有延时抖动、并且延时增大，即rx_delay_jitter为正数，当(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit为负数时，表示接收装置有延时抖动、但延时减小，即rx_delay_jitter为负数，(rx_bit_sum-rx_constant_bit_sum)*rx_compensate_unit和rx_delay_jitter相减可以动态抵消接收装置的延时抖动。因此使用补偿后的时戳计算时间偏差时，能自动抵消延时抖动，使得发送装置和接收装置中的路径延时趋近于固定值，从而提高对时精度。
如图4所示，1588协议中的1588主时钟设备包括发送装置和接收装置，1588从时钟设备也包括发送装置和接收装置。在本实施例中，1588主时钟设备中的发送装置进行上述延时抖动补偿方法，得到第一补偿时戳；1588从时钟设备中的接收装置进行上述延时抖动补偿方法，得到第二补偿时戳；1588从时钟设备中的发送装置进行上述延时抖动补偿方法，得到第三补偿时戳；1588主时钟设备中的接收装置进行上述延时抖动补偿方法，得到第四补偿时戳。根据1588协议的对时机制，使用第一补偿时戳、第二补偿时戳、第三补偿时戳和第四补偿时戳进行主从时钟设备的对时，使得发送装置和接收装置中的路径延时趋近于固定值，提高主从时钟设备的对时精度。
以10吉比特以太网(10 Gigabit Ethernet，10GE)为例，如图5所示，选取以太网的介质访问控制(Media Access Control，MAC)层作为本公开实施例中的协议层，以太网的物理编码子层(Physical Coding Sublayer，PCS)和物理介质连接(Physical Medium Attachment，PMA)子层作为本公开实施例中的数据链路层，串行器/解串器(SERializer/DESerializer，SERDES)和光模块作为本公开实施例中的物理接口层。
10GE发送装置中的MAC层记录发送PTP包的第一初始时戳。PCS和PMA子层传送以太网业务数据，获取第一前一时刻数据累积量，根据第一当前时刻数据写入量、第一当前时刻数据读出量以及第一前一时刻数据累积量，获得第一当前时刻数据累积量。第一时戳补偿组件获得10GE发送装置中的PCS和PMA子层发送的第一当前时刻数据累积量，将第一当前时刻数据累积量记录为第一数据累积量，根据最新记录的第一数据累积量以及数据累积量的第一固定值，确定10GE发送装置中的PCS和PMA子层当前的延时抖动，根据当前的延时抖动补偿MAC层记录发送PTP包的第一初始时戳，获得第一补偿时戳。10GE发送装置中的SERDES和光模块将PCS和PMA子层传输的逻辑数字信号转换为光信号，并将光信号传输至光纤。光纤将光信号传输至10GE接收装置中的SERDES和光模块。
10GE接收装置中的SERDES和光模块将光纤传输的光信号转换为逻辑数字信号，并将逻辑数字信号传输至10GE接收装置中的PCS和PMA子层。PCS和PMA子层获取第二前一时刻数据累积量，根据第二当前时刻数据写入量、第二当前时刻数据读出量以及第二前一时刻数据累积量，获得第二当前时刻数据累积量。第二时戳补偿组件获得10GE接收装置中的PCS和PMA子层发送的第二当前时刻数据累积量，将第二当前时刻数据累积量记录为第二数据累积量，根据最新记录的第二数据累积量以及数据累积量的第二固定值，确定10GE接收装置中的PCS和PMA子层当前的延时抖动。10GE接收装置中的MAC层记录接收PTP包的第二初始时戳。第二时戳补偿组件获取第二初始时戳，根据10GE接收装置中的PCS和PMA子层当前的延时抖动补偿第二初始时戳，获得第二补偿时戳。因此，使用补偿后的时戳计算时间偏差时，能自动抵消延时抖动，使得10GE发送装置和10GE接收装置中的路径延时趋近于固定值，从而提高对时精度。
以上关于多层的描述可以理解为位于相应层的逻辑实体。
本公开实施例提供一种延时抖动补偿装置，图6为本公开实施例提供的一种延时抖动补偿的结构示意图，如图6所示，所述延时抖动补偿装置600包括：确定单元601以及补偿单元602。
确定单元601，设置为根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量；
补偿单元602，设置为获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
在一实施例中，所述装置600还可以包括：
记录单元603，设置为接收数据链路层发送的当前时刻数据累积量，将所述当前时刻数据累积量记录为数据累积量。
在一实施例中，所述记录单元603还设置为根据当前周期内记录的多个数据累积量，获得当前周期内数据累积量的最大值和最小值；根据所述当前周期内数据累积量的最大值和最小值，计算数据累积量的固定值。
这里，所述确定单元601、补偿单元602和所述记录单元603可以位于上述技术方案描述中的时戳补偿组件。
在一实施例中，所述装置600还可以包括：
获取单元604，设置为数据链路层获取当前时刻数据写入量和当前时刻数据读出量；所述数据链路层获取前一时刻数据累积量；所述数据链路层根据所述当前时刻数据写入量、当前时刻数据读出量以及前一时刻数据累积量，获得当前时刻数据累积量。
在一实施例中，所述装置600还可以包括：
发送单元605，设置为所述数据链路层发送所述当前时刻数据累积量至所述时戳补偿组件。
这里，所述获取单元604和发送单元605可以位于上述技术方案中的数据链路层。
在一实施例中，所述延时抖动补偿装置设置于发送装置和/或接收装置中。
在本公开实施例中的多个组成部分可以集成在一个处理单元中，也可以是每个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。
所述集成的单元如果以软件功能模块的形式实现并非作为独立的产品进行销售或使用时，可以存储在一个计算机可读取存储介质中，本公开实施例的技术方案可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括多个指令用以使得一台计算机设备(可以是个人计算机，服务器， 或者网络设备等)或processor(处理器)执行本公开实施例所述方法的全部或部分步骤。而前述的存储介质包括：通用串行总线闪存盘(Universal Serial Bus flash disk，U盘)、移动硬盘、只读存储器(ROM，Read Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等多种可以存储程序代码的介质。
因此，本公开实施例提供了一种计算机存储介质，该计算机存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现上述实施例所述的方法。
参见图7，示出了本公开实施例提供的一种延时抖动补偿装置700的硬件结构，包括：网络接口701、存储器702和处理器703；多个组件通过总线系统704耦合在一起。总线系统704设置为实现这些组件之间的连接通信。总线系统704除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。在图7中将多种总线都标为总线系统704。其中，
其中，所述网络接口701，设置为在与其他外部网元之间进行收发信息过程中，信号的接收和发送；
存储器702，设置为存储能够在处理器703上运行的计算机程序；
处理器703，设置为在运行所述计算机程序时，执行：
时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量；
所述时戳补偿组件获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿所述初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
所述处理器703还设置为运行所述计算机程序时，执行：
所述时戳补偿组件接收数据链路层发送的当前时刻数据累积量，将所述当前时刻数据累积量记录为数据累积量。
所述处理器703还设置为运行所述计算机程序时，执行：
所述时戳补偿组件根据当前周期内记录的多个数据累积量，获得当前周期内数据累积量的最大值和最小值；
所述时戳补偿组件根据所述当前周期内数据累积量的最大值和最小值，获得数据累积量的固定值。
所述处理器703还设置为运行所述计算机程序时，执行：
数据链路层获取当前时刻数据写入量和当前时刻数据读出量；
所述数据链路层获取前一时刻数据累积量，根据所述当前时刻数据写入量、当前时刻数据读出量以及前一时刻数据累积量，获得当前时刻数据累积量。
所述处理器703还设置为运行所述计算机程序时，执行：
所述数据链路层发送所述当前时刻数据累积量至所述时戳补偿组件；
所述时戳补偿组件将数据链路层的当前时刻数据累积量记录为数据累积量。
可以理解，本公开实施例中的存储器702可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Sync Link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本文描述的方法的存储器702旨在包括这些和任意其它适合类型的存储器。
而处理器703可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的多个步骤可以通过处理器703中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器703可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本公开实施例中的公开的多个方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本公开实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等存储介质中。该存储介质位于存储器702，处理器703读取存储器702中的信息，结合其硬件完成上述方法。
说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书多处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。在本公开的多种实施例中，上述多个过程的序号的大小并不意味着执行顺序的先后，多个过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
在一实施例中，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，所揭露的方法和装置，可以通过其它的方式实现。以上所描述的终端实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的多个组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。

Claims (10)

  1. 一种延时抖动补偿方法，包括：
    时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值；
    所述时戳补偿组件获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿所述初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
  2. 根据权利要求1所述的方法，在所述时戳补偿组件根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动之前，还包括：
    所述时戳补偿组件接收所述数据链路层发送的当前时刻数据累积量，将所述当前时刻数据累积量记录为所述最新记录的数据累积量。
  3. 根据权利要求2所述的方法，其中，所述将所述当前时刻数据累积量记录为所述最新记录的数据累积量之前，还包括：
    所述时戳补偿组件根据当前周期内记录的多个数据累积量，获得所述当前周期内数据累积量的最大值和最小值；
    所述时戳补偿组件根据所述当前周期内数据累积量的最大值和最小值，获得所述数据累积量的固定值。
  4. 根据权利要求2所述的方法，在所述时戳补偿组件接收所述数据链路层发送的当前时刻数据累积量之前，还包括：
    所述数据链路层获取当前时刻数据写入量和当前时刻数据读出量；
    所述数据链路层获取前一时刻数据累积量；
    所述数据链路层根据所述当前时刻数据写入量、所述当前时刻数据读出量以及所述前一时刻数据累积量，获得所述当前时刻数据累积量；
    在所述根据所述当前时刻数据写入量、所述当前时刻数据读出量以及所述前一时刻数据累积量，获得所述当前时刻数据累积量之后，还包括：所述数据链路层发送所述当前时刻数据累积量至所述时戳补偿组件。
  5. 根据权利要求4所述的方法，所述数据链路层根据所述当前时刻数据写入量、所述当前时刻数据读出量以及所述前一时刻数据累积量，获得所述当前时刻数据累积量，包括：
    根据输入接口的数据总线位宽和写使能计算出所述当前时刻数据写入量以 及根据输出接口的数据总线位宽、读使能和当前时刻所述数据链路层的输入接口到输出接口中数据流速率的膨胀或收缩系数计算出所述当前时刻数据读出量；
    将所述前一时刻数据累积量与所述当前时刻数据写入量之和减去所述当前时刻数据读出量作为所述当前时刻数据累积量。
  6. 一种延时抖动补偿装置，包括：
    确定单元，设置为根据最新记录的数据累积量以及数据累积量的固定值，确定数据链路层当前的延时抖动，所述数据累积量的固定值表示所述数据链路层中没有延时抖动的数据累积量的值；
    补偿单元，设置为获取协议层记录的初始时戳，根据所述数据链路层当前的延时抖动补偿初始时戳，获得补偿时戳，所述补偿时戳为对所述初始时戳进行补偿后的时戳。
  7. 根据权利要求6所述的装置，还包括：
    记录单元，设置为接收所述数据链路层发送的当前时刻数据累积量，将所述当前时刻数据累积量记录为所述最新记录的数据累积量。
  8. 根据权利要求7所述的装置，所述装置设置于发送装置以及接收装置的至少之一，其中，所述记录单元还设置为根据当前周期内记录的多个数据累积量，获得所述当前周期内数据累积量的最大值和最小值；
    根据所述当前周期内数据累积量的最大值和最小值，计算所述数据累积量的固定值。
  9. 一种延时抖动补偿装置，所述装置包括网络接口、存储器和处理器；其中，
    所述网络接口，配置为实现组件之间的连接通信；
    所述存储器，配置为存储能够在所述处理器上运行的计算机程序；
    所述处理器，配置为在运行所述计算机程序的情况下，执行权利要求1至5任一项所述方法。
  10. 一种计算机存储介质，所述计算机存储介质存储有计算机程序，所述计算机程序被至少一个处理器执行时实现如权利要求1至5中任一项所述方法。
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