WO2020113856A1

WO2020113856A1 - Preparation method for array substrate, array substrate, display panel, and display device

Info

Publication number: WO2020113856A1
Application number: PCT/CN2019/079192
Authority: WO
Inventors: 向明
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2018-12-05
Filing date: 2019-03-22
Publication date: 2020-06-11
Also published as: CN109860235A; CN109860235B

Abstract

An embodiment of the present invention discloses a preparation method for an array substrate, the array substrate, a display panel, and a display device. In the embodiment of the present invention, a gate electrode insulating layer above a channel region is doped with fluorine atoms, and since a fluorine-containing inorganic layer can absorb hydrogen atoms, hydrogen atoms can be prevented from diffusing downwards into a metal oxide semiconductor so as to prevent same from affecting the electrical properties of a thin film transistor. In addition, only one kind of metal is needed to serve as a metal gate electrode layer, thereby simplifying the technological process and reducing the production cost.

Description

Array substrate preparation method, array substrate, display panel and display device

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a method for preparing an array substrate, an array substrate, a display panel, and a display device.

Background technique

AMOLED (English full name: Active-matrix organic light-emitting diode, Chinese full name: active matrix organic light-emitting diode or active matrix organic light-emitting diode) is a display technology. Among them, AM (active matrix or active matrix) refers to the pixel addressing technology behind; OLED (organic light-emitting diode) is a specific type of description of thin-film display technology: organic electroluminescence display. Compared with the traditional LCD displays used in most mobile phones, AMOLED currently has a wider viewing angle, higher refresh rate and thinner size, so it is being widely adopted by smart phones and continues to move towards low power consumption, low cost and large size Direction development.

At present, thin-film transistors (Thin-film transistor, TFT) and capacitor (C) are arranged separately in space. When metal oxide semiconductors are used to fabricate TFTs, hydrogen atoms in the hydrogenation process need to enter the metal oxide layer, thereby improving the conductivity of the metal oxide layer and making these regions form conductors. On the other hand, hydrogen atoms cannot enter the channel region In order to maintain the characteristics of the semiconductor in this area, in order to achieve this purpose, the metal gate layer needs to use different metal materials, and this is also the method currently widely used.

technical problem

However, the use of different metal materials for the metal gate layer increases the material requirements on the one hand, and on the other hand, due to the need to process multiple materials, it increases the difficulty of production and the production cost.

Technical solution

Embodiments of the present invention provide a method for preparing an array substrate, an array substrate, a display panel, and a display device. By doping the gate insulating layer above the channel region of the thin film transistor with fluorine atoms, only one metal is needed as the metal gate Polar layer, which simplifies the process and reduces production costs.

In a first aspect, the present application provides a method for preparing an array substrate, the method comprising:

Depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer in sequence on the substrate, the metal oxide layer including a first region and a second region, the second region including a channel region;

Doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layers in other regions do not contain fluorine atoms;

Forming a metal gate layer and an interlayer dielectric layer in sequence on the gate insulating layer;

After the hydrogenation activation process, the metal oxide layer of the channel region contains fluorine atoms to block the diffusion of hydrogen atoms due to the gate insulating layer above the channel region, still maintaining the characteristics of the semiconductor, so that hydrogen atoms pass through the division The metal oxide layer in other regions outside the channel region to form a conductor;

Forming a source-drain wiring layer, an organic flat layer, an anode wiring layer and a pixel definition layer on the metal oxide layer in sequence;

Wherein, the step of sequentially depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer on the substrate includes:

Deposit a buffer layer and a metal oxide layer on the substrate in sequence, and then etch to form a patterned metal oxide layer;

Depositing and forming a gate insulating layer on the metal oxide layer;

The step of doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms, includes:

Coating a photoresist on the gate insulating layer, and exposing and developing to form a patterned photoresist layer;

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma, so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms;

After ashing and peeling cleaning, the photoresist layer is removed.

Further, the gate insulating layer is doped with fluorine atoms using a plasma containing fluorine, so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain The fluorine atom steps include:

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine atoms to form an inorganic layer, while the gate insulating layer in other regions does not contain fluorine atom.

Further, the step of sequentially forming a source-drain wiring layer, an organic flat layer, an anode wiring layer and a pixel definition layer on the metal oxide layer includes:

Etching the metal oxide layer to form an ILD via, and depositing and etching to form a patterned source-drain wiring layer;

An organic flat layer, an anode wiring layer and a pixel definition layer are sequentially formed on the source-drain wiring layer.

Further, the step of sequentially forming an organic flat layer, an anode wiring layer and a pixel definition layer on the source-drain wiring layer includes:

Coating, exposing, developing and curing the source-drain wiring layer to form a patterned organic flat layer;

Depositing and etching on the organic flat layer to form a patterned anode wiring layer;

A patterned pixel definition layer is coated, exposed, developed and cured on the anode wiring layer.

Further, the interlayer dielectric layer includes two layers of SiNx and SiO2.

Further, the material of the metal gate layer is at least one of molybdenum, aluminum, indium tin oxide, and indium zinc oxide.

In a second aspect, the present application provides a method for preparing an array substrate, the method comprising:

A source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer are sequentially formed on the metal oxide layer.

Further, the step of sequentially depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer on the substrate includes:

A gate insulating layer is deposited on the metal oxide layer.

Further, the step of doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms, include:

After ashing and peeling cleaning, the photoresist layer is removed.

Further, the interlayer dielectric layer includes two layers of SiNx and SiO2.

In a third aspect, the present application provides an array substrate. The array substrate includes:

Substrate

A buffer layer, prepared on the surface of the substrate;

A metal oxide layer is prepared on the surface of the buffer layer, the metal oxide layer includes a channel region and a conductor region, and an ILD via is formed on the metal oxide layer by etching;

A gate insulating layer, prepared on the metal oxide layer, the gate insulating layer includes a non-fluorine atom doped region and a fluorine atom doped region, the fluorine atom doped region is above the channel region ;

Metal gate layer, prepared above the gate insulation layer;

An interlayer dielectric layer, prepared on the metal gate layer,

A source-drain wiring layer formed in the ILD via;

And an organic flat layer prepared on the interlayer dielectric layer, an anode wiring layer and a pixel definition layer.

Further, the metal gate layer includes a first metal gate region and a second metal gate region, the first metal gate region is prepared on the fluorine atom doped region, and the second metal gate region The polar region is prepared on the non-fluorine atom doped region.

Further, the conductor area includes a first conductor area, a second conductor area, and a third conductor area, the first conductor area and the second conductor area are on both sides of the channel area, and are on the source Below the drain trace layer, the third conductor region is located below the second metal gate region.

Further, the interlayer dielectric layer includes two layers of SiNx and SiO2.

According to a fourth aspect, the present application provides a display panel, the display panel comprising the array substrate according to any one of the second aspect.

According to a fifth aspect, the present application provides a display device including the display panel according to the third aspect.

Beneficial effect

In the embodiment of the present invention, the gate insulating layer above the channel region is doped with fluorine atoms. Since the fluorine-containing inorganic layer can absorb hydrogen atoms, it can block hydrogen atoms from diffusing downward into the metal oxide semiconductor, thereby avoiding affecting the thin film transistor Electrical properties. On the other hand, the metal oxide semiconductor as the lower electrode of the capacitor can still accept hydrogen atoms to become a conductor, and form a capacitor with the metal gate layer. By doping the gate insulating layer above the thin film transistor channel region with fluorine atoms, only It is necessary to use a metal as the metal gate layer, thereby simplifying the process flow and reducing the production cost.

BRIEF DESCRIPTION

In order to more clearly explain the technical solutions in the embodiments of the present invention, the drawings required in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without paying any creative work, other drawings can be obtained based on these drawings.

1 is a cross-sectional view of an existing array substrate;

2 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate in an embodiment of the present invention;

3 is a schematic structural view of a method for manufacturing an array substrate in the embodiment of the present invention after sequentially depositing a buffer layer and a metal oxide layer on the substrate;

4 is a schematic structural view of a method for manufacturing an array substrate after depositing a gate insulating layer on a metal oxide layer in an embodiment of the present invention;

5 is a schematic structural view of a patterned photoresist layer coated on a gate insulating layer and exposed and developed in a method for manufacturing an array substrate in an embodiment of the present invention;

6 is a method for preparing an array substrate in the embodiment of the present invention, the gate insulating layer is doped with fluorine atoms using a plasma containing fluorine, so that the gate insulating layer above the channel region contains fluorine atoms, while other regions Schematic diagram of the structure after the gate insulating layer does not contain fluorine atoms;

7 is a schematic structural view after removing the photoresist layer after ashing and stripping cleaning in the method for preparing an array substrate in an embodiment of the present invention;

8 is a schematic structural view after a patterned metal gate layer is deposited and etched on a gate insulating layer in the method for manufacturing an array substrate in an embodiment of the present invention;

9 is a schematic structural view of the method for manufacturing an array substrate after depositing an interlayer dielectric layer on a metal gate layer in an embodiment of the invention

10 is a schematic structural view of a method for manufacturing an array substrate after a hydrogenation activation process in an embodiment of the present invention;

11 is a schematic view of the structure of the array substrate in the embodiment of the present invention after etching the metal oxide layer 220b region and 220c region to form an ILD via hole, and then deposited and etched to form a patterned source and drain trace layer structure diagram;

12 is a schematic structural view of the method for manufacturing an array substrate in the embodiment of the present invention after coating, exposing, developing, and curing a patterned organic flat layer on a source-drain wiring layer;

13 is a schematic structural view after a patterned anode wiring layer is deposited and etched on an organic flat layer in the method for manufacturing an array substrate in an embodiment of the present invention;

14 is a schematic structural diagram of an embodiment of an array substrate in an embodiment of the present invention.

Embodiments of the invention

The technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " The orientation or positional relationship indicated by "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation shown in the drawings Or the positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as limiting the present invention. In addition, the terms “first” and “second” are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise specifically limited.

As shown in FIG. 1, it is a cross-sectional view of an existing array substrate, in which thin film transistors (TFTs) and capacitors (C) are spaced apart. When a metal oxide semiconductor is used to fabricate a TFT, hydrogen atoms in the hydrogenation activation process need to enter the metal oxide layer (including three regions: 120b, 120c, and 120d), thereby improving the conductivity of the metal oxide layer and forming these regions In the conductor, on the other hand, hydrogen atoms cannot enter the channel region 120a of the metal oxide layer, so that this region still maintains the characteristics of a semiconductor. In order to achieve this, different metal materials need to be used for the metal gate layer. As shown in FIG. 1, the region 140a in the gate insulating layer is made of a metal that is impermeable to hydrogen atoms, such as titanium (Ti), titanium-molybdenum alloy or Alumina (Al2O3), and the 140b region in the gate insulating layer is made of a metal that can permeate hydrogen atoms, such as: molybdenum (Mo), aluminum (Al), indium tin oxide (ITO) or indium zinc oxide (IZO), metal The use of different metal materials for the gate layer increases the material requirements on the one hand, and on the other hand, due to the need to process multiple materials, the complexity of the process flow is increased, and the difficulty and cost of production are increased.

Based on this, an embodiment of the present invention provides a method for preparing an array substrate, an array substrate, a display panel, and a display device.

First, an embodiment of the present invention provides a method for preparing an array substrate. The method includes: sequentially depositing and forming a buffer layer, a metal oxide layer, and a gate insulating layer on the substrate, the metal oxide layer including a first region And a second region, the second region includes a channel region; the gate insulating layer is doped with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gates in other regions The insulating layer does not contain fluorine atoms; a metal gate layer and an interlayer dielectric layer are sequentially formed on the gate insulating layer; after a hydrogenation activation process, the metal oxide layer of the channel region is caused by the channel region The upper gate insulating layer contains fluorine atoms to block the diffusion of hydrogen atoms, and still maintain the characteristics of the semiconductor, so that hydrogen atoms pass through the metal oxide layer in other regions than the channel region to form a conductor; in the metal oxide A source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer are sequentially formed on the layer.

As shown in FIG. 2, it is a schematic diagram of an embodiment of a method for preparing an array substrate in an embodiment of the present invention. The method includes:

101. Deposit a buffer layer, a metal oxide layer and a gate insulating layer in sequence on the substrate.

Wherein, the metal oxide layer includes a first region and a second region, the second region includes a channel region, and the first region and the second region are used to form a TFT and a capacitor, respectively. In the embodiment of the present invention, the substrate may be a glass substrate. Specifically, the glass substrate may be a glass substrate that has been previously cleaned, for example, cleaning to remove residual particles, metals, and organic matter.

The gate insulating layer refers to the GI layer. The GI layer is formed by a process in an LTPS called GI Deposition, which is the deposition of the GI layer. GI is generally an insulating layer between a metal gate layer and a semiconductor layer in a TFT, usually SiNx/SiOx, which is called Gate Insulator, that is, a gate insulating layer.

Further, the step of sequentially depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer on the substrate may include: sequentially depositing the buffer layer and the metal oxide layer on the substrate, and then etching to form a patterned metal An oxide layer; a gate insulating layer is deposited on the metal oxide layer.

As shown in FIG. 3, a buffer layer 210 and a metal oxide layer are sequentially deposited on the substrate 200, and then etched to form a patterned metal oxide layer 220. The metal oxide layer 220 includes two metal oxide regions: the first The region and the second region are respectively used to form a thin film transistor TFT and a capacitor C. As shown in FIG. 4, a gate insulating layer 230 is deposited on the metal oxide layer 220.

102. Doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layers in other regions do not contain fluorine atoms.

In the embodiment of the present invention, the gate insulating layer is doped with fluorine atoms, so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms The step may further include: coating a photoresist on the gate insulating layer, and exposing and developing to form a patterned photoresist layer; doping the gate insulating layer with fluorine atoms using fluorine-containing plasma, The gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms; after ashing and stripping cleaning, the photoresist layer is removed.

Photoresist, also known as photoresist, is a photosensitive material used in many industrial processes. Like photolithography, a patterned coating layer can be carved on the surface of the material. There are two types of photoresist, positive photoresist (positive photoresist) and negative photoresist (negative photoresist), positive photoresist is a type of photoresist, the part that hits the light will dissolve in the photoresist developer, and the part that does not hit the light will not dissolve in the photoresist Developer. Negative photoresist is another type of photoresist. The part exposed to light will not dissolve in the photoresist developer, while the part not exposed to light will dissolve in the photoresist developer. The embodiments of the present invention may use a forward photoresist to form a patterned photoresist layer.

Wherein, the gate insulating layer is doped with fluorine atoms with fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine The atom step may include: doping the gate insulating layer with fluorine atoms using a fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine atoms to form an inorganic layer, while other regions The gate insulating layer does not contain fluorine atoms. Further, the inorganic layer may include SiNF and SiOF.

Specifically, as shown in FIG. 5, a patterned photoresist layer PR310 is coated and exposed on the gate insulating layer 230; as shown in FIG. 6 in conjunction with FIG. 10, the gate is insulated with fluorine-containing plasma The layer is doped with fluorine atoms, so that the gate insulating layer 230b above the channel region 220d contains fluorine atoms (forming inorganic layers SiNF and SiOF), while the gate insulating layer 230a in other regions does not contain fluorine atoms; as shown in FIG. 7 It is shown that the photoresist layer 310 is removed after ashing and peeling cleaning.

103. Form a metal gate layer and an interlayer dielectric layer in sequence on the gate insulating layer.

Wherein, the step of sequentially forming a metal gate layer and an interlayer dielectric layer on the gate insulating layer includes: depositing and etching a patterned metal gate layer on the gate insulating layer, and forming a patterned metal gate layer on the metal gate An interlayer dielectric layer ILD is deposited on the polar layer. The ILD is called an intermediate insulating layer, also called an interlayer dielectric layer. The interlayer dielectric layer mainly provides electrical insulation between the conductor area inside the device, metal and isolation from the surrounding environment Protection. In the embodiment of the present invention, the interlayer dielectric layer ILD includes two layers of SiNx and SiO2. The material of the metal gate layer may be molybdenum (Mo), aluminum (Al), indium tin oxide (ITO), or indium zinc oxide ( IZO).

Specifically, as shown in FIG. 8, a patterned metal gate layer 240 is deposited and etched on the gate insulating layer 230; as shown in FIG. 9, a layer of interlayer dielectric is deposited on the metal gate layer 240 Layer ILD250, interlayer dielectric layer ILD250 includes two layers of SiNx and SiO2.

104. After the hydrogenation activation process, the metal oxide layer of the channel region contains fluorine atoms to block the diffusion of hydrogen atoms due to the gate insulating layer above the channel region, still maintaining the characteristics of the semiconductor, so that hydrogen atoms pass through The metal oxide layer in other regions than the channel region forms a conductor.

Specifically, as shown in FIG. 10, in the hydrogenation activation process, hydrogen atoms in the gate insulating layer (such as the SiNx layer) pass through the metal gate layer 240 and the 230a region of the gate insulating layer not containing fluorine atoms, and enter To the 220b region, 220c region and 220d region of the metal oxide layer, the metal oxide of these regions forms a conductor, and the 230b region of the gate insulating layer above the channel region 220a of the metal oxide layer contains fluorine atoms, which can The diffusion of hydrogen atoms is blocked, so that the metal oxide in the region 220a still maintains the characteristics of a semiconductor.

In addition, in the embodiment of the present invention, in the hydrogenation activation process, a plasma hydrogenation method or a solid-state diffusion method may be used.

105. Form a source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer on the metal oxide layer in this order.

Wherein, the step of sequentially forming an organic flat layer, an anode wiring layer and a pixel definition layer on the source-drain wiring layer may further include: coating, exposing and developing on the source-drain wiring layer And curing to form a patterned organic flat layer; depositing and etching on the organic flat layer to form a patterned anode wiring layer; coating, exposing, developing and curing on the anode wiring layer to form patterned pixels Define the layer.

Specifically, as shown in FIG. 11, an ILD via is etched on the 220b and 220c regions of the metal oxide layer, and then a patterned source-drain trace layer 260 is deposited and etched; as shown in FIG. 12, A patterned organic flat layer 270 is coated, exposed, developed and cured on the drain trace layer 260; as shown in FIG. 13, a patterned anode trace layer 280 is deposited and etched on the organic flat layer 270; finally, as shown in FIG. As shown in FIG. 14, a patterned pixel definition layer 290 is formed by coating, exposing, developing and curing on the anode wiring layer 280.

In the method for preparing an array substrate in the embodiment of the present invention, the gate insulating layer above the channel region is doped with fluorine atoms. Since the fluorine-containing inorganic layer can absorb hydrogen atoms, it can block hydrogen atoms from diffusing downward into the metal oxide semiconductor , So as not to affect the electrical properties of the thin film transistor. On the other hand, the metal oxide semiconductor as the lower electrode of the capacitor can still accept hydrogen atoms to become a conductor, and form a capacitor with the metal gate layer. By doping the gate insulating layer above the thin film transistor channel region with fluorine atoms, only It is necessary to use a metal as the metal gate layer, thereby simplifying the process flow and reducing the production cost.

In order to better implement the manufacturing method of the array substrate in the embodiment of the present invention, based on the manufacturing method of the array substrate, an embodiment of the present invention also provides an array substrate, the array substrate includes:

Substrate

A buffer layer, prepared on the surface of the substrate;

Metal gate layer, prepared above the gate insulation layer;

An interlayer dielectric layer, prepared on the metal gate layer,

A source-drain wiring layer formed in the ILD via;

Further, the interlayer dielectric layer includes two layers of SiNx and SiO2.

Specifically, as shown in FIG. 14, the array substrate includes a substrate 200, a buffer layer 210, a metal oxide layer 220, a gate insulating layer, a metal gate layer 240, an interlayer dielectric layer ILD 250, and a source-drain trace layer 260 , An organic flat layer 270, an anode trace layer 280, and a pixel definition layer 290, wherein the metal oxide layer 220 includes a channel region 220a, conductor regions 220b, 220c, and 220d, and the gate insulating layer includes a non-fluorine atom doped region 230a With the fluorine atom doped region 230b, the metal gate layer 240 includes two metal gate layers 240a and 240b, where 240a is above the channel region 220a and 240b is above the capacitor lower electrode 220d.

In the embodiment of the present invention, the gate insulating layer above the channel region of the array substrate is doped with fluorine atoms. Since the fluorine-containing inorganic layer can absorb hydrogen atoms, it can block hydrogen atoms from diffusing downward into the metal oxide semiconductor, thereby avoiding influence Electrical properties of thin film transistors. On the other hand, the metal oxide semiconductor as the lower electrode of the capacitor can still accept hydrogen atoms to become a conductor, and form a capacitor with the metal gate layer. By doping the gate insulating layer above the thin film transistor channel region with fluorine atoms, only It is necessary to use a metal as the metal gate layer, thereby simplifying the process flow and reducing the production cost.

On the basis of the array substrate, an embodiment of the present invention further provides a display panel. The display panel includes the array substrate as described in the embodiment of the present invention. Specifically, the display panel may be an AMOLED display panel.

Based on the display panel, an embodiment of the present invention further provides a display device, and the display device includes the display panel as described in the embodiment of the present invention.

In the above embodiments, the description of each embodiment has its own emphasis. For a part that is not detailed in an embodiment, you can refer to the detailed descriptions in other embodiments above, which are not repeated here.

During specific implementation, the above units or structures can be implemented as independent entities, or they can be combined in any combination as one or several entities. For the specific implementation of the above units or structures, please refer to the previous method embodiments. No longer.

The preparation method of the array substrate, the array substrate, the display panel, and the display device provided by the embodiments of the present invention have been described in detail above. Specific examples are used in this article to explain the principle and implementation of the present invention. The description is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application, in summary The content of this specification should not be construed as a limitation of the present invention.

Claims

A method for preparing an array substrate, wherein the method includes:

Depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer in sequence on the substrate, the metal oxide layer including a first region and a second region, the second region including a channel region;

Doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layers in other regions do not contain fluorine atoms;

Forming a metal gate layer and an interlayer dielectric layer in sequence on the gate insulating layer;

After the hydrogenation activation process, the metal oxide layer of the channel region contains fluorine atoms to block the diffusion of hydrogen atoms due to the gate insulating layer above the channel region, still maintaining the characteristics of the semiconductor, so that hydrogen atoms pass through the division The metal oxide layer in other regions outside the channel region to form a conductor;

Forming a source-drain wiring layer, an organic flat layer, an anode wiring layer and a pixel definition layer on the metal oxide layer in sequence;

Wherein, the step of sequentially depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer on the substrate includes:

Deposit a buffer layer and a metal oxide layer on the substrate in sequence, and then etch to form a patterned metal oxide layer;

Depositing and forming a gate insulating layer on the metal oxide layer;

The step of doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms, includes:

Coating a photoresist on the gate insulating layer, and exposing and developing to form a patterned photoresist layer;

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma, so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms;

After ashing and peeling cleaning, the photoresist layer is removed.
The method for manufacturing an array substrate according to claim 1, wherein the gate insulating layer is doped with fluorine atoms with a fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine Atoms, and the gate insulating layer in other regions does not contain fluorine atoms, including:

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine atoms to form an inorganic layer, while the gate insulating layer in other regions does not contain fluorine atom.
The method for manufacturing an array substrate according to claim 1, wherein the step of sequentially forming a source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer on the metal oxide layer includes:

Etching the metal oxide layer to form an ILD via, and depositing and etching to form a patterned source-drain wiring layer;

An organic flat layer, an anode wiring layer and a pixel definition layer are sequentially formed on the source-drain wiring layer.
The method for manufacturing an array substrate according to claim 3, wherein the step of sequentially forming an organic flat layer, an anode wiring layer and a pixel definition layer on the source-drain wiring layer includes:

Coating, exposing, developing and curing the source-drain wiring layer to form a patterned organic flat layer;

Depositing and etching on the organic flat layer to form a patterned anode wiring layer;

A patterned pixel definition layer is coated, exposed, developed and cured on the anode wiring layer.
The method for manufacturing an array substrate according to claim 1, wherein the interlayer dielectric layer includes two layers of SiNx and SiO2.
The method for manufacturing an array substrate according to claim 1, wherein the material of the metal gate layer is at least one of molybdenum, aluminum, indium tin oxide, and indium zinc oxide.
A method for preparing an array substrate, wherein the method includes:

Depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer in sequence on the substrate, the metal oxide layer including a first region and a second region, the second region including a channel region;

Doping the gate insulating layer with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layers in other regions do not contain fluorine atoms;

Forming a metal gate layer and an interlayer dielectric layer in sequence on the gate insulating layer;

After the hydrogenation activation process, the metal oxide layer of the channel region contains fluorine atoms to block the diffusion of hydrogen atoms due to the gate insulating layer above the channel region, still maintaining the characteristics of the semiconductor, so that hydrogen atoms pass through the division The metal oxide layer in other regions outside the channel region to form a conductor;

A source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer are sequentially formed on the metal oxide layer.
The method for manufacturing an array substrate according to claim 7, wherein the step of sequentially depositing and forming a buffer layer, a metal oxide layer and a gate insulating layer on the substrate includes:

Deposit a buffer layer and a metal oxide layer on the substrate in sequence, and then etch to form a patterned metal oxide layer;

A gate insulating layer is deposited on the metal oxide layer.
The method for manufacturing an array substrate according to claim 7, wherein the gate insulating layer is doped with fluorine atoms so that the gate insulating layer above the channel region contains fluorine atoms, while other regions The step of the gate insulating layer does not contain fluorine atoms, including:

Coating a photoresist on the gate insulating layer, and exposing and developing to form a patterned photoresist layer;

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma, so that the gate insulating layer above the channel region contains fluorine atoms, while the gate insulating layer in other regions does not contain fluorine atoms;

After ashing and peeling cleaning, the photoresist layer is removed.
The method for manufacturing an array substrate according to claim 9, wherein the gate insulating layer is doped with fluorine atoms with a fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine Atoms, and the gate insulating layer in other regions does not contain fluorine atoms, including:

Doping the gate insulating layer with fluorine atoms using fluorine-containing plasma so that the gate insulating layer above the channel region contains fluorine atoms to form an inorganic layer, while the gate insulating layer in other regions does not contain fluorine atom.
The method for manufacturing an array substrate according to claim 7, wherein the step of sequentially forming a source-drain wiring layer, an organic flat layer, an anode wiring layer, and a pixel definition layer on the metal oxide layer includes:

Etching the metal oxide layer to form an ILD via, and depositing and etching to form a patterned source-drain wiring layer;

An organic flat layer, an anode wiring layer and a pixel definition layer are sequentially formed on the source-drain wiring layer.
The method for manufacturing an array substrate according to claim 11, wherein the step of sequentially forming an organic flat layer, an anode wiring layer and a pixel definition layer on the source-drain wiring layer includes:

Coating, exposing, developing and curing the source-drain wiring layer to form a patterned organic flat layer;

Depositing and etching on the organic flat layer to form a patterned anode wiring layer;

A patterned pixel definition layer is coated, exposed, developed and cured on the anode wiring layer.
The method for manufacturing an array substrate according to claim 7, wherein the interlayer dielectric layer includes two layers of SiNx and SiO2.
The method for manufacturing an array substrate according to claim 7, wherein the material of the metal gate layer is at least one of molybdenum, aluminum, indium tin oxide, and indium zinc oxide.
An array substrate, wherein the array substrate comprises:

Substrate

A buffer layer, prepared on the surface of the substrate;

A metal oxide layer is prepared on the surface of the buffer layer, the metal oxide layer includes a channel region and a conductor region, and an ILD via is formed on the metal oxide layer by etching;

A gate insulating layer, prepared on the metal oxide layer, the gate insulating layer includes a non-fluorine atom doped region and a fluorine atom doped region, the fluorine atom doped region is above the channel region ;

Metal gate layer, prepared above the gate insulation layer;

An interlayer dielectric layer, prepared on the metal gate layer,

A source-drain wiring layer formed in the ILD via;

And an organic flat layer prepared on the interlayer dielectric layer, an anode wiring layer and a pixel definition layer.
The array substrate according to claim 15, wherein the metal gate layer includes a first metal gate region and a second metal gate region, the first metal gate region is prepared in the fluorine atom doped region Above, the second metal gate region is prepared on the non-fluorine atom doped region.
The method for manufacturing an array substrate according to claim 15, wherein the interlayer dielectric layer includes two layers of SiNx and SiO2.
The method for manufacturing an array substrate according to claim 15, wherein the material of the metal gate layer is at least one of molybdenum, aluminum, indium tin oxide, and indium zinc oxide.
A display panel, wherein the display panel includes the array substrate according to claim 15.
A display device, wherein the display device includes the display panel according to claim 19.