WO2020113851A1 - 显示面板 - Google Patents

显示面板 Download PDF

Info

Publication number
WO2020113851A1
WO2020113851A1 PCT/CN2019/078548 CN2019078548W WO2020113851A1 WO 2020113851 A1 WO2020113851 A1 WO 2020113851A1 CN 2019078548 W CN2019078548 W CN 2019078548W WO 2020113851 A1 WO2020113851 A1 WO 2020113851A1
Authority
WO
WIPO (PCT)
Prior art keywords
trace
display area
display panel
opening
connect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/078548
Other languages
English (en)
French (fr)
Inventor
张筱霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/342,546 priority Critical patent/US10726758B2/en
Publication of WO2020113851A1 publication Critical patent/WO2020113851A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to a display panel, and particularly to a display panel with an opening design in a display area.
  • the screen-to-body ratio of the display panel can be improved in two ways: one is to reduce the border, and the other is to adopt a special-shaped design, that is, the display area uses a special-shaped (notch)-shaped ( Non-rectangular) design.
  • the display panel 1 includes a display area 11, an opening 12, a non-display area 13, a pair of gate lines 15, 16, and a pair of data lines 17, 18.
  • the display area 11 adopts a special-shaped (non-rectangular) design for providing the arrangement of the opening 12, wherein the opening 12 is reserved for devices such as cameras, and the gate lines 15, 16 and the data lines 17, 18, etc. need to be routed Open this area. And the area around the opening 12 where the gate lines 15 and 16 and the data lines 17 and 18 are bypassed (that is, the non-display area 13) cannot normally set the pixel unit.
  • the display panel 2 includes a display area 21, an opening 22, a non-display area 23, and a pair of gate lines 25, 26, wherein the non-display area 23 cannot normally set a pixel unit.
  • the screen ratio of the display panel is affected not only by the size of the opening, but also by the size of the space occupied by the display area. Therefore, for the special-shaped display panel, reducing the space occupied by the signal line distribution (that is, the non-display area) is one of the directions to increase the screen ratio of the display panel.
  • the purpose of the present disclosure is to provide a display panel which can reduce the space occupied by the distribution of signal lines, thereby increasing the screen ratio of the display panel.
  • the present disclosure provides a display panel including: a display area, wherein a notch is formed at an edge of the display area; an opening is opened in an area surrounded by the outline of the notch; and a non-display area, Located between the display area and the opening; the first trace and the second trace are provided in the non-display area, wherein the second trace is adjacent to the first trace and electrically Sexual isolation; the source driver chip is adjacent to the non-display area, and the opening is between the display area and the source driver chip, wherein the first trace and the second trace Connecting the source driver chip and the display area; a third trace and a fourth trace are provided in the non-display area, wherein the third trace and the fourth trace are adjacent and electrically isolated , And the third trace is used to connect the gate lines in the same row in the display area, and the fourth trace is used to connect the gate lines in the other row in the display area; and Wherein the first trace and the second trace extend from one side of the non-display area to the opposite
  • the first trace is used to connect the first pin of the source driver chip and the first data line of the display area
  • the second trace is used to connect The second pin of the source driver chip and the second data line of the display area.
  • the present disclosure also provides a display panel, including: a display area, wherein a notch is formed at an edge of the display area; an opening is opened in an area surrounded by the outline of the notch; a non-display area is located in the Between the display area and the opening; and the first trace and the second trace are provided in the non-display area, wherein the second trace is adjacent to the first trace and electrically isolated; Wherein the first trace and the second trace extend from one side of the non-display area to the opposite side, and a serpentine bending section is formed at a position around the opening; and wherein The first trace and the second trace are located on different layers.
  • the display panel further includes a source driving chip adjacent to the non-display area, and the opening is located between the display area and the source driving chip, wherein The first trace and the second trace connect the source driver chip and the display area.
  • the first trace is used to connect the first pin of the source driver chip and the first data line of the display area
  • the second trace is used to connect The second pin of the source driver chip and the second data line of the display area.
  • the display panel further includes a third trace and a fourth trace, which are disposed in the non-display area, wherein the third trace and the fourth trace are adjacent And electrically isolated, and the third trace is used to connect the gate lines in the same row in the display area, and the fourth trace is used to connect the gates in the other row in the display area Polar line.
  • the third trace and the fourth trace are located on the same layer, and the lateral distance between the first trace and the second trace is smaller than the third trace The lateral distance between the line and the fourth trace.
  • the display panel further includes a source driving chip adjacent to the non-display area, and the opening is located between the display area and the source driving chip, wherein The first trace is used to connect the gate lines in the same row in the display area, and the second trace is used to connect the gate lines in the other row in the display area.
  • the display panel further includes a third trace and a fourth trace, which are disposed in the non-display area, wherein the third trace and the fourth trace are adjacent Furthermore, the third trace and the fourth trace are connected to the source driving chip and the display area.
  • the third trace and the fourth trace are located on the same layer, and the lateral distance between the first trace and the second trace is smaller than the third trace The lateral distance between the line and the fourth trace.
  • the display panel further includes a source driving chip adjacent to the display area, and the display area is located between the opening and the source driving chip, and the The source driving chip and the opening are respectively located on opposite sides of the display panel.
  • the first trace is used to connect the gate lines in the same row in the display area
  • the second trace is used to connect the gate lines in the display area to another A row of gate lines.
  • the present disclosure reduces the distance from the display area to the opening by using two data lines or two gate lines to increase the display area.
  • the distance between the metal wires of the same layer must be large enough to reduce the risk of short circuit.
  • the distance between the metal wires of different layers and the metal wires is relatively small, for example The distance between two metal wires in different layers can be reduced by more than 50% compared to the distance between two metal wires in the same layer.
  • the gate line needs to be set to bypass the opening, and the distance between the display area and the opening can be reduced by using two layers of gate lines.
  • the display area increases and the screen ratio increases.
  • FIG. 1 shows a schematic structural diagram of an existing special-shaped display panel
  • FIG. 2 shows a schematic structural diagram of another existing special-shaped display panel
  • FIG. 3 shows a schematic structural view of a display panel according to the first preferred embodiment of the present disclosure
  • Figure 4 shows an enlarged schematic view of part D of Figure 3;
  • Figure 5 shows an enlarged schematic view of part E of Figure 3;
  • FIG. 6 shows a partial schematic sectional view of FIG. 3
  • FIG. 7 shows another partial cross-sectional schematic diagram of FIG. 3
  • FIG. 8 shows a schematic structural view of a display panel according to a second preferred embodiment of the present disclosure
  • FIG. 10 shows an enlarged schematic view of part G of FIG. 8
  • FIG. 11 shows a partial cross-sectional schematic diagram of FIG. 8.
  • FIG. 12 shows another partial schematic sectional view of FIG. 8.
  • FIG. 13 shows a schematic structural diagram of a display panel according to a third preferred embodiment of the present disclosure.
  • FIG. 3 shows a schematic structural view of the display panel 3 according to the first preferred embodiment of the present disclosure.
  • the display panel 3 includes a display area 31, an opening 32, a non-display area 33, a source driving chip 34, a first trace 35, a second trace 36, a third trace 37, and a fourth trace 38.
  • the display area 31 adopts a special-shaped (non-rectangular) design for providing the arrangement of the opening 32. Specifically, the edge of the display area 31 is formed with a notch N, and the opening 32 is opened in an area surrounded by the outline of the notch N. The opening 32 is reserved for cameras and other devices.
  • the non-display area 33 is located between the display area 31 and the opening 32.
  • the first trace 35, the second trace 36, the third trace 37, and the fourth trace 38 are disposed in the non-display area 33, and the traces need to be arranged around the area of the opening 32.
  • the first trace 35, the second trace 36, the third trace 37, and the fourth trace 38 all extend from one side of the non-display area 33 to the opposite side, and each trace A serpentine bending section is formed at the position where the wire bypasses the opening 32, respectively. That is to say, the non-display area 33 is an area for providing bypass of the traces.
  • the source driving chip 34 is adjacent to the non-display area 33, and the opening 32 is located between the display area 31 and the source driving chip 34.
  • the first trace 35 and the second trace 36 connect the source driver chip 34 and the display area 31.
  • FIGS. 4 and 5. show an enlarged schematic view of part D of FIG. 3
  • FIG. 5 shows an enlarged schematic view of part E of FIG. 3.
  • the display area 31 is provided with a plurality of pixel units P arranged in an array, and the non-display area 33 has no pixel units P.
  • the first trace 35 connects the first pin 341 of the source driver chip 34 and the first data line D1 of the display area 31.
  • the second trace 36 connects the second pin 342 of the source driver chip 34 and the second data line D2 of the display area 31.
  • the third trace 37 is used to connect the gate lines of the display area 31 located in the same row
  • the fourth trace 38 is used to connect the gate lines of the display area 31 located in another row.
  • FIG. 6 shows a partial cross-sectional schematic diagram of FIG. 3, and FIG. 7 shows another partial cross-sectional schematic diagram of FIG. 3.
  • FIGS. 6 and 7 only show the film layers where the first trace 35, the second trace 36, the third trace 37, and the fourth trace 38 are located, and the remaining film structures are omitted.
  • the first trace 35 and the second trace 36 are adjacent and electrically isolated, and the first trace 35 and the second trace 36 are located at different layers, that is, the first trace 35 is located at the first Layer L1, and the second trace 36 is located in the second layer L2, wherein the first trace 35 and the second trace 36 are separated from each other by a lateral distance C1.
  • FIG. 6 shows a partial cross-sectional schematic diagram of FIG. 3
  • FIG. 7 shows another partial cross-sectional schematic diagram of FIG. 3.
  • FIGS. 6 and 7 only show the film layers where the first trace 35, the second trace 36, the third trace 37, and the fourth trace 38 are located, and the remaining film structures are omitted.
  • the third trace 37 and the fourth trace 38 are adjacent and electrically isolated, and the third trace 37 and the fourth trace 38 are located on the same layer, that is, the third trace 37 and the fourth trace
  • the lines 38 are all located in the film layer L3, wherein the third trace 37 and the fourth trace 38 are separated from each other by a lateral distance C2.
  • the distance between the metal wires of the same layer must be large enough to reduce the risk of short circuit.
  • the distance between the metal wires of different layers and the metal wires is relatively small, for example That is to say, the distance between two metal wires in different layers can be reduced by more than 50% compared to the distance between two metal wires in the same layer.
  • the lateral distance C1 of the first trace 35 and the second trace 36 is smaller than the lateral distance C2 of the third trace 37 and the fourth trace 38.
  • the size of the non-display area 33 can be effectively reduced, thereby increasing the area of the display area 31 and increasing the screen-to-body ratio.
  • the distance A3 from the display area 31 to the side of the opening 32 or the distance B3 from the display area 31 to the other side of the opening 32 can be used Effective reduction, in which the reduction of distance A3 is greater.
  • the third trace 37 and the fourth trace 38 can be designed to be located at different layers, so that the size of the non-display area 33 can be more effectively reduced, thereby increasing the display area 31 area, increase the screen ratio.
  • FIG. 8 shows a schematic structural diagram of a display panel 4 according to a second preferred embodiment of the present disclosure.
  • the display panel 4 includes a display area 41, an opening 42, a non-display area 43, a source driver chip 44, a first trace 45, a second trace 46, a third trace 47, and a fourth trace 48, of which the second
  • the structure of the display panel 4 of the embodiment is substantially the same as the structure of the display panel 3 of the first embodiment, and the same parts will not be repeated here.
  • the source driving chip 44 is adjacent to the non-display area 43, and the opening 42 is located between the display area 41 and the source driving chip 44.
  • the first trace 45 and the second trace 46 are used to connect the gate lines in the same row in the display area 41.
  • FIGS. 9 and 10 show an enlarged schematic view of part F of FIG. 8, and FIG. 10 shows an enlarged schematic view of part G of FIG. 8.
  • the display area 41 is provided with a plurality of pixel units P arranged in an array, and the non-display area 43 does not have pixel units P.
  • the first trace 45 is used to connect the first gate line G1 of the display area 41 in the same row, and the second trace 46 is used to connect the second gate line G2 of the display area 41 in the second row.
  • a gate line G1 and a second gate line G2 are two adjacent gate lines.
  • the third trace 47 and the fourth trace 48 connect the source driver chip 44 and the display area 41.
  • FIG. 11 shows a partial cross-sectional schematic diagram of FIG. 8
  • FIG. 12 shows another partial cross-sectional schematic diagram of FIG. 8.
  • FIGS. 11 and 12 only show the film layers where the first trace 45, the second trace 46, the third trace 47, and the fourth trace 48 are located, and the remaining film structures are omitted.
  • the first trace 45 and the second trace 46 are adjacent and electrically isolated, and the first trace 45 and the second trace 46 are located at different layers, that is, the first trace 45 is located at the first layer L1 And the second trace 46 is located in the second layer L2, wherein the first trace 45 and the second trace 46 are separated from each other by a lateral distance C1.
  • FIG. 11 shows a partial cross-sectional schematic diagram of FIG. 8
  • FIG. 12 shows another partial cross-sectional schematic diagram of FIG. 8.
  • FIGS. 11 and 12 only show the film layers where the first trace 45, the second trace 46, the third trace 47, and the fourth trace 48 are located, and the remaining film structures are omitted.
  • the third trace 47 and the fourth trace 48 are adjacent and electrically isolated, and the third trace 47 and the fourth trace 48 are located on the same layer, that is, the third trace 47 and the fourth trace
  • the lines 48 are all located in the film layer L3, wherein the third trace 47 and the fourth trace 48 are separated from each other by a lateral distance C2.
  • the distance between the metal wires of the same layer must be large enough to reduce the risk of short circuit.
  • the distance between the metal wires of different layers and the metal wires is relatively small, for example That is to say, the distance between two metal wires in different layers can be reduced by more than 50% compared to the distance between two metal wires in the same layer.
  • the lateral distance C1 of the first trace 45 and the second trace 46 is smaller than the lateral distance C2 of the third trace 47 and the fourth trace 48.
  • the size of the non-display area 43 can be effectively reduced, thereby increasing the area of the display area 41 and increasing the screen-to-body ratio.
  • the distance A4 from the display area 41 to the side of the opening 42 or the distance B4 from the display area 41 to the other side of the opening 42 can be used Effective reduction, in which the reduction of distance B4 is greater.
  • the third trace 47 and the fourth trace 48 can be designed to be located at different layers, so that the size of the non-display area 43 can be more effectively reduced, thereby increasing the display area 41 area, increase the screen ratio.
  • FIG. 13 shows a schematic structural diagram of a display panel 5 according to a third preferred embodiment of the present disclosure.
  • the display panel 5 includes a display area 51, an opening 52, a non-display area 53, a source driver chip 54, a first trace 55, and a second trace 56.
  • the display area 51 adopts a special-shaped (non-rectangular) design for providing the arrangement of the opening 52. Specifically, the edge of the display area 51 is formed with a notch N, and the opening 52 is opened in an area surrounded by the outline of the notch N. The opening 52 is reserved for the camera and other devices.
  • the non-display area 53 is located between the display area 51 and the opening 52.
  • the first trace 55 and the second trace 56 are disposed in the non-display area 53, and the traces need to be arranged around the area of the opening 52.
  • the first trace 55 and the second trace 56 both extend from one side of the non-display area 53 to the opposite side, and each trace is formed with a meandering curve at a position around the opening 52 Fold. That is to say, the non-display area 53 is an area for providing bypass for the traces.
  • the source driving chip 54 is adjacent to the display area 51, and the display area 51 is located between the opening 52 and the source driving chip 54, and the source driving chip 54 and the opening 52 are respectively located on the display panel 5 Opposite sides.
  • the first trace 55 and the second trace 56 are used to connect the gate lines in the same row in the display area 51. Specifically, the first trace 55 is used to connect the first gate line of the display area 51 in the same row, and the second trace 56 is used to connect the second gate line of the display area 51 in the second row, The first gate line and the second gate line are two adjacent gate lines.
  • the first trace 55 and the second trace 56 are adjacent and electrically isolated, and the first trace 55 and the second trace 56 are located in different layers (similar to the first trace of the second embodiment Line 45 and second trace 46).
  • the distance between the metal wires of the same layer must be large enough to reduce the risk of short circuit.
  • the distance between the metal wires of different layers and the metal wires is relatively small, for example That is to say, the distance between two metal wires in different layers can be reduced by more than 50% compared to the distance between two metal wires in the same layer.
  • the size of the non-display area 53 can be effectively reduced, thereby increasing the area of the display area 51 and increasing the screen occupation ratio.
  • the distance A5 from the display area 51 to the side of the opening 52 or the distance B5 from the display area 51 to the other side of the opening 52 can be Effective reduction, in which the reduction of distance B5 is greater.
  • the present disclosure reduces the distance from the display area to the opening by using two data lines or two gate lines to achieve the purpose of increasing the display area.
  • the distance between the metal wires of the same layer must be large enough to reduce the risk of short circuit.
  • the distance between the metal wires of different layers and the metal wires is relatively small, for example The distance between two metal wires in different layers can be reduced by more than 50% compared to the distance between two metal wires in the same layer.
  • both the data line and the gate line need to be set to bypass the opening, and the display area can be reduced by using two data lines or two gate lines The distance of the hole, so that the display area increases, the screen ratio increases.
  • the gate line needs to be set to bypass the opening, and the distance between the display area and the opening can be reduced by using two layers of gate lines.
  • the display area increases and the screen ratio increases.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板(3, 4, 5)，包含：显示区(31, 41, 51)，其中显示区(31, 41, 51)的边缘形成有凹口(N)；开孔(32, 42, 52)，开设在凹口(N)的轮廓围绕的区域内；非显示区(33, 43, 53)，位于显示区(31, 41, 51)与开孔(32, 42, 52)之间；以及第一走线(35, 45, 55)和第二走线(36, 46, 56)，设置在非显示区(33, 43, 53)，其中第二走线(36, 46, 56)与第一走线(35, 45, 55)相邻且电性隔离；其中第一走线(35, 45, 55)和第二走线(36, 46, 56)从非显示区(33, 43, 53)的一侧延伸至相对的另一侧，并且绕过开孔(32, 42, 52)的位置分别形成有蛇行弯折段；以及其中第一走线(35, 45, 55)和第二走线(36, 46, 56)位于不同层。

Description

显示面板 技术领域
本揭示涉及一种显示面板，特别是涉及一种在显示区内具有开孔设计的显示面板。
 背景技术
现今，全面屏手机越来越受人们的青睐。如何提升显示面板的屏占比，成为了显示面板的研究热点。为了将屏占比最大化，主要可从两方面提高显示面板的屏占比：其一为缩减边框(border)，其二为采用异形设计，即显示区采用具有凹口(notch)的异形(非矩形)设计。
请参照图1和图2，其显示两种现有的异形显示面板的结构示意图。如图1所示，显示面板1包含显示区11、开孔12、非显示区13、一对栅极线15、16、和一对数据线17、18。显示区11采用异形(非矩形)设计以用于提供开孔12的设置，其中开孔12为摄像头等装置预留区域，并且栅极线15、16和数据线17、18等走线需绕开此区域分布。并且在开孔12周围提供栅极线15、16和数据线17、18绕行的区域(即非显示区13)无法正常设置像素单元。同样的，如图2所示，显示面板2包含显示区21、开孔22、非显示区23、和一对栅极线25、26，其中非显示区23无法正常设置像素单元。
因此，显示面板的屏占比除受开孔的大小影响外，还受显示区所占空间大小的影响。因此，对于异形显示面板而言，减少信号线分布所占空间(即非显示区)是提高显示面板屏占比的方向之一。
有鉴于此，有必要提出一种显示面板，以解决现有技术中存在的问题。
 技术问题
为解决上述现有技术的问题，本揭示的目的在于提供一种显示面板，其可减少信号线分布所占空间，进而提高显示面板屏占比。
 技术解决方案
为达成上述目的，本揭示提供一种显示面板，包含：显示区，其中所述显示区的边缘形成有凹口；开孔，开设在所述凹口的轮廓围绕的区域内；非显示区，位在所述显示区与所述开孔之间；第一走线和第二走线，设置在所述非显示区，其中所述第二走线与所述第一走线相邻且电性隔离；源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线和所述第二走线连接所述源驱动芯片和所述显示区；第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线用于连接所述显示区中位在同一排的栅极线，所述第四走线用于连接所述显示区中位在另一排的栅极线；以及其中所述第一走线和所述第二走线从所述非显示区的一侧延伸至相对的另一侧，并且绕过所述开孔的位置分别形成有蛇行弯折段；以及其中所述第一走线和所述第二走线位于不同层，以及所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
本揭示其中之一优选实施例中，所述第一走线用于连接所述源驱动芯片的第一引脚和所述显示区的第一数据线，以及所述第二走线用于连接所述源驱动芯片的第二引脚和所述显示区的第二数据线。
本揭示还提供一种显示面板，包含：显示区，其中所述显示区的边缘形成有凹口；开孔，开设在所述凹口的轮廓围绕的区域内；非显示区，位在所述显示区与所述开孔之间；以及第一走线和第二走线，设置在所述非显示区，其中所述第二走线与所述第一走线相邻且电性隔离；其中所述第一走线和所述第二走线从所述非显示区的一侧延伸至相对的另一侧，并且绕过所述开孔的位置分别形成有蛇行弯折段；以及其中所述第一走线和所述第二走线位于不同层。
本揭示其中之一优选实施例中，所述显示面板还包含源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线和所述第二走线连接所述源驱动芯片和所述显示区。
本揭示其中之一优选实施例中，所述第一走线用于连接所述源驱动芯片的第一引脚和所述显示区的第一数据线，以及所述第二走线用于连接所述源驱动芯片的第二引脚和所述显示区的第二数据线。
本揭示其中之一优选实施例中，所述显示面板还包含第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线用于连接所述显示区中位在同一排的栅极线，所述第四走线用于连接所述显示区中位在另一排的栅极线。
本揭示其中之一优选实施例中，所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
本揭示其中之一优选实施例中，所述显示面板还包含源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线用于连接所述显示区中位在同一排的栅极线，所述第二走线用于连接所述显示区中位在另一排的栅极线。
本揭示其中之一优选实施例中，所述显示面板还包含第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线和所述第四走线连接所述源驱动芯片和所述显示区。
本揭示其中之一优选实施例中，所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
本揭示其中之一优选实施例中，所述显示面板还包含源驱动芯片，与所述显示区相邻，且所述显示区位在所述开孔和所述源驱动芯片之间，以及所述源驱动芯片和所述开孔分别位在所述显示面板的相对两侧。
本揭示其中之一优选实施例中，所述第一走线用于连接所述显示区中位在同一排的栅极线，所述第二走线用于连接所述显示区中位在另一排的栅极线。
 有益效果
相较于先前技术，本揭示通过采用两层数据线或两层栅极线的方式来减少显示区到开孔的距离，达到增加显示区的目的。在工艺制作中同层的金属线与金属线之间的间距必须要足够大，才可减少短路的风险，反观，异层的金属线与金属线之间的间距要求相对较小，举例来说，异层的两金属线相较同层的两金属线的间距可减少50%以上。当显示区的凹口与源驱动芯片在同一侧时，数据线和栅极线皆需要被设置为绕过开孔，通过采用两层数据线或两层栅极线的方式可减少显示区到开孔的距离，从而显示区域增加，屏占比提高。又，当显示区的凹口与源驱动芯片在相对两侧时，栅极线需要被设置为绕过开孔，通过采用两层栅极线的方式可减少显示区到开孔的距离，从而显示区域增加，屏占比提高。
 附图说明
图1显示一种现有的异形显示面板的结构示意图；
图2显示另一种现有的异形显示面板的结构示意图；
图3显示根据本揭示第一优选实施例的显示面板的结构示意图；
图4显示图3的D部分放大示意图；
图5显示图3的E部分放大示意图；
图6显示图3的局部剖面示意图；
图7显示图3的另一局部剖面示意图；
图8显示根据本揭示第二优选实施例的显示面板的结构示意图；
图9显示图8的F部分放大示意图；
图10显示图8的G部分放大示意图；
图11显示图8的局部剖面示意图；
图12显示图8的另一局部剖面示意图；以及
图13显示根据本揭示第三优选实施例的显示面板的结构示意图。
 本发明的实施方式
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。
请参照图3，其显示根据本揭示第一优选实施例的显示面板3的结构示意图。显示面板3包含显示区31、开孔32、非显示区33、源驱动芯片34、第一走线35、第二走线36、第三走线37、和第四走线38。显示区31采用异形(非矩形)设计以用于提供开孔32的设置。具体来说，显示区31的边缘形成有凹口N，并且开孔32开设在凹口N的轮廓围绕的区域内。开孔32为摄像头等装置预留区域。非显示区33位在显示区31与开孔32之间。第一走线35、第二走线36、第三走线37、和第四走线38设置在非显示区33，并且该等走线需绕开开孔32的区域布置。具体来说，第一走线35、第二走线36、第三走线37、和第四走线38皆是从非显示区33的一侧延伸至相对的另一侧，并且每一走线绕过开孔32的位置分别形成有蛇行弯折段。也就是说，非显示区33是用于提供该等走线绕行的区域。
如图3所示，源驱动芯片34与非显示区33相邻，且开孔32位在显示区31和源驱动芯片34之间。第一走线35和第二走线36连接源驱动芯片34和显示区31。具体来说，请参照图4和图5，图4显示图3的D部分放大示意图，以及图5显示图3的E部分放大示意图。显示区31设置有阵列排布的多个像素单元P，以及非显示区33中不具有像素单元P。第一走线35连接源驱动芯片34的第一引脚341和显示区31的第一数据线D1。第二走线36连接源驱动芯片34的第二引脚342和显示区31的第二数据线D2。
如图3所示，第三走线37用于连接显示区31位在同一排的栅极线，以及第四走线38用于连接显示区31位在另一排的栅极线。
请参照图6和图7，图6显示图3的局部剖面示意图，以及图7显示图3的另一局部剖面示意图。应当注意的是，图6和图7仅显示第一走线35、第二走线36、第三走线37、和第四走线38所在的膜层，其余膜层结构皆省略。如图6所示，第一走线35和第二走线36相邻且电性隔离，并且第一走线35和第二走线36位于不同层，即第一走线35位在第一层L1，且第二走线36位在第二层L2，其中第一走线35和第二走线36彼此相隔横向距离C1。如图7所示，第三走线37和第四走线38相邻且电性隔离，并且第三走线37和第四走线38位于相同层，即第三走线37和第四走线38皆位在膜层L3，其中第三走线37和第四走线38彼此相隔横向距离C2。在工艺制作中，同层的金属线与金属线之间的间距必须要足够大，才可减少短路的风险，反观，异层的金属线与金属线之间的间距要求相对较小，举例来说，异层的两金属线相较同层的两金属线的间距可减少50%以上。因此，第一走线35和第二走线36的横向距离C1小于第三走线37和第四走线38的横向距离C2。在本揭示中，通过将第一走线35和第二走线36设置在不同层的设计，可有效的减小非显示区33的大小，从而增加显示区31的面积，提高屏占比。具体来说，相较于先前技术的显示面板1(如图1所示)，显示区31到开孔32一侧的距离A3或显示区31到开孔32另一侧的距离B3皆可被有效地缩减，其中又以距离A3的缩减幅度较大。可选地，在另一实施例中，可将第三走线37和第四走线38设计为位于不同层，如此，可更为有效地减小非显示区33的大小，从而增加显示区31的面积，提高屏占比。
请参照图8，其显示根据本揭示第二优选实施例的显示面板4的结构示意图。显示面板4包含显示区41、开孔42、非显示区43、源驱动芯片44、第一走线45、第二走线46、第三走线47、和第四走线48，其中第二实施例的显示面板4的结构大致相同于第一实施例的显示面板3的结构，相同的部分在此不加以赘述。
如图8所示，源驱动芯片44与非显示区43相邻，且开孔42位在显示区41和源驱动芯片44之间。第一走线45和第二走线46用于连接显示区41中位在同一排的栅极线。具体来说，请参照图9和图10，图9显示图8的F部分放大示意图，以及图10显示图8的G部分放大示意图。显示区41设置有阵列排布的多个像素单元P，以及非显示区43中不具有像素单元P。第一走线45用于连接显示区41位在同一排的第一栅极线G1，以及第二走线46用于连接显示区41位在第二排的第二栅极线G2，其中第一栅极线G1与第二栅极线G2为相邻的两条栅极线。
又，如图8所示，第三走线47和第四走线48连接源驱动芯片44和显示区41。
请参照图11和图12，图11显示图8的局部剖面示意图，以及图12显示图8的另一局部剖面示意图。应当注意的是，图11和图12仅显示第一走线45、第二走线46、第三走线47、和第四走线48所在的膜层，其余膜层结构皆省略。如图11所示，第一走线45第二走线46相邻且电性隔离，并且第一走线45第二走线46位于不同层，即第一走线45位在第一层L1，且第二走线46位在第二层L2，其中第一走线45第二走线46彼此相隔横向距离C1。如图12所示，第三走线47和第四走线48相邻且电性隔离，并且第三走线47和第四走线48位于相同层，即第三走线47和第四走线48皆位在膜层L3，其中第三走线47和第四走线48彼此相隔横向距离C2。在工艺制作中，同层的金属线与金属线之间的间距必须要足够大，才可减少短路的风险，反观，异层的金属线与金属线之间的间距要求相对较小，举例来说，异层的两金属线相较同层的两金属线的间距可减少50%以上。因此，第一走线45第二走线46的横向距离C1小于第三走线47和第四走线48的横向距离C2。在本揭示中，通过将第一走线45第二走线46设置在不同层的设计，可有效的减小非显示区43的大小，从而增加显示区41的面积，提高屏占比。具体来说，相较于先前技术的显示面板1(如图1所示)，显示区41到开孔42一侧的距离A4或显示区41到开孔42另一侧的距离B4皆可被有效地缩减，其中又以距离B4的缩减幅度较大。可选地，在另一实施例中，可将第三走线47和第四走线48设计为位于不同层，如此，可更为有效地减小非显示区43的大小，从而增加显示区41的面积，提高屏占比。
请参照图13，其显示根据本揭示第三优选实施例的显示面板5的结构示意图。显示面板5包含显示区51、开孔52、非显示区53、源驱动芯片54、第一走线55、和第二走线56。显示区51采用异形(非矩形)设计以用于提供开孔52的设置。具体来说，显示区51的边缘形成有凹口N，并且开孔52开设在凹口N的轮廓围绕的区域内。开孔52为摄像头等装置预留区域。非显示区53位在显示区51与开孔52之间。第一走线55和第二走线56设置在非显示区53，并且该等走线需绕开开孔52的区域布置。具体来说，第一走线55和第二走线56皆是从非显示区53的一侧延伸至相对的另一侧，并且每一走线绕过开孔52的位置分别形成有蛇行弯折段。也就是说，非显示区53是用于提供该等走线绕行的区域。
如图13所示，源驱动芯片54与显示区51相邻，且显示区51位在开孔52和源驱动芯片54之间，以及源驱动芯片54和开孔52分别位在显示面板5的相对两侧。第一走线55和第二走线56用于连接显示区51中位在同一排的栅极线。具体来说，第一走线55用于连接显示区51位在同一排的第一栅极线，以及第二走线56用于连接显示区51位在第二排的第二栅极线，其中第一栅极线与第二栅极线为相邻的两条栅极线。
如图13所示，第一走线55和第二走线56相邻且电性隔离，并且第一走线55和第二走线56位于不同层(相似于第二实施例的第一走线45和第二走线46)。在工艺制作中，同层的金属线与金属线之间的间距必须要足够大，才可减少短路的风险，反观，异层的金属线与金属线之间的间距要求相对较小，举例来说，异层的两金属线相较同层的两金属线的间距可减少50%以上。因此，在本揭示中，通过将第一走线55和第二走线56设置在不同层的设计，可有效的减小非显示区53的大小，从而增加显示区51的面积，提高屏占比。具体来说，相较于先前技术的显示面板2(如图2所示)，显示区51到开孔52一侧的距离A5或显示区51到开孔52另一侧的距离B5皆可被有效地缩减，其中又以距离B5的缩减幅度较大。
综上所述，本揭示通过采用两层数据线或两层栅极线的方式来减少显示区到开孔的距离，达到增加显示区的目的。在工艺制作中同层的金属线与金属线之间的间距必须要足够大，才可减少短路的风险，反观，异层的金属线与金属线之间的间距要求相对较小，举例来说，异层的两金属线相较同层的两金属线的间距可减少50%以上。当显示区的凹口与源驱动芯片在同一侧时，数据线和栅极线皆需要被设置为绕过开孔，通过采用两层数据线或两层栅极线的方式可减少显示区到开孔的距离，从而显示区域增加，屏占比提高。又，当显示区的凹口与源驱动芯片在相对两侧时，栅极线需要被设置为绕过开孔，通过采用两层栅极线的方式可减少显示区到开孔的距离，从而显示区域增加，屏占比提高。
以上仅是本揭示的优选实施方式，应当指出，对于所属领域技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (12)

  1. 一种显示面板，包含：
    显示区，其中所述显示区的边缘形成有凹口；
    开孔，开设在所述凹口的轮廓围绕的区域内；
    非显示区，位在所述显示区与所述开孔之间；
    第一走线和第二走线，设置在所述非显示区，其中所述第二走线与所述第一走线相邻且电性隔离；
    源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线和所述第二走线连接所述源驱动芯片和所述显示区；
    第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线用于连接所述显示区中位在同一排的栅极线，所述第四走线用于连接所述显示区中位在另一排的栅极线；以及
    其中所述第一走线和所述第二走线从所述非显示区的一侧延伸至相对的另一侧，并且绕过所述开孔的位置分别形成有蛇行弯折段；以及
    其中所述第一走线和所述第二走线位于不同层，以及所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
  2. 如权利要求1的显示面板，其中所述第一走线用于连接所述源驱动芯片的第一引脚和所述显示区的第一数据线，以及所述第二走线用于连接所述源驱动芯片的第二引脚和所述显示区的第二数据线。
  3. 一种显示面板，包含：
    显示区，其中所述显示区的边缘形成有凹口；
    开孔，开设在所述凹口的轮廓围绕的区域内；
    非显示区，位在所述显示区与所述开孔之间；以及
    第一走线和第二走线，设置在所述非显示区，其中所述第二走线与所述第一走线相邻且电性隔离；
    其中所述第一走线和所述第二走线从所述非显示区的一侧延伸至相对的另一侧，并且绕过所述开孔的位置分别形成有蛇行弯折段；以及
    其中所述第一走线和所述第二走线位于不同层。
  4. 如权利要求3的显示面板，其中所述显示面板还包含源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线和所述第二走线连接所述源驱动芯片和所述显示区。
  5. 如权利要求4的显示面板，其中所述第一走线用于连接所述源驱动芯片的第一引脚和所述显示区的第一数据线，以及所述第二走线用于连接所述源驱动芯片的第二引脚和所述显示区的第二数据线。
  6. 如权利要求4的显示面板，其中所述显示面板还包含第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线用于连接所述显示区中位在同一排的栅极线，所述第四走线用于连接所述显示区中位在另一排的栅极线。
  7. 如权利要求6的显示面板，其中所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
  8. 如权利要求3的显示面板，其中所述显示面板还包含源驱动芯片，与所述非显示区相邻，且所述开孔位在所述显示区和所述源驱动芯片之间，其中所述第一走线用于连接所述显示区中位在同一排的栅极线，所述第二走线用于连接所述显示区中位在另一排的栅极线。
  9. 如权利要求8的显示面板，其中所述显示面板还包含第三走线和第四走线，设置在所述非显示区，其中所述第三走线和所述第四走线相邻且电性隔离，并且所述第三走线和所述第四走线连接所述源驱动芯片和所述显示区。
  10. 如权利要求9的显示面板，其中所述第三走线和所述第四走线位于相同层，并且所述第一走线和所述第二走线的横向距离小于所述第三走线和所述第四走线的横向距离。
  11. 如权利要求3的显示面板，其中所述显示面板还包含源驱动芯片，与所述显示区相邻，且所述显示区位在所述开孔和所述源驱动芯片之间，以及所述源驱动芯片和所述开孔分别位在所述显示面板的相对两侧。
  12. 如权利要求11的显示面板，其中所述第一走线用于连接所述显示区中位在同一排的栅极线，所述第二走线用于连接所述显示区中位在另一排的栅极线。
PCT/CN2019/078548 2018-12-04 2019-03-18 显示面板 Ceased WO2020113851A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/342,546 US10726758B2 (en) 2018-12-04 2019-03-18 Display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811474755.XA CN109493726A (zh) 2018-12-04 2018-12-04 显示面板
CN201811474755.X 2018-12-04

Publications (1)

Publication Number Publication Date
WO2020113851A1 true WO2020113851A1 (zh) 2020-06-11

Family

ID=65698240

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/078548 Ceased WO2020113851A1 (zh) 2018-12-04 2019-03-18 显示面板

Country Status (2)

Country Link
CN (1) CN109493726A (zh)
WO (1) WO2020113851A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111682055A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117456827A (zh) * 2023-03-17 2024-01-26 广州华星光电半导体显示技术有限公司 显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170033129A1 (en) * 2011-01-28 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20180005588A1 (en) * 2016-06-29 2018-01-04 Semiconductor Energy Laboratory Co., Ltd. Electronic device, operation method of the electronic device, and moving vehicle
CN108389881A (zh) * 2018-02-28 2018-08-10 上海天马微电子有限公司 显示面板和显示装置
CN108806513A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 显示面板及显示装置
CN108807426A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 一种阵列基板以及显示面板
CN108847415A (zh) * 2018-06-29 2018-11-20 厦门天马微电子有限公司 一种阵列基板、栅极驱动电路以及显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990332B (zh) * 2015-02-17 2019-11-05 群创光电股份有限公司 薄膜晶体管基板及其显示面板
KR102526110B1 (ko) * 2016-04-12 2023-04-27 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
CN107331295B (zh) * 2016-04-29 2020-10-27 群创光电股份有限公司 显示器面板
CN106782270A (zh) * 2017-01-09 2017-05-31 厦门天马微电子有限公司 一种显示面板及显示装置
KR102377906B1 (ko) * 2017-04-21 2022-03-23 삼성디스플레이 주식회사 유기 발광 표시 장치
CN107993581B (zh) * 2017-11-30 2019-12-13 武汉天马微电子有限公司 一种显示面板及显示装置
CN107966864B (zh) * 2017-12-15 2020-08-04 昆山龙腾光电股份有限公司 一种液晶显示装置
CN108646492A (zh) * 2018-06-29 2018-10-12 厦门天马微电子有限公司 一种阵列基板、其驱动方法、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170033129A1 (en) * 2011-01-28 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20180005588A1 (en) * 2016-06-29 2018-01-04 Semiconductor Energy Laboratory Co., Ltd. Electronic device, operation method of the electronic device, and moving vehicle
CN108389881A (zh) * 2018-02-28 2018-08-10 上海天马微电子有限公司 显示面板和显示装置
CN108806513A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 显示面板及显示装置
CN108807426A (zh) * 2018-06-29 2018-11-13 厦门天马微电子有限公司 一种阵列基板以及显示面板
CN108847415A (zh) * 2018-06-29 2018-11-20 厦门天马微电子有限公司 一种阵列基板、栅极驱动电路以及显示面板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111682055A (zh) * 2020-06-24 2020-09-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置
CN111682055B (zh) * 2020-06-24 2022-08-30 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板和显示装置

Also Published As

Publication number Publication date
CN109493726A (zh) 2019-03-19

Similar Documents

Publication Publication Date Title
US9075466B2 (en) Touch panel with single electrode layer
CN118759747B (zh) 显示面板
CN105552090B (zh) 像素阵列基板
CN111384066A (zh) 阵列基板、显示装置
CN102844803B (zh) 有源矩阵基板和显示装置
CN106707646A (zh) 一种阵列基板和显示面板
CN206098392U (zh) 一种显示面板及显示装置
CN107479283A (zh) 一种阵列基板、显示面板及显示装置
TWI602002B (zh) 顯示面板
US20180074357A1 (en) Touch panel and manufacturing method therefor, display apparatus
US20210183327A1 (en) Display panel and display device
CN115425046B (zh) 一种显示面板以及电子设备
CN113937109A (zh) 一种显示面板、显示装置、制备方法及掩膜版
CN114981976A (zh) 显示面板、显示装置
CN108962117B (zh) 一种可折叠的显示面板及可折叠显示装置
WO2019210662A1 (zh) 显示面板和显示装置
CN115132760A (zh) 显示面板及显示装置
WO2020113851A1 (zh) 显示面板
JP7358240B2 (ja) デマルチプレクサ、それを備えたアレイ基板、及び表示装置
US10726758B2 (en) Display panel
US12282236B2 (en) Circuit board, display substrate and display apparatus
US12032776B2 (en) Display panel and mobile terminal
CN114284302B (zh) 阵列基板、显示面板及显示装置
US11563036B2 (en) Array substrate and fabrication method thereof, display panel and display module
CN114740664A (zh) 显示面板及显示屏

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19893108

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19893108

Country of ref document: EP

Kind code of ref document: A1