WO2020113647A1 - 显示面板及驱动方法和显示装置 - Google Patents

显示面板及驱动方法和显示装置 Download PDF

Info

Publication number
WO2020113647A1
WO2020113647A1 PCT/CN2018/120834 CN2018120834W WO2020113647A1 WO 2020113647 A1 WO2020113647 A1 WO 2020113647A1 CN 2018120834 W CN2018120834 W CN 2018120834W WO 2020113647 A1 WO2020113647 A1 WO 2020113647A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixels
column
sub
gate
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/120834
Other languages
English (en)
French (fr)
Inventor
吴川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,178 priority Critical patent/US11488555B2/en
Publication of WO2020113647A1 publication Critical patent/WO2020113647A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a driving method and a display device.
  • liquid crystal displays have become the mainstream products of displays due to their advantages of thin body, power saving and low radiation, and have been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a display panel and a backlight module.
  • the working principle of the display panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage to the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light from the backlight module to generate a picture.
  • Half-Source Driver is a low-cost production solution commonly used in the display panel industry.
  • the solution is to double the number of scan lines so that a single data line can correspond to two adjacent columns Pixels, thereby saving half of the source driver integrated chips, but there will be a phenomenon of vertical bright and dark lines.
  • the present application provides a display panel, a driving method and a display device, so as to achieve brightness balance.
  • the present application provides a display panel, including: a substrate; the substrate is provided with: a plurality of data lines, a plurality of gate lines, a plurality of pixel units and a gate driving chip; the pixel unit Including sub-pixels of different colors; the gate driving chip outputs a gate start signal to the gate line to turn on the pixel unit; each row of the pixel unit includes a plurality of pixel groups, and each of the pixel groups includes a phase The neighboring first column of subpixels and the second column of subpixels are connected to the same data line, and the first column of subpixels and the second column of subpixels are connected to two Different gate lines; the polarity of the data driving signal adopted by each pixel group and the adjacent pixel group in the pixel unit of each row is opposite; the gate start signal voltage of the sub-pixels in the first column is greater than that in the second column The gate start signal voltage corresponding to the pixel.
  • the charging voltages of the sub-pixels in the first column and the sub-pixels in the second column are the same.
  • the polarities of the data driving voltages corresponding to the first column of subpixels and the second column of subpixels are opposite, the first column of subpixels are odd column subpixels, and the second column of subpixels are even column subpixels; corresponding to the odd number
  • the voltage of the first gate start signal of the column subpixels is greater than the voltage of the second gate start signal of the even column subpixels.
  • the difference between the voltage of the first gate start signal corresponding to the odd-numbered sub-pixels and the voltage of the second gate start signal corresponding to the even-numbered sub-pixels is y, and the value of y is greater than 0 and less than or equal to 10 volts.
  • the waveforms of the voltages of the first gate start signal and the voltages of the second gate start signal are both cut-angle waveforms.
  • the slope of the cut angle of the first gate activation signal is greater than the slope of the cut angle of the second gate activation signal.
  • each cycle of the first gate start signal includes a first pre-cut angle interval and a first angle-cut interval; each cycle of the second gate start signal includes a second pre-cut angle interval and a second cut angle Interval; the voltage in the first pre-angle-cut interval is greater than the voltage in the second pre-angle-cut interval; the lowest voltage in the first angle-cut interval is equal to the voltage in the second angle-cut interval.
  • the start time of the first angle-cutting interval and the second angle-cutting interval are the same.
  • the slope of the first angle-cutting interval is greater than the slope of the second angle-cutting interval.
  • the voltage of the first gate start signal after the corner cut of the odd-numbered sub-pixels is equal to the voltage of the second gate start signal after the corner cut of the even-numbered sub-pixels.
  • the display panel uses a half-source driving architecture.
  • the display panel is in dual drive mode.
  • the present application also discloses a driving method using the display panel as described above, including the steps of:
  • the gate drive chip outputs a gate start signal to each row of pixel units according to the control signal
  • the data driving chip outputs the same data signal to the first column of subpixels and the second column of subpixels of each row of pixels;
  • the gate driving chip controls the voltage of the gate activation signal corresponding to the sub-pixels in the first column to be greater than the voltage of the gate activation signal corresponding to the sub-pixels in the second column.
  • the polarities of the data driving voltages corresponding to the first column of subpixels and the second column of subpixels are opposite, the first column of subpixels are odd column subpixels, and the second column of subpixels are even column subpixels; corresponding to the odd number
  • the voltage of the first gate start signal of the column subpixels is greater than the voltage of the second gate start signal of the even column subpixels.
  • the charging voltages of the sub-pixels in the first column and the sub-pixels in the second column are the same.
  • the difference between the voltage of the first gate start signal corresponding to the odd-numbered sub-pixels and the voltage of the second gate start signal corresponding to the even-numbered sub-pixels is y, and the value of y is greater than 0 and less than or equal to 10 volts.
  • the waveforms of the voltages of the first gate start signal and the voltages of the second gate start signal are both angle-cut waveforms; each cycle of the first gate start signal includes a first pre-cut angle interval and a first Angle-cutting interval; the second grid start signal includes a second angle-cutting interval and a second angle-cutting interval every period; the voltage of the first angle-cutting interval is greater than the voltage of the second angle-cutting interval; The lowest voltage in the first angular interval is equal to the voltage in the second angular interval.
  • the slope of the first angle-cutting interval is greater than the slope of the second angle-cutting interval.
  • the application also discloses a display device, including the display panel as described above.
  • the display device is one of a twisted nematic display device, a plane switching display device, and a multi-quadrant vertical alignment display device.
  • the corresponding gate can be made faster by enhancing the voltage of the gate start signal corresponding to the first column of subpixels Turn on, so that the first column of sub-pixels can reach a higher charging voltage faster than before, reducing or even eliminating the difference between the charging voltages of the two pixels before and after polarity reversal, making the charging voltage of two adjacent pixels tend to In the same way, to solve the phenomenon of visual vertical bright and dark lines; in addition, this solution does not need to change the design, only the interlace output gate start signal with different voltage, and the operation is convenient.
  • FIG. 1 is a schematic diagram of a half-source driving architecture according to an embodiment of the present application
  • FIG. 2 is a partially enlarged schematic view of area A in FIG. 1;
  • FIG. 3 is a schematic diagram of a data output waveform of a half-source driving architecture according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of actual output waveforms of half-source driving architecture data according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a pixel voltage of a half-source driving architecture according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a display panel according to an embodiment of the application.
  • FIG. 7 is a schematic diagram of an output waveform of a data line of a display panel according to an embodiment of the application.
  • FIG. 8 is a schematic diagram of an actual output waveform of a display panel data line according to an embodiment of the application.
  • FIG. 9 is a schematic diagram of a pixel voltage of a display panel according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of an output waveform of a cut-angle waveform data line of a display panel according to an embodiment of the application;
  • FIG. 11 is a schematic diagram of an actual output waveform of a cut-angle waveform data line of a display panel according to an embodiment of the application;
  • FIG. 12 is a schematic flowchart of a display panel driving method according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a block diagram of a display device according to an embodiment of the present application.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • FIGS. 1 and 2 two adjacent columns of sub-pixels share a data line, and adjacent pixel units are connected to different gate lines.
  • the gate start signal is turned on, the thin film transistors in the corresponding row are turned on.
  • the corresponding data signal is sent into the data line in the vertical direction to charge the storage capacitor to an appropriate voltage, and a line of images can be displayed.
  • Data represents the waveform of the data line
  • Gate is the waveform of the gate line. When Gate is the highest peak, it is turned on, and the corresponding odd column sub-pixel Odd and even column sub-pixel even are turned on.
  • the data driving voltage of the corresponding odd-numbered column sub-pixel after polarity inversion will take a certain time to reach the preset voltage intensity, resulting in the current
  • the odd-numbered column sub-pixels and the even-numbered column sub-pixels that share a data line with its adjacent column are turned on under the same gate start signal.
  • the voltage of the even-numbered sub-pixels is greater than that of the odd-numbered sub-pixels
  • Vp_even is the voltage of the sub-pixels corresponding to the even-numbered columns
  • Vp_odd is the voltage of the sub-pixels corresponding to the odd-numbered columns, so that the brightness of the even-numbered sub-pixels is brighter than that of the odd-numbered sub-pixels. Therefore, there is a phenomenon of vertical bright and dark lines.
  • an embodiment of the present application discloses a display panel 101, including: a substrate 104; the substrate 104 is provided with: a plurality of data lines 120, a plurality of gate lines 110, a plurality of pixels
  • the pixel unit 130 includes a plurality of pixel groups, and each of the pixel groups includes an adjacent first column of sub-pixels 131 and a subsequent second column of sub-pixels 132, the first column of sub-pixels 131 and the second column of sub-pixels 132 is connected to the same data line 120, and the first column of sub-pixels 131 and the second column of sub-pixels 132 are connected to two different gate lines 110; each pixel group and adjacent pixels in the pixel unit of each row The polarities of the data driving signals used in the group are opposite; the voltage of the gate
  • the gate activation signal voltage corresponding to the first column of sub-pixels 131 is greater than the gate activation signal voltage corresponding to the second column of sub-pixels 132, and the corresponding gate is enhanced by enhancing the voltage of the gate activation signal corresponding to the first column of sub-pixels 131 It can be turned on faster, so that the first column of sub-pixels 131 can reach a higher charging voltage faster than before, reducing or even eliminating the difference between the charging voltages of the two pixels before and after polarity inversion, making the two adjacent pixels
  • the charging voltage tends to be the same, so as to solve the phenomenon of visual vertical bright and dark lines; in addition, this solution does not need to change the design, only the interlace output gate start signal with different voltage, and the operation is convenient.
  • the arrangement direction of the sub-pixels of different colors may be arranged along the direction of the gate line or the data line.
  • the polarities of the data driving voltages corresponding to the first column of subpixels 131 and the second column of subpixels 132 are opposite, the first column of subpixels 131 are odd column subpixels, and the second column of subpixels 132 are even column subpixels Pixel; the voltage of the first gate start signal corresponding to the sub-pixels of odd columns is greater than the voltage of the second gate start signal of the sub-pixels of even columns.
  • the data driving voltage of the odd-numbered sub-pixels after polarity inversion can reach the preset voltage strength after a certain period of time, resulting in the odd-numbered and sub-pixels starting at the same gate
  • the conduction time of the two is the same, which makes the difference in the final charge state of the two sub-pixels, resulting in the phenomenon of bright and dark lines; the charging of the pixel is the result of the overlapping use of the data signal and the gate signal.
  • the polarity change will cause signal delay, while the pixel without signal polarity change, its data line signal will not cause delay.
  • the data line signal in which the polarity of the data signal changes is low, and the data signal in which the polarity of the data signal does not change is high.
  • the gate line signal is lower, and the pixel with a low data line signal (that is, a pixel with polarity change), the gate
  • the polar line signal is a little higher, and the mutual charge is finally reached to be equivalent, and the brightness is equal.
  • This scheme uses one high and one low gate start signal.
  • the higher gate start signal corresponds to driving odd-numbered sub-pixels
  • the lower gate start signal corresponds to driving even-numbered sub-pixels, so that the odd-numbered gate scanning signals have polarity inversion.
  • the even column gate signal corresponds to the data line signal without polarity conversion
  • the odd column subpixel corresponds to the high data signal and low gate start signal
  • the even column subpixel corresponds to the low data line signal and high gate start signal, one high one Low
  • the two are complementary to each other, the balance is reached, and the final charge is equivalent to reduce the difference in the state of charge of the two, reduce the phenomenon of bright and dark lines, and make the brightness equal
  • the final charge is equivalent to reduce the difference in the state of charge of the two, reduce the phenomenon of bright and dark lines, and make the brightness equal; in addition, relative to the original gate start signal, if the gate of the odd-numbered sub-pixel If the start signal is higher, and the gate start signal of the even-numbered sub-pixels is lower, it can be adjusted so that the charging states of
  • the difference between the first gate start signal voltage corresponding to the odd-numbered sub-pixels and the second gate start signal voltage corresponding to the even-numbered sub-pixels is y, and the value of y is greater than 0 and less than or equal to 10 volt.
  • the voltage difference of the gate start signal voltage is too small to solve the phenomenon of vertical bright and dark lines; the charging voltage difference is too large, the brightness may cause the original dark line to be brighter than the original bright line, and the situation of reversed bright and dark lines occurs.
  • the waveforms of the first gate start signal voltage and the second gate start signal voltage are both cut-angle waveforms.
  • the waveforms of the gate start signal are all waveforms with chamfered angles, which have chamfered angles, which are located at the end of each period of the waveform.
  • the chamfered waveform makes the circuit more stable, and the swept waveform can be adjusted more flexibly.
  • the chamfered angle of the swept waveform with a slope is most closely affected by the RC delay caused by the resistance and capacitance of the panel at different positions of the panel. The uniformity is good, to achieve a better picture display effect.
  • the slope of the cut angle of the first gate enable signal is greater than the slope of the cut angle of the second gate enable signal.
  • the dual-drive is used for the large-size panel, and the gate start signal enters from both sides. Due to the presence of a signal delay (RC delay), the charging effect of the entry terminals on both sides is better than that in the middle section, so the two sides The brightness of the charging at the entry end is higher, and the brightness of the middle section is darker, so there is a phenomenon of whitening on both sides.
  • the gate is chamfered. Due to the chamfered angle, the charging effect on the inlets on both sides becomes slightly worse, so that the difference in brightness between the middle and the sides is reduced, thereby reducing the effect of whitening on both sides of the display panel. .
  • the slope of the cut angle of the first gate activation signal is greater than the slope of the cut angle of the second gate activation signal, which is one of the options for achieving this effect.
  • each cycle of the first gate activation signal includes a first pre-cut angle interval and a first angle-cut interval; each cycle of the second gate activation signal includes a second pre-cut angle interval and a second The chamfered interval; the voltage in the first pre-angled interval is greater than the voltage in the second pre-angled interval; the lowest voltage in the first chamfered interval is equal to the voltage in the second chamfered interval.
  • the time point of starting the chamfering is basically the same. When the chamfering is completed, the voltage is equivalent. Therefore, the slope of the first chamfering interval is greater than the slope of the second chamfering interval.
  • the voltage of the first gate start signal before the chamfering of the odd-numbered sub-pixels is greater than the voltage of the second gate start signal before the chamfering of the even-numbered sub-pixels, and the first gate after the chamfering of the odd-numbered sub-pixels starts The voltage of the signal is equal to the voltage of the second gate start signal after the corner-cutting of the even-numbered sub-pixels.
  • the voltage of the first gate activation signal of the odd-numbered sub-pixels is greater than the voltage of the second gate activation signal of the even-numbered sub-pixels
  • the first gate activation signal of the odd-numbered sub-pixels Is equal to the voltage of the second gate enable signal of the even-numbered sub-pixels, so that the absolute value of the difference between the turn-on voltage VGH and the turn-off voltage VGL of the odd-numbered sub-pixels is greater than the absolute value of the difference between the turn-on voltage VGH and the turn-off voltage VGL of the even-numbered columns
  • the size of Flicker is related to the size of the absolute value of (VGH-VGL)
  • reducing the VGH voltage can reduce Flicker, which can improve the Margin on the process and improve uniformity.
  • a display panel 101 including: a substrate 104; the substrate 104 is provided with: a plurality of data lines 120 and a plurality of gate lines 110.
  • the gate line 110 turns on the pixel unit 130; each row of the pixel unit includes a plurality of pixel groups, and each pixel group includes an adjacent first column of sub-pixels 131 and a second column of sub-pixels 132, the first column of subpixels 131 and the second column of subpixels 132 are connected to the same data line 120, and the first column of subpixels 131 and the second column of subpixels 132 are connected to two different gate lines 110;
  • One column of subpixels 131 is an odd column of subpixels
  • the second column of subpixels 132 is an even column of subpixels
  • the voltage of the first gate start signal corresponding to the odd column of subpixels is greater than the voltage of the second gate start of the even column of subpixels
  • the The difference between the voltage of the first gate start signal corresponding to the sub-pixels in odd columns and the voltage of the second gate start signal corresponding to the sub-pixels in even columns is y, and the value of y is greater than 0 and less than or equal to 10 volts
  • the waveforms of the voltages of the second gate start signal are all cut-angle waveforms; each period of the first gate start signal includes a first pre-cut angle interval and a first cut-angle interval; each cycle of the second gate start signal It includes a second angle-cutting interval and a second angle-cutting interval; the voltage of the first angle-cutting interval is greater than the voltage of the second angle-cutting interval; the lowest voltage of the first angle-
  • the actual charging time of the two is different due to the positive and negative polarity conversion of the data line 120, which ultimately leads to the charging of the pixels
  • the voltage difference causes vertical bright and dark lines.
  • the gate activation signal voltage corresponding to the first column of sub-pixels 131 is greater than the gate activation signal voltage corresponding to the second column of sub-pixels 132, and the corresponding gate is enhanced by enhancing the voltage of the gate activation signal corresponding to the first column of sub-pixels 131 Can be turned on faster, so that the first column of sub-pixels 131 can reach a higher charging voltage faster than before, reducing or even eliminating the difference between the charging voltages of the two pixels before and after polarity reversal, making two adjacent pixels
  • the charging voltage tends to be the same, so as to solve the visual vertical bright and dark line phenomenon.
  • this solution does not need to change the design, only the interlace output gate start signal with different voltage, and the operation is convenient.
  • a driving method of a display panel including the steps of:
  • the gate driving chip outputs a gate start signal to each row of pixel units according to the control signal
  • the data driving chip outputs the same data signal to the first column of subpixels and the second column of subpixels of each row of pixels;
  • the gate driving chip controls the voltage of the gate start signal corresponding to the sub-pixels in the first column to be greater than the voltage of the gate start signal corresponding to the sub-pixels in the second column.
  • the driving method of the display panel is applicable to the structure of the display panel described above.
  • the gate voltage of the adjacent even-numbered sub-pixels is equal to the gate signal of the odd-numbered sub-pixels, due to the positive and negative polarity conversion of the data line 120, the actual charging time of the two is different, and finally the pixel's charging voltage is different, resulting in a vertical The phenomenon of bright and dark lines.
  • the gate activation signal voltage corresponding to the first column of sub-pixels 131 is greater than the gate activation signal voltage corresponding to the second column of sub-pixels 132, and the corresponding gate is enhanced by enhancing the voltage of the gate activation signal corresponding to the first column of sub-pixels 131 Can be turned on faster, so that the first column of sub-pixels 131 can reach the predetermined charging voltage faster, reduce or even eliminate the difference in charging before and after polarity reversal, so that the two adjacent pixels have the same charging voltage, thereby solving the visual problem
  • the phenomenon of vertical bright and dark lines; in addition, this solution does not need to change the design, only the interlace output gate start signal with different voltage is required, and the operation is convenient.
  • the polarities of the data driving voltages corresponding to the first column of subpixels 131 and the second column of subpixels 132 are opposite, the first column of subpixels 131 are odd column subpixels, and the second column of subpixels 132 are even column subpixels Pixel; the voltage of the first gate start signal corresponding to the sub-pixels of odd columns is greater than the voltage of the second gate start signal of the sub-pixels of even columns.
  • the data driving voltage of the odd-numbered sub-pixels after polarity inversion takes a certain time to reach the preset voltage intensity, resulting in the same gate start signal when the odd-numbered sub-pixels and the even-numbered sub-pixels are at the same gate start signal
  • the on-time of the two is the same, which makes the final charge state of the two pixels different, resulting in the phenomenon of bright and dark lines; and this solution uses one high and one low gate start signal, the higher gate start signal corresponds to the drive
  • the odd-numbered sub-pixels enable the thin-film transistors of the odd-numbered sub-pixels to be turned on faster, so that the actual charging time of the odd-numbered sub-pixels is slightly longer than that of the even-numbered sub-pixels, so as to reduce the difference in the state of charge of the two and reduce the phenomenon of bright and dark lines; Compared with the original gate start signal, if the gate start signal of the odd-numbered sub-pixels is adjusted higher, and
  • the difference between the first gate start signal voltage corresponding to the odd-numbered sub-pixels and the second gate start signal voltage corresponding to the even-numbered sub-pixels is y, and the value of y is greater than 0 and less than or equal to 10 volts.
  • the waveforms of the voltages of the first gate start signal and the voltages of the second gate start signal are both angle-cut waveforms; each cycle of the first gate start signal includes the first pre-cut angle interval and The first angular interval; the second gate start signal of each cycle includes a second pre-cut angle interval and a second pre-cut angle interval; the voltage of the first pre-cut angle interval is greater than the voltage of the second pre-cut angle interval; The lowest voltage in the first angle-cutting interval is equal to the voltage in the second angle-cutting interval.
  • the voltage of the first gate activation signal of the odd-numbered sub-pixels is greater than the voltage of the second gate activation signal of the even-numbered sub-pixels
  • the first gate activation signal of the odd-numbered sub-pixels Is equal to the voltage of the second gate enable signal of the even-numbered sub-pixels, so that the absolute value of the difference between the turn-on voltage VGH and the turn-off voltage VGL of the odd-numbered sub-pixels is greater than the absolute value of the difference between the turn-on voltage VGH and the turn-off voltage VGL of the even-numbered columns
  • the flicker size is related to the absolute value of (VGH-VGL)
  • reducing the VGH voltage can reduce Flicker, which can improve the process range (Margin) and improve uniformity.
  • a display device 100 including the display panel 101 as described above.
  • the actual charging time of the two is different due to the positive and negative polarity conversion of the data line 120, which ultimately leads to the charging of the pixels
  • the voltage difference causes the phenomenon of vertical bright and dark lines.
  • the gate activation signal voltage corresponding to the first column of sub-pixels 131 is greater than the gate activation signal voltage corresponding to the second column of sub-pixels 132, and the corresponding gate is enhanced by enhancing the voltage of the gate activation signal corresponding to the first column of sub-pixels 131 Can be turned on faster, so that the first column of sub-pixels 131 can reach a higher charging voltage faster than before, reducing or even eliminating the difference between the charging voltages of the two pixels before and after polarity reversal, making two adjacent pixels
  • the charging voltage tends to be the same, so as to solve the phenomenon of visual vertical bright and dark lines; in addition, this solution does not need to change the design, only the interlace output gate start signal with different voltage, and the operation is convenient.
  • the panel of this application may be a TN panel (full name Twisted Nematic, ie twisted nematic panel), IPS panel (In-Plane Switching), VA panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels can also be used.
  • TN panel full name Twisted Nematic, ie twisted nematic panel
  • IPS panel In-Plane Switching
  • VA panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板(101)及驱动方法和显示装置(100)。显示面板(101)包括：基板(104)；基板(104)上设置有：多条数据线(120)、多条栅极线(110)、多个像素单元(130)和栅极驱动芯片(102)；像素单元(130)包括不同颜色的子像素；栅极驱动芯片(102)输出栅启动信号到栅极线(110)以打开像素单元(130)；每一行像素单元(130)包括多个像素组，每个像素组包括第一列子像素(131)和第二列子像素(132)，第一列子像素(131)的栅启动信号电压大于第二列子像素(132)对应的栅启动信号电压。

Description

显示面板及驱动方法和显示装置
本申请要求于2018年12月05日提交中国专利局，申请号为CN201811480085.2，申请名称为“一种显示面板及驱动方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及驱动方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等优点而成为显示器的主流产品，得到了广泛应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括显示面板及背光模组(back light module)。显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
半源极驱动架构(half-Source Driver，HSD)是显示面板业界常用的一种低成本生产方案，该方案是将扫描线的数目增加一倍，使单一数据线可以对应相邻两列的子像素，藉此节省半数的源极驱动集成芯片，但会有垂直亮暗线的现象产生。
技术解决方案
本申请提供一种显示面板及驱动方法和显示装置，以实现亮度均衡。
为实现上述目的，本申请提供了一种显示面板，包括：基板；所述基板上设置有：多条数据线、多条栅极线、多个像素单元和栅极驱动芯片；所述像素单元包括不同颜色的子像素；所述栅极驱动芯片输出栅启动信号到所述栅极线以打开所述像素单元；每一行所述像素单元包括多个像素组，每个所述像素组包括相邻的在前的第一列子像素和在后的第二列子像素，所述第一列子像素和第二列子像素与同一数据线连接，且所述第一列子像素和第二列子像素连接至两条不同的栅极线；每一行所述像素单元中的每个像素组和相邻的像素组采用的数据驱动信号的极性相反；所述第一列子像素的栅启动信号电压大于第二列子像素对应的栅启动信号电压。
可选的，所述第一列子像素和第二列子像素的充电电压相同。
可选的，所述第一列子像素和第二列子像素对应的数据驱动电压极性相反，所述第一列 子像素为奇数列子像素，所述第二列子像素为偶数列子像素；对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
可选的，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。
可选的，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形。
可选的，所述第一栅启动信号的切角的斜率大于所述第二栅启动信号的切角的斜率。
可选的，每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；所述第一切角前区间的电压大于第二切角前区间的电压；所述第一切角区间的最低电压等于第二切角区间的电压。
可选的，所述第一切角区间和第二切角区间的起始时间相同。
可选的，所述第一切角区间的斜率大于第二切角区间的斜率。
可选的，所述奇数列子像素的切角后的第一栅启动信号的电压等于所述偶数列子像素的切角后的第二栅启动信号的电压。
可选的，所述显示面板采用半源极驱动架构。
可选的，所述显示面板为双驱动模式。
本申请还公开了一种应用如上所述的显示面板的驱动方法，包括步骤：
栅极驱动芯片按照控制信号输出栅启动信号到每一行像素单元；
数据驱动芯片输出同一数据信号给每一行像素的第一列子像素和第二列子像素；
控制每一行像素中的每个像素组和相邻的像素组采用极性相反的数据驱动信号；
栅极驱动芯片控制对应第一列子像素的栅启动信号电压大于对应第二列子像素的栅启动信号电压。
可选的，所述第一列子像素和第二列子像素对应的数据驱动电压极性相反，所述第一列子像素为奇数列子像素，所述第二列子像素为偶数列子像素；对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
可选的，所述第一列子像素和第二列子像素的充电电压相同。
可选的，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。
可选的，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形；每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；所述第一切角前区间的电压大于第二切角前区间的电压；所述第一切角区间的最低电压等于第二切角区间的电压。
可选的，所述第一切角区间的斜率大于第二切角区间的斜率。
本申请还公开了一种显示装置，包括如上述的显示面板。
可选的，所述显示装置为扭曲向列型显示装置、平面转换显示装置和多象限垂直配向显示装置中的一种。
半源驱动架构中，当相邻偶数列子像素的栅极电压等于奇数列子像素的栅极信号时，由于数据线正负极性转换导致两者实际的充电时间有差异，最后导致像素的充电电压差异，从而出现垂直亮暗线的现象。本方案中，通过让第一列子像素对应的栅启动信号电压大于第二列子像素对应的栅启动信号电压，通过增强对应第一列子像素的栅启动信号的电压来使得对应的栅极可以更快的导通，使得第一列子像素可以更快达到较原来更高的充电电压，减少甚至消除极性反转前后两个像素对应的充电电压的差异，使得两个相邻的像素的充电电压趋于相同，从而解决视觉上的垂直亮暗线的现象；另外，本方案不用更改设计，只需隔行输出电压不同的栅启动信号即可，操作方便。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例半源极驱动架构的示意图；
图2是图1中A区域局部放大的示意图；
图3是本申请一实施例半源极驱动架构数据输出波形的示意图；
图4是本申请一实施例半源极驱动架构数据实际输出波形的示意图；
图5是本申请一实施例半源极驱动架构像素电压的示意图；
图6是本申请一实施例一种显示面板的示意图；
图7是本申请一实施例一种显示面板数据线输出波形的示意图；
图8是本申请一实施例一种显示面板数据线实际输出波形的示意图；
图9是本申请一实施例一种显示面板像素电压的示意图；
图10是本申请一实施例一种显示面板切角波形数据线输出波形的示意图；
图11是本申请一实施例一种显示面板切角波形数据线实际输出波形的示意图；
图12是本申请一实施例一种显示面板驱动方法的流程示意图；
图13是本申请一实施例一种显示装置框图的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和可选实施例对本申请作说明。
参考图1、图2，相邻的两列子像素共用一数据线，相邻的像素单元之间与不同的栅极线连接。当栅启动信号打开时，将相应一行的薄膜晶体管打开。此时，垂直方向的数据线送入对应的数据信号，对存储电容充电至适当的电压，便可显示一行的图像。参考图3和图4，其中Data表示的是数据线的波形，Gate为栅极线的波形，当Gate为最高峰的时候为打开状态，打开对应的奇数列子像素Odd和偶数列子像素even。由于数据线会有正负极性的转换，当数据线正负极性转换时，极性反转之后的对应的奇数列子像素的数据驱动电压要一定时间才达到预设的电压强度，导致当前奇数列子像素和与它相邻列且共用一条数据线的偶数列子像素在同样的栅启动信号启动下，两者的导通时间一样，C1为第一行栅启动信号导通的时间，C2为第二行栅启动信号导通的时间，此时C1＝C2；而使得两像素最终的充电状态有差异。参考图5，偶数列子像素的电压大于奇数列子像素的电压，Vp_even为偶数列对应的子像素 电压，Vp_odd为奇数列对应的子像素电压，从而偶数列子像素的亮度亮于奇数列子像素的亮度，因此存在垂直亮暗线的现象。
参考图6至图9所示，本申请实施例公开了一种显示面板101，包括：基板104；所述基板104上设置有：多条数据线120、多条栅极线110、多个像素单元130和栅极驱动芯片102；所述像素单元130包括不同颜色的子像素；所述栅极驱动芯片102输出栅启动信号到所述栅极线110以打开所述像素单元130；每一行所述像素单元130包括多个像素组，每个所述像素组包括相邻的在前的第一列子像素131和在后的第二列子像素132，所述第一列子像素131和第二列子像素132与同一数据线120连接，且所述第一列子像素131和第二列子像素132连接至两条不同的栅极线110；每一行所述像素单元中的每个像素组和相邻的像素组采用的数据驱动信号的极性相反；所述第一列子像素131的栅启动信号电压大于第二列子像素132对应的栅启动信号电压。
半源驱动架构中，当相邻偶数列子像素的栅极电压等于奇数列子像素的栅极信号时，由于数据线正负极性转换导致两者实际的充电时间有差异，最后导致像素的充电电压差异，从而出现垂直亮暗线。本方案中，通过让第一列子像素131对应的栅启动信号电压大于第二列子像素132对应的栅启动信号电压，通过增强对应第一列子像素131的栅启动信号的电压来使得对应的栅极可以更快的导通，使得第一列子像素131更快达到较原来更高的充电电压，减少甚至消除极性反转前后两个像素对应的充电电压的差异，使得两个相邻的像素的充电电压趋于相同，从而解决视觉上的垂直亮暗线的现象；另外，本方案不用更改设计，只需隔行输出电压不同的栅启动信号即可，操作方便。
其中，不同颜色的子像素的设置方向可以沿着栅极线或数据线方向设置。
在一实施例中，所述第一列子像素131和第二列子像素132对应的数据驱动电压极性相反，所述第一列子像素131为奇数列子像素，所述第二列子像素132为偶数列子像素；对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
由于数据线120正负极性转换时，极性反转之后的奇数列子像素的数据驱动电压经过一定时间才可以达到预设的电压强度，导致当奇数列子像素和偶数列子像素在同样的栅启动信号启动下，两者的导通时间一样，而使得两子像素最终的充电状态有差异，造成亮暗线的现象；像素的充电，是数据信号和栅极信号的交叠使用结果,有数据信号极性转变的会造成信号延迟，而没有信号极性转变的像素，其数据线信号不会造成延迟。因此，数据信号极性转变的数据线信号低，数据信号极性不转变的数据信号高。为了让两者充电能力相当，就要让数据线信号高(即没有极性转变)的像素，栅极线信号低一点，而数据线信号低(即有极性转变的像素)的像素，栅极线信号高一点，达到相互平衡最终充电相当，亮度均等。本方案采用一高一低两个栅启动信号，该较高的栅启动信号对应驱动奇数列子像素，较低的栅启动 信号对应驱动偶数列子像素，使奇数列栅极扫描信号对应具有极性转换后的数据线信号，偶数列栅极信号对应无极性转换的数据线信号，奇数列子像素对应高数据信号和低栅启动信号，偶数列子像素对应低数据线信号和高栅启动信号，一高一低，两者相互互补，达到相互平衡最终充电相当,以减少两者的充电状态差异，减轻亮暗线的现象,使亮度均等；另外，相对于原来的栅启动信号，若是该奇数列子像素的栅启动信号调高一些，而偶数列子像素的栅启动信号调低一些的话，可以调整使得最终两者的充电状态一致，以避免亮暗线的现象发生。
参考图7，在一实施例中，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。栅启动信号电压的电压差太小，无法解决垂直亮暗线的现象；充电的电压差太大，亮度可能会造成原来的暗线比原来的亮线更亮，而出现对调的亮暗线的情况。
参考图10和图11，在一实施例中，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形。栅启动信号的波形均为带切角波形，具有切角，该切角位于每一周期波形的最后。切角波形，使得电路更加稳定，扫描波形可调整的灵活度更高，可使得具有斜率的扫描波形的切角受面板不同位置由于面板本身的电阻电容造成的RC延迟的影响最接近，面板的均齐度好，达到更佳画面显示效果。
在一实施例中，所述第一栅启动信号的切角的斜率大于所述第二栅启动信号的切角的斜率。
显示面板中，对于大尺寸面板采用的是双驱动，栅启动信号从两侧进入，由于有信号延迟(RC delay)的存在，两侧进入端的充电效果比中间段的充电效果好，因而两侧进入端充电的亮度较高，中间段的亮度较暗，因此存在两侧泛白的现象。本方案中，所以把gate进行切角，由于切角的存在，使得两侧进入端的充电效果变得稍微差点，让中间跟两侧端的亮度差异缩小，从而减弱了显示面板两侧泛白的影响。所述的第一栅启动信号的切角的斜率大于所述第二栅启动信号的切角斜率，是实现本效果可选的方案之一。
在一实施例中，每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；所述第一切角前区间的电压大于第二切角前区间的电压；所述第一切角区间的最低电压等于第二切角区间的电压。其中，开始切角的时间点基本相当，当切角完成时，电压相当，所以，该第一切角区间的斜率大于第二切角区间的斜率。所述奇数列子像素的切角前的第一栅启动信号的电压大于所述偶数列子像素的切角前的第二栅启动信号的电压，所述奇数列子像素的切角后的第一栅启动信号的电压等于所述偶数列子像素的切角后的第二栅启动信号的电压。
本方案中，切角前，所述奇数列子像素的第一栅启动信号的电压大于所述偶数列子像素的第二栅启动信号的电压，而切角后，奇数列子像素的第一栅启动信号的电压等于偶数列子 像素的第二栅启动信号的电压，从而奇数列子像素的打开电压VGH和关闭电压VGL的差值的绝对值大于偶数列的打开电压VGH和关闭电压VGL的差值的绝对值，而是因为闪烁(Flicker)大小跟(VGH-VGL)绝对值的大小相关，所以降低VGH电压可以减小Flicker，这样可以提升制程上面的Margin，提高均一性。
作为本申请的另一实施例，参考图6至图11所示，公开了一种显示面板101，包括：基板104；所述基板104上设置有：多条数据线120、多条栅极线110、多个像素单元130和栅极驱动芯片102；所述像素单元130包括沿着栅极线110方向分别设置的不同颜色的子像素；所述栅极驱动芯片102输出栅启动信号到所述栅极线110以打开所述像素单元130；每一行所述像素单元包括多个像素组，每个所述像素组包括相邻的在前的第一列子像素131和在后的第二列子像素132，所述第一列子像素131和第二列子像素132与同一数据线120连接，且所述第一列子像素131和第二列子像素132连接至两条不同的栅极线110；每一行所述像素单元中的每个像素组和相邻的像素组采用的数据驱动信号的极性相反；所述第一列子像素131和第二列子像素132对应的数据驱动电压极性相反，所述第一列子像素131为奇数列子像素，所述第二列子像素132为偶数列子像素；对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压；所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特；所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形；每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；所述第一切角前区间的电压大于第二切角前区间的电压；所述第一切角区间的最低电压等于第二切角区间的电压。
半源驱动架构中，当相邻偶数列子像素的栅极电压等于奇数列子像素的栅极信号时，由于数据线120正负极性转换导致两者实际的充电时间有差异，最后导致像素的充电电压差异，从而出现垂直亮暗线。本方案中，通过让第一列子像素131对应的栅启动信号电压大于第二列子像素132对应的栅启动信号电压，通过增强对应第一列子像素131的栅启动信号的电压来使得对应的栅极可以更快的导通，使得第一列子像素131可以更快达到较原来更高的充电电压，减少甚至消除极性反转前后两个像素对应的充电电压的差异，使得两个相邻的像素的充电电压趋于相同，从而解决视觉上的垂直亮暗线现象；另外，本方案不用更改设计，只需隔行输出电压不同的栅启动信号即可，操作方便。
作为本申请的另一实施例，参考图12所示，公开了一种显示面板的驱动方法，包括步骤：
S121：栅极驱动芯片按照控制信号输出栅启动信号到每一行像素单元；
S122：数据驱动芯片输出同一数据信号给每一行像素的第一列子像素和第二列子像素；
S123：控制每一行像素单元中的每个像素组和相邻的像素组采用极性相反的数据驱动信号；
S124：栅极驱动芯片控制对应第一列子像素的栅启动信号电压大于对应第二列子像素的栅启动信号电压。
其中，显示面板的驱动方法适用上述的显示面板的结构。当相邻偶数列子像素的栅极电压等于奇数列子像素的栅极信号时，由于数据线120正负极性转换导致两者实际的充电时间有差异，最后导致像素的充电电压差异，从而出现垂直亮暗线的现象。本方案中，通过让第一列子像素131对应的栅启动信号电压大于第二列子像素132对应的栅启动信号电压，通过增强对应第一列子像素131的栅启动信号的电压来使得对应的栅极可以更快的导通，使得第一列子像素131可以更快达到预定的充电电压，减少甚至消除极性反转前后的充电差异，使得两个相邻的像素充电电压相同，从而解决视觉上的垂直亮暗线的现象；另外，本方案不用更改设计，只需隔行输出电压不同的栅启动信号即可，操作方便。
在一实施例中，所述第一列子像素131和第二列子像素132对应的数据驱动电压极性相反，所述第一列子像素131为奇数列子像素，所述第二列子像素132为偶数列子像素；对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
由于数据线120正负极性转换时，极性反转之后的奇数列子像素的数据驱动电压要一定时间才达到预设的电压强度，导致当奇数列子像素和偶数列子像素在同样的栅启动信号启动下，两者的导通时间一样，而使得两像素最终的充电状态有差异，造成亮暗线现象；而本方案采用一高一低两个栅启动信号，该较高的栅启动信号对应驱动奇数列子像素，使得奇数列子像素的薄膜晶体管更快导通，使得该奇数列子像素的实际充电时间略微长于偶数列子像素的充电时间，以减少两者的充电状态差异，减轻亮暗线的现象；另外，相对于原来的栅启动信号，若是该奇数列子像素的栅启动信号调高一些，而偶数列子像素的栅启动信号调低一些的话，可以调整使得最终两者的充电状态一致，以避免亮暗线的现象发生。
在一实施例中，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。
在一实施例中，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形；每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；所述第一切角前区间的电压大于第二切角前区间的电压；所述第一切角区间的最低电压等于第二切角区间的电压。
本方案中，切角前，所述奇数列子像素的第一栅启动信号的电压大于所述偶数列子像素的第二栅启动信号的电压，而切角后，奇数列子像素的第一栅启动信号的电压等于偶数列子像素的第二栅启动信号的电压，从而奇数列子像素的打开电压VGH和关闭电压VGL的差 值的绝对值大于偶数列的打开电压VGH和关闭电压VGL的差值的绝对值，而是因为闪烁(Flicker)大小跟(VGH-VGL)绝对值的大小相关，所以降低VGH电压可以减小Flicker，这样可以提升制程上的范围(Margin)，提高均一性。
作为本申请的另一实施例，参考图13所示，公开了一种显示装置100，包括如上所述的显示面板101。
半源驱动架构中，当相邻偶数列子像素的栅极电压等于奇数列子像素的栅极信号时，由于数据线120正负极性转换导致两者实际的充电时间有差异，最后导致像素的充电电压差异，从而出现垂直亮暗线的现象。本方案中，通过让第一列子像素131对应的栅启动信号电压大于第二列子像素132对应的栅启动信号电压，通过增强对应第一列子像素131的栅启动信号的电压来使得对应的栅极可以更快的导通，使得第一列子像素131可以更快达到较原来更高的充电电压，减少甚至消除极性反转前后两个像素对应的充电电压的差异，使得两个相邻的像素的充电电压趋于相同，从而解决视觉上的垂直亮暗线的现象；另外，本方案不用更改设计，只需隔行输出电压不同的栅启动信号即可，操作方便。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的可选的实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种显示面板，包括：
    基板；
    所述基板上设置有：
    多条数据线、多条栅极线及多个像素单元；
    栅极驱动芯片，输出栅启动信号到所述栅极线以打开所述像素单元；
    其中，所述像素单元包括沿着所述栅极线方向分别设置的不同颜色的子像素；
    每一行所述像素单元包括多个像素组，每个所述像素组包括相邻的在前的第一列子像素和在后的第二列子像素，所述第一列子像素和第二列子像素与同一数据线连接，且所述第一列子像素和第二列子像素连接至两条不同的栅极线；
    每一行所述像素单元中的每个像素组和相邻的像素组采用的数据驱动信号的极性相反；
    所述第一列子像素的栅启动信号电压大于第二列子像素对应的栅启动信号电压。
  2. 如权利要求1所述的一种显示面板，其中，所述第一列子像素和第二列子像素的充电电压相同。
  3. 如权利要求1所述的一种显示面板，其中，所述第一列子像素和第二列子像素对应的数据驱动电压极性相反，所述第一列子像素为奇数列子像素，所述第二列子像素为偶数列子像素；
    对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
  4. 如权利要求1所述的一种显示面板，其中，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。
  5. 如权利要求3所述的一种显示面板，其中，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形。
  6. 如权利要求5所述的一种显示面板，其中，所述第一栅启动信号的切角的斜率大于所述第二栅启动信号的切角的斜率。
  7. 如权利要求5所述的一种显示面板，其中，每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；
    每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；
    所述第一切角前区间的电压大于第二切角前区间的电压；
    所述第一切角区间的最低电压等于第二切角区间的电压。
  8. 如权利要求7所述的一种显示面板，其中，所述第一切角区间和第二切角区间的起始时间相同。
  9. 如权利要求5所述的一种显示面板，其中，所述第一切角区间的斜率大于第二切角区间的斜率。
  10. 如权利要求5所述的一种显示面板，其中，所述奇数列子像素的切角后的第一栅启动信号的电压等于所述偶数列子像素的切角后的第二栅启动信号的电压。
  11. 如权利要求1所述的一种显示面板，其中，所述显示面板采用半源极驱动架构。
  12. 如权利要求1所述的一种显示面板，其中，所述显示面板为双驱动模式。
  13. 一种显示面板的驱动方法，包括步骤：
    栅极驱动芯片按照控制信号输出栅启动信号到每一行像素单元；
    数据驱动芯片输出同一数据信号给每一行像素的第一列子像素和第二列子像素；
    控制每一行像素中的每个像素组和相邻的像素组采用极性相反的数据驱动信号；以及
    栅极驱动芯片控制对应第一列子像素的栅启动信号电压大于对应第二列子像素的栅启动信号电压。
  14. 如权利要求13所述的显示面板的驱动方法，其中，所述第一列子像素和第二列子像素对应的数据驱动电压极性相反，所述第一列子像素为奇数列子像素，所述第二列子像素为偶数列子像素；
    对应所述奇数列子像素的第一栅启动信号电压大于所述偶数列子像素的第二栅启动信号电压。
  15. 如权利要求13所述的显示面板的驱动方法，其中，所述第一列子像素和第二列子像素的充电电压相同。
  16. 如权利要求13所述的显示面板的驱动方法，其中，所述奇数列子像素对应的第一栅启动信号电压与偶数列子像素对应的第二栅启动信号电压之差为y，y的值大于0且小于或等于10伏特。
  17. 如权利要求14所述的显示面板的驱动方法，其中，所述第一栅启动信号电压和所述第二栅启动信号电压的波形均为带切角波形；
    每一周期所述第一栅启动信号包括第一切角前区间和第一切角区间；
    每一周期所述第二栅启动信号包括第二切角前区间和第二切角区间；
    所述第一切角前区间的电压大于第二切角前区间的电压；
    所述第一切角区间的最低电压等于第二切角区间的电压。
  18. 如权利要求17所述的显示面板的驱动方法，其中，所述第一切角区间的斜率大于第二切角区间的斜率。
  19. 一种显示装置，包括显示面板，所述显示面板包括：
    基板，所述基板上设置有：
    多条数据线、多条栅极线及多个像素单元；
    所述像素单元包括沿着所述栅极线方向分别设置的不同颜色的子像素；
    栅极驱动芯片，输出栅启动信号到所述栅极线以打开所述像素单元；
    每一行所述像素单元包括多个像素组，每个所述像素组包括相邻的在前的第一列子像素和在后的第二列子像素，所述第一列子像素和第二列子像素与同一数据线连接，且所述第一列子像素和第二列子像素连接至两条不同的栅极线；
    每一行所述像素单元中的每个像素组和相邻的像素组采用的数据驱动信号的极性相反；
    所述第一列子像素的栅启动信号电压大于第二列子像素对应的栅启动信号电压。
  20. 如权利要求19所述的一种显示装置，其中，所述显示装置为扭曲向列型显示装置、平面转换显示装置和多象限垂直配向显示装置中的一种。
PCT/CN2018/120834 2018-12-05 2018-12-13 显示面板及驱动方法和显示装置 Ceased WO2020113647A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/042,178 US11488555B2 (en) 2018-12-05 2018-12-13 Display panel, driving method thereof and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811480085.2 2018-12-05
CN201811480085.2A CN109410867B (zh) 2018-12-05 2018-12-05 一种显示面板及驱动方法和显示装置

Publications (1)

Publication Number Publication Date
WO2020113647A1 true WO2020113647A1 (zh) 2020-06-11

Family

ID=65457295

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/120834 Ceased WO2020113647A1 (zh) 2018-12-05 2018-12-13 显示面板及驱动方法和显示装置

Country Status (3)

Country Link
US (1) US11488555B2 (zh)
CN (1) CN109410867B (zh)
WO (1) WO2020113647A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110288959A (zh) * 2019-06-27 2019-09-27 北海惠科光电技术有限公司 一种显示面板、显示面板的驱动电路及其驱动方法
CN111369926B (zh) * 2020-03-18 2022-09-27 Tcl华星光电技术有限公司 显示面板的充电方法及装置
CN112731719A (zh) * 2020-12-31 2021-04-30 重庆惠科金渝光电科技有限公司 显示面板及其驱动方法、计算机存储介质
CN114170984B (zh) * 2021-11-30 2023-06-23 重庆惠科金渝光电科技有限公司 显示面板的驱动方法及显示面板
CN114242007B (zh) * 2021-12-10 2023-06-30 重庆惠科金渝光电科技有限公司 像素驱动方法以及显示设备
US12387669B2 (en) * 2022-12-16 2025-08-12 Apple Inc. Display panel brightness control based on gaussian edges
US20250336376A1 (en) * 2024-04-24 2025-10-30 Novatek Microelectronics Corp. Driving circuit, driving method adapted for driving a data line of a display panel and method of establishing at least one predetermined table thereof
CN119889204B (zh) * 2025-02-28 2025-10-03 惠科股份有限公司 显示面板、驱动方法及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075505A (en) * 1996-08-30 2000-06-13 Nec Corporation Active matrix liquid crystal display
CN101520998A (zh) * 2009-04-02 2009-09-02 友达光电股份有限公司 可改善画面闪烁的液晶显示器和相关驱动方法
CN102354486A (zh) * 2011-08-31 2012-02-15 华映光电股份有限公司 可补偿闸极电压的液晶显示器及其方法
CN102568398A (zh) * 2012-03-02 2012-07-11 福州华映视讯有限公司 亮度均匀的双闸极液晶显示器
US20130050171A1 (en) * 2011-08-22 2013-02-28 Ming-Han Tsai Liquid crystal display which can compensate gate voltages and method thereof
CN104317086A (zh) * 2014-11-14 2015-01-28 深圳市华星光电技术有限公司 一种用于驱动液晶显示面板的方法
CN107767832A (zh) * 2017-11-07 2018-03-06 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板和栅极驱动电路
CN108847194A (zh) * 2018-06-22 2018-11-20 惠科股份有限公司 显示装置和驱动方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060023395A (ko) * 2004-09-09 2006-03-14 삼성전자주식회사 액정 표시 장치 및 그 구동 방법
KR101235698B1 (ko) * 2006-03-20 2013-02-21 엘지디스플레이 주식회사 액정표시장치 및 이의 화상구현방법
KR101429905B1 (ko) * 2006-09-29 2014-08-14 엘지디스플레이 주식회사 액정표시장치
TWI336461B (en) * 2007-03-15 2011-01-21 Au Optronics Corp Liquid crystal display and pulse adjustment circuit thereof
KR101287477B1 (ko) * 2007-05-01 2013-07-19 엘지디스플레이 주식회사 액정표시장치
JP4890614B2 (ja) * 2007-06-12 2012-03-07 シャープ株式会社 液晶表示装置、液晶表示装置の駆動方法、およびテレビジョン受像機
CN101349820B (zh) * 2007-07-20 2012-01-11 胜华科技股份有限公司 数据驱动器及应用其的液晶显示器
TWI389071B (zh) * 2008-01-25 2013-03-11 友達光電股份有限公司 平面顯示裝置、控制電路及其控制方法
CN101533597B (zh) * 2009-04-02 2010-10-13 深圳华映显示科技有限公司 平面显示器的扫描线的驱动方法
KR101752834B1 (ko) * 2009-12-29 2017-07-03 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시장치
CN102237048B (zh) * 2010-04-22 2014-10-08 瀚宇彩晶股份有限公司 闸极波型产生方法及其电路
CN103399440A (zh) * 2013-08-08 2013-11-20 京东方科技集团股份有限公司 阵列基板、显示装置及驱动方法
CN104376818B (zh) * 2013-08-14 2017-07-11 联咏科技股份有限公司 液晶显示器及其栅极驱动器
CN103985365B (zh) * 2014-04-24 2016-08-24 京东方科技集团股份有限公司 液晶显示面板的极性反转驱动方法和装置
CN105702189B (zh) * 2014-11-26 2019-10-08 群创光电股份有限公司 扫描驱动电路及应用其的显示面板
CN104391411B (zh) * 2014-12-16 2017-06-06 深圳市华星光电技术有限公司 一种液晶显示面板
CN104882106B (zh) * 2015-06-02 2017-05-31 武汉华星光电技术有限公司 列翻转模式的液晶显示面板及其驱动方法
CN107644605B (zh) * 2016-07-22 2020-11-27 瀚宇彩晶股份有限公司 闸极驱动电路和显示装置
CN109410866B (zh) * 2018-12-05 2021-04-02 惠科股份有限公司 一种显示面板及驱动方法和显示装置
CN109307965B (zh) * 2018-12-05 2021-08-06 惠科股份有限公司 一种显示面板和显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075505A (en) * 1996-08-30 2000-06-13 Nec Corporation Active matrix liquid crystal display
CN101520998A (zh) * 2009-04-02 2009-09-02 友达光电股份有限公司 可改善画面闪烁的液晶显示器和相关驱动方法
US20130050171A1 (en) * 2011-08-22 2013-02-28 Ming-Han Tsai Liquid crystal display which can compensate gate voltages and method thereof
CN102354486A (zh) * 2011-08-31 2012-02-15 华映光电股份有限公司 可补偿闸极电压的液晶显示器及其方法
CN102568398A (zh) * 2012-03-02 2012-07-11 福州华映视讯有限公司 亮度均匀的双闸极液晶显示器
CN104317086A (zh) * 2014-11-14 2015-01-28 深圳市华星光电技术有限公司 一种用于驱动液晶显示面板的方法
CN107767832A (zh) * 2017-11-07 2018-03-06 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板和栅极驱动电路
CN108847194A (zh) * 2018-06-22 2018-11-20 惠科股份有限公司 显示装置和驱动方法

Also Published As

Publication number Publication date
US11488555B2 (en) 2022-11-01
CN109410867B (zh) 2020-10-16
CN109410867A (zh) 2019-03-01
US20210118382A1 (en) 2021-04-22

Similar Documents

Publication Publication Date Title
WO2020113647A1 (zh) 显示面板及驱动方法和显示装置
CN101960371B (zh) 有源矩阵基板、液晶面板、液晶显示装置、液晶显示单元、以及电视接收机
US10510308B2 (en) Display device with each column of sub-pixel units being driven by two data lines and driving method for display device
CN106249498B (zh) 一种像素结构及液晶显示面板
US8248336B2 (en) Liquid crystal display device and operating method thereof
US9230498B2 (en) Driving circuit and method of driving liquid crystal panel and liquid crystal display
US20180053478A1 (en) Liquid crystal display panel and driving method thereof
KR102000048B1 (ko) 액정 표시 장치 및 그 구동 방법
TWI393094B (zh) 液晶顯示裝置及其驅動方法
CN103454823B (zh) 一种阵列基板及液晶显示面板
CN109410866B (zh) 一种显示面板及驱动方法和显示装置
US10466518B2 (en) Driving methods and driving apparatuses for a display panel
US11250799B2 (en) Display panel and display device suitable for low color cast display
CN116364031A (zh) 像素驱动电路、驱动电路和驱动方法
WO2020113630A1 (zh) 显示面板和显示装置
US20210366428A1 (en) Display panel, display panel driving method, and display device
CN109658889B (zh) 一种驱动架构、显示面板及显示装置
US7898515B2 (en) Liquid crystal display
CN100595643C (zh) 液晶显示器件及其驱动方法
CN102621730A (zh) 液晶面板
WO2020098095A1 (zh) 显示面板、显示面板的驱动方法和显示装置
CN103295539B (zh) 液晶显示面板
US20170330522A1 (en) Thin film transistor-liquid crystal display device and its driving method
JP2010026324A (ja) 液晶表示パネル、液晶表示ユニット、液晶表示装置、テレビジョン受像機
CN203673178U (zh) 胆固醇液晶显示设备及其驱动电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18942352

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18942352

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 30.09.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18942352

Country of ref document: EP

Kind code of ref document: A1