WO2020105003A1 - System and method for providing and designing unlimited dynamic range analogue-to-digital conversion - Google Patents

Abstract

The present disclosure provides a system and method for providing unlimited dynamic range analogue-to-digital conversion. The system includes: a sample-and-hold circuit to sample input analogue signal to generate first set of samples; a modulo circuit configured to compute modulo operation on first set of samples against a reference level to generate set of modulo samples centered about zero; a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit configured to quantize the generated set of modulo samples to generate a set of output digital samples.

Description

SYSTEM AND METHOD FOR PROVIDING AND DESIGNING UNLIMITED DYNAMIC RANGE ANALOGUE-TO-DIGITAL CONVERSION

TECHNICAL FIELD

[1] The present disclosure relates generally to analogue-to-digital converter (ADC) architectures. In particular, the present disclosure relates to ADC architectures with an unlimited input dynamic range.

BACKGROUND

[2] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.

[3] An analogue-to-digital converter (ADC) converts an analogue signal, such as the sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC may also provide an isolated measurement such as the one obtained from an electronic device that converts an input analogue voltage or current to a digital number representing the amplitude/magnitude of the voltage or current. Typically, the digital output is a binary representation of the input. Analog-to-digital converters (ADCs) provide the link between continuous-time signals and their discrete-time counterparts, and the Shannon- Nyquist sampling theorem provides the mathematical foundation.

[4] Dynamic Range (DR) is a common performance metric for ADCs. Typically expressed in dB, the dynamic range is defined as the ratio between the largest and smallest values of the input that the ADC can reliably measure or resolve. For an ADC, the dynamic range is also related to the number of bits that are used to digitize the analogue signal. Considering an ideal N-bit ADC, the minimum value that can be detected is one least significant bit (LSB) and the maximum value is (2^W_1) times the LSB value.

[5] Dynamic range is important for various data acquisition applications including, but not limited to communication, geological and biomedical sensing applications, where the signal strengths vary dramatically. If the signal is too large, it drives an existing ADC into saturation, which causes clipping in the output to a level determined by the power rails. If the signal is too weak, it gets lost in the ADC’s quantization noise.

[6] Most of real-world signals have a variable amplitude range, whereas ADCs, by design, have a limited input dynamic range, which results in out-of-range signals getting clipped. A crucial parameter that limits the performance of an ADC is the mismatch between the signal dynamic range and the ADC dynamic range (DR). The dynamic range, expressed in dB, is the ratio of the largest signal amplitude to the smallest detectable signal amplitude that the ADC can accurately resolve. A weak signal might get lost in the quantization noise whereas a large signal would drive an ADC into saturation, which clips the signal to a level determined by the power rails. Clipping is a serious problem as it is nonlinear, noninvertible, and severely degrades the spectral content and quality of the digitized signal.

[7] Efforts have been made in the related art to improve performance metrics such as sampling rate, power dissipation, and resolution have been optimized extensively. But, the problem of clipping was not solved efficiently and accurately.

[8] There is, therefore, a requirement in the art for an ADC with an input dynamic range that is large enough to be able to accommodate a wide range of signal strengths and to alleviate the problem of clipping.

[9] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.

[10] In some embodiments, the numbers expressing quantities or dimensions of items, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term“about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding-off techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[11] As used in the description herein and throughout the claims that follow, the meaning of“a,”“an,” and“the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of“in” includes“in” and“on” unless the context clearly dictates otherwise.

[12] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g.“such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

[13] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.

OBJECTS OF THE INVENTION

[14] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.

[15] It is an object of the present invention to provide a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC) with reduced power consumption.

[16] It is another object of the present invention to develop an efficient system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC) with improvement in performance metrics such as area, power, and SQNR.

[17] It is another object of the present invention to provide a method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited dynamic range (UDR) in principle. [18] It is another object of the present invention to provide an unlimited dynamic range (UDR) analogue to digital converter with reduced number of quantization levels and number of bits used for encoding.

[19] It is another object of the present invention to provide a method for designing ADCs that do not clip the input signal or go into saturation.

[20] It is another object of the present invention to provide a generic hardware design in the sense that any standard ADC can be developed into a UDR ADC.

SUMMARY

[21] The present disclosure relates generally to analogue-to-digital converter (ADC) architectures. In particular, the present disclosure relates to ADC architectures with an unlimited input dynamic range.

[22] This summary is provided to introduce simplified concepts of a system for time bound availability check of an entity, which are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended for use in determining/limiting the scope of the claimed subject matter.

[23] An aspect of the present disclosure pertains to a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC). The system includes: a sample-and-hold circuit that can be configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal; a modulo circuit that can be operatively coupled to the sample-and-hold circuit and can be configured to compute modulo operation on the first set of samples against a reference (voltage) signal to generate a set of modulo samples centered about zero; a comparator that can be operatively coupled to the modulo circuit and can be configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit operatively coupled to the comparator such that the quantization unit can be configured to quantize the generated set of modulo samples to generate a set of output digital signals.

[24] In an aspect, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

[25] In an aspect, the modulo circuit can be configured to stop, when the first set of samples are within the predefined dynamic range, as there is no requirement to wrap and fold the first set of samples. The input analogue signal can be converted directly to the set of output digital signals.

[26] In an aspect, the system can include a retrieving unit. The retrieving unit can be configured to retrieve, using at least one of a predefined set of signal reconstruction techniques and a reset logic, a high dynamic range signal from the set of modulo samples.

[27] In an aspect, the reference voltage signal can be such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference voltage signal.

[28] Another aspect of the present disclosure pertains to a method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited or high dynamic range. The method includes steps of: sampling, using a sample-and-hold circuit, an input analogue signal to generate a first set of samples corresponding to the input analogue signal; computing, using a modulo circuit, modulo operation on the first set of samples against a reference voltage signal to generate a set of modulo samples centered about zero; determining, using a comparator, the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and quantizing, using a quantizing unit, the generated set of modulo samples to generate a set of output digital samples.

[29] In an aspect, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

[30] In an aspect, when the first set of samples are within the predefined dynamic range, the computation of the modulo operation is stopped.

[31] In an aspect, the method can include a step of retrieving, using at least one of a predefined set of signal reconstruction techniques and a reset logic, a high dynamic range signal from the set of modulo samples. [32] In an aspect, the reference voltage signal of the ADC can be such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference voltage signal.

[33] Another aspect of the present disclosure pertains to an unlimited dynamic range (UDR) analogue-to-digital converter (ADC). The UDR ADC includes: a sample-and- hold circuit configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal; a modulo circuit operatively coupled to the sample-and-hold circuit and configured to perform modulo operation on the first set of samples against a reference (voltage) signal to generate a set of modulo samples centered about zero; a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit operatively coupled to the comparator, and configured to quantize the generated set of modulo samples to generate a set of output digital signals.

[34] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS

[35] The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:

[36] FIG. 1 illustrates an exemplary block diagram representation of a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC), in accordance with an embodiment of the present disclosure.

[37] FIG. 2 illustrates an exemplary flow diagram representation of a method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited dynamic range, in accordance with an embodiment of the present disclosure.

[38] FIG. 3 illustrates an exemplary block diagram of unlimited dynamic range ADC (UDR- ADC), in accordance with an embodiment of the present disclosure. [39] FIG. 4 illustrates an exemplary plot for providing input-output characteristics of UDR-ADC and standard ADC, in accordance with an embodiment of the present disclosure.

[40] FIG. 5 A illustrates original samples x[n] and corresponding modulo samples [n], in accordance with an embodiment of the present disclosure.

[41] FIG. 5B illustrates reset information d[n], in accordance with an embodiment of the present disclosure.

[42] FIG. 5C illustrates discrete-time piecewise-constant signal obtained by a cumulative sum of d[n] and the reset instants {/_¾}, in accordance with an embodiment of the present disclosure.

[43] FIG. 6 illustrates an exemplary system-level block diagram of the UDR-ADC of FIG. 3 with details of modulo circuit, in accordance with an embodiment of the present disclosure.

[44] FIG. 7 illustrates an exemplary schematic representation of a successive approximation register (SAR) UDR-ADC, in accordance with an embodiment of the present disclosure.

[45] FIG. 8 illustrates CMOS circuit simulation results to show input analogue signal (a sum of sinusoids) and the modulo samples of the UDR-ADC. The bottom plot shows the signal reconstructed from the UDR- ADC measurements, in accordance with an embodiment of the present disclosure.

[46] FIGs. 9A-9F illustrate the CMOS circuit simulation results with a speech signal as an input with 9A-9C illustrate time domain signals, 9D-9F illustrate corresponding spectrograms, in accordance with an embodiment of the present disclosure.

[47] FIG. 10A-10C illustrate an exemplary hardware prototype of a 12-bit UDR- ADC demonstrating real-time implementation, where 10A illustrates block diagram, 10B illustrates circuit board, and IOC illustrates results pertaining to sum-of-sinusoids input, in accordance with an embodiment of the present disclosure.

[48] FIG. 11 illustrates an exemplary plot for comparison of area required for standard flash ADC and flash UDR-ADC for different folding factors as a function of number of bits, in accordance with an embodiment of the present disclosure.

[49] FIG. 12 illustrates an exemplary plot of providing a comparison of dynamic power dissipation in standard ADC versus UDR-ADC for different folding factors as a function of the voltage resolution, in accordance with an embodiment of the present disclosure.

[50] FIG. 13 illustrates a plot of SQNR versus loading factor g for various input distributions. The number of bits (n) used for quantization are color-coded and indicated at the extreme right of FIG. 13. The solid lines correspond to the standard ADC and the dashed lines correspond to the UDR-ADC. The shaded areas in the figure panels highlight the region in which the UDR-ADC outperforms the standard ADC, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

[51] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[52] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention can be practiced without some of these specific details.

[53] Embodiments of the present invention include various steps, which will be described below. The steps can be performed by hardware components or can be embodied in machine-executable instructions, which can be used to cause a general-purpose or special- purpose processor programmed with the instructions to perform the steps. Alternatively, steps can be performed by a combination of hardware, software, and firmware and/or by human operators.

[54] The present disclosure relates generally to analogue-to-digital converter (ADC) architectures. In particular, the present disclosure relates to ADC architectures with an unlimited input dynamic range.

[55] An aspect of the present disclosure pertains to a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC). The system includes: a sample-and-hold circuit that can be configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal; a modulo circuit that can be operatively coupled to the sample-and-hold circuit and can be configured to perform modulo operation on the first set of samples against a reference (voltage) signal to generate a set of modulo samples centered about zero; a comparator that can be operatively coupled to the modulo circuit and can be configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit operatively coupled to the comparator such that the quantization unit can be configured to quantize the generated set of modulo samples to generate a set of output digital samples.

[56] In an aspect, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

[57] In an aspect, the modulo circuit can be configured to stop, when the first set of samples are within the predefined dynamic range, as there is no requirement to wrap and fold the first set of samples. The input analogue signal can be converted directly to the set of output digital signals.

[58] In an aspect, the system can include a retrieving unit. The retrieving unit can be configured to retrieve, using at least one of a predefined set of signal reconstruction techniques and reset logic, a high dynamic range signal from the set of modulo samples.

[59] In an aspect, the reference voltage signal can be such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference voltage signal.

[60] Another aspect of the present disclosure pertains to a method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited or high dynamic range. The method includes steps of: sampling, using a sample-and-hold circuit, an input analogue signal to generate a first set of samples corresponding to the input analogue signal; computing, using a modulo circuit, modulo operation on the first set of samples against a reference voltage signal to generate a set of modulo samples centered about zero; determining, using a comparator, the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and quantizing, using a quantizing unit, the generated set of modulo samples to generate a set of output digital samples. [61] In an aspect, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

[62] In an aspect, when the first set of samples are within the predefined dynamic range, the computation of the modulo operation is stopped.

[63] In an aspect, the method can include a step of retrieving, using at least one of a predefined set of signal reconstruction techniques and a reset logic, and a high dynamic range signal from the set of modulo samples.

[64] In an aspect, the reference voltage signal of the ADC can be such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference voltage signal.

[65] Another aspect of the present disclosure pertains to an unlimited dynamic range (UDR) analogue-to-digital converter (ADC). The UDR ADC includes: a sample-and- hold circuit configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal; a modulo circuit operatively coupled to the sample-and-hold circuit and configured to perform modulo operation on the first set of samples against a reference (voltage) signal to generate a set of modulo samples centered about zero; a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit operatively coupled to the comparator, and configured to quantize the generated set of modulo samples to generate a set of output digital samples.

[66] FIG. 1 illustrates an exemplary block diagram representation of a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC), in accordance with an embodiment of the present disclosure.

[67] According to an embodiment, the system 100 can include one or more processor(s) 102. The one or more processor(s) 102 can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, logic circuitries, and/or any devices that manipulate data based on operational instructions. Among other capabilities, the one or more processor(s) 102 are configured to fetch and execute computer-readable instructions stored in a memory 104 of the system 100. The memory 104 can store one or more computer-readable instructions or routines, which can be fetched and executed to create or share the data units over a network service. The memory 104 can include any non-transitory storage device including, for example, volatile memory such as RAM, or non-volatile memory such as EPROM, flash memory, and the like.

[68] Various components/units of the proposed system 100 can be implemented as a combination of hardware and programming (for example, programmable instructions) to implement their one or more functionalities as elaborated further themselves or using processors 102. In examples described herein, such combinations of hardware and programming can be implemented in several different ways. For example, the programming for the units can be processor executable instructions stored on a non-transitory machine- readable storage medium and the hardware for units can include a processing resource (for example, one or more processors), to execute such instructions. In the present examples, the machine-readable storage medium can store instructions that, when executed by the processing resource, implements the various units. In such examples, the system 100 can include the machine -readable storage medium storing the instructions and the processing resource to execute the instructions, or the machine-readable storage medium can be separate but accessible to the system 100 and the processing resource. In other examples, the units can be implemented by electronic circuitry. A database can include data that is either stored or generated as a result of functionalities implemented by any of the other components /units of the proposed system 100.

[69] In an embodiment, the system 100 for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC) is disclosed. The system 100 can include: a sample-and-hold circuit 106 that is operatively coupled to the processors 102; a modulo circuit 108 operatively coupled to the sample-and-hold circuit 106; a comparator 110 that can be operatively coupled to the modulo circuit 108; and a quantization unit 112.

[70] In an embodiment, the sample-and-hold circuit 106 can be configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal.

[71] In an embodiment, the modulo circuit 108 can be configured to compute modulo operation on the first set of samples against a reference voltage signal to generate a set of modulo samples centered about zero.

[72] In an embodiment, the comparator 110 is configured to determine the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation.

[73] In an embodiment, the quantization unit 112 can be configured to quantize the generated set of modulo samples to generate a set of output digital signals.

[74] In an embodiment, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

[75] In an embodiment, the modulo circuit 108 can be configured to stop, when the first set of samples are within the predefined dynamic range, computation of the modulo operation.

[76] In an embodiment, the system 100 can include a retrieving unit that can be configured to retrieve, using at least one of a predefined set of signal reconstruction techniques and a reset logic, a high dynamic range signal from the set of modulo samples.

[77] In one embodiment, the reference voltage signal can be such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference voltage signal.

[78] FIG. 2 illustrates an exemplary flow diagram representation of a method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited dynamic range, in accordance with an embodiment of the present disclosure.

[79] According to an embodiment, the method 200 can include at a step 202, sampling, using a sample-and-hold circuit, an input analogue signal to generate a first set of samples corresponding to the input analogue signal.

[80] In an embodiment, the method 200 can include at a step 204, computing, using a modulo circuit, modulo operation on the first set of samples against a reference (voltage) signal to generate a set of modulo samples centered about zero.

[81] In an embodiment, the method 200 can include at a step 206, determining, using a comparator, the deviation of the first set of samples based on a comparison of the first set of samples with the reference signal, wherein when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation.

[82] In an embodiment, the method 200 can further include at a step 208, quantizing, using a quantizing unit, the generated set of modulo samples to generate a set of output digital samples. [83] FIG. 3 illustrates an exemplary block diagram of unlimited dynamic range ADC (UDR-ADC), in accordance with an embodiment of the present disclosure. Referring to FIG. 3, the proposed ADC 300 takes modulo measurements whenever the signal goes out of range. V_ref is the reference voltage against which the modulo is computed, both on the positive and negative voltage swings, and this process can be termed as modulo sampling. The input analogue signal x (t) is provided to s ample- and-hold circuit 302 to produce x ( nT ) as output. The sampled output x (nT) is provided as an input to modulo unit 304 to produce y (nT), wherein T being sampling interval.

y (nT) = My_ref {x (nT)}, (1)

where M_Vref (x (nT)} : = mod (x (nT) + V_ref , 2V_ref ) - V_ref (2)

Subtraction of V_ref in (2) ensures that the modulo sample/signal is centered about zero. The signal y (nT) is quantized to obtain the samples y[n]

Where Q denotes the quantization operator. Effectively, the modulo folds the signal back to the quantizer dynamic range.

[84] FIG. 4 illustrates an exemplary plot for providing input-output characteristics of UDR-ADC and standard ADC, in accordance with an embodiment of the present disclosure. It shows the input-output characteristics of the modulo sampler and illustrates the advantage of the UDR. A standard ADC results in clipping ( ys-ADciⁿ ]) whenever the input x (t) goes beyond its dynamic range, whereas a UDR-ADC folds it back (yuDR-ADc[ⁿ])_> thus preserving the input signal up to a modulo.

[85] The generic UDR-ADC architecture 300 is proposed that incorporates the self reset feature by means of a custom-designed modulo circuit. The achievable dynamic range in practice is limited not by the quantization block, but only by the voltage supply to the sample-and-hold and modulo circuits, which could be as high as allowed by the process technology.

[86] Referring to FIG. 3, as mentioned-above, the proposed UDR-ADC 300 includes three main blocks: sample-and-hold (S/H) circuit 302, modulo circuit 304 that wraps the input to the predefined range [-V_ref, +V_ref], and the quantization circuit 306. Blocks 302 and 306 are part of any standard ADC. A standard ADC can be converted into a UDR-ADC by plugging the modulo circuit 304 in between blocks 302 and 306.

[87] In an exemplary embodiment, a counter keeps track of reset information. However, it is not necessary to transmit counter bits. The counter encodes the reset information in only two bits assuming that the signal does not change by more than ± 2V_ref between two consecutive sampling instants. This assumption is reasonable and is directly related to the growth rate of the input signal and the sampling rate. This also significantly reduces the A/D conversion time since the counter can make use of the previous sample reset information. Further, circuit simulation results of the UDR ADC employing the quantization module of a successive approximation register (SAR)-ADC and a hardware prototype made of discrete components are also presented as a proof of concept.

SIGNAL MODEL FOR MODULO SAMPLING

[88] Let x[n] denote the samples of the input signal x (t) and let y[n ] denote the modulo measurements. The sequence x[n] can be expressed as the sum of y[n ] and a discrete-time piecewise constant signal z[n]:

x[n] = y[n] + z[n] (3)

Where z[n] is an integer multiple of 2V_ref and 1 _[ni,n2\ '^s the discrete-time indicator of the interval [ni, ¾]. The reset instants {¾} _ez ^arc ordered, i.e., %> i¾_i·

[89] FIG. 5A illustrates reconstruction of original signal from modulo measurements and reset information with original samples A[ P] and corresponding modulo samples [n], in accordance with an embodiment of the present disclosure.

[90] FIG. 5B illustrates reconstruction of original signal from modulo measurements and reset information with reset information d[n], in accordance with an embodiment of the present disclosure.

[91] FIG. 5C illustrates reconstruction of original signal from modulo measurements and reset information with discrete-time piecewise-constant signal obtained by a cumulative sum of d[n] and the reset instants {_¾}, in accordance with an embodiment of the present disclosure. The various sequences are related as x[n] = y[n] + z[n]. The sequences are in discrete-time domain, but their plots are shown in a continuous fashion to aid readability. The reset information is encoded in d[n], which is a series of impulses. The piecewise constant signal z[n] is obtained by accumulating d[n] as

z[n] = 2V_ref å_k=-_¥ d [k]

[92] In an embodiment, a robust reconstruction algorithm is developed using wavelets based on a certain regularity assumption on the ground-truth signal. These approaches, despite their robustness and accuracy of reconstruction, require a significantly oversampled input. The reconstruction algorithms are capable of estimating {¾} from y[n] alone provided that x(t) is sufficiently oversampled, i.e., the reset information is not encoded separately. On the contrary, in the proposed UDR-ADC architecture, the oversampling requirement is relaxed to a large extent as the reset information is separately encoded. At every sampling instant, the input is either within [-V_ref, +V_ref] or outside of it. Whenever it goes outside of [-V_ref, +V_ref], it could be doing so either with a positive slope or a negative slope. These three possibilities are encoded as no reset, positive reset, or a negative reset. With respect to FIG. 5B, the positive resets occur at ni; ns; 115 and hg, whereas the negative ones occur at ¾; ¾; and ¾. Every sample has two bits dedicated for encoding the reset information and the remaining n-2 bits are used for quantizing the amplitude. Although it might appear that more quantization noise is introduced in the process, it turns out that this scheme offers a clear advantage when the input signal swings outside the quantizer dynamic range.

[93] Since UDR-ADC performs a modulo operation on the input signal samples x ( nT ), T being the sampling period, there is an inherent non-uniqueness in the input-output mapping, i.e., the output samples given by y (nT) = M_v {x (nT) + m2V_ref } are the same for all m e Z⁺. In order to avoid this scenario, a sufficient condition on the sampling period T is arrived such that the measurements do not change by more than 2V_ref in a sampling interval. Let us assume that the input signal x(t) is Lipschitz-continuous, i.e., x(t) satisfies the property:

[94] I x(a) — x(b) \ <= a\b - a |, for some a e R⁺ and 0a, b e R; the parameter a is the Lipschitz constant. Effectively, this property places a restriction on the growth-rate of the signal. The sufficient condition is obtained by enforcing that

(5)

[95] Referring to FIG. 3, the modulo circuit 304 performs a modulo on the input Vi_n and results in the output V_mod = M_v { V_in }as per (2). With respect to FIGs. 5A, 5B & 5C

(collectively referred as FIG. 5), V_in = x[n], V_mod = y[n] The input and output of the modulo circuit are sampled analogue signals, i.e., real-valued signals defined in discrete-time.

[96] FIG. 6 illustrates an exemplary system-level block diagram of the UDR-ADC of FIG. 3 with details of modulo circuit, in accordance with an embodiment of the present disclosure.

[97] In UDR-ADC 600, the modulo is performed with respect to 2V_ref, which is either added to or subtracted from Vi_n, depending on the sign of Vi_n, and is performed by sub- block (a) in Fig. 6. An op-amp (sub-block (b)) compares the result V_m0d with the reference voltage V_ref to determine whether it is within the range [-V_ref, V_ref] or not. The logic to enable or disable addition or subtraction of 2V_ref to Vi_n is performed by sub-block (c). The modulo circuit 604 utilizes a counter and a feedback mechanism to perform these operations. The counter operates at a higher clock frequency (CLK_CNT) than the sample-and-hold circuit (CLK_SH) 602 and keeps track of the number of times 2V_ref has been added to or subtracted from Vi_n. To start with, the counter output CNT_OUT is set to zero and is enabled by making CNT_EN high. The signals SIGN_IN and SIGN_MOD represent the polarities of Vi_n and V_mod, respectively. For instance, if Vi_n is positive, SIGN_IN will be high, otherwise it will be low. As the counter output is unsigned, during feedback, CNT_OUT is multiplied with +/- 2V_ref based on SIGN_IN.

[98] In an embodiment, the input Vi_n obtained using a sample-and-hold circuit 602 is fed to the subtractor and its output (V_m0d) is compared with the reference voltage (V_ref) using an op-amp comparator. If \V_mod \ < \V_ref \, it indicates the end of modulo (EoM) operation, and EoM goes high keeping the counter output unchanged. On the other hand, if I V_mod I > I V_ref I , the EoM signal can be low and the CNT_OUT is either incremented or decremented based on the signs of V_m0d and Vi_n according to the truth table given in Table I. Table I: Truth table for the counter and reset logic. ACNT_OUT indicates the change in CNT_OUT and Dz denotes the change in z

[99] Based on the sampling rate consideration, CNT_OUT may change by ±1 or remain unchanged compared with its previous value. Thus, the modulo circuit takes a maximum of two cycles of CLK_CNT in order to generate the result V_m0d- After the modulo is completed, CNT_EN goes low, and QNT_EN goes high in order to activate the quantization block 606. The sample-and-hold circuit 602 can hold the input sample Vi_n for at least two cycles of the counter clock CLK_CNT and the delay I introduced by the quantization block 606, i.e.,T_CLK SH >= 2 * T_CLK CNT + A where G_{{ }} denotes the corresponding time period. The synchronization circuit ensures that the data transfer between sub-block (c) and the Reset logic block is synchronized.

[100] Two bits RiRo can be employed to encode the three reset possibilities (positive reset, negative reset, or no reset). For every input sample, at the end of the modulo operation, the CNT_OUT value is compared with that of the previous sample and encoded using RiRo- The ‘reset’ logic and the corresponding truth table are shown in FIG. 6 and Table I, respectively. The column Dz in the truth table denotes the change in the signal value that is fed to the subtractor circuit in sub-block (a) of FIG. 6 and corresponds to the change in z[n] (cf. FIG. 5C for z[n]).

[101] In an exemplary embodiment, Since the modulo circuit 604 is generic, the quantization blocks of flash, SAR, dual slope or any other ADCs type can be implemented.

[102] FIG. 7 illustrates an exemplary schematic representation of a successive approximation register (SAR) UDR-ADC, in accordance with an embodiment of the present disclosure. The SAR ADC employs binary search for discretizing an analogue signal. It utilizes a comparator that successively compares its input V_m0d (which is the output of the modulo circuit) with the output of a digital-to-analogue converter (DAC), thereby setting the registers appropriately and arriving at the corresponding quantization level. FIG. 7 shows a system level block diagram of the proposed SAR UDR-ADC. The SAR has N bits (DO; Dl; _

_ ; DN-1) for quantization and a sign bit (SIGN_MOD) to indicate the polarity of the input.

The proposed quantization circuit can deal with both positive and negative signal voltages. The operation of the quantizer based on the polarity of V_m0d can be further analyzed.

[103] Case: 1 V_m0d ^>= 0. In this case, SIGN_MOD goes high and a DAC converts the SAR value to its analogue counterpart VDAC, which is compared with V_m0d (cf. FIG. 7). The SAR bits are set/reset appropriately to arrive at a suitable digital representation of V_m0d and at the end of the digitization operation, the end-of-conversion (EoC) signal goes high. The operation in this case is similar to that of a conventional SAR ADC.

[104] Case: 2 V_m0d ^< 0. In this case, SIGN_MOD goes low and the reference voltage of the DAC is changed to -V_ref. Initially, the SAR is set to (100 _ 00) and the DAC output

VDAC is compared with V_m0d- If |V_m0d| > |VDAC|, the MSB of SAR is retained as 1, else it is set to 0. The conversion operation as in Case: 1 is repeated to get an equivalent N-bit representation of |V_m0d|- At the end of the operation, the EoC pulse goes high and the SAR output is inverted. To get the digital equivalent of V_m0d, inside the SAR block, XOR operation is performed on each of the SAR output bits with that of SIGN_MOD bit. [105] FIG. 8 illustrates CMOS circuit simulation results to show input analogue signal (a sum of sinusoids) and the modulo samples of the UDR-ADC, in accordance with an embodiment of the present disclosure. The plot of the modulo samples must be read with the help of the y-axis shown on the right-hand side, which corresponds to a 9-bit representation. The bottom plot shows the signal reconstructed from the UDR-ADC measurements.

[106] In an exemplary embodiment, SAR UDR-ADC can be implemented in Cadence design environment with 65 nm CMOS process technology. A double-buffered sample-and-hold circuit with CMOS switch is implemented. The subtractor and multiplier are implemented using op-amps, and a two-stage unity-gain Miller-compensated op-amp is realized. Digital circuits such as SAR, counter, and reset logic are modelled in Verilog. A total of 11 bits per sample are allocated for A/D conversion, out of which, 9 bits are used for quantization and 2 bits for encoding the reset information. An R-2R binary ladder is used as the DAC. Multiplication of CNT_OUT with ±2V_ref is achieved by multiplying ±V_ref with CNT_OUT value left-shifted by 1 bit. This eliminates the need for a separate voltage source operating at ±2V_ref. To illustrate the performance of the circuit, we first consider a sum of sinusoids consisting of frequencies 70; 30; 200; and 300 Hz. The maximum amplitude of the input is 1.2V and reference voltage of the UDR-ADC is set to 0.2V. The operating frequency of the sample-and-hold circuit is chosen as 53 kHz. FIG. 8 shows the input signal, the output samples of the UDR-ADC, and the reconstructed signal. The FIG. 8 shows that the proposed circuit is capable of successfully implementing the modulo operation. The reconstruction from the modulo measurements and the reset information is also accurate. The accuracy is quantified by comparing the reconstruction against the input signal sampled at 53 kHz and quantized using 32 bits per sample. The signal-to-reconstruction-error ratio was computed to be 75.24 dB, which indicates a high accuracy.

[107] FIGs. 9A-9F illustrate the CMOS circuit simulation results with a speech signal as an input with 9A-9C illustrate time domain signals, 9D-9F illustrate corresponding spectrograms, in accordance with an embodiment of the present disclosure. The illustrations employ a speech signal of bandwidth 4 kHz as the input. The reference voltage of the ADC is set to 0.2V, whereas the maximum voltage of the input signal is 1.2V. FIG. 9A-9C show the input speech signal, the modulo samples, and the reconstructed signal, respectively. The corresponding spectrograms are shown in FIG. 9D-9F. The signal-to-reconstruction-error ratio in this case turned out to be 63.36 dB.

[108] FIGs. 10A-10C illustrate an exemplary hardware prototype of a 12-bit UDR- ADC demonstrating real-time implementation with 10A illustrates block diagram, 10B illustrates circuit board, and IOC illustrates results pertaining to sum-of-sinusoids input, in accordance with an embodiment of the present disclosure.

[109] In an embodiment, the block diagram that forms the basis for our prototype is shown in FIG. 10A. Since MCP3008 can handle only positive-valued inputs, the prototype is designed to handle only such inputs. The SAR-ADC is interfaced with the rest of the circuit using an ATmega328P microcontroller by serial peripheral interface (SPI) protocol and is programmed to work at 200 kilo samples per second. The subtractor circuit is implemented using Texas Instrument’s standard LM741 op-amp and the offset voltages of the IC are adjusted by a trimming potentiometer provided in the IC. The circuit is built to accommodate up to three resets per sample (i.e., a folding factor of 3). To achieve the reset operation, a 4 X 2 analogue multiplexer IC 74HC4052 is employed (cf. Fig. 10A). A single power -rail IC LM358 is used as the comparator for the end of modulo (EoM) as well as for the polarity of V_mod (SIGN_MOD). Based on EoM and SIGN_MOD, the counter implemented in ATmega328P is either incremented or decremented appropriately. The control bits SO and SI for the multiplexer are provided depending on the counter output. The control bits also act as the reset bits. The prototype UDR-ADC is shown in FIG. 10B. For illustration, a signal having a mixture of sinusoids is given as the input to the prototype. FIG. IOC shows the input signal (measured by a digital storage oscilloscope), the corresponding modulo samples (output of the UDR-ADC), and the reconstructed signal (in MATLAB). The hardware implementation results reaffirm the inferences made from circuit simulations.

[110] In an exemplary embodiment, the performance of the UDR-ADC vis-a-vis a standard ADC is compared in terms of the area and power requirements, and signal-to- quantization-noise ratio (SQNR). The folding factor is denoted as A= V_max/V_ref, where V_max is the maximum amplitude of the input analogue signal and V_ref is the reference voltage of the UDR-ADC with respect to which the modulo happens. For instance, l= 4 indicates that the input signal amplitude is more than 4V_ref.

[111] In an embodiment, the area required by an ADC is measured in terms of the transistor count, which in turn depends on the number of bits used for digitization. Let ni be the number of bits employed in a UDR-ADC, corresponding to which the quantization step is given by

Let _¾ be the number of bits employed in a standard flash ADC corresponding to the same quantization step size, i.e.

[112] Considering V_max>= V_ref, the number of bits required by a flash ADC is given by n₂ = n₁ + \log_z ], (8) which is log 2 ] bits more than that of a UDR-ADC for the same quantization step-size.

[113] FIG. 11 illustrates an exemplary plot for comparison of area required for standard flash ADC and flash UDR-ADC for different folding factors as a function of number of bits, in accordance with an embodiment of the present disclosure.

[114] In a standard flash ADC, the area increases exponentially, with the number of bits as it requires 2^{n2 _1} comparators and 2ⁿ² resistors. On the other hand, a UDR-ADC requires a smaller number of bits ni, which in turn reduces the number of comparators and resistors required. Also, with an increase in the folding factor , the area required by the UDR- ADC further reduces as shown in FIG. 11 for various folding factors. As A increases, the area utilized by the additional circuitry required to perform the modulo operation also increases, but the increase is small compared to the total area.

[115] Since the sample-and-hold circuit is common to both ADCs, the comparison is restricted to the quantization block. The dynamic power dissipation P_d^s_TD) in an ADC is proportional to the supply voltage V_s(STD) ^and the operating clock frequency ^as given by

^Pd (STD ) ^K Vs(STD)fclk (STD )

[116] For a given quantization step-size, the reference voltage of a UDR-ADC (V_ref) could be made lower than the threshold of the standard ADC. Hence, the voltage supply V_S(UDR) to the quantization block of a UDR-ADC could also be made lower than that of the standard ADC by the folding factor A, i.e.,

Consequently, the overall dynamic power dissipation in the quantizer of a UDR-ADC is

2

which is A times lesser than that of standard ADC. The price to pay for the reduced power of the quantizer is the power dissipation in the modulo circuit in a UDR-ADC. [117] FIG. 12 illustrates an exemplary plot of providing a comparison of dynamic power dissipation in standard ADC versus UDR-ADC for different folding factors as a function of voltage resolution, in accordance with an embodiment of the present disclosure.

[118] FIG. 12 shows plots of the dynamic power dissipated for a unit capacitance. The dynamic power dissipation of the standard ADC is higher than that of UDR-ADC for a given quantization step-size. As the folding factor increases, the dynamic power dissipation of the UDR-ADC decreases. The static power dissipation is directly proportional to the transistor count. Since the area required in a UDR-ADC is smaller than that of the standard ADC, the static power dissipation is lower in a UDR-ADC.

[119] FIG. 13 illustrates a plot of SQNR versus loading factor g for various input distributions, different folding factors as function of number of bits, in accordance with an embodiment of the present disclosure. Signal-to-quantization-noise ratio is an important parameter used to evaluate the performance of an ADC.

SQNR = Signal variance/ (Quantization noise variance + Overload distortion)

[120] The quantization noise is a function of the threshold of the ADC and the number of bits used for digitization. A standard ADC introduces quantization noise and also overload distortion when the input signal amplitude exceeds V_ref, whereas the UDR-ADC introduces only quantization noise. Then, the UDR-ADC requires two bits for encoding the reset information. Hence, the SQNRs are not the same and depend on the parameters V_ref, V_max, n, and the distribution of the input signal amplitudes. In this work, we consider three types of input distributions: uniform, Gaussian, and Laplacian, and confine the analysis to the uniform quantization scheme.

[121] SQNR_UDR-ADC = 3(2²ⁿ)/(16y²)

[122] FIG. 13 depicts SQNR trends versus the loading factor for various distributions. The loading factor is a measure of how much in excess of V_ref the input signal swings, and is defined as g =

s_c where s_c is the standard deviation of the input distribution under consideration.

[123] In Uniform distribution, let the dynamic range of the input signal be limited to [-V_max, V_max], which corresponds to a standard deviation of V_max/ 3. Whenever the loading factor YU> 3, there is no overload distortion as the dynamic range of the signal is well within the saturation threshold of the standard ADC. Hence, the SQNR depends only on the quantization noise variance. Since n and n - 2 bits are used for quantization in the standard and UDR-ADCs, respectively, the quantization noise is less in the case of the former. Consequently, the SQNR is higher for the standard ADC whenever yu>V3.

[124] Next, consider the case where gu^<= V3, i.e., there is both quantization noise and overload distortion in a standard ADC. The UDR-ADC does not suffer from overload distortion by design and is expected to have a higher SQNR. However, since the number of bits available for quantization is two less than that of a standard ADC, there is a transition region in which the quantization noise of UDR-ADC is more than the quantization noise and the overload distortion put together of a standard ADC. Beyond this region, the UDR-ADC offers dramatic SQNR gains over the standard ADC. The crossover point is a function of the number of bits. The regions beyond the crossover where the UDR-ADC can be gainfully deployed are highlighted in FIG. 13.

[125] In Gaussian and Laplacian distributions, the probability distribution of the input signal amplitudes is modelled as a Gaussian or a heavy-tailed distribution such as the Laplacian. For higher values of the loading factor, the overload distortion in the case of standard ADC is negligible and hence the SQNR of the standard ADC is better than that of UDR-ADC. On the contrary, for large input variance, or equivalently, a high input dynamic range, the SQNR of the standard ADC deteriorates and drops below that of the UDR-ADC. The SQNR curves for different values of n are shown in FIG. 13. Again, the shaded areas are the operating regions where the UDR-ADC offers a clear advantage over the standard ADC. One can also observe that, for a given loading factor, the SQNR gain of UDR-ADC over a standard ADC is more for the Laplacian distribution than the Gaussian. This is expected because the Laplacian has a heavier tail than the Gaussian, which results in a higher probability of a larger dynamic range.

[126] Hence, UDR-ADC with the self-reset feature, which allows for an unlimited dynamic range at the input is proposed. The self-reset happens by means of a modulo sampler, and a pair of dedicated bits that encode the reset information. Given the modulo samples and the reset information, the reconstruction is straightforward. As an illustration, it has been shown, how a SAR-ADC could be converted to a UDR-ADC by introducing the modulo circuit between the sample-and-hold and the quantization blocks. The proposed architecture is simulated using 65 nm CMOS technology in Cadence design environment. Simulation results showed that the quality of signal reconstruction from the modulo measurements is highly accurate. A hardware prototype built using discrete components further supported the feasibility of a real-time realization. A performance assessment in terms of the area, power, and SQNR showed that the proposed UDR-ADC has definitive advantages over the standard ADCs thus making it an ideal candidate for applications requiring a high dynamic range, low area, and low power.

[127] In an embodiment, the UDR-ADC employs a modulo circuit whose input and output are sampled analogue signals, i.e., un-quantized signal amplitudes defined in discrete time. Hence, it was placed exactly in between the sample-and-hold and the quantization blocks. On the other hand, if one were to realize the modulo circuit in the continuous -time domain, it could simply precede an existing ADC thereby enabling ready conversion to a UDR-ADC.

[128] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention can be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION

[129] The present invention provides a system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC) with reduced power consumption.

[130] The present invention provides an efficient system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC) with improvement in performance metrics such as area, power, and SQNR.

[131] The present invention provides a method for designing a self-reset analogue- to-digital converter (ADC) with an unlimited dynamic range (UDR) in principle.

[132] The present invention provides an unlimited dynamic range (UDR) analogue to digital converter with reduced number of quantization levels and number of bits used for encoding.

[133] The present invention provides a method for designing ADCs that do not clip the input signal or go into saturation. [134] The present invention provides a generic hardware design in the sense that any standard ADC can be developed into a UDR ADC.

Claims

We Claim:

1. A system for providing unlimited dynamic range (UDR) analogue-to-digital conversion (ADC), the system comprising:

a sample-and-hold circuit configured to sample an input analogue signal to generate the first set of samples corresponding to the input analogue signal;

a modulo circuit operatively coupled to the sample-and-hold circuit and configured to perform modulo operation on the first set of samples against a reference signal to generate a set of modulo samples centered about zero;

a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on the comparison of the first set of samples with the reference signal,

where in, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and

a quantization unit operatively coupled to the comparator and configured to quantize the generated set of modulo samples to generate a set of output digital samples.

2. The system as claimed in claim 1, wherein the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

3. The system as claimed in claim 1, wherein the modulo circuit is configured to stop computation of the modulo operation when the first set of samples are within the predefined dynamic range.

4. The system as claimed in claiml, wherein the system comprises a retrieving unit configured to retrieve, using at least one of a predefined set of signal reconstruction techniques and a reset logic, a high dynamic range signal from the set of modulo samples.

5. The system as claimed in claiml, wherein the reference signal is such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference signal.

6. A method for designing a self-reset analogue-to-digital converter (ADC) with an unlimited dynamic range, the method comprising the following:

sampling, using a sample-and-hold circuit, an input analogue signal to generate a first set of samples corresponding to the input analogue signal; computing, using a modulo circuit, modulo operation on the first set of samples against a reference signal to generate a set of modulo samples centered about zero;

determining, using a comparator, the deviation of the first set of samples based on the comparison of the first set of samples with the reference signal, wherein when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and

quantizing, using a quantizing unit, the generated set of modulo samples to generate a set of output digital samples.

7. The method as claimed in claim6, wherein the first set of samples are reset and wrapped to generate reset information pertaining to the deviation by either adding or subtracting two times of the reference signal to the first set of samples, when the first set of samples are deviated from the predefined dynamic range.

8. The method as claimed in claim6, wherein when the first set of samples are within the predefined dynamic range, the computation of the modulo operation is stopped.

9. The method as claimed in claim6, wherein the method comprising a step of retrieving, using at least one of a predefined set of signal reconstruction techniques and a reset logic, a high dynamic range signal from the set of modulo samples.

10. The method as claimed in claim6, wherein the reference signal of the ADC is such that the modulo operation is performed on any or a combination of a positive voltage swing and a negative voltage swing of the reference signal.

11. An unlimited dynamic range (UDR) analogue-to-digital converter, the UDR ADC comprising

a sample-and-hold circuit configured to sample an input analogue signal to generate a first set of samples corresponding to the input analogue signal;

a modulo circuit operatively coupled to the sample-and-hold circuit and configured to compute the modulo operation on the first set of samples against a reference signal to generate a set of modulo samples centered about zero;

a comparator operatively coupled to the modulo circuit and configured to determine the deviation of the first set of samples based on the comparison of the first set of samples with the reference signal;

wherein, when the deviation exceeds a predefined dynamic range, the first set of samples are reset and wrapped to generate reset information pertaining to the deviation; and a quantization unit operatively coupled to the comparator and configured to quantize the generated set of modulo samples to generate a set of output digital samples.