WO2020103229A1 - 显示装置以及驱动方法和显示系统 - Google Patents

显示装置以及驱动方法和显示系统

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Publication number
WO2020103229A1
WO2020103229A1 PCT/CN2018/120789 CN2018120789W WO2020103229A1 WO 2020103229 A1 WO2020103229 A1 WO 2020103229A1 CN 2018120789 W CN2018120789 W CN 2018120789W WO 2020103229 A1 WO2020103229 A1 WO 2020103229A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
display
delay circuit
capacitor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/120789
Other languages
English (en)
French (fr)
Inventor
黄笑宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US17/042,892 priority Critical patent/US11308911B2/en
Publication of WO2020103229A1 publication Critical patent/WO2020103229A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display

Definitions

  • the present application relates to the field of display technology, and in particular, to a display device, a driving method, and a display system.
  • Flat panel displays include thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal (TFT-LCD) and organic light-emitting diode (Organic Light-Emitting Diode, OLED) displays, etc.
  • TFT-LCD Thi Film Transistor-Liquid Crystal
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display controls the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture, which has many advantages such as thin body, power saving, no radiation and so on.
  • the organic light emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • Thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal, TFT-LCD), as one of the main varieties of flat panel displays, has become an important display platform in modern IT and video products.
  • TFT-LCD driver In the design of the TFT-LCD driver known to the applicant, it may happen that the gate driver chip has been working normally when the power is turned on, and the source driver chip is still not working normally, which may cause abnormal images.
  • the present application provides a display device, a driving method, and a display system to ensure that the driving chip works normally at the same time when it is turned on.
  • the present application provides a circuit board, including: a display panel including a scan line and a data line; a source driving chip configured to output a source driving signal of the display panel, configured as A gate drive chip that outputs the gate drive signal of the display panel; a signal delay circuit, the gate drive signal is output to the scan line through the signal delay circuit, and the source drive signal is directly output to the data line .
  • the signal delay circuit includes a D flip-flop, a resistor, a power supply, a ground wire, a capacitor, and an active switch, the D flip-flop C terminal is connected to the resistor, and the other end of the resistor is connected to the gate
  • the output end of the driving chip is connected, the D end of the D flip-flop is connected to the power supply; one end of the capacitor is connected to the ground line, the other end of the capacitor is connected to the control end of the active switch, and the D trigger
  • the Q terminal of the device is connected, and the signal delay circuit further includes a signal input terminal and a signal output terminal; the output terminal of the gate drive chip is connected to the scanning line through an active switch.
  • the active switch is a thin film transistor, a gate of the thin film transistor is connected to the capacitor, a source is connected to the output end of the gate driving chip, and a drain is connected to the scan line.
  • the charging time of the capacitor is greater than the display time of one frame of the display panel.
  • the charging time of the capacitor is equal to the display time of one frame of the display panel.
  • one scan line corresponds to one signal delay circuit.
  • each signal delay circuit there are at least two signal delay circuits, and the delay time of each signal delay circuit is equal.
  • the signal delay circuit is integrated into the gate driving chip.
  • the display panel includes a display area and a non-display area, the non-display area surrounds the display area, the gate driving chip is connected to the first side of the non-display area, and the source electrode The driving chip is connected to the second side of the non-display area.
  • the present application also discloses a driving method of a display device.
  • the steps of the driving method include:
  • the gate drive signal is output to the scanning line through the signal delay circuit
  • the source driving signal is directly output to the data line.
  • the delayed output time of the gate drive chip signal is controlled to be greater than the display time of one frame.
  • the delayed output time of the gate drive chip signal is equal to the display time of one frame.
  • the present application also discloses a display system including a display device.
  • the display device includes a display panel including a scan line and a data line; a source driver chip that outputs a source drive signal of the display panel;
  • the gate drive chip outputs the gate drive signal of the display panel; the signal delay circuit, the gate drive signal is output to the scan line through the signal delay circuit; the source drive signal is directly output to the data line ;
  • a backlight module set to provide a light source for the display device.
  • the signal delay circuit includes a D flip-flop, a resistor, a power supply, a ground wire, a capacitor, and an active switch, the D flip-flop C terminal is connected to the resistor, and the other end of the resistor is connected to the gate
  • the output end of the driving chip is connected, the D end of the D flip-flop is connected to the power supply; one end of the capacitor is connected to the ground line, the other end of the capacitor is connected to the control end of the active switch, and the D trigger
  • the Q terminal of the device is connected, and the signal delay circuit further includes a signal input terminal and a signal output terminal; the output terminal of the gate drive chip is connected to the scanning line through an active switch.
  • the charging time of the capacitor is greater than or equal to the display time of one frame of the display panel.
  • each scanning line corresponds to one of the signal delay circuits.
  • the signal delay circuit is integrated into the gate driving chip.
  • the display panel includes a display area and a non-display area, the non-display area surrounds the display area, the gate driving chip is connected to the first side of the non-display area, and the source electrode The driving chip is connected to the second side of the non-display area.
  • this application adds a signal delay circuit to the gate drive chip to delay the transmission of the gate drive signal by one frame of display time, giving the source drive chip more time to build the internal Potential, to avoid the abnormal picture caused by the internal potential of the source driver chip is not fully established when starting up.
  • FIG. 1 is a schematic diagram of a display device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a signal delay circuit of a display device according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a driving method of a display device according to another embodiment of the present application.
  • FIG. 4 is a schematic diagram of a display system according to another embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more features.
  • the meaning of “plurality” is two or more.
  • the term “comprising” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • an embodiment of the present application discloses a circuit board, including: a display panel 100 including a scan line and a data line; a source drive configured to output a source drive signal of the display panel 100 Chip 200, a gate drive chip 300 configured to output the gate drive signal of the display panel 100; a signal delay circuit 400, the gate drive signal is output to the scan line through the signal delay circuit 400, and the source drive signal is directly output to the data line .
  • a design known to the applicant may cause a screen abnormality during startup, that is, the gate driver chip 300 has started to work normally and the source driver chip 200 has not yet worked normally. Since the normal working time of the gate driving chip 300 and the source driving chip 200 is the time after the system is powered on, the signal of the source driving chip 200 cannot be advanced.
  • a signal delay circuit 400 is added to the gate drive chip 300, so that the gate drive signal transmits a signal to the scanning line through the signal delay circuit 400, and the gate drive signal is delayed. In this way, the gate driving signal and the source driving signal arrive at the display panel 100 at the same time, which avoids the abnormality of the screen when starting up.
  • the signal delay circuit includes a D flip-flop 410, a resistor R, a power supply VDD, a ground line GND, a capacitor C, and an active switch M.
  • the C terminal of the D flip-flop 410 is connected to the resistor R, and the other end of the resistor R is connected to
  • the output terminal of the gate driving chip 300 is connected, the D terminal of the D flip-flop 410 is connected to the power supply VDD; one end of the capacitor C is connected to the ground line GND, the other end of the capacitor C is connected to the control terminal of the active switch M, and the Q of the D flip-flop 410
  • the signal delay circuit further includes a signal input terminal and a signal output terminal; the output terminal of the gate driving chip 300 is connected to the scanning line through an active switch.
  • the power supply VDD is at a logic high level and set to H
  • the ground line GND is at a logic low level and set to L.
  • the D flip-flop 410 When the C terminal of the D flip-flop 410 receives the rising edge of the signal input terminal, the D flip-flop 410 assigns the high level of the D terminal to Q, at which time the capacitor C starts to charge. When the capacitor C is charged to a high level, the active switch M is turned on. The charging time of the capacitor C is the delay time of the signal delay circuit 400.
  • the active switch M is a thin film transistor
  • the gate of the thin film transistor is connected to the capacitor C
  • the source is connected to the output end of the gate driving chip 300
  • the drain is connected to the scan line.
  • the thin film transistor is used to control the active switch M, wherein the gate of the thin film transistor is connected to the capacitor, and the source is connected to the output end of the gate driving chip 300 to control the gate driving signal.
  • the charging time of the capacitor C is greater than or equal to the display time of the display panel 100 for one frame.
  • the charging time of the capacitor C is greater than or equal to the display time of one frame of the display panel 100, the gate drive chip 300 does not output when scanning to the corresponding row for the first time, the capacitor C is charged, and the gate drive chip 300 is charged for the second time During scanning, the MOS tube is turned on, and the gate driving chip 300 outputs normally.
  • the charging time of the capacitor C is greater than or equal to the display time of one frame, to avoid charging the capacitor C too fast during the first scan of the gate driving chip 300, which causes the MOS tube to be turned on in advance.
  • one scan line corresponds to one signal delay circuit 400.
  • each signal delay circuit 400 has a corresponding scan line, and there is a one-to-one correspondence between the two, which can achieve precise control.
  • each signal delay circuit 400 delays for the same time.
  • the signal delay circuit 400 corresponds to each scan line, and the signal delay circuit 400 delay time is equal to ensure that the transmission time of the gate drive signal on each scan line is equal.
  • the signal delay circuit 400 is integrated into the gate driving chip 300.
  • the signal driving circuit 400 is connected to the gate driving chip 300 and the display panel 100, and the signal output terminal in the signal delay circuit 400 is the start signal actually input to the display panel 100, and is connected to the display panel 100 to delay the signal
  • the integration of the circuit 400 on the gate driving chip 300 can save space and improve space utilization.
  • the display panel 100 includes a display area 110 and a non-display area 120.
  • the non-display area 120 surrounds the display area 110.
  • the gate driving chip 300 is connected to the first side 121 of the non-display area 120.
  • the source electrode The driving chip 200 is connected to the second side 122 of the non-display area 120.
  • the gate driving chip 300 is connected to the first side 121 of the non-display area 120, and the second side 122 adjacent to the non-display area 120 is connected to the source driving chip 200.
  • the driving chip is connected to the non-display area 120, and the final signal is transmitted to the display area 110 through the non-display area 120.
  • a display device including:
  • the display panel 100 which includes a scan line and a data line; a source driving chip 200 configured to output a source driving signal of the display panel, and a gate driving chip 300 configured to output a gate driving signal of the display panel 100;
  • Signal delay circuit 400 the gate drive signal is output to the scanning line through the signal delay circuit 400; the source drive signal is directly output to the data line; the signal delay circuit 400 is integrated into the gate drive chip 300, and the signal delay circuit includes D Flip-flop 410, resistor R, power supply VDD, ground line GND, capacitor C and active switch M, the C terminal of D flip-flop 410 is connected to resistor R, the other end of resistor R is connected to the output terminal of gate drive chip 300, D trigger The D end of the device 410 is connected to the power supply VDD; one end of the capacitor C is connected to the ground line GND, the other end of the capacitor C is connected to the control end of the active switch M, and the Q end of the D flip-flop 410, the signal delay circuit further includes a signal input end 1. Signal output terminal; the output terminal of the gate driving chip 300 is connected to the scanning line through an active switch, and the charging time of the capacitor C is greater than or equal to the display time of the display panel 100 for one frame.
  • the gate driving signal and the source driving signal arrive at the display panel 100 at the same time, which avoids the abnormality of the screen when starting up.
  • the power supply VDD is set to H at a logic high level
  • the ground line GND is set to a logic low level to L.
  • the active switch M When the signal input terminal 420 outputs the gate-on signal for the first time, the active switch M is turned off, and the signal output terminal 420 is not output.
  • the C terminal of the D flip-flop 410 receives the rising edge of the signal input terminal 420, the D flip-flop 410 assigns the high level of the D terminal to Q, at which time the capacitor C starts to charge.
  • the active switch M When the capacitor C is charged to a high level, the active switch M is turned on.
  • the charging time of the capacitor C is the delay time of the signal delay circuit 400.
  • the charging time of the capacitor C is greater than or equal to the display time of one frame of the display panel 100. The first time the gate driving chip 300 scans to the corresponding row does not output, and charges the capacitor C.
  • the signal delay circuit 400 connects the gate driving chip 300 and the display panel 100, and the signal output terminal 420 in the signal delay circuit 400 is an opening signal actually input to the display panel 100, and is connected to the display panel 100 to connect the signal delay circuit 400 Integration on the gate driving chip 300 can save space and improve space utilization.
  • a driving method of a display device is disclosed, and the steps of the driving method include:
  • the delayed output time of the gate driver chip signal is greater than or equal to the display time of one frame.
  • the gate driver chip signal output delay time is controlled so that the output time is greater than or equal to the display time of one frame, to avoid the capacitor charging speed being too fast during the first gate drive chip scan, resulting in the first scan There is output, which affects the picture quality.
  • a display system 500 including a display device 600.
  • the display device 600 includes: a display panel 100, and the display panel 100 includes scan lines and data lines;
  • the source driving chip 200 configured to output the source driving signal of the display panel 100, the gate driving chip 300 configured to output the gate driving signal of the display panel 100;
  • the signal delay circuit 400, the gate driving signal passes through the signal delay circuit 400 Output to the scanning line, the source driving signal is directly output to the data line;
  • the backlight module 700 is configured to provide the display device 600 with a light source.
  • a design known by the applicant may cause a screen abnormality during booting, that is, the gate driving chip 300 has started to work normally and the source driving chip 200 has not yet worked normally. Since the normal working time of the gate driving chip 300 and the source driving chip 200 is the time after the system is powered on, the signal of the source driving chip 200 cannot be advanced.
  • a signal delay circuit 400 is added to the gate drive chip 300, so that the gate drive signal transmits a signal to the scanning line through the signal delay circuit 400, and the gate drive signal is delayed. In this way, the gate driving signal and the source driving signal arrive at the display panel 100 at the same time, which avoids the abnormality of the screen when starting up.
  • the signal delay circuit includes a D flip-flop 410, a resistor R, a power supply VDD, a ground line GND, a capacitor C, and an active switch M.
  • the C terminal of the D flip-flop 410 is connected to the resistor R, and the other end of the resistor R is connected to
  • the output terminal of the gate driving chip 300 is connected, the D terminal of the D flip-flop 410 is connected to the power supply VDD; one end of the capacitor C is connected to the ground line GND, the other end of the capacitor C is connected to the control terminal of the active switch M, and the Q of the D flip-flop 410
  • the signal delay circuit further includes a signal input terminal and a signal output terminal; the output terminal of the gate driving chip 300 is connected to the scanning line through an active switch.
  • the power supply VDD is at a logic high level and is set to H
  • the ground line GND is at a logic low level and is set to L.
  • the D flip-flop 410 When the C terminal of the D flip-flop 410 receives the rising edge of the signal input terminal, the D flip-flop 410 assigns the high level of the D terminal to Q, at which time the capacitor C starts to charge. When the capacitor C is charged to a high level, the active switch M is turned on. The charging time of the capacitor C is the delay time of the signal delay circuit 400.
  • the charging time of the capacitor C is greater than or equal to the display time of the display panel 100 for one frame.
  • the charging time of the capacitor C is greater than or equal to the display time of one frame of the display panel 100, the gate drive chip 300 does not output when scanning to the corresponding row for the first time, the capacitor C is charged, and the gate drive chip 300 is charged for the second time During scanning, the MOS tube is turned on, and the gate driving chip 300 outputs normally.
  • the charging time of the capacitor C is greater than or equal to the display time of one frame, to avoid charging the capacitor C too fast during the first scan of the gate driving chip 300, which causes the MOS tube to be turned on in advance.
  • each signal delay circuit 400 delays for the same time.
  • the signal delay circuit 400 corresponds to each scan line, and the signal delay circuit 400 delay time is equal to ensure that the transmission time of the gate drive signal on each scan line is equal.
  • the signal delay circuit 400 is integrated into the gate driving chip 300.
  • the signal driving circuit 400 is connected to the gate driving chip 300 and the display panel 100, and the signal output terminal in the signal delay circuit 400 is the start signal actually input to the display panel 100, and is connected to the display panel 100 to delay the signal
  • the integration of the circuit 400 on the gate driving chip 300 can save space and improve space utilization.
  • the display panel 100 includes a display area 110 and a non-display area 120, the non-display area 120 surrounds the display area 110, the gate driving chip 300 is connected to the first side 121 of the non-display area 120, and the source driving chip 200 is connected to the second side 122 of the non-display area 120.
  • the gate driving chip 300 is connected to the first side 121 of the non-display area 120, and the second side 122 adjacent to the non-display area 120 is connected to the source driving chip 200.
  • the driving chip is connected to the non-display area 120, and the final signal is transmitted to the display area 110 through the non-display area 120.
  • TN panel Transmission Nematic, twisted nematic panel
  • IPS panel In-PaneSwitcing, plane conversion
  • VA panel Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示装置（600）以及驱动方法和显示系统（500），显示装置（600）包括显示面板（100），显示面板（100）包括扫描线和数据线；被设置为输出显示面板（100）的源极驱动信号的源极驱动芯片（200）和被设置为输出显示面板（100）的栅极驱动信号的栅极驱动芯片（300）；信号延时电路（400），栅极驱动信号通过信号延时电路（400）输出至扫描线；源极驱动信号直接输出至数据线。

Description

显示装置以及驱动方法和显示系统
本申请要求于2018年11月21日提交中国专利局，申请号为CN201811389136.0，申请名称为“一种显示装置以及驱动方法和显示器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置以及驱动方法和显示系统。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。而有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)作为当前平板显示的主要品种之一，已经成为现代IT、视讯产品中的重要显示平台。申请人知晓的TFT-LCD驱动设计中，可能会发生开机时栅极驱动芯片已经正常工作，源极驱动芯片仍未正常工作的情况从而导致画面异常。
技术解决方案
本申请提供一种显示装置以及驱动方法和显示系统，保证开机时驱动芯片同时正常工作。
为实现上述目的，本申请提供了一种电路板，包括：显示面板，所述显示面板包括扫描线和数据线；设置为输出所述显示面板的源极驱动信号的源极驱动芯片，设置为输出所述显示面板的栅极驱动信号的栅极驱动芯片；信号延时电路，所述栅极驱动信号通 过所述信号延时电路输出至扫描线，所述源极驱动信号直接输出至数据线。
可选的，所述信号延时电路包括D触发器、电阻、电源、接地线、电容和主动开关，所述D触发器C端与所述电阻连接，所述电阻另一端与所述栅极驱动芯片的输出端连接，所述D触发器D端与所述电源连接；所述电容一端与所述接地线连接，所述电容另一端和所述主动开关的控制端，以及所述D触发器Q端连接，所述信号延时电路还包括信号输入端、信号输出端；所述栅极驱动芯片的输出端通过主动开关连接所述扫描线。
可选的，所述主动开关为薄膜晶体管，所述薄膜晶体管的栅极连接所述电容，源极连接所述栅极驱动芯片的输出端，漏极连接所述扫描线。
可选的，所述电容充电时间大于所述显示面板一帧的显示时间。
可选的，所述电容充电时间等于所述显示面板一帧的显示时间。
可选的，一条所述扫描线对应一个所述信号延时电路。
可选的，所述信号延时电路至少有两个，每一个所述信号延时电路延时的时间相等。
可选的，所述信号延时电路集成到所述栅极驱动芯片。
可选的，所述显示面板包括显示区和非显示区，所述非显示区包围所述显示区，所述栅极驱动芯片连接在所述非显示区的第一侧边，所述源极驱动芯片连接在所述非显示区的第二侧边。
本申请还公开了一种显示装置的驱动方法，所述驱动方法的步骤包括：
栅极驱动信号通过信号延时电路输出至扫描线；
源极驱动信号直接输出至数据线。
可选的，控制栅极驱动芯片信号延时输出时间大于一帧的显示时间。
可选的，控制栅极驱动芯片信号延时输出时间等于一帧的显示时间。
本申请还公开了一种显示系统，包括显示装置，所述显示装置包括：显示面板，所述显示面板包括扫描线和数据线；源极驱动芯片，输出所述显示面板的源极驱动信号；栅极驱动芯片，输出所述显示面板的栅极驱动信号；信号延时电路，所述栅极驱动信号通过所述信号延时电路输出至扫描线；所述源极驱动信号直接输出至数据线；以及背光模组，设置为给显示装置提供光源。
可选的，所述信号延时电路包括D触发器、电阻、电源、接地线、电容和主动开关，所述D触发器C端与所述电阻连接，所述电阻另一端与所述栅极驱动芯片的输出端连接，所述D触发器D端与所述电源连接；所述电容一端与所述接地线连接，所述电容另一端和所述主动开关的控制端，以及所述D触发器Q端连接，所述信号延时电路还包括信号输入端、信号输出端；所述栅极驱动芯片的输出端通过主动开关连接所述扫描线。
可选的，所述电容充电时间大于等于所述显示面板一帧的显示时间。
可选的，所述扫描线至少两条，每一条扫描线对应一个所述信号延时电路。
可选的，所述信号延时电路集成到所述栅极驱动芯片。
可选的，所述显示面板包括显示区和非显示区，所述非显示区包围所述显示区，所述栅极驱动芯片连接在所述非显示区的第一侧边，所述源极驱动芯片连接在所述非显示区的第二侧边。
相对于没有信号延时传输的方案来说，本申请通过在栅极驱动芯片增加信号延时电路，使栅极驱动信号传输延后一帧的显示时间，给源极驱动芯片更多时间建立内部电位，避免了开机时源极驱动芯片内部电位未完全建立导致的画面异常。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，进行例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示装置的示意图；
图2是本申请实施例一种显示装置的信号延时电路的示意图；
图3是本申请另一实施例一种显示装置驱动方法的流程示意图。
图4是本申请另一实施例一种显示系统的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是进行描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和可选的实施例对本申请作说明。
参考图1至图2所示，本申请实施例公开了一种电路板，包括：显示面板100，显示面板100包括扫描线和数据线；设置为输出显示面板100源极驱动信号的源极驱动芯片200，设置为输出显示面板100栅极驱动信号的栅极驱动芯片300；信号延时电路400，栅极驱动信号通过信号延时电路400输出至扫描线，源极驱动信号直接输出至数据线。
本方案中，作为当前平板显示的主要品种，薄膜晶体液晶显示器广泛的运用到现代IT、视讯产品中。申请人知晓的一种设计在开机过程中可能会发生画面异常，即栅极驱 动芯片300已经开始正常工作而源极驱动芯片还200未正常工作。由于栅极驱动芯片300和源极驱动芯片200正常工作时间都是在系统上电完成后的时间，源极驱动芯片200信号无法进行提前。在本设计中，在栅极驱动芯片300上增加信号延时电路400，使栅极驱动信号通过信号延时电路400传输信号至扫描线，将栅极驱动信号延时传输。这样栅极驱动信号和源极驱动信号同时到达显示面板100，避免了开机时出现画面异常。
在一实施例中，信号延时电路包括D触发器410、电阻R、电源VDD、接地线GND、电容C和主动开关M，D触发器410的C端与电阻R连接，电阻R另一端与栅极驱动芯片300的输出端连接，D触发器410的D端与电源VDD连接；电容C一端与接地线GND连接，电容C另一端和主动开关M的控制端，以及D触发器410的Q端连接，信号延时电路还包括信号输入端、信号输出端；栅极驱动芯片300的输出端通过主动开关连接扫描线。
本方案中，电源VDD为逻辑高电平设为H，接地线GND为逻辑低电平设为L，当栅极驱动芯片300控制信号为H时，主动开关M开启，当栅极驱动芯片300控制信号为L时，主动开关M关闭。电路中的电容C作用就是延缓主动开关M的开启时间。工作状态下，当系统上电时，栅极驱动芯片400正常工作，当信号输入端420初次输出栅极开启信号时，主动开关M关闭，信号输出端430没有输出。D触发器410的C端受到信号输入端上升沿时，D触发器410将D端的高电平赋值给Q，此时电容C开始充电。当电容C充电到高电平时，主动开关M开启。电容C的充电时间为信号延时电路400的延时时间。
在一实施例中，主动开关M为薄膜晶体管，薄膜晶体管的栅极连接电容C，源极连接栅极驱动芯片300的输出端，漏极连接所述扫描线。
本方案中，利用薄膜晶体管进行控制主动开关M，其中薄膜晶体管的栅极连接电容，源极连接栅极驱动芯片300的输出端，对栅极驱动信号进行控制。
在一实施例中，电容C充电时间大于等于显示面板100一帧的显示时间。
本方案中，电容C充电时间大于或等于显示面板100一帧的显示时间，第一次栅极驱动芯片300扫描到对应行时不输出，对电容C进行充电，第二次栅极驱动芯片300扫 描时，MOS管开启，栅极驱动芯片300正常输出。电容C充电时间大于等于一帧的显示时间，避免第一次栅极驱动芯片300扫描时对电容C充电过快，导致MOS管提前开启。
在一实施例中，一条扫描线对应一个信号延时电路400。
本方案中，每个信号延时电路400有对应的扫描线，两者之间一一对应，可以做到精准控制。
在一实施例中，信号延时电路400至少有两个，每一个信号延时电路400延时的时间相等。
本方案中，信号延时电路400对应每一条扫描线，信号延时电路400延时时间相等，保证每一条扫描线上栅极驱动信号传输的时间相等。
在一实施例中，信号延时电路400集成到栅极驱动芯片300。
本方案中，信号驱动电路400连接栅极驱动芯片300和显示面板100，信号延时电路400中的信号输出端为实际输入到显示面板100的开启信号，与显示面板100连接，将信号延时电路400集成在栅极驱动芯片300上可以节省空间，提高空间利用率。
在一实施例中，显示面板100包括显示区110和非显示区120，非显示区120包围显示区110，栅极驱动芯片300连接在所述非显示区120的第一侧边121，源极驱动芯片200连接在非显示区120的第二侧边122。
本方案中，栅极驱动芯片300连接在非显示区120的第一侧边121上，非显示区120相邻的第二侧边122与源极驱动芯片200连接。驱动芯片连接在非显示区120，通过非显示区120最终信号传递至显示区110。
作为本申请的另一实施例，参考图1至图2所示，公开了一种显示装置，包括：
显示面板100，显示面板100包括扫描线和数据线；设置为输出显示面板源极驱动信号的源极驱动芯片200，设置为输出显示面板100栅极驱动信号的栅极驱动芯片300；
信号延时电路400，栅极驱动信号通过信号延时电路400输出至扫描线；源极驱动信号直接输出至数据线；信号延时电路400集成到栅极驱动芯片300，信号延时电路包括D触发器410、电阻R、电源VDD、接地线GND、电容C和主动开关M，D触发器 410的C端与电阻R连接，电阻R另一端与栅极驱动芯片300的输出端连接，D触发器410的D端与电源VDD连接；电容C一端与接地线GND连接，电容C另一端和主动开关M的控制端，以及D触发器410的Q端连接，信号延时电路还包括信号输入端、信号输出端；栅极驱动芯片300的输出端通过主动开关连接扫描线，电容C充电时间大于等于显示面板100一帧的显示时间。
本方案中，作为当前平板显示的主要品种，薄膜晶体液晶显示器广泛的运用到现代IT、视讯产品中。申请人知晓的设计在开机过程中可能会发生画面异常，即栅极驱动芯片300已经开始正常工作而源极驱动芯片200还未正常工作。由于栅极驱动芯片300和源极驱动芯片200正常工作时间都是在系统上电完成后的时间，源极驱动芯片200信号无法进行提前。在本设计中，在栅极驱动芯片300上增加信号延时电路400，使栅极驱动信号300通过信号延时电路400传输信号至扫描线，将栅极驱动信号延时传输。这样栅极驱动信号和源极驱动信号同时到达显示面板100，避免了开机时出现画面异常。电源VDD为逻辑高电平设为H，接地线GND为逻辑低电平设为L，当栅极驱动芯片300控制信号为H时，主动开关M开启，当栅极驱动芯片300控制信号为L时，主动开关M关闭。电路中的电容C作用就是延缓主动开关M的开启时间。工作状态下，当系统上电时，栅极驱动芯片300正常工作，当信号输入端420初次输出栅极开启信号时，主动开关M关闭，信号输出端420没有输出。D触发器410的C端受到信号输入端420上升沿时，D触发器410将D端的高电平赋值给Q，此时电容C开始充电。当电容C充电到高电平时，主动开关M开启。电容C的充电时间为信号延时电路400的延时时间。电容C充电时间大于等于显示面板100一帧的显示时间，第一次栅极驱动芯片300扫描到对应行时不输出，对电容C进行充电，第二次栅极驱动芯片300扫描时，主动开关M开启，栅极驱动芯片300正常输出。电容C充电时间大于等于一帧的显示时间，避免第一次栅极驱动芯片300扫描时对电容C充电过快，导致主动开关M提前开启。信号延时电路400连接栅极驱动芯片300和显示面板100，信号延时电路400中的信号输出端420为实际输入到显示面板100的开启信号，与显示面板100连接，将信号延时电路400集成在栅极驱动芯片300上可以节省空间，提高空间利用率。
作为本申请的另一实施例，参考图3所示，公开了一种显示装置的驱动方法，驱动方法的步骤包括：
S11:栅极驱动信号通过信号延时电路输出至扫描线；
S12:源极驱动信号直接输出至数据线。
本方案中，显示面板在开机时，数据经过栅极驱动芯片和源极驱动芯片传递到显示区，使显示装置获得所需信号。在栅极驱动芯片增加了延时电路，使栅极驱动信号延时到达扫描线，避免开机时源极驱动芯片内部电位未完全建立导致画面异常。
在一实施例中，控制栅极驱动芯片信号延时输出时间大于或等于一帧的显示时间。
本方案中，控制栅极驱动芯片信号延时输出的时间，使输出时间大于或等于一帧的显示时间，避免第一次栅极驱动芯片扫描时电容充电速度过快，导致第一次扫描时存在输出，影响画面质量。
作为本申请的另一实施例，参考图1至图4所示，公开了一种显示系统500，包括显示装置600，显示装置600包括：显示面板100，显示面板100包括扫描线和数据线；设置为输出显示面板100源极驱动信号的源极驱动芯片200，设置为输出显示面板100栅极驱动信号的栅极驱动芯片300；信号延时电路400，栅极驱动信号通过信号延时电路400输出至扫描线，源极驱动信号直接输出至数据线；以及背光模组700，设置为给显示装置600提供光源。
本方案中，作为当前平板显示的主要品种，薄膜晶体液晶显示器广泛的运用到现代IT、视讯产品中。申请人知晓的一种设计在开机过程中可能会发生画面异常，即栅极驱动芯片300已经开始正常工作而源极驱动芯片还200未正常工作。由于栅极驱动芯片300和源极驱动芯片200正常工作时间都是在系统上电完成后的时间，源极驱动芯片200信号无法进行提前。在本设计中，在栅极驱动芯片300上增加信号延时电路400，使栅极驱动信号通过信号延时电路400传输信号至扫描线，将栅极驱动信号延时传输。这样栅极驱动信号和源极驱动信号同时到达显示面板100，避免了开机时出现画面异常。
在一实施例中，信号延时电路包括D触发器410、电阻R、电源VDD、接地线GND、电容C和主动开关M，D触发器410的C端与电阻R连接，电阻R另一端与栅极驱动 芯片300的输出端连接，D触发器410的D端与电源VDD连接；电容C一端与接地线GND连接，电容C另一端和主动开关M的控制端，以及D触发器410的Q端连接，信号延时电路还包括信号输入端、信号输出端；栅极驱动芯片300的输出端通过主动开关连接扫描线。
本方案中，电源VDD为逻辑高电平设为H，接地线GND为逻辑低电平设为L，当栅极驱动芯片300控制信号为H时，主动开关M开启，当栅极驱动芯片300控制信号为L时，主动开关M关闭。电路中的电容C作用就是延缓主动开关M的开启时间。工作状态下，当系统上电时，栅极驱动芯片400正常工作，当信号输入端420初次输出栅极开启信号时，主动开关M关闭，信号输出端430没有输出。D触发器410的C端受到信号输入端上升沿时，D触发器410将D端的高电平赋值给Q，此时电容C开始充电。当电容C充电到高电平时，主动开关M开启。电容C的充电时间为信号延时电路400的延时时间。
在一实施例中，电容C充电时间大于等于显示面板100一帧的显示时间。
本方案中，电容C充电时间大于或等于显示面板100一帧的显示时间，第一次栅极驱动芯片300扫描到对应行时不输出，对电容C进行充电，第二次栅极驱动芯片300扫描时，MOS管开启，栅极驱动芯片300正常输出。电容C充电时间大于等于一帧的显示时间，避免第一次栅极驱动芯片300扫描时对电容C充电过快，导致MOS管提前开启。
在一实施例中，信号延时电路400至少有两个，每一个信号延时电路400延时的时间相等。
本方案中，信号延时电路400对应每一条扫描线，信号延时电路400延时时间相等，保证每一条扫描线上栅极驱动信号传输的时间相等。
在一实施例中，信号延时电路400集成到栅极驱动芯片300。
本方案中，信号驱动电路400连接栅极驱动芯片300和显示面板100，信号延时电路400中的信号输出端为实际输入到显示面板100的开启信号，与显示面板100连接，将信号延时电路400集成在栅极驱动芯片300上可以节省空间，提高空间利用率。
在一实施例中，显示面板100包括显示区110和非显示区120，非显示区120包围显示区110，栅极驱动芯片300连接在非显示区120的第一侧边121，源极驱动芯片200连接在非显示区120的第二侧边122。
本方案中，栅极驱动芯片300连接在非显示区120的第一侧边121上，非显示区120相邻的第二侧边122与源极驱动芯片200连接。驱动芯片连接在非显示区120，通过非显示区120最终信号传递至显示区110。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛使用在TN面板(Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PaneSwitcing，平面转换)、VA面板(Multi-domain Vertica Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (18)

  1. 一种显示装置，包括：
    显示面板，所述显示面板包括扫描线和数据线；
    源极驱动芯片，输出所述显示面板的源极驱动信号；
    栅极驱动芯片，输出所述显示面板的栅极驱动信号；以及
    信号延时电路，所述栅极驱动信号通过所述信号延时电路输出至扫描线；所述源极驱动信号直接输出至数据线。
  2. 如权利要求1所述的一种显示装置，其中，所述信号延时电路包括D触发器、电阻、电源、接地线、电容和主动开关，所述D触发器C端与所述电阻连接，所述电阻另一端与所述栅极驱动芯片的输出端连接，所述D触发器D端与所述电源连接；所述电容一端与所述接地线连接，所述电容另一端和所述主动开关的控制端，以及所述D触发器Q端连接，所述信号延时电路还包括信号输入端、信号输出端；所述栅极驱动芯片的输出端通过主动开关连接所述扫描线。
  3. 如权利要求2所述的一种显示装置，其中，所述主动开关为薄膜晶体管，所述薄膜晶体管的栅极连接所述电容，源极连接所述栅极驱动芯片的输出端，漏极连接所述扫描线。
  4. 如权利要求2所述的一种显示装置，其中，所述电容充电时间大于所述显示面板一帧的显示时间。
  5. 如权利要求2所述的一种显示装置，其中，所述电容充电时间等于所述显示面板一帧的显示时间。
  6. 如权利要求1所述的一种显示装置，其中，一条所述扫描线对应一个所述信号延时电路。
  7. 如权利要求6所述的一种显示装置，其中，所述信号延时电路至少有两个，每一个所述信号延时电路延时的时间相等。
  8. 如权利要求2所述的一种显示装置，其中，所述信号延时电路集成到所述栅极驱动芯片。
  9. 如权利要求1所述的一种显示装置，其中，所述显示面板包括显示区和非显示区，所述非显示区包围所述显示区，所述栅极驱动芯片连接在所述非显示区的第一侧边，所述源极驱动芯片连接在所述非显示区的第二侧边。
  10. 一种显示装置的驱动方法，所述驱动方法的步骤包括：
    栅极驱动信号通过信号延时电路输出至扫描线；
    源极驱动信号直接输出至数据线。
  11. 如权利要求10所述的一种显示装置的驱动方法，包括：控制栅极驱动芯片信号延时输出时间大于一帧的显示时间。
  12. 如权利要求10所述的一种显示装置的驱动方法，包括：控制栅极驱动芯片信号延时输出时间等于一帧的显示时间。
  13. 一种显示系统，包括显示装置，所述显示装置包括：
    显示面板，所述显示面板包括扫描线和数据线；
    源极驱动芯片，输出所述显示面板的源极驱动信号；
    栅极驱动芯片，输出所述显示面板的栅极驱动信号；
    信号延时电路，所述栅极驱动信号通过所述信号延时电路输出至扫描线；所述源极驱动信号直接输出至数据线；以及
    背光模组，设置为给显示装置提供光源。
  14. 如权利要求13所述的一种显示系统，其中，所述信号延时电路包括D触发器、电阻、电源、接地线、电容和主动开关，所述D触发器C端与所述电阻连接，所述电阻另一端与所述栅极驱动芯片的输出端连接，所述D触发器D端与所述电源连接；所述电容一端与所述接地线连接，所述电容另一端和所述主动开关的控制端，以及所述D触发器Q端连接，所述信号延时电路还包括信号输入端、信号输出端；所述栅极驱动芯片的输出端通过主动开关连接所述扫描线。
  15. 如权利要求14所述的一种显示系统，其中，所述电容充电时间大于等于所述显示面板一帧的显示时间。
  16. 如权利要求13所述的一种显示系统，其中，所述扫描线至少两条，每一条扫 描线对应一个所述信号延时电路。
  17. 如权利要求13所述的一种显示系统，其中，所述信号延时电路集成到所述栅极驱动芯片。
  18. 如权利要求13所述的一种显示系统，其中，所述显示面板包括显示区和非显示区，所述非显示区包围所述显示区，所述栅极驱动芯片连接在所述非显示区的第一侧边，所述源极驱动芯片连接在所述非显示区的第二侧边。
PCT/CN2018/120789 2018-11-21 2018-12-13 显示装置以及驱动方法和显示系统 Ceased WO2020103229A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN115210797B (zh) * 2020-12-22 2025-04-08 京东方科技集团股份有限公司 显示装置、显示装置驱动方法
CN115273739B (zh) 2022-09-26 2023-01-24 惠科股份有限公司 显示面板、驱动方法及显示设备
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030034965A1 (en) * 2001-08-14 2003-02-20 Kim Chang Gone Power sequence apparatus and driving method thereof
CN101256760A (zh) * 2007-03-02 2008-09-03 瑞鼎科技股份有限公司 开机画面修正装置及应用其的源极驱动器
CN101334969A (zh) * 2007-06-28 2008-12-31 中华映管股份有限公司 栅极驱动电路与电源控制电路
CN101620828A (zh) * 2008-07-04 2010-01-06 群康科技(深圳)有限公司 液晶显示装置及其驱动方法
JP2010117654A (ja) * 2008-11-14 2010-05-27 Toshiba Tec Corp 電子機器

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0176429B1 (ko) * 1996-02-28 1999-04-01 윤종용 엘시디 모듈의 직류 충격 예방 방법
JP3856919B2 (ja) * 1997-08-29 2006-12-13 株式会社東芝 液晶表示装置
CN2745164Y (zh) * 2004-09-30 2005-12-07 四川长虹电器股份有限公司 液晶显示屏花屏抑制电路
CN100365697C (zh) * 2005-04-13 2008-01-30 友达光电股份有限公司 液晶显示器及其集成驱动芯片
KR101274054B1 (ko) * 2007-12-20 2013-06-12 엘지디스플레이 주식회사 액정 표시장치 및 그의 구동방법
TW201218163A (en) * 2010-10-22 2012-05-01 Au Optronics Corp Driving circuit for pixels of an active matrix organic light-emitting diode display and method for driving pixels of an active matrix organic light-emitting diode display
US8994439B2 (en) * 2012-04-19 2015-03-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, image display device, storage device, and electronic device
CN106448543B (zh) * 2016-12-20 2019-05-24 上海中航光电子有限公司 一种栅极驱动电路、显示面板和显示装置
KR102473299B1 (ko) * 2017-12-12 2022-12-05 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN108305592B (zh) * 2018-02-14 2021-01-22 京东方科技集团股份有限公司 同步输出的驱动单元、显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030034965A1 (en) * 2001-08-14 2003-02-20 Kim Chang Gone Power sequence apparatus and driving method thereof
CN101256760A (zh) * 2007-03-02 2008-09-03 瑞鼎科技股份有限公司 开机画面修正装置及应用其的源极驱动器
CN101334969A (zh) * 2007-06-28 2008-12-31 中华映管股份有限公司 栅极驱动电路与电源控制电路
CN101620828A (zh) * 2008-07-04 2010-01-06 群康科技(深圳)有限公司 液晶显示装置及其驱动方法
JP2010117654A (ja) * 2008-11-14 2010-05-27 Toshiba Tec Corp 電子機器

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