WO2020097861A1

WO2020097861A1 - Chip-based puf structure and method

Info

Publication number: WO2020097861A1
Application number: PCT/CN2018/115683
Authority: WO
Inventors: 李运宁; 王文轩; 沈健
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-05-22
Also published as: CN111436210B; CN111436210A

Abstract

The present application relates to the field of electronics, and in particular, to a chip-based PUF structure and method. The structure comprises a first electrode matrix and a second electrode matrix; the first electrode matrix is provided in a chip package; an overlapping region is formed between the first electrode matrix and the second electrode matrix; an electrode in the first electrode matrix is connected to a chip internal circuit; an electrode in the second electrode matrix is connected to a fixed electrical level. In addition, the present application further provides a chip-based PUF method. The method comprises: detecting a capacitance matrix formed between the first electrode matrix and the second electrode matrix; obtaining an identity information matrix of a chip by means of the capacitance matrix. The method for forming the capacitance matrix by providing the first electrode matrix and the second electrode matrix according to the present application solves the problem that it is very difficult to obtain stable chip identity information due to the environmental influence, and also solves the problem that the chip identity information is easily cracked by means of electrology.

Description

A chip-based PUF structure and method

Technical field

This application relates to the field of electronics, in particular to a chip-based PUF structure and method.

Background technique

PUF (Physical Unclonable Technology, Physical Unclonable Function), as an emerging technology in the field of hardware security, has been widely used in the authorization of electronic devices and the generation of electronic keys. In the era of the Internet of Things, information security is facing more and more severe challenges. Every day, a large number of different types of electronic devices need to be connected to the network, so it is particularly important to provide each device with a unique identity that cannot be copied.

The PUF method based on analog circuits or SRAM (Static Random-Access Memory) threshold voltage is a more common method to realize the PUF function. Among them, the PUF method based on analog circuits is usually easily affected by the environment, such as temperature, electromagnetic radiation, etc., it is difficult to obtain stable chip identity information; the PUF method based on the SRAM threshold voltage is easily affected by the environment, and it is difficult to obtain stable Chip identity information, and it cannot prevent cracking by electrical means.

Summary of the invention

In view of the above problems in the PUF method in the prior art, embodiments of the present application provide a chip-based PUF structure and method.

The first aspect of the embodiments of the present application provides a chip-based PUF structure, including a first electrode matrix and a second electrode matrix, and a capacitance matrix is formed between the first electrode matrix and the second electrode matrix to realize the physical inability of the chip Cloning; the first electrode matrix is set in the chip package; the overlap area is formed between the first electrode matrix and the second electrode matrix; the electrodes in the first electrode matrix are connected to the internal circuit of the chip; the electrodes in the second electrode matrix are fixedly connected Level.

In addition, with reference to the first aspect, in an implementation manner of the first aspect, the fixed connection level of the electrodes in the second electrode matrix includes: the electrodes in the second electrode matrix are connected to the same fixed level.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the internal circuit of the chip includes a capacitance detection circuit, and the capacitance detection circuit is used to detect the capacitance value of the capacitance matrix.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the connection between the electrodes in the first electrode matrix and the internal circuit of the chip includes: the electrodes in the first electrode matrix are connected to the capacitance detection circuit .

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the capacitance detection circuit includes a multiplexer.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the second electrode matrix is disposed in the chip package.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix are disposed on the same component in the chip package.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix disposed on the same component in the chip package include: the first electrode matrix and the second The electrode matrix is arranged on the same chip; or the first electrode matrix and the second electrode matrix are arranged on the same substrate.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix are provided on different components in the chip package.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix are disposed on different components in the chip package including: the first electrode matrix is disposed on the On a chip, the second electrode matrix is arranged on the second chip.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix is disposed on the first chip, and the second electrode matrix is disposed on the second chip including: the first electrode The matrix and the second electrode matrix are respectively disposed on two adjacent surfaces of the first chip and the second chip.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix are disposed on different components in the chip package including: the first electrode matrix is disposed on the chip On the top, the second electrode matrix is arranged on the substrate.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix is disposed on the chip, and the second electrode matrix is disposed on the substrate includes: the first electrode matrix is disposed on the chip The lower surface of the second electrode matrix is provided on the upper surface of the substrate.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix and the second electrode matrix are disposed on different components in the chip package including: the first electrode matrix is disposed on the substrate Above, the second electrode matrix is arranged on another substrate.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the second electrode matrix is provided on the circuit board, and the circuit board and the chip package are connected.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix is disposed on the substrate.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix is provided on the chip.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, the first electrode matrix is disposed on the lower surface of the chip; the second electrode matrix is disposed on the upper surface of the circuit board.

In addition, with reference to the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, a filler is further included; the filler is disposed between the first electrode matrix and the second electrode matrix; the filler is an insulating material .

In addition, in combination with the first aspect and the foregoing implementation manners, in another implementation manner of the first aspect, dielectric particles are provided in the insulating material.

The second aspect of the embodiments of the present application provides a chip-based PUF method for the chip-based PUF structure. The method includes: detecting a capacitance matrix formed between a first electrode matrix and a second electrode matrix; The capacitance matrix obtains the chip's identity information matrix.

In addition, with reference to the second aspect, in an implementation manner of the second aspect, obtaining the identity information matrix of the chip from the capacitance matrix includes: calculating an average value of capacitance values in the capacitance matrix; and calculating a difference between the capacitance matrix and the average value The identity information matrix of the chip.

Compared with the prior art, the beneficial effects of the embodiments of the present application are: The embodiments of the present application provide a chip-based PUF structure and method, by providing a first electrode matrix and a second electrode matrix, wherein the first electrode matrix It is arranged in the chip package, and at the same time, an overlapping area is formed between the first electrode matrix and the second electrode matrix, so as to obtain a corresponding capacitance matrix. On the one hand, each capacitor value in the capacitor matrix has the same tendency to be affected by the environment, so the data processing of the capacitor matrix is simpler, and it is easier to obtain stable chip identity information; The first electrode matrix is arranged in the chip package, which not only increases the difficulty of disassembly, but also it is not easy to read the identity information of the chip through electrical connection after disassembly, and physical or chemical cracking may also cause the identity information of the chip to change Or lost, greatly reducing the possibility of being cracked by electrical methods.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those skilled in the art, without paying any creative labor, other drawings can be obtained based on these drawings.

FIG. 1 is a first structural diagram in which both the first electrode matrix and the second electrode matrix of the embodiment of the present application are provided on the same chip;

FIG. 2 is a second structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both provided on the same chip;

FIG. 3 is a third structural diagram in which both the first electrode matrix and the second electrode matrix of the embodiment of the present application are provided on the same chip;

4 is a fourth structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both provided on the same chip;

5 is an electrode distribution diagram in the first electrode matrix in the embodiment of the present application;

6 is an electrode distribution diagram in the second electrode matrix in the embodiment of the present application;

FIG. 7 is a first structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same substrate;

8 is a second structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same substrate;

9 is a structural diagram of a first electrode matrix disposed on a first chip and a second electrode matrix disposed on a second chip according to an embodiment of the present application;

10 is a structural diagram of a first electrode matrix provided on a chip and a second electrode matrix provided on a substrate according to an embodiment of the present application;

11 is a structural diagram of a first electrode matrix disposed on a substrate and a second electrode matrix disposed on another substrate according to an embodiment of the present application;

12 is a structural diagram of a first electrode matrix provided on a substrate and a second electrode matrix provided on a circuit board according to an embodiment of the present application;

13 is a structural diagram of a first electrode matrix provided on a chip and a second electrode matrix provided on a circuit board according to an embodiment of the present application;

14 is a flowchart of a chip-based PUF method according to an embodiment of the present application.

detailed description

In order to make the purpose, technical solutions and advantages of the present application clearer, some embodiments of the present application will be explained in detail by way of example with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each example, many technical details are proposed in order for the reader to better understand the application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in this application can be realized.

The embodiments of the present application provide a chip-based PUF structure and method. By providing a first electrode matrix in a chip package and a second electrode matrix in a chip package or module, an overlapping area is formed between the two To get the corresponding panel capacitance matrix. On the one hand, due to random and uncontrollable and unpredictable process deviations during chip packaging or module installation, for example: the thickness of the filler injection is different; the relative dielectric caused by the incorporation of irregular dielectric particles in the filler The constant is different; or the area of the overlapping area is caused by the error of the mounting position of the chip, substrate and circuit board. These process deviations cause the capacitor matrix formed by different chips to be unique and unpredictable and unreproducible. Therefore, the capacitor matrix can be used as the unique identity information of the corresponding chip. Moreover, since each capacitor value in the capacitor matrix is affected by the environment in the same trend, even if the chip is in different environments (such as temperature, electromagnetic radiation, etc.), the data processing of the capacitor matrix is simpler, and it is easier to obtain stable chip identity information . On the other hand, the chip identity information formed in the embodiment of the present application is stored in the capacitor matrix, and the first electrode matrix is provided in the chip package, which not only increases the difficulty of disassembly, but also makes it difficult to read the chip through electrical connection after disassembly Identity information, and even if it is disassembled by physical or chemical means, it is very easy to cause the structure of the capacitor matrix to change, so that the identity information of the chip is changed or lost. In addition, the embodiments of the present application may not need to use additional non-volatile storage devices to store the error correction information of the chip identity information, which also greatly reduces the possibility of being cracked electrically.

An embodiment of the present application provides a chip-based PUF structure, which includes a first electrode matrix and a second electrode matrix. A capacitance matrix is formed between the first electrode matrix and the second electrode matrix to realize the physical unclonability of the chip. After the PUF structure of the chip is determined, the capacitance value of the capacitor matrix formed by the first electrode matrix and the second electrode matrix is generally not affected by factors other than the environment to ensure a stable chip identity information matrix to realize the chip Cannot be cloned. The first electrode matrix is disposed in the chip package, and an overlap region is formed between the first electrode matrix and the second electrode matrix, thereby obtaining a corresponding capacitance matrix. It should be noted that there may be components such as chips, substrates or fillers in the chip package, but it is not limited to chips, substrates or fillers, and the number of chips, substrates or fillers is not limited, and chips and fillers may be There are one or more, and the base can be zero, one or more. The internal circuit of the chip is set in the chip and can be used to collect the capacitance value of the capacitance matrix. In this embodiment, the first electrode matrix is arranged in the chip package. On the one hand, it is convenient for the first electrode matrix to connect with the internal circuit of the chip. On the other hand, the electrode matrix is arranged in the chip package, which not only increases the difficulty of disassembly, disassembly It is not easy to read the capacitance value of the capacitor matrix by electrical connection to obtain the identity information of the chip, and the physical or chemical cracking method may also cause the identity information of the chip to be changed or lost. Therefore, the security of the identity information of the chip can be Guarantee.

It should be noted that the identity information of the capacitor matrix as a chip is only for illustrative purposes. In actual use, the capacitor matrix can also be used as identity information of a module or system, which is not limited in this embodiment. In this embodiment, a capacitor matrix is used to distinguish each chip, and the cost is lower. In addition, this embodiment can be used for Flip Chip packaging and other packaging methods. This embodiment does not limit the packaging method of the chip.

Based on the above embodiment, the following describes in detail from various possible placement positions of the first matrix and the second matrix:

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, both the first electrode matrix and the second electrode matrix are provided in the chip package, wherein the first electrode matrix and the second electrode matrix may be provided in the chip package On the same component, in this embodiment, the first electrode matrix and the second electrode matrix may both be arranged on the same chip. Please refer to FIG. 1. FIG. 1 is a first structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same chip. As shown in FIG. 1, the first electrode matrix 101 and the second electrode matrix Both 102 are provided on the chip 100. Specifically, the first electrode matrix 101 and the second electrode matrix 102 are provided on the upper surface and the lower surface of the chip 100, respectively, but those skilled in the art should understand that the first electrode The arrangement of the matrix and the second electrode matrix on the upper surface and the lower surface of the chip, respectively, is for illustrative purposes only. In actual use, those skilled in the art may refer to the solutions of the embodiments of the present application to set the first electrode matrix on the chip The outer upper surface or the upper surface inside the chip is provided with the second electrode matrix on the lower surface inside the chip or the lower surface outside the chip, which is not limited in this embodiment.

In addition, please refer to FIG. 2, which is a second structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same chip. As shown in FIG. 2, the first electrode matrix 101 and the second The electrode matrix 102 may be embedded on the upper surface and the lower surface of the chip 100, respectively. In addition, please refer to FIG. 3, which shows that both the first electrode matrix and the second electrode matrix of the embodiment of the present application are provided on the same chip. In the third structural diagram, as shown in FIG. 3, part of the electrodes of the first electrode matrix 101 may be provided on the upper surface inside the chip 100, another part of the electrodes may be provided on the upper surface outside the chip 100, and a part of the electrodes may be embedded It is arranged on the upper surface of the chip 100, part of the electrodes of the second electrode matrix 102 can be arranged on the lower surface inside the chip 100, another part of the electrodes can be arranged on the lower surface outside the chip 100, and part of the electrodes can be embedded on the chip The lower surface of 100. It should be noted that the above situations are only exemplary descriptions, and those skilled in the art can obtain other positions of the first electrode matrix and the second electrode matrix on the chip according to this embodiment.

Based on the locations of the first electrode matrix 101 and the second electrode matrix 102 described above, an overlap region 103 is formed between the two. It should be noted that an overlap region is formed between the first electrode matrix and the second electrode matrix. The electrode matrix and the second electrode matrix may all overlap or partly overlap. When all overlap, there is an overlap area between the electrodes of the first electrode matrix and the electrodes of the second electrode matrix, all of which overlap The situation is shown in FIG. 1, FIG. 2 or FIG. 3, and it should be noted that there are many other situations in which all overlap, which will not be repeated here. When partially overlapping, there is no overlapping area between the partial electrodes of the first electrode matrix and the electrodes of the second electrode matrix, or there is no overlapping area between the partial electrodes of the second electrode matrix and the electrodes of the first electrode matrix, Refer to Figure 4 for partial overlap. It should be noted that there are many other situations in the partial overlap, which will not be repeated here. As shown in FIG. 1, FIG. 2, FIG. 3, or FIG. 4, the electrode 105 in the first electrode matrix 101 and the electrode 106 in the second electrode matrix 102 have an inter-electrode overlap region 104. This inter-electrode overlap region 104 may be Corresponding to a capacitance value in the capacitance matrix, it is clear that when partially overlapping, there is no inter-electrode overlap region between the partial electrodes of the first electrode matrix and the electrodes of the second electrode matrix, or the partial electrodes of the second electrode matrix and the first electrode matrix There is no inter-electrode overlap region between the electrodes of an electrode matrix; in addition, in the case of full overlap, there may also be no inter-electrode overlap region between some electrodes of the first electrode matrix and the electrodes of the second electrode matrix, or There may not be an inter-electrode overlap region between some electrodes of the second electrode matrix and the electrodes of the first electrode matrix. It should be noted that, in this embodiment, the electrode thicknesses of the first electrode matrix and the second electrode matrix are not limited, and the electrode thicknesses of the electrodes of the first electrode matrix or the second electrode matrix may be the same or different .

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the first electrode matrix are connected to the internal circuit of the chip for reading the capacitance matrix. Please refer to FIG. 5, which is an electrode distribution diagram in the first electrode matrix in the embodiment of the present application. As shown in FIG. 5, the chip 100 is provided with a first electrode matrix 101, and the electrodes in the first electrode matrix 101 are Internal circuit connection of the chip. In this embodiment, the electrodes in the first electrode matrix 101 are rectangular, but it should be understood by those skilled in the art that the electrodes are rectangular in shape for illustrative purposes only. In actual use, the shape of the electrodes and the shape of the electrodes are not limited. The shape may be any regular or irregular shape; in this embodiment, the electrodes in the first electrode matrix 101 are regularly distributed, but it should be understood by those skilled in the art that the regular distribution of the electrodes is only for illustrative purposes. In actual use, the distribution mode of the electrodes is not limited, and may be regular distribution or irregular distribution; in this embodiment, all electrodes in the first electrode matrix 101 have the same shape, but those skilled in the art should understand Yes, the electrodes are all set in the same shape for illustrative purposes only. In actual use, the shapes of all electrodes may be the same or different.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix are connected to a fixed level, where the fixed level may be any level. In addition, the electrodes in the second electrode matrix may be connected to the same fixed level, or may be connected to different fixed levels. This embodiment does not limit this. In one embodiment, the electrodes in the second electrode matrix are connected to the same fixed level, so that the capacitance matrix can be directly tested without excluding the effects of different levels. Please refer to FIG. 6, which is an electrode distribution diagram in the second electrode matrix in the embodiment of the present application. As shown in FIG. 6, a second electrode matrix 102 is provided on the chip 100, and the second electrode matrix 102 is connected to the same fixed Level. It should be noted that in this embodiment, the first electrode matrix 101 and the second electrode matrix 102 have the same number of electrodes, but those skilled in the art should understand that the first electrode matrix and the second electrode matrix have the same number of electrodes For illustrative purposes only, in actual use, the number of electrodes of the first electrode matrix and the second electrode matrix is not limited, and the number of electrodes of the first electrode matrix and the second electrode matrix may be the same or different.

Based on the content disclosed in the above embodiment, optionally, in this embodiment, the internal circuit of the chip may include a capacitance detection circuit, the capacitance detection circuit is used to detect the capacitance value of the capacitance matrix, and the capacitance value of the capacitance matrix is used to generate the chip identity information matrix ; In addition, capacitance detection methods include but are not limited to the bridge method, resonance method, oscillation method or charge and discharge method.

Based on the content disclosed in the above embodiment, optionally, in this embodiment, the electrodes in the first electrode matrix are connected to a capacitance detection circuit, and the capacitance detection circuit is used to detect the capacitance matrix formed by the first electrode matrix and the second electrode matrix For the capacitance value, the electrodes in the first electrode matrix are connected to the capacitance detection circuit of the internal circuit of the chip, which can enhance the anti-cracking performance.

Based on the content disclosed in the above embodiments, optionally, the capacitance detection circuit may include a multiplexer, which is used for signal selection of multiple capacitance signals to reduce hardware circuits, save costs, and facilitate integration.

An embodiment of the present application provides a chip-based PUF structure, by providing a first electrode matrix and a second electrode matrix, wherein the first electrode matrix is provided in a chip package, and at the same time, the first electrode matrix and the second electrode matrix Overlap areas are formed between them to obtain the corresponding capacitance matrix. On the one hand, each capacitor value in the capacitor matrix has the same tendency to be affected by the environment, so the data processing of the capacitor matrix is simpler, and it is easier to obtain stable chip identity information; on the other hand, the chip identity information is stored in the capacitor matrix, The first electrode matrix is arranged in the chip package, which not only increases the difficulty of disassembly, but also it is not easy to read the identity information of the chip through electrical connection after disassembly, and physical or chemical cracking may also cause the identity information of the chip to change Or lost, greatly reducing the possibility of being cracked by electrical methods.

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, the first electrode matrix and the second electrode matrix are also provided in the chip package, wherein the first electrode matrix and the second electrode matrix are also provided in the chip package On the same component, unlike the above embodiment, in this embodiment, the first electrode matrix and the second electrode matrix are both arranged on the same substrate. Please refer to FIG. 7, which is a first structure diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same substrate. As shown in FIG. 7, the first electrode matrix 201 and the second electrode The matrix 202 is arranged on the substrate 200. In this embodiment, the first electrode matrix 201 and the second electrode matrix 202 are respectively disposed on the upper surface and the lower surface of the substrate 200. It should be noted that in this embodiment, the first electrode matrix and the second electrode matrix are on the substrate The installation positions of Δ are only exemplary, and those skilled in the art can obtain other installation positions of the first electrode matrix and the second electrode matrix on the substrate according to the foregoing embodiments without paying creative efforts. In this embodiment, an overlap region 103 is formed between the first electrode matrix 201 and the second electrode matrix 202, and there is an inter-electrode overlap region between the electrode 105 in the first electrode matrix 201 and the electrode 106 in the second electrode matrix 202 104, corresponding to a capacitance value in the capacitance matrix.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix 202 are connected to a fixed level, and the electrodes in the first electrode matrix 201 are connected to the internal circuit of the chip for reading the capacitance matrix. In an embodiment, the electrodes in the second electrode matrix can be connected to the same fixed level, so that the capacitance matrix can be directly tested without excluding the effects of different levels.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the first electrode matrix are connected to the internal circuits of the chip. Different from the above embodiment, because the first electrode matrix in this embodiment is provided on the substrate, the electrodes in the first electrode matrix cannot be directly connected to the internal circuit of the chip, so the electrodes in the first electrode matrix need to be connected to the chip Connected to the internal circuit of the chip through the electrodes on the chip. Referring to FIG. 7, the first electrode matrix 201 is on the substrate 200. The first electrode matrix 201 needs to be connected to the electrode 401 on the chip 100, and the electrode 401 on the chip 100 is connected to the internal circuit of the chip. 109 in FIG. 7 refers to the electrical connection between the first electrode matrix 201 of the substrate 200 and the electrode 401 on the chip 100. It should be noted that between the first electrode matrix 201 of the substrate 200 and the electrode 401 on the chip 100 The connection methods include but are not limited to solder balls or metal bonding. In addition, there is a filler 108 between the substrate 200 and the chip 100. The filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be Solid, gas or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

Optionally, if the electrodes in the first electrode matrix cannot be directly connected to the electrodes on the chip, the electrodes on the chip can be connected through the electrodes on other substrates to achieve the purpose of connecting with the internal circuit of the chip. The specific implementation manner is as follows: the electrodes in the first electrode matrix are connected to the electrodes on other substrates, the electrodes on the other substrates are connected to the electrodes on the chip, and the electrodes on the chip are connected to the internal circuits of the chip. Please refer to FIG. 8, which is a second structural diagram in which the first electrode matrix and the second electrode matrix of the embodiment of the present application are both disposed on the same substrate. As shown in FIG. 8, the second electrode matrix 102 is on the substrate 200 , The first electrode matrix 101 on the substrate 200 is connected to the electrode 211 on the substrate 210, the electrode 211 on the substrate 210 is connected to the electrode 401 on the chip 100, and the electrode 401 on the chip 100 is connected to the internal circuit of the chip, wherein the substrate 200 There is a filler 108 between the substrate 210 and a filler 108 between the substrate 210 and the chip 100. The filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, in this embodiment, the filler The physical state of is not limited, and can be solid, gas, or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited. Among them, the first electrode matrix 101 on the substrate 200 is connected to the electrode 211 on the substrate 210 through the electrical connection 109, the electrode 211 on the substrate 210 is connected to the electrode 212 on the substrate 210, and the electrode 212 on the substrate 210 is connected through the electrical connection 109 The electrode 401 on the chip 100 is connected.

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, the first electrode matrix and the second electrode matrix are both provided in the chip package. Unlike the above embodiment, the first electrode matrix and the second electrode The matrix is arranged on different components in the chip package. In this embodiment, the first electrode matrix is arranged on the first chip, and the second electrode matrix is arranged on the second chip. Optionally, the first electrode matrix and the second electrode matrix are respectively disposed on two adjacent surfaces of the first chip and the second chip. Please refer to FIG. 9, which is a structural diagram of a first electrode matrix disposed on a first chip and a second electrode matrix disposed on a second chip according to an embodiment of the present application. As shown in FIG. 9, the first electrode matrix 101 is provided on one surface of the first chip 100 adjacent to the second chip 110, and the second electrode matrix 102 is provided on the other surface of the first chip 100 adjacent to the second chip 110 On the surface. This method of setting the position of the electrode matrix greatly increases the difficulty of disassembly, and even through physical or chemical cracking methods will cause the capacitance value of the capacitance matrix to change, so that the identity information of the chip is changed or lost, almost not It may be cracked by electrical methods. It should be noted that, in this embodiment, the first electrode matrix and the second electrode matrix are respectively disposed on two surfaces adjacent to the first chip and the second chip, which are only exemplary descriptions, and those skilled in the art do not pay Under the premise of creative work, other placement positions of the first electrode matrix and the second electrode matrix on the first chip and the second chip can be obtained according to the above embodiments. For example, the first electrode matrix can be placed inside the first chip The upper surface or the lower surface, or the first electrode matrix is provided on the upper surface outside the first chip, and the second electrode matrix is provided on the upper or lower surface inside or outside the second chip.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix 102 are connected to a fixed level, and the electrodes in the first electrode matrix 101 are connected to the internal circuit of the chip for reading the capacitance matrix. In one embodiment, the electrodes in the second electrode matrix 102 can be connected to the same fixed level, so that the capacitance matrix can be directly tested without excluding the effects of different levels.

Optionally, in this embodiment, the structure further includes a filler, and the filler is disposed between the first electrode matrix and the second electrode matrix. Different from the above embodiment, in the above embodiment, no filler is provided between the first electrode matrix and the second electrode matrix, because the first electrode matrix and the second electrode matrix in the above embodiment are provided in the chip package On the same component, between the first electrode matrix and the second electrode matrix is a substrate or a chip, and no filler can be provided. Please refer to FIG. 9, the filler 107 is disposed between the first electrode matrix 101 and the second electrode matrix 102, that is, between the chip 100 and the chip 110, and the filler is insulation including but not limited to resin or rubber that is not good at conducting current In addition, in this embodiment, the physical state of the filler is not limited, and it may be solid, gas, or liquid. In addition, dielectric particles may be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, both the first electrode matrix and the second electrode matrix are provided in the chip package, wherein the first electrode matrix and the second electrode matrix may be provided in the chip package The different internal components are different from the above-mentioned embodiments. In this embodiment, the first electrode matrix is arranged on the chip, and the second electrode matrix is arranged on the substrate. Optionally, the first electrode matrix is provided on the lower surface of the chip, and the second electrode matrix is provided on the upper surface of the substrate. Please refer to FIG. 10, which is a structural diagram of a first electrode matrix disposed on a chip and a second electrode matrix disposed on a substrate according to an embodiment of the present application. As shown in FIG. 10, the first electrode matrix 101 is provided on the lower surface of the chip 100, and the second electrode matrix 201 is provided on the upper surface of the substrate 200. This method of setting the position of the electrode matrix greatly increases the difficulty of disassembly, and even through physical or chemical cracking methods will cause the capacitance value of the capacitance matrix to change, thus causing the identity information of the chip to be changed or lost, almost not It may be cracked by electrical methods. Specifically, the first electrode matrix 101 and the second electrode matrix 201 are respectively provided on the lower surface outside the chip 100 and the upper surface outside the substrate 200. In this embodiment, the first electrode matrix 101 and the second electrode matrix 201 are respectively The lower surface provided outside the chip 100 and the upper surface outside the substrate 200 are only exemplary illustrations, and those skilled in the art can obtain the first electrode matrix and the second electrode matrix according to the above embodiments without creative efforts. At other locations on the chip and the substrate, for example, the first electrode matrix may be disposed on the upper or lower surface inside the chip, or the first electrode matrix may be disposed on the upper surface outside the chip, and the second electrode matrix may be disposed on The upper or lower surface inside or outside the substrate.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix 201 on the substrate 200 are connected to a fixed level, and the electrodes in the first electrode matrix 101 are connected to the internal circuit of the chip for reading the capacitance matrix take. In one embodiment, the electrodes in the second electrode matrix 201 on the substrate 200 can be connected to the same fixed level, so that the capacitance matrix can be directly tested without excluding the effects of different levels.

Optionally, in this embodiment, the structure further includes a filler, please refer to FIG. 10, the filler 107 is disposed between the first electrode matrix 101 and the second electrode matrix 201, that is, between the chip 100 and the substrate 200, filled The object is an insulating material that includes but is not limited to resin or rubber, which is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and it can be solid, gas, or liquid, etc., and can be provided in the insulating material. For electric particles, the dielectric constant of the dielectric particles is not limited.

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, both the first electrode matrix and the second electrode matrix are provided in the chip package, wherein the first electrode matrix and the second electrode matrix may be provided in the chip package Different from the above-mentioned embodiments on different internal components, in this embodiment, the first electrode matrix is arranged on the substrate, and the second electrode matrix is arranged on the other substrate. Please refer to FIG. 11, which is a structural diagram of a first electrode matrix disposed on a substrate and a second electrode matrix disposed on another substrate according to an embodiment of the present application. As shown in FIG. 11, the first electrode matrix 211 is provided on the substrate 210 and the second electrode matrix 201 is provided on the substrate 200. Specifically, the first electrode matrix 211 is provided on the lower surface outside the substrate 210 and the second electrode matrix 201 It is provided on the upper surface outside the substrate 200, but those skilled in the art should understand that the first electrode matrix 211 and the second electrode matrix 201 are respectively provided on the lower surface outside the substrate 210 and the upper surface outside the substrate 200 Exemplary description, those skilled in the art can obtain other placement positions of the first electrode matrix and the second electrode matrix on one substrate and another substrate according to the above embodiment without paying any creative labor, for example, The first electrode matrix is arranged on the upper or lower surface inside the substrate, or the first electrode matrix is arranged on the upper surface outside the substrate, and the second electrode matrix is arranged on the upper or lower surface inside or outside the other substrate.

Optionally, in this embodiment, the structure further includes a filler, please refer to FIG. 11, the filler 108 is disposed between the first electrode matrix 211 and the second electrode matrix 201, that is, between the substrate 200 and the substrate 210 , The filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be solid, gas, or liquid, etc., and may be in the insulating material When the dielectric particles are set, the dielectric constant of the dielectric particles is not limited.

Based on the content disclosed in the above embodiments, in this embodiment, the electrodes in the second electrode matrix 201 are connected to a fixed level. In one embodiment, the electrodes in the second electrode matrix can be connected to the same fixed level, so that you can directly The test results in a capacitance matrix without eliminating the effects of different levels.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the first electrode matrix 211 are connected to the internal circuit of the chip for reading the capacitance matrix. Since the first electrode matrix is provided on the substrate, the electrodes in the first electrode matrix need to be connected to the electrodes on the chip, and then connected to the internal circuit of the chip through the electrodes on the chip. Referring to FIG. 11, the first electrode matrix 211 is on the substrate 210. The first electrode matrix 211 needs to be connected to the electrode 401 on the chip 100, and the electrode 401 on the chip 100 is connected to the internal circuit of the chip. Among them, the first electrode matrix 211 is connected to the electrode 212 on the substrate 210, and the electrode 212 is connected to the electrode 401 on the chip 100. In FIG. 11, 109 refers to between the electrode 212 on the substrate 210 and the electrode 401 on the chip 100. For electrical connection, it should be noted that the connection between the electrode 212 of the substrate 210 and the electrode 401 on the chip 100 includes, but is not limited to, solder ball or metal bonding. In addition, a filler 108 is provided between the substrate 210 and the chip 100. The filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be Solid, gas or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

Optionally, if the electrodes in the first electrode matrix cannot be directly connected to the electrodes on the chip, the electrodes on the chip can be connected through the electrodes on other substrates to achieve the purpose of connecting with the internal circuit of the chip. The specific implementation manner is as follows: the electrodes in the first electrode matrix are connected to the electrodes on other substrates, the electrodes on the other substrates are connected to the electrodes on the chip, and the electrodes on the chip are connected to the internal circuits of the chip. The connection method in this case has been described in the foregoing embodiment, and will not be repeated here.

An embodiment of the present application provides a chip-based PUF structure. Unlike the above embodiment, in this embodiment, the first electrode matrix is provided in the chip package, and the second electrode matrix is provided on the circuit board. The chip package and the circuit The boards are connected to form a module or part of a module. Among them, the first electrode matrix is provided on the substrate, and the second electrode matrix is provided on the circuit board. Referring to FIG. 12, FIG. 12 is a structural diagram of a first electrode matrix disposed on a substrate and a second electrode matrix disposed on a circuit board according to an embodiment of the present application. As shown in FIG. 12, the first electrode matrix 201 is provided on the lower surface outside the substrate 210, and the second electrode matrix 301 is provided on the upper surface outside the circuit board 300. Those skilled in the art should understand that the first electrode matrix The arrangement of 201 and the second electrode matrix 301 on the lower surface outside the substrate 210 and the upper surface outside the circuit board 300 are exemplary only, and those skilled in the art can obtain the first The one electrode matrix and the second electrode matrix are arranged at other positions on the substrate and the circuit board, for example, the first electrode matrix can be arranged on the upper or lower surface inside the substrate, or the first electrode matrix can be arranged on the outside of the substrate On the upper surface, the second electrode matrix is provided on the upper surface or the lower surface inside the circuit board or outside the circuit board. It should be noted that the circuit board includes PCB (Printed Circuit Board Printed Circuit Board) and FPC (Flexible Circuit Board Flexible Printed Circuit).

Optionally, in this embodiment, the structure further includes a filler, the filler is disposed between the first electrode matrix and the second electrode matrix, please refer to FIG. 12, the filler 108 is disposed between the first electrode matrix 201 and the second Between the electrode matrix 301, that is, between the substrate 210 and the circuit board 300, the filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be It is solid, gas or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix 301 are connected to a fixed level. In one embodiment, the electrodes in the second electrode matrix can be connected to the same fixed level, so that you can directly The test results in a capacitance matrix without eliminating the effects of different levels.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the first electrode matrix are connected to the internal circuit of the chip for reading the capacitance matrix. Since the first electrode matrix is provided on the substrate, the electrodes in the first electrode matrix need to be connected to the electrodes on the chip, and then connected to the internal circuit of the chip through the electrodes on the chip. The first electrode matrix 201 is on the substrate 210. The first electrode matrix 201 needs to be connected to the electrode 401 on the chip 100, and the electrode 401 on the chip 100 is connected to the internal circuit of the chip. The first electrode matrix 201 is connected to the electrode 202 of the substrate 210, and the electrode 202 of the substrate 210 is connected to the electrode 401 on the chip 100. In FIG. 12, 109 refers to between the electrode 202 of the substrate 210 and the electrode 401 of the chip 100 For electrical connection, it should be noted that the connection between the electrode 202 of the substrate 210 and the electrode 401 on the chip 100 includes but is not limited to solder balls or metal bonding. In addition, a filler 108 is provided between the substrate 210 and the chip 100. The filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be Solid, gas or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

An embodiment of the present application provides a chip-based PUF structure. In this embodiment, the first electrode matrix is provided in the chip package, and the second electrode matrix is provided on the circuit board. Unlike the previous embodiment, the chip is directly soldered On the circuit board, the first electrode matrix may be provided on the chip, and the second electrode matrix may be provided on the circuit board. Optionally, the first electrode matrix is provided on the lower surface of the chip, and the second electrode matrix is provided on the upper surface of the circuit board. Please refer to FIG. 13, which is a structural diagram of a first electrode matrix disposed on a chip and a second electrode matrix disposed on a circuit board according to an embodiment of the present application. As shown in FIG. 13, the first electrode matrix 101 is provided on the lower surface of the chip 100, and the second electrode matrix 301 is provided on the upper surface of the circuit board 300. This method of setting the position of the electrode matrix greatly increases the difficulty of disassembly, and even through physical or chemical cracking methods will cause the capacitance value of the capacitance matrix to change, thus causing the identity information of the chip to be changed or lost, almost not It may be cracked by electrical methods. It should be understood by those skilled in the art that the arrangement of the first electrode matrix 101 and the second electrode matrix 301 on the lower surface outside the chip 100 and the upper surface outside the circuit board 300 are only exemplary descriptions, and those skilled in the art Other creative positions of the first electrode matrix and the second electrode matrix on the chip and the circuit board can be obtained according to the above embodiment without paying any creative labor, for example, the first electrode matrix can be arranged on the upper surface inside the chip Or the lower surface, or the first electrode matrix is arranged on the upper surface outside the chip, and the second electrode matrix is arranged on the upper surface or lower surface inside the circuit board or outside the circuit board.

Optionally, in this embodiment, the structure further includes a filler, the filler is disposed between the first electrode matrix and the second electrode matrix, please refer to FIG. 13, the filler 107 is disposed between the first electrode matrix 101 and the second Between the electrode matrix 301, that is, between the circuit board 300 and the chip 100, the filler is an insulating material including but not limited to resin or rubber that is not good at conducting current. In addition, the physical state of the filler is not limited in this embodiment, and may be It is solid, gas or liquid, etc., and dielectric particles can be provided in the insulating material, and the dielectric constant of the dielectric particles is not limited.

Based on the content disclosed in the above embodiment, in this embodiment, the electrodes in the second electrode matrix 301 are connected to a fixed level, and the electrodes in the first electrode matrix 101 are connected to the internal circuit of the chip for reading the capacitance matrix. In one embodiment, the electrodes in the second electrode matrix can be connected to the same fixed level, so that the capacitance matrix can be directly tested without excluding the effects of different levels.

This embodiment also provides a chip-based PUF method for the chip-based PUF structure proposed in the foregoing embodiments, please refer to FIG. 14, which is a chip-based PUF method according to an embodiment of the present application. Flow chart, the method includes the following steps:

001: Detect the capacitance matrix formed between the first electrode matrix and the second electrode matrix;

002: The chip identity information matrix is obtained from the capacitor matrix.

In step 001, the chip detects that the capacitance value of the capacitance matrix may not be stored in the chip, and the chip may perform capacitance detection on the electrode matrix as needed. After the chip detects the capacitance matrix, the chip can transfer the capacitance matrix to other required components. In step 002, the step of obtaining the chip's identity information matrix from the capacitor matrix may be performed by the chip or by other components. The detected capacitance matrix may be directly used as the chip's identity information matrix, or the capacitor matrix may be processed after data processing to obtain the chip's identity information matrix, which is not limited in this embodiment.

Optionally, obtaining the chip's identity information matrix from the capacitor matrix includes the following steps:

010: Calculate the average value of capacitance in the capacitance matrix;

020: Calculate the difference between the capacitance matrix and the average value to obtain the identity information matrix of the chip.

The capacitance value of the capacitance matrix formed between the first electrode matrix and the second electrode matrix is easily affected by the environment. Since the tendency of the capacitance value to be affected by the environment is generally the same, the data processing of the capacitance matrix is relatively simple. The relative value of each capacitor value in the capacitor matrix can be selected as the chip's identity information matrix. However, it should be understood by those skilled in the art that using the relative value of each capacitor value in the capacitor matrix as the chip's identity information matrix is only an exemplary description. In actual use, those skilled in the art may refer to the embodiments of the present application Scheme, select other capacitor matrix processing method to get the chip's identity information matrix. In this embodiment, the average value of all capacitance values of the capacitance matrix can be obtained first, and then all the capacitance values of the capacitance matrix are subtracted from the average value to obtain a matrix of relative values, which can be used as the identity information matrix of the chip .

An embodiment of the present application provides a chip-based PUF method, which is applied to the chip-based PUF structure, by providing a first electrode matrix and a second electrode matrix, wherein the first electrode matrix is provided in the chip package, and , An overlapping area is formed between the first electrode matrix and the second electrode matrix, so as to obtain a corresponding capacitance matrix. On the one hand, each capacitor value in the capacitor matrix has the same tendency to be affected by the environment, so the data processing of the capacitor matrix is simpler, and it is easier to obtain stable chip identity information; on the other hand, the chip identity information is stored in the capacitor matrix, The first electrode matrix is arranged in the chip package, which not only increases the difficulty of disassembly, but also it is not easy to read the identity information of the chip through electrical connection after disassembly, and physical or chemical cracking may also cause the identity information of the chip to change Or lost, greatly reducing the possibility of being cracked by electrical methods.

It should be noted that the above method embodiments of the present application may be applied to a processor, or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method embodiment may be completed by an integrated logic circuit of hardware in a processor or instructions in the form of software. The aforementioned processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an existing programmable gate array (FPGA), or other available Programming logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps, and logical block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied and executed by a hardware decoding processor, or may be executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, and registers. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

It can be understood that the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (read-only memory (ROM), programmable read-only memory (programmable rom, PROM), erasable programmable read-only memory (erasable PROM, EPROM), electronically Erasable programmable read-only memory (electrically EPROM, EEPROM) or flash memory. The volatile memory may be a random access memory (random access memory, RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), dynamic random access memory (dynamic RAM, DRAM), synchronous dynamic random access memory (synchronous RAM), SDRAM), double data rate synchronous dynamic random access memory (double data SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (synchlink DRAM, SLDRAM) ) And direct memory bus random access memory (direct RAMbus RAM, DR RAM). It should be noted that the memories of the systems and methods described herein are intended to include, but are not limited to these and any other suitable types of memories.

It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B based on A does not mean determining B based on A alone, and B may also be determined based on A and / or other information.

In addition, the term "and / or" in this article is just an association relationship that describes the related objects, indicating that there can be three relationships, for example, A and / or B, which can mean: A exists alone, A and B exist at the same time, There are three cases of B alone. In addition, the character "/" in this article generally indicates that the related objects before and after are in an "or" relationship.

Those of ordinary skill in the art may realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application of the technical solution and design constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and conciseness of the description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a division of logical functions. In actual implementation, there may be other divisions, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application essentially or part of the contribution to the existing technology or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to enable a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes .

The above is only the specific implementation of this application, but the scope of protection of this application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A chip-based PUF structure is characterized in that it includes a first electrode matrix and a second electrode matrix, and a capacitance matrix is formed between the first electrode matrix and the second electrode matrix to achieve physical non-cloning of the chip;

The first electrode matrix is arranged in the chip package;

An overlapping area is formed between the first electrode matrix and the second electrode matrix;

The electrodes in the first electrode matrix are connected to the internal circuit of the chip;

The electrodes in the second electrode matrix are connected at a fixed level.
The chip-based PUF structure according to claim 1, wherein the fixed level of electrode connection in the second electrode matrix comprises:

The electrodes in the second electrode matrix are connected to the same fixed level.
The chip-based PUF structure according to claim 1 or 2, wherein the chip internal circuit includes a capacitance detection circuit, and the capacitance detection circuit is used to detect a capacitance value of the capacitance matrix.
The chip-based PUF structure according to claim 3, wherein the connection between the electrodes in the first electrode matrix and the internal circuit of the chip comprises: the electrodes in the first electrode matrix and the capacitance detection circuit connection.
The chip-based PUF structure according to claim 3 or 4, wherein the capacitance detection circuit includes a multiplexer.
The chip-based PUF structure according to any one of claims 1 to 5, wherein the second electrode matrix is provided in the chip package.
The chip-based PUF structure according to claim 6, wherein the first electrode matrix and the second electrode matrix are provided on the same component in the chip package.
The chip-based PUF structure according to claim 7, wherein the arrangement of the first electrode matrix and the second electrode matrix on the same component in the chip package includes:

The first electrode matrix and the second electrode matrix are arranged on the same chip; or

The first electrode matrix and the second electrode matrix are arranged on the same substrate.
The chip-based PUF structure according to claim 6, wherein the first electrode matrix and the second electrode matrix are disposed on different components in the chip package.
The chip-based PUF structure according to claim 9, wherein the arrangement of the first electrode matrix and the second electrode matrix on different components in the chip package includes:

The first electrode matrix is provided on the first chip, and the second electrode matrix is provided on the second chip.
The chip-based PUF structure of claim 10, wherein the first electrode matrix is disposed on the first chip, and the second electrode matrix is disposed on the second chip includes:

The first electrode matrix and the second electrode matrix are respectively disposed on two adjacent surfaces of the first chip and the second chip.
The chip-based PUF structure according to claim 9, wherein the arrangement of the first electrode matrix and the second electrode matrix on different components in the chip package includes:

The first electrode matrix is provided on the chip, and the second electrode matrix is provided on the substrate.
The chip-based PUF structure according to claim 12, wherein the first electrode matrix is disposed on the chip, and the second electrode matrix is disposed on the substrate including:

The first electrode matrix is arranged on the lower surface of the chip;

The second electrode matrix is provided on the upper surface of the substrate.
The chip-based PUF structure according to claim 9, wherein the arrangement of the first electrode matrix and the second electrode matrix on different components in the chip package includes:

The first electrode matrix is provided on a substrate, and the second electrode matrix is provided on another substrate.
The chip-based PUF structure according to any one of claims 1 to 5, wherein the second electrode matrix is provided on a circuit board, and the circuit board and the chip package are connected.
The chip-based PUF structure according to claim 15, wherein the first electrode matrix is provided on a substrate.
The chip-based PUF structure according to claim 15, wherein the first electrode matrix is provided on the chip.
The chip-based PUF structure according to claim 17, wherein the first electrode matrix is provided on the lower surface of the chip;

The second electrode matrix is provided on the upper surface of the circuit board.
The chip-based PUF structure according to any one of claims 9 to 18, further comprising a filler;

The filler is disposed between the first electrode matrix and the second electrode matrix;

The filler is an insulating material.
The chip-based PUF structure according to claim 19, wherein dielectric particles are provided in the insulating material.
A chip-based PUF method, applied to the chip-based PUF structure according to any one of claims 1 to 20, characterized in that it includes:

Detecting the capacitance matrix formed between the first electrode matrix and the second electrode matrix;

The chip identity information matrix is obtained from the capacitance matrix.
The chip-based PUF method according to claim 21, wherein the obtaining the identity information matrix of the chip from the capacitance matrix includes:

Calculating an average value of the capacitance values in the capacitance matrix;

The difference between the capacitance matrix and the average value is calculated to obtain the identity information matrix of the chip.