WO2020094959A1

WO2020094959A1 - Power electronic module

Info

Publication number: WO2020094959A1
Application number: PCT/FR2019/052605
Authority: WO
Inventors: Menouar Ameziani; Hadi ALAWIEH
Original assignee: Institut Vedecom
Priority date: 2018-11-07
Filing date: 2019-11-04
Publication date: 2020-05-14
Also published as: FR3088138A1; FR3088138B1

Abstract

The module comprises at least one substrate (SUB_L) and first and second switching sections forming a switching bridge branch, the switching sections comprising in equal number at least one first electronic chip (T2_HS) and a second electronic chip (T1_LS), each having first and second electrode faces respectively supporting first and second power electrodes (S, D), and the substrate comprising a conductive layer (CH_L), on which the chips are implanted. According to the invention, the first and second chips are implanted head-to-end, the first chip being fixed on the conductive layer by its first face and the second chip being fixed on the conductive layer by its second face, and the second face of the first chip and the first face of the second chip respectively being connected to first and second DC bus bars (DC-, DC+).

Description

DESCRIPTION

TITLE: ELECTRONIC POWER MODULE

! The present invention claims priority from French application 1871394 filed on November 7, 2018, the content of which (text, drawings and claims) is hereby incorporated by reference.

The invention relates generally to the field of power electronics. More particularly, the invention relates to an electronic power module for the production of electronic power switching devices such as inverters and power converters, but not exclusively. The invention also relates to an electronic power switching device incorporating the above-mentioned electronic power module.

[0003] Electronic power switching devices are very present in many fields of activity such as transport, industry, lighting, heating, etc. With the desired energy transition to renewable energy sources that produce less CO2 emissions, power electronics are set to become more widespread and must respond to growing economic and technological constraints.

The various constraints applying to electronic power devices have led to a modular architecture of switching bridges. Thus, an elementary power switching module, called "power module", which is corresponding to a switching branch, or single-phase inverter, is frequently used, several power modules being associable in parallel to pass more current or to form a multi-phase inverter .

The new large gap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN) and diamond, have become major players in the power electronics industry. Silicon carbide in particular is expected to gradually replace silicon in the coming years in integrated power electronic components operating above 1000 Volts. These large gap semiconductors have an electric field of high breakdown, high switching speed and high thermal conductivity which give them excellent power switching capabilities. These new semiconductors now make it possible to have electronic power components which operate at higher voltages, temperatures and switching frequencies, and which allow higher current densities.

In a power module, special attention must be paid to reducing the inductance of the switching loop, in particular to protect the module against potentially destructive overvoltages, limit electromagnetic radiation and reduce the heat generated.

The switching loop is essentially formed by the connection links through the DC bus bars, the substrate usually of DBC type (for "Direct Bond Copper" in English) and the wired electrical interconnections called "wire bonding ”in English. The value of the inductance of the switching loop is proportional to the area of the loop. The architecture of the power module must therefore be designed so as to reduce the area of the switching loop as much as possible.

In US2014 / 0084993A1, there is proposed an electronic power device comprising first and second switching branches. The first switching branch includes first and second transistors and first and second diodes. The second switching branch includes third and fourth transistors and third and fourth diodes. The first transistor is juxtaposed with the second transistor in a first direction and is juxtaposed with the fourth transistor in a second direction. The third transistor is juxtaposed with the fourth transistor in the first direction and is juxtaposed with the second transistor in the second direction. A first voltage is applied to electrodes of the first and third transistors. A voltage of opposite polarity to the first voltage is applied to electrodes of the second and fourth transistors.

It now seems desirable to propose a power module architecture which is optimized in particular for a maximum reduction of the switching loop inductance and electromagnetic radiation. According to a first aspect, the invention relates to an electronic power module comprising at least a first substrate and first and second switching sections forming a switching bridge branch, the first and second switching sections comprising respectively, in equal number, at least a first electronic chip and a second electronic switch chip and being connected respectively to a first continuous power bar bus and to a second continuous power bar bus, the first and second electronic chips each comprising first and second electrode faces respectively supporting first and second power electrodes, and the first substrate comprising a first conductive layer on which the electronic chips are implanted and supporting a switching output terminal of the electronic power module. According to the invention, the first and second electronic chips are implanted head to tail on the first conductive layer, the first electronic chip being fixed on the first conductive layer by its first electrode face and the second electronic chip being fixed on the first conductive layer by its second electrode face, and the second electrode face of the first electronic chip and the first electrode face of the second electronic chip being connected respectively to the first and second bus bus.

According to a particular embodiment, the electronic power module comprises, in equal number, a first plurality of first electronic chips and a second plurality of second electronic chips, the first and second electronic chips being implanted on the first conductive layer being arranged in first and second rows, the first and second electronic chips being implanted alternately in the first and second rows and with first and second adjacent electronic chips implanted in a row opposite respectively of second and first adjacent electronic chips located in the other row.

According to a particular characteristic, the first substrate comprises a second conductive layer isolated from the first conductive layer by a first dielectric layer, and a first heat sink attached to the second conductive layer.

According to another particular characteristic, the first substrate is of the DBC type.

According to yet another particular characteristic, the electronic power module comprises third and fourth conductive layers stacked on the first conductive layer and forming respectively the first and second bus continuous power bar, the first, third and fourth conductive layers being insulated from each other by second and third dielectric layers, and each second electrode face of the first electronic chip and each first electrode face of the second electronic chip being connected respectively to the first and second bus bus bar by a wire electrical interconnection.

According to another particular embodiment, the electronic power module comprises a second substrate comprising fifth and sixth conductive layers in which the first and second DC bus bars are formed respectively, the fifth and sixth conductive layers being isolated from each other by a fourth dielectric layer, and each second electrode face of the first electronic chip being fixed to the first bus continuous power bar through a conductive pad arranged in the sixth conductive layer and metallized vias arranged in the fourth layer dielectric and each first electrode face of the second electronic chip being fixed directly to the second bus continuous power bar.

According to a particular characteristic, the second substrate comprises a seventh conductive layer isolated from the fifth conductive layer by a fifth dielectric layer, and a second heat sink fixed on the seventh conductive layer.

According to another particular characteristic, the second substrate is of the DBC type.

According to yet another particular characteristic, the electronic chips of electronic switches are MOSFET type transistors. The invention also relates to an electronic power switching device comprising at least one electronic power module as briefly described above.

Other advantages and characteristics of the present invention will appear more clearly on reading the detailed description below of several particular embodiments of the invention, with reference to the accompanying drawings, in which:

[Fig. 1] is a simplified electrical diagram of an exemplary embodiment of a power module according to the invention;

[Fig. 2] is a plan view showing a front electrode face of an electronic chip of a MOSFET transistor, as an electronic switch that can be integrated into a power module according to the invention;

[Fig. 3] is a plan view showing a rear electrode face of an electronic chip of a MOSFET transistor, as an electronic switch that can be integrated into a power module according to the invention;

[Fig. 4] is a first schematic perspective view showing architectural concepts relating to different embodiments of the power module according to the invention;

[Fig. 5] is a second schematic perspective view showing architectural concepts relating to different embodiments of the power module according to the invention;

[Fig. 6] is a third schematic perspective view showing architectural concepts relating to different embodiments of the power module according to the invention;

[Fig. 7] is a fourth schematic perspective view showing architectural concepts relating to different embodiments of the power module according to the invention;

[Fig. 8] is a schematic plan view of a particular embodiment of the power module according to the invention;

[Fig. 9] is a schematic sectional view of the particular embodiment of FIG. 8 of the power module according to the invention; [Fig. 10] is a schematic plan view of another particular embodiment of the power module according to the invention; and

[Fig.1 1] is a schematic sectional view of the particular embodiment of FIG. 10 of the power module according to the invention.

First and second particular embodiments MP1 and MP2 of the power module according to the invention are described here with reference to Figs.8, 9, and Figs.10, 1 1, respectively. Figs. 1 to 7 schematically show architectural concepts and structures relating to different embodiments of the invention.

As shown by the electrical diagram in principle of Fig .1, an MP power module according to the invention comprises at least one branch of a switching bridge (single-phase inverter) and includes a high FIS switching section, called " high side "in English, and a low LS switching section, called" low side "in English.

In general, according to the invention, the high HS and low LS switching sections have substantially the same configuration and include the same number of electronic switches, each HS, LS switching section, comprising at least one switch. electronic.

In the power module MP of Fig.1, the high HS and low LS switching sections each include two electronic switches mounted in parallel, T1 HS, T2HS and T1 LS, T2LS, respectively. In general, in accordance with the invention, the high HS and low LS switching sections may include the same number of electronic switches connected in parallel. The number of electronic switches mounted in parallel will depend in particular on the electrical power requested from the power module.

In general, in the present invention, the electronic switches may be in particular transistors of the MOSFET, IGBT, GTO type and transistors of the large gap semiconductor type such as SiC, GaN, HEMT and others.

As is known to those skilled in the art, it is generally advantageous to mount a Schottky diode in antiparallel with each of the switches electronic, so as to ensure rapid switching recovery and protect the switches. Certain embodiments of the invention may therefore incorporate Schottky diodes mounted in antiparallel with the electronic switches.

In the exemplary embodiments described here, the electronic switches are MOSFET transistors of the SiC type. The transistors are considered here as having efficient PIN intrinsic diodes (PIN for “Positive - Intrinsic - Negative” in English), so that the Schottky diodes mounted in antiparallel are not provided in these embodiments.

As shown in Fig .1, the PM power module has three PHS, PLS and Ps power connection points connected respectively to a DC + continuous power bus bus of positive polarity, a power bus bus DC- electric current of negative polarity and a switched output terminal OUT of the module. The connection point Ps is a common connection point between the high HS and low LS switching sections.

In the high switching section HS, drain electrodes D of the transistors T1 HS and T2HS are connected together and connected to the connection point PHS. Source electrodes S of transistors T1 HS and T2HS are connected together and connected to the common connection point Ps. Gate electrodes G of transistors T1 HS and T2HS are connected together and connected to a control terminal Cd _H s of the module MP power.

In the low LS switching section, drain electrodes D of the transistors T1 LS and T2LS are connected together and connected to the common connection point Ps. Source electrodes S of the transistors T1 LS and T2LS are connected together and connected at the PLS connection point. Grid electrodes G of the transistors T1 LS and T2LS are connected together and connected to a control terminal Cd _L s of the power module MP.

In the present invention, it is recommended to use electronic switches having first and second power electrodes located respectively on first and second opposite faces of the chips. More specifically, in the case of a MOSFET transistor, the source electrode is located on a first face of the chip, namely, the metallized front face, and the drain electrode is located on the other face of the chip, namely, the metallized rear face.

Figs.2 and 3 show by way of example an implantation of electrodes on the front and rear faces of a chip, as available from suppliers of semiconductor components for MOSFET transistors of SiC type. Such an implantation of electrodes is suitable for the transistors T1 HS, T2HS, and T1 LS, T2LS, of the power module MP.

As shown in FIG. 2, the front face F _A v of the transistor chips T1 HS, T2HS, and T1 LS, T2LS, comprises three metal blocks of electrode PS1, PS2 and PG, provided for connection by soldering or brazing. The blocks PS1 and PS2 correspond to the source electrode S. The block PG corresponds to the gate electrode G. FIG. 3 shows the rear face FAR of the transistor chips T1 HS, T2HS, and T1 LS, T2LS, which comprises a metallic pad of PD electrode corresponding to the drain electrode D and provided for a connection by welding or brazing.

Fig. 4 shows schematically the layout and electrical connection configuration of the transistors T1 HS, T2HS, and T1 LS, T2LS, in the power module MP.

As clearly seen in Fig.4, the transistors T1 HS, T2HS, and T1 LS, T2LS, are here located at the four corners of a rectangle, or square, on the same SUB substrate. The substrate SUB is here of the DBC type and comprises a central dielectric layer CD sandwiched between high CFI and low CL conductive layers. The conductive layers CFI and CL are made of copper. The high conductive layer CFI supports the common connection point Ps of the power module MP, common connection point Ps which corresponds to the switched output terminal OUT of the module MP.

The two transistors of the same switching section are located at diagonally opposite corners of the rectangle. Thus, the transistors T1 HS and T2HS are located respectively in diagonally opposite corners C3 and C1 of the rectangle and the transistors T1 LS and T2LS are located respectively in diagonally opposite corners C2 and C4 of the rectangle.

According to the invention, as described above with reference to Figs.2 and 3, transistor chips are used with an implantation of the power electrodes on the two faces. This characteristic of the invention makes it possible to minimize the lengths of the connection links and, correspondingly, the areas of the switching loops.

For the transistors T1 HS and T2HS, diagonally opposite, the drain electrodes S, present on the front faces (cf. FIG. 2) of the chips, are soldered on the high conductive layer CH of the substrate SUB. The source electrodes D, present on the rear faces (see Fig. 3) of the chips, are connected to the bus DC DC power supply bar.

The diagonally opposite chips of the T1 LS and T2LS transistors are implanted on the substrate SUB head to tail with respect to the chips of the T1 HS and T2HS transistors (that is to say, with a 180 degree reversal). The drain electrodes D, present on the rear faces (cf. FIG. 3) of the chips, are welded on the high conductive layer CH of the substrate SUB. The source electrodes S, present on the front faces (cf. Fig. 2) of the chips, are connected to the bus DC continuous power supply bar.

The different possible current flow paths T12, T14, T34 and T32 between the transistors T1 HS, T2HS, T1 LS and T2LS are shown in Fig.4. It will be noted that the directions of current flow are reversed in the parallel paths corresponding to two opposite sides of the rectangle, which introduces a phenomenon of self-compensation of the electromagnetic radiation which reduces the electromagnetic emissions of the power module MP. Thus, paths T12 and T34 have opposite directions of current flow and the same applies to paths T14 and T32.

Fig.5 shows schematically by way of example the surface of the switching loop for the current flow path T34 between the transistors T1 HS and T2LS. With the layout and electrical connection configuration of the transistors described above, the surface of the switching loop is greatly reduced compared to the solutions known in the prior art. Indeed, as it appears in the illustrative example of Fig.5, the width La of the switching loop can be small given that the thickness of the transistor chips which is only a few hundred micrometers. The length Lo of the switching loop is determined by the spacing between the transistor chips. Figs.6 and 7 show other examples of architecture corresponding respectively to power modules MPa and MPb.

The power module MPa is a minimal embodiment with a single transistor THS, TLS, per switching section HS, LS.

The MPb power module is an embodiment with three transistors in parallel per switching section. The high HS switching section includes the transistors T1 HS, T2HS and T3HS. The LS low switching section includes the T1 LS, T2LS and T3LS transistors.

As well illustrated by the embodiment of Fig.7, generally in the present invention, the chips of the transistors are implanted on the substrate SUB by being distributed over two substantially parallel rows R1 and R2. The row R1 here comprises the transistors T1 LS, T2HS and T3LS and the row R2 comprises the transistors T1 HS, T2LS and T3HS. In the same row R1 or R2, the chips are implanted alternately, a chip of a switching section being followed by a chip of the other switching section, and two adjacent chips are implanted head to tail. In addition, the chips opposite in rows R1 and R2 are installed head to tail.

With reference to FIGS. 8 and 9, the architecture of the power module MP1 is now described in detail, as the first particular embodiment of the present invention.

In the architecture of the power module MP1, the transistors T1 HS, T2HS, T1 LS and T2LS are soldered onto the high conductive layer CH of the substrate SUB of the DBC type, as described above with reference to FIGS. 4 and 5.

As shown in Figs.8 and 9, the upper conductive layer CH comprises a majority portion, supporting the connection (Ps) to the switched output terminal OUT, on which the source electrodes S of the transistors T1 HS are welded and T2HS and the drain electrodes D of the transistors T1 LS and T2LS. Four conductive gate control tracks PG1 HS, PG2HS, PG1 LS and PG2LS are formed in the high CH conductive layer for connection of the gate electrodes of the transistors T1 HS, T2HS, T1 LS and T2LS, respectively.

A DIS heat sink is fixed, in close thermal contact, against the low conductive layer CB of the SUB substrate. The dielectric layer CD has a thickness which is reduced to the minimum required so as to facilitate the evacuation of the calories emitted by the transistors T1 HS, T2HS, T1 LS and T2LS towards the heat sink DIS.

As clearly visible in FIG. 4B, the DC + and DC- continuous power supply bus bars are formed respectively by conductive layers CS1 and CS2 made of copper. The conductive layers CS1 and CS2 are stacked and laminated on the substrate SUB, above the high conductive layer CH, being electrically insulated by dielectric layers DS1 and DS2. The dielectric layer DS1 is interposed between the high conductive layer CH and the conductive layer CS1. The dielectric layer DS2 is interposed between the conductive layer CS1 and the conductive layer CS2.

WB welded electrical interconnection wires are used to connect the transistors T1 HS, T2HS, T1 LS and T2LS to the conductive layers CS1 and CS2 corresponding respectively to the DC + and DC- bus bars. The drain electrodes D of the transistors T1 HS and T2HS are connected by welded interconnection wires WB to the conductive layer CS1. The source electrodes S of the transistors T1 LS and T2LS are connected by welded electrical interconnection wires WB to the conductive layer CS2.

As clearly visible in Figs.8 and 9, the conductive tracks for gate control PG1 HS, PG2HS, PG1 LS and PG2LS, for the electrical connection of the gate electrodes G of transistors T1 HS, T2HS, T1 LS and T2LS , are arranged in the high CH conductive layer by removal of metal, typically by known techniques of photolithography and wet etching.

The gate electrodes G of the transistors T1 HS and T2HS are welded directly to the conductive tracks for gate control PG1 HS, PG2HS, respectively. The gate electrodes G of the transistors T1 LS and T2LS are connected to the conductive gate control tracks PG 1 LS and PG2LS, respectively, by means of welded electrical interconnection wires WB.

Referring to Figs.10 and 11, it is now described in detail the architecture of the power module MP2, as a second particular embodiment of the present invention. In the architecture of the power module MP2, the transistors T1 HS, T2HS, T1 LS and T2LS are soldered between a lower substrate SUBL and an upper substrate SUBH.

The lower substrate SUB _L , of DBC type, is analogous to the lower substrate SUB of the power module MP1. The transistors T 1 HS, T2HS, T1 LS and T2LS are soldered onto the high conductive layer CH _L of the substrate SUB _L.

As shown in Figs. 10 and 11, the upper conductive layer CH _L comprises a majority portion, supporting the connection (Ps) to the switched output terminal OUT, on which the source electrodes S of the transistors T1 HS are welded. and T2HS and the drain electrodes D of the transistors T1 LS and T2LS. Two conductive gate control tracks PL1 HS and PL2HS are formed in the high conductive layer CH _L for the connection of the gate electrodes G of the transistors T1 HS and T2HS, respectively. The gate electrodes G of the transistors T1 HS and T2HS are soldered directly to the conductive gate control tracks PL1 HS and PL2HS, respectively.

A DIS _L heat sink is fixed, in close thermal contact, against the low conductive layer CB _L of the lower substrate SUB _L. The dielectric layer CD _L has a thickness which is reduced to the minimum required so as to facilitate the evacuation of the calories emitted by the transistors T1 HS, T2HS, T1 LS and T2LS towards the heat sink DIS _L.

The SUB _H upper substrate is also of the DBC type and comprises three conductive layers CBH, CIH and CHH and two dielectric layers CD1 H and CD2H. The conductive layers CB _H and CH _H are respectively low and high conductive layers of the upper substrate SUB _H. The conductive layer CI _H is an intermediate conductive layer of the upper substrate SUB _H. The dielectric layer CD1 _H is interposed between the low conductive layer CB _H and the intermediate conductive layer CI _H. The dielectric layer CD2 _H is interposed between the intermediate conductive layer CI _H and the high conductive layer CB _H.

A DIS _H heat sink is fixed, in close thermal contact, against the high conductive layer CH _H of the substrate SUB _H. The dielectric layers CD1 _H and CD2 _H have thicknesses which are reduced to the minimum required in order to facilitate the evacuation of the calories emitted by the transistors T1 HS, T2HS, T1 LS and T2LS towards the heat sink DISH.

The low conductive layer CBH comprises a majority portion, corresponding to the DC bus power bus DC-, on which are welded the source electrodes S of the transistors T1 LS and T2LS and the drain electrodes D of the transistors T1 HS and T2HS. Two conductive gate control tracks PL1 LS and PL2LS are formed in the low conductive layer CBH for the connection of the gate electrodes G of the transistors T1 LS and T2LS, respectively. Only the conductive gate control track PL1 LS is visible in Fig. 1 1. The location of the conductive gate control tracks PL1 LS and PL2LS above the gates G of the transistors T1 LS and T2LS is shown in a thin line in FIG. 10. The gate electrodes G of the transistors T1 LS and T2LS are welded directly to the conductive gate control tracks PL1 LS and PL2LS, respectively.

The drain electrodes D of the transistors T1 HS and T2HS are electrically connected to the intermediate conductive layer CIH, corresponding to the bus DC power supply bus DC +, through conductive connection pads of drain and metal vias. A conductive drain connection pad and a plurality of vias are formed for the connection of each of the drain electrodes D of the transistors T1 HS and T2HS. Each drain electrode D is welded to a conductive drain connection pad. The conductive drain connection pad C2HS and vias V2HS for the transistor T2HS are visible in Fig. 1 1. The drain connection conductive pads are formed in the low conductive layer CBH and are electrically connected to the intermediate conductive layer CIH by the vias formed in the dielectric layer CD1 H.

The conductive drain connection pads can be formed in the low conductive layer CBH by metal removal, typically by known techniques of photolithography and wet etching. The vias can be formed by drilling and metallization.

Of course, the invention is not limited to the particular embodiments which have been described here by way of example. The skilled person, depending on the applications considered, may make various modifications and variants falling within the scope of protection of the invention.

Claims

[Claims 1]! Electronic power module comprising at least a first substrate (SUB) and first and second switching sections (HS, LS) forming a switching bridge branch, said first and second switching sections (HS, LS ) comprising, in equal number, respectively, at least a first electronic chip (THS) and a second electronic chip (TLS) of electronic switches and being connected respectively to a first bus DC bus (DC +) and to a second bus continuous power bar (DC-), said first and second electronic chips (THS, TLS) each comprising first and second electrode faces (FAV, FAR) respectively supporting first and second power electrodes (S, D) , and said first substrate (SUB) comprising a first conductive layer (CH) on which are implanted said electronic chips (THS, TLS) and supporting a sol terminal switching rtie (OUT, PS) of said electronic power module, characterized in that said first and second electronic chips (THS, TLS) are installed head to tail on said first conductive layer (CH), said first electronic chip (THS) being fixed to said first conductive layer (CH) by its first electrode face (FAV, S) and said second electronic chip (TLS) being fixed to said first conductive layer (CH) by its second electrode face (FAR, D ), and said second electrode face (FAR, D) of said first electronic chip (THS) and said first electrode face (FAV, S) of said second electronic chip (TLS) being connected respectively to said first and second bus continuous power bar (DC +, DC-).

[Claims 2] Electronic power module according to claim 1, characterized in that it comprises, in equal number, a first plurality of said first electronic chips (T1 HS, T2HS, T3HS) and a second plurality of said second electronic chips (T1 LS, T2LS, T3LS), said first and second electronic chips (T1 HS, T2HS, T3HS; T1 LS, T2LS, T3LS) being implanted on said first conductive layer (CH) by being arranged in first and second rows ( R1, R2), said first and second electronic chips (T1 HS, T2HS, T3HS; T1 LS, T2LS, T3LS) being alternately implanted (T1 LS, T2HS, T3LS; T1 HS, T2LS, T3HS) in said first and second rows (R1, R2) and with first and second adjacent electronic chips (T2HS; T1 LS, T3LS) implanted in a said row (R1) opposite respectively second and first adjacent electronic chips (T2LS; T1 HS, T3HS) located in the other row (R2).

[Claims 3] Electronic power module according to claim 1 or 2, characterized in that said first substrate (SUB) comprises a second conductive layer (CB) isolated from said first conductive layer (CH) by a first dielectric layer (CD) , and a first heat sink (DIS) fixed on said second conductive layer (CB).

[Claims 4] Electronic power module according to claim 3, characterized in that said first substrate (SUB, SUB _L ) is of the DBC type.

[Claims 5] Electronic power module according to any one of claims 1 to 4, characterized in that it comprises third and fourth conductive layers (CS1, CS2) stacked on said first conductive layer (CH) and respectively forming said first and second bus DC bus (DC +, DC-), said first, third and fourth conductive layers (CH, CS1, CS2) being isolated from each other by second and third dielectric layers (DS1, DS2), and each said second electrode face (FAR, D) of first electronic chip (T1 HS, T2HS) and each said first electrode face (FAV, S) of second electronic chip (T1 LS, T2LS) being connected respectively to said first and second bus continuous power bar (DC +, DC-) by an electrical interconnection wire (WB).

[Claims 6] Electronic power module according to any one of claims 1 to 4, characterized in that it comprises a second substrate (SUBH) comprising fifth and sixth conductive layers (CIH, CBH) in which said said are formed respectively first and second DC busbar bus (DC +, DC-), said fifth and sixth conductive layers (CIH, CBH) being isolated from each other by a fourth dielectric layer (CD1 H), and each said second face electrode (FAR, D) of first electronic chip (T1 HS, T2HS) being fixed to said first bus continuous power bar (DC +) through a conductive pad (C2 _HS ) arranged in said sixth conductive layer (CB _H ) and metallized vias (V2 _HS ) arranged in said fourth dielectric layer (CD1 H) and each said first electrode face (FAV, S) of second electronic chip (T1 _LS , T2 _LS ) being fixed directly to said second bus bus d '' continuous supply (DC-).

[Claims 7] Electronic power module according to claim 6, characterized in that said second substrate (SUB _H ) comprises a seventh conductive layer (CFI _H ) isolated from said fifth conductive layer (CI _H ) by a fifth dielectric layer (CD2 _H ), and a second heat sink (DIS _H ) fixed on said seventh conductive layer (CFIH).

[Claims 8] Electronic power module according to claim 6 or 7, characterized in that said second substrate (SUB _H ) is of the DBC type.

[Claims 9] Electronic power module according to any one of claims 1 to 8, characterized in that said electronic chips of electronic switches are MOSFET type transistors.

[Claims 10] Electronic power switching device characterized in that it comprises at least one electronic power module (MP, MPa, MPb, MP1, MP2) according to any one of claims 1 to 9.