WO2020094863A3 - Dispositif de calcul d'une transformee de fourier analogique - Google Patents

Dispositif de calcul d'une transformee de fourier analogique Download PDF

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Publication number
WO2020094863A3
WO2020094863A3 PCT/EP2019/080745 EP2019080745W WO2020094863A3 WO 2020094863 A3 WO2020094863 A3 WO 2020094863A3 EP 2019080745 W EP2019080745 W EP 2019080745W WO 2020094863 A3 WO2020094863 A3 WO 2020094863A3
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WO
WIPO (PCT)
Prior art keywords
components
calculating
fourier transform
functions
analog fourier
Prior art date
Application number
PCT/EP2019/080745
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English (en)
Other versions
WO2020094863A2 (fr
Inventor
Patrick Garrec
Jean-Michel Hode
Victor VAILLANT
Original Assignee
Thales
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Thales filed Critical Thales
Priority to EP19804669.0A priority Critical patent/EP3877872A2/fr
Priority to US17/291,258 priority patent/US20220004595A1/en
Publication of WO2020094863A2 publication Critical patent/WO2020094863A2/fr
Publication of WO2020094863A3 publication Critical patent/WO2020094863A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements
    • G06J1/005—Hybrid computing arrangements for correlation; for convolution; for Z or Fourier Transform

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Algebra (AREA)
  • Discrete Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Fuzzy Systems (AREA)
  • Evolutionary Computation (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Complex Calculations (AREA)

Abstract

Le dispositif transformant un signal d'entrée analogique à N composantes x(0), x(1)... x(N-1) en un signal de sortie à N composantes X(0), X(1)... X(N-1) fonctions desdites composantes x(0), x(1)... x(N-1), ledit dispositif comportant des cellules élémentaires d'addition et/ou de soustraction chaînées selon une architecture de type papillon pour réaliser lesdites fonctions, chaque cellule élémentaire comporte un opérateur réalisant une division par deux conditionnelle du résultat de l'opération d'addition (31) ou de soustraction effectué, la condition étant la saturation (33) dudit opérateur.
PCT/EP2019/080745 2018-11-08 2019-11-08 Dispositif de calcul d'une transformee de fourier analogique WO2020094863A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19804669.0A EP3877872A2 (fr) 2018-11-08 2019-11-08 Dispositif de calcul d'une transformee de fourier analogique
US17/291,258 US20220004595A1 (en) 2018-11-08 2019-11-08 Device for calculating an analog fourier transform

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1871456A FR3088451A1 (fr) 2018-11-08 2018-11-08 Dispositif de calcul d'une transformee de fourier analogique
FR1871456 2018-11-08

Publications (2)

Publication Number Publication Date
WO2020094863A2 WO2020094863A2 (fr) 2020-05-14
WO2020094863A3 true WO2020094863A3 (fr) 2020-07-02

Family

ID=67660133

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2019/080745 WO2020094863A2 (fr) 2018-11-08 2019-11-08 Dispositif de calcul d'une transformee de fourier analogique

Country Status (4)

Country Link
US (1) US20220004595A1 (fr)
EP (1) EP3877872A2 (fr)
FR (1) FR3088451A1 (fr)
WO (1) WO2020094863A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11531497B2 (en) * 2020-02-19 2022-12-20 National Institute of Technology Data scheduling register tree for radix-2 FFT architecture

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000073872A2 (fr) * 1999-05-26 2000-12-07 Infineon Technologies Ag Mecanisme de support de materiel a transformation de fourier rapide (fft) a virgule flottante bloc pour processeur de signaux numeriques a virgule fixe

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481488A (en) * 1994-10-21 1996-01-02 United Microelectronics Corporation Block floating point mechanism for fast Fourier transform processor
US20080071848A1 (en) * 2006-09-14 2008-03-20 Texas Instruments Incorporated In-Place Radix-2 Butterfly Processor and Method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000073872A2 (fr) * 1999-05-26 2000-12-07 Infineon Technologies Ag Mecanisme de support de materiel a transformation de fourier rapide (fft) a virgule flottante bloc pour processeur de signaux numeriques a virgule fixe

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
BIDET E ET AL: "A FAST SINGLE-CHIP IMPLEMENTATION OF 8192 COMPLEX POINT FFT", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 30, no. 3, March 1995 (1995-03-01), pages 300 - 305, XP000502815, ISSN: 0018-9200, DOI: 10.1109/4.364445 *
JOHANSSON S ET AL: "Wordlength optimization of a pipelined FFT processor", CIRCUITS AND SYSTEMS, 2000. 42ND MIDWEST SYMPOSIUM ON AUGUST 8 - 11, 1999, PISCATAWAY, NJ, USA,IEEE, vol. 1, 8 August 1999 (1999-08-08), pages 501 - 503, XP010510678, ISBN: 978-0-7803-5491-3 *

Also Published As

Publication number Publication date
WO2020094863A2 (fr) 2020-05-14
FR3088451A1 (fr) 2020-05-15
EP3877872A2 (fr) 2021-09-15
US20220004595A1 (en) 2022-01-06

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