WO2020093271A1

WO2020093271A1 - Gating circuit and method

Info

Publication number: WO2020093271A1
Application number: PCT/CN2018/114367
Authority: WO
Inventors: 洪宗会; 高鹏; 张广飞
Original assignee: 北京晶视智能科技有限公司
Priority date: 2018-11-07
Filing date: 2018-11-07
Publication date: 2020-05-14

Abstract

A gating circuit (200) and a gating method. The gating circuit (200) comprises: a system clock signal input end (201) used to receive a system clock signal having a clock period T_clk; a first controlled signal input end (203) used to receive a first controlled signal; a second controlled signal input end (205) used to receive a second controlled signal; a gating signal output end (207) used to output a gating signal for gating input of the first controlled signal and input of the second controlled signal; and a gating logic generation module (209) used to count, on the basis of the system clock signal, the number of valid controlled signal clock cycles in which the first controlled signal and the second controlled signal are both valid within a current gating period of the gating signal, and to adjust, on the basis of the number of the valid controlled signal clock cycles, the number of subsequent valid gating signal clock cycles within the next gating cycle of the gating signal. The gating circuit (200) slows the speed at which power consumption increases when a circuit such as a TPU executes computer instructions.

Description

Gating circuit and gating method

Technical field

The present disclosure relates to digital circuits, and in particular to a gate control circuit and a gate control method.

Background technique

TPU (Tensor Processing Unit) is a kind of processor (chip) dedicated to machine learning, which is used to process various machine learning algorithms such as convolution operations. In order to ensure performance, the TPU includes many calculation units, which can pipeline calculation instructions.

The TPU of the prior art usually includes several computing arrays, and each computing array includes several computing units, also called EU (Execute Unit). Between the computing arrays and the EUs within the computing arrays, pipeline processing is used to execute respective data transmission instructions and data calculation instructions.

FIG. 1 shows a schematic diagram of the array structure of the prior art TPU. As shown in FIG. 1, the dpcmd (data transfer instruction) module in the TPU is used to control the execution of data transmission operations, and the eucmd (data calculation execution instruction) module in the TPU is used to control the execution of data calculation operations. The dpcmd module and eucmd module complete the entire operation of data transmission and calculation through the handshake signals valid and ready. The valid signal is the output of the dpcmd module, indicating that the current data is valid and can be used for data transmission; the ready signal is the output of the eucmd module, indicating that the current computing unit can receive data. If the valid signal and the ready signal are valid at the same time in one clock cycle (cycle), it means that a set of data (for example, 128 bytes) is successfully transmitted.

As shown in Figure 1, the TPU computing array and EU share a dpcmd module and eucmd module. Data and instructions are transferred from the first array to the last array in sequence, and from the first EU to the last EU in the array . The transfer of instructions and data within each array is parallel.

Therefore, when the computing task arrives, if all valid and ready signals continue to be valid, after the pipeline establishment time passes, all EUs will enter a continuous working state. The total number of stages in the pipeline is several cycles). Therefore, the macro power consumption of the TPU suddenly increases in a short time, and the instantaneous increase in power consumption will affect the stability of the power supply system of the TPU chip.

The same problem exists in other digital circuits that use handshake signals. Therefore, it is necessary to propose new technical solutions to slow down the speed of power consumption increase when the TPU and other circuits execute calculation instructions.

The above background content is only used to help understand this application, and does not mean that any content mentioned is recognized or recognized as part of the common general knowledge relative to this application.

Summary of the invention

An embodiment of the present disclosure provides a gating circuit, including:

The system clock signal input terminal is used to receive the system clock signal whose clock period is T _clk ;

The first controlled signal input terminal is used to receive the first controlled signal;

The second controlled signal input terminal is used to receive the second controlled signal;

The gate control signal output terminal is used to output a gate control signal that gates the first controlled signal input and the second controlled signal input;

Gating logic generation module, which is based on the system clock signal, statistics of the first controlled signal and the second controlled signal within the current gating cycle of the gating signal, the number of effective controlled signal clock cycles simultaneously valid based on the effective control The number of signal clock cycles to adjust the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal.

The above gating circuit also includes:

Common gate enable input, used to receive common gate enable signal;

The first AND gate is used to perform and operate the common gate enable signal and the first controlled signal, and output the gated first controlled signal;

The second AND gate is used to perform and operate the common gate enable signal and the second controlled signal, and output the gated second controlled signal;

The first multiplexing module is used to multiplex the first controlled signal and the gated first controlled signal;

A second multiplexing module for multiplexing the second controlled signal and the gated second controlled signal,

Wherein, when the common gating enable signal is valid, the first multiplexing module and the second multiplexing module respectively output the gated first controlled signal and the gated second controlled signal When the common gating enable signal is invalid, the first multiplexing module and the second multiplexing module output the first controlled signal and the second controlled signal, respectively.

In the above gate control circuit, the first controlled signal is the TPU data transmission ready signal, and the second controlled signal is the TPU data calculation ready signal.

In the above gating circuit, the gating logic generation module is also used to adjust the number of clock cycles of the next valid gating signal in the next gating cycle of the gating signal through the following steps:

Determine the total number of clock cycles included in the gating cycle;

Determine the clock cycle number adjustment step size and level number n, taking the clock cycle number adjustment step size as the basic unit, divide the gating cycle into n levels with the clock cycle number increasing sequentially;

If the number of clock cycles of the effective controlled signal is equal to the number of clock cycles of the current effective gating signal, the number of clock cycles of the next effective gating signal is adjusted to the number of clock cycles corresponding to the next stage with a larger cycle number

If the number of effective controlled signal clock cycles is less than the current effective gating signal clock cycles, then adjust the next effective gating signal clock cycles to the number of clock cycles corresponding to the corresponding level with a lower number of cycles,

Among them, the number of clock cycles of the next valid gating signal is less than or equal to the total number of clock cycles of the gating cycle.

In the above gating circuit, the clock period of the next gating signal is evenly distributed within the maximum effective continuous period of the first controlled signal and the second controlled signal.

An embodiment of the present disclosure provides a gating method, including:

Receive the system clock signal whose clock period is T _clk ;

Receive the first controlled signal;

Receive the second controlled signal;

Output a gating signal that gates the input of the first controlled signal and the input of the second controlled signal;

Based on the system clock signal, statistics of the first controlled signal and the second controlled signal, the number of effective controlled signal clock cycles simultaneously valid in the current gating cycle of the gating signal, and adjusting the gating based on the number of effective controlled signal clock cycles The number of clock cycles of the next valid gating signal within the next gating cycle of the signal.

The above gating method also includes:

Receive public gating enable signal;

It is used to operate and operate the common gated enable signal and the first controlled signal, and output the gated first controlled signal;

Used to operate the common gated enable signal and the second controlled signal, and output the gated second controlled signal;

Multiplexing the first controlled signal and the gated first controlled signal;

Multiplexing the second controlled signal and the gated second controlled signal,

Among them, when the public gating enable signal is valid, the gated first controlled signal and the gated second controlled signal are respectively output, and when the public gating enable signal is invalid, respectively output the first The controlled signal and the second controlled signal.

In the above gating method, the first controlled signal is a TPU data transmission ready signal, and the second controlled signal is a TPU data calculation ready signal.

The above gating method also includes adjusting the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal through the following steps:

Determine the total number of clock cycles included in the gating cycle;

If the number of clock cycles of the effective controlled signal is equal to the number of clock cycles of the current effective gating signal, the number of clock cycles of the next effective gating signal is adjusted to the number of clock cycles corresponding to the next stage with a larger number of cycles;

In the above gating method, the clock period of the next gating signal is evenly distributed within the maximum effective continuous period of the first controlled signal and the second controlled signal.

The above technical solutions of the present disclosure can slow down the speed at which the power consumption rises when circuits such as TPUs execute calculation instructions.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present disclosure. For those of ordinary skill in the art, without paying creative labor, other drawings may be obtained based on these drawings.

FIG. 1 is a schematic structural diagram of a data processing circuit in the prior art;

2 is a schematic structural diagram of a gate control circuit 200 according to an embodiment of the present disclosure;

3 is a schematic flowchart of a gating method according to an embodiment of the present disclosure;

FIG. 4 shows the beneficial effects of the gating scheme according to an embodiment of the present disclosure.

detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Those skilled in the art know that the embodiments of the present disclosure may be implemented as a system, device, device, method, or computer program product. Therefore, the present disclosure may be specifically implemented in the form of complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

As mentioned in the background section, in order to keep the power consumption of digital circuits stable, new technical solutions need to be proposed. The present disclosure is based on the concept of adding gating to handshake signals such as the valid and ready signals in the TPU, and achieves the goal of keeping the power consumption of digital circuits such as TPU stable. This will be described in detail below in conjunction with the drawings.

2 is a schematic structural diagram of a gate control circuit 200 according to an embodiment of the present disclosure.

As shown by the solid line box in FIG. 2, this example gating circuit 200 includes:

The system clock signal input terminal 201 is used to receive a system clock signal whose clock period is T _clk ;

The first controlled signal input terminal 203 is used to receive the first controlled signal;

The second controlled signal input terminal 205 is used to receive the second controlled signal;

The gate control signal output terminal 207 is used to output a gate control signal that gates the input of the first controlled signal and the input of the second controlled signal;

The gating logic generation module 209 is used to calculate the number of effective controlled signal clock cycles that are simultaneously valid within the current gating cycle of the gating signal based on the system clock signal, statistics of the first controlled signal and the second controlled signal, based on the effective received The number of clock cycles of the control signal to adjust the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal.

Optionally, as shown by the dotted box in FIG. 2, the gate control circuit 200 further includes:

The common gate enable input 211 is used to receive the common gate enable signal;

The first AND gate 213 is used to perform and operate the common gate enable signal and the first controlled signal, and output the gated first controlled signal;

The second AND gate 215 is used to perform and operate the common gate enable signal and the second controlled signal, and output the gated second controlled signal;

The first multiplexing module 217 is used to multiplex the first controlled signal (for example, the valid signal in FIG. 1) and the gated first controlled signal (for example, corresponding to the valid signal in FIG. 1 , Hereafter expressed by valid_out signal);

The second multiplexing module 219 is used to multiplex the second controlled signal (for example, the ready signal in FIG. 1) and the gated second controlled signal (for example, the ready signal in FIG. 1, In the text, it is represented by the ready_out signal),

Among them, when the common gating enable signal is valid, the first multiplexing module 217 and the second multiplexing module 219 respectively output the gated first controlled signal and the gated second received signal Control signal, when the common gating enable signal is invalid, the first multiplexing module 217 and the second multiplexing module 219 output the first controlled signal and the second controlled signal, respectively.

Optionally, the first controlled signal is a TPU data transmission ready signal (ie, the aforementioned valid signal), and the second controlled signal is a TPU data calculation ready signal (ie, the aforementioned ready signal).

Those skilled in the art can know that the first controlled signal and the second controlled signal can also be used interchangeably without affecting the effect of the technical solution of the present disclosure.

In the above technical solution, by adding a gating function and a common gating enable signal to the valid signal and the ready signal, the transmission of the valid and ready signals is restricted. When the common gating enable signal is valid (that is, when the gating is open), the dpcmd module (the function is the same as the dpcmd module in FIG. 1, however, the connection method is different from that in FIG. 1. The dpcmd module is connected to the first controlled signal input terminal 203 and the output terminal of the second multiplexing module 219, not shown in FIG. 2) and the eucmd module (the function is the same as the eucmd module in FIG. 1, however, the connection The method is different from that in FIG. 1, in the above-mentioned solution of the present disclosure, the eucmd module is connected to the second controlled signal input terminal 205 and the output terminal of the first multiplexing module 217, not shown in FIG. 2) In order to pass valid and ready signals to each other. The greater the proportion of gate open time, the greater the allowed power consumption, and conversely, the smaller the allowed power consumption.

Optionally, the gating logic generation module 209 is further configured to adjust the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal through the following steps:

Determine the total number of clock cycles included in the gating cycle;

For example, the following specific steps can be used to control the ratio of gate opening (that is, to adjust the number of clock cycles of the next valid gate signal within the next gate cycle of the gate signal).

The opening or closing of the gate control is controlled by the gate control logic (ie, the gate control logic generation module 209), and when the gate control signal is high, it indicates that the gate control is open. Use ctrl_step_len (generally 2 ^l ) to indicate how many cycles of a gating cycle (that is, the total number of clock cycles included in the gating cycle), the total clock cycle included in the gating cycle can be determined according to the pipeline establishment time or period Number, the gating period is the unit of statistics and control; use ctrl_step_num (that is, the above-mentioned level number n, generally 2 ^m , and can not exceed ctrl_step_len, that is, m≤l) to indicate that the proportion of gate opening is divided from the smallest to the largest Several levels; use gate_open_cnt (that is, the number of clock cycles of the currently valid gate control signal) to represent the cycle of gate opening within a gate cycle. Therefore, the ratio of the gate opening = gate_open_cnt / ctrl_step_len, the difference between the gate_open_cnt of two adjacent stages is ctrl_step_len / ctrl_step_num, which is recorded as ctrl_step_height (that is, the above-mentioned clock cycle number adjustment step).

1) If data_valid_cnt (that is, the number of valid controlled signal clock cycles) = gate_open_cnt, then gate_open_cnt_next (that is, the next valid gated signal clock cycle) = gate_open_cnt + ctrl_step_height, where gate_open_cnt_next≤ctrl_step_len;

2) If gate_open_cnt> data_valid_cnt≥gate_open_cnt–ctrl_step_height, then gate_open_cnt_next = gate_open_cnt;

3) If data_valid_cnt <gate_open_cnt–ctrl_step_height, then gate_open_cnt_next = gate_open_cnt–k * ctrl_step_height such that gate_open_cnt_next–ctrl_step_height≤data_valid_cnt <gate_open_cnt_next.

That is, the above technical solution controls the proportion of gate opening by controlling the size of gate_open_cnt in a gate period. The busier the TPU, the larger the gate_open_cnt, and vice versa. When ready_out and valid_out are both high, it means that a data was successfully transferred with the addition of gating, and data_valid_cnt is used to indicate a cycle in which ready_out and valid_out are both high during a gating cycle. The larger data_valid_out, the busier the TPU. Therefore, the present invention controls the size of gate_open_cnt through data_valid_cnt through the following rules.

For example, to simplify implementation, the first level of gate_open_cnt can be set to ctrl_step_height, so that each level of gate_open_cnt is k * ctrl_step_height (ctrl_step_num≥k> 0).

ctrl_step_len * ctrl_step_num is the cycle required to increase the power consumption from the lowest to the highest. The larger the product, the slower the power consumption rises. The size of these two values can be adjusted according to specific needs.

Optionally, the clock period of the next gating signal is evenly distributed within the maximum effective continuous period of the first controlled signal and the second controlled signal.

For example, the following steps can be used to achieve the purpose of uniformly distributing the clock period of the next gated signal within the maximum effective continuous period of the first controlled signal and the second controlled signal.

After determining the size of gate_open_cnt in each gating cycle, in order to make the power consumption in a gating cycle more balanced, it is necessary to evenly distribute the gate-opening cycles in a gating cycle. At this time, a gating cycle can be divided into several smaller control sub-periods as much as possible. The number of cycles in the control sub-period is recorded as gate_period. In this control sub-period, the gate signal needs to be pulled up several cycles, which is recorded as gate_high_cnt . The gate_period and gate_high_cnt are calculated as follows:

1) Find the lowest bit in the gate_open_cnt of 1 and record it as low_1bit. For example, gate_open_cnt = 4, then its low_1bit = 2;

2) gate_period = ctrl_step_len >> low_1bit; gate_high_cnt = gate_open_cnt >> low_1bit.

That is, the first step of the above operation is to find the greatest common divisor of ctrl_step_len and gate_open_cnt, and then divide each by the greatest common divisor, respectively, to get the minimum divided period and the number of cycles that the gate signal needs to be pulled up for each control sub-cycle . For example, gate_open_cnt = 12, ctrl_step_len = 32, then gate_period = 8, and gate_high_cnt = 3.

Therefore, the above technical solution can keep the power consumption stable.

3 is a schematic flowchart of a gating method according to an embodiment of the present disclosure.

As shown by the solid line box in FIG. 3, this example gating method includes:

Step S302: Receive a system clock signal whose clock period is T _clk ;

Step S304: Receive the first controlled signal;

Step S306: Receive the second controlled signal;

Step S308: output a gating signal that gates the input of the first controlled signal and the input of the second controlled signal;

Step S310: based on the system clock signal, counting the first controlled signal and the second controlled signal, the number of effective controlled signal clock cycles simultaneously valid in the current gating cycle of the gating signal, based on the number of effective controlled signal clock cycles Adjust the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal.

Optionally, as shown by the dotted box in FIG. 3, the example gating method further includes:

Step S312: Receive a common gating enable signal;

Step S314: Perform and operate the common gating enable signal and the first controlled signal, and output the gated first controlled signal;

Step S316: Perform and operate the common gating enable signal and the second controlled signal, and output the gated second controlled signal;

Step S318: multiplexing the first controlled signal and the gated first controlled signal;

Step S320: Multiplexing the second controlled signal and the gated second controlled signal,

Among them, when the public gating enable input is valid, the gated first controlled signal and the gated second controlled signal are output separately, and when the public gating enable input is invalid, they are respectively output The first controlled signal and the second controlled signal.

Optionally, the first controlled signal is a TPU data transmission ready signal, and the second controlled signal is a TPU data calculation ready signal.

Optionally, the example gating method further includes (not shown in FIG. 3), adjusting the number of clock cycles of the next valid gating signal in the next gating cycle of the gating signal through the following steps:

Determine the total number of clock cycles included in the gating cycle;

As shown in FIG. 4, relative to the cycle-power curve of the technical solution shown in FIG. 1 (the first oblique line in the left part of FIG. 4, no gating is used), the cycle-gating of the gating solution according to an embodiment of the present disclosure The slope of the power curve (the second slope in the left part of Figure 4, using gating) is smaller. This shows that the above technical solutions of the present disclosure can slow down the speed of power consumption increase when the TPU executes calculation instructions (the same applies to other circuits with handshake signals).

Therefore, the above technical solution of the present disclosure adds (threshold-based) gating to the control path of data transmission, and adjusts the length of the threshold opening time according to the busy state of the TPU and other systems, so that the power consumption of the TPU can be increased in stages to avoid The sudden increase makes the power supply system more stable and also guarantees performance to a certain extent.

That is, the above-mentioned technical solutions of the present disclosure can slow down the speed at which power consumption rises when circuits such as TPUs execute calculation instructions, and can also stabilize power consumption.

It should be noted that although the operations of the disclosed method are described in a specific order in the drawings, this does not require or imply that the operations must be performed in the specific order, or that all the operations shown must be performed to achieve the desired results. . Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution.

Those skilled in the art should understand that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowchart and / or block diagram and a combination of the flow and / or block in the flowchart and / or block diagram may be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processing machine, or other programmable data processing device to produce a machine that enables the generation of instructions executed by the processor of the computer or other programmable data processing device An apparatus for realizing the functions specified in one block or multiple blocks of one flow or multiple flows of a flowchart and / or one block or multiple blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device The instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.

This disclosure uses specific examples to explain the principles and implementations of this disclosure. The descriptions of the above examples are only used to help understand the methods and core ideas of this disclosure; meanwhile, for those of ordinary skill in the art, based on this The disclosed ideas are subject to change in specific implementation and application scope. In summary, the content of this specification should not be construed as limiting the disclosure.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features thereof may be equivalently replaced; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions of the technical solutions of the embodiments of the present disclosure range.

Claims

A gating circuit is characterized by comprising:

The system clock signal input terminal is used to receive the system clock signal whose clock period is T clk ;

The first controlled signal input terminal is used to receive the first controlled signal;

The second controlled signal input terminal is used to receive the second controlled signal;

A gate control signal output terminal for outputting a gate control signal that gates the input of the first controlled signal and the input of the second controlled signal;

Gating logic generation module, which is used to calculate the effective controlled signals that are valid at the same time in the current gating period of the gating signal based on the system clock signal, statistics of the first controlled signal and the second controlled signal The number of clock cycles, based on the number of effective controlled signal clock cycles, adjusts the number of clock cycles of the next effective gating signal within the next gating cycle of the gating signal.
The gate control circuit according to claim 1, further comprising:

Common gate enable input, used to receive common gate enable signal;

A first AND gate, used to perform AND operation on the common gating enable signal and the first controlled signal, and output the gated first controlled signal;

A second AND gate, configured to perform AND operation on the common gating enable signal and the second controlled signal, and output the gated second controlled signal;

A first multiplexing module, configured to multiplex the first controlled signal and the gated first controlled signal;

A second multiplexing module for multiplexing the second controlled signal and the gated second controlled signal,

Wherein, when the common gating enable signal is valid, the first multiplexing module and the second multiplexing module respectively output the gated first controlled signal and the After the gated second controlled signal, when the common gate enable signal is invalid, the first multiplexed module and the second multiplexed module respectively output the first controlled Signal and the second controlled signal.
The gate control circuit according to claim 1, wherein the first controlled signal is a TPU data transmission ready signal, and the second controlled signal is a TPU data calculation ready signal.
The gating circuit according to claim 1, wherein the gating logic generation module is further configured to adjust the number of clock cycles of the next gating signal in the next gating cycle of the gating signal through the following steps:

Determine the total number of clock cycles included in the gating cycle;

Determining the step size and the number of levels n of clock cycle adjustments, taking the step size of the clock cycle adjustments as the basic unit, dividing the gating cycle into n levels in which the number of clock cycles increases in sequence;

If the number of clock cycles of the effective controlled signal is equal to the number of clock cycles of the current effective gate signal, the number of clock cycles of the next effective gate signal is adjusted to the clock cycle corresponding to the next stage with a larger number of cycles number;

If the number of clock cycles of the effective controlled signal is less than the number of clock cycles of the current effective gating signal, the number of clock cycles of the next effective gating signal is adjusted to the number of clock cycles corresponding to the corresponding level with a lower number of cycles ,

Wherein, the number of clock cycles of the next valid gating signal is less than or equal to the total number of clock cycles of the gating cycle.
The gating circuit according to claim 4, wherein the clock period of the next gating signal is evenly distributed within the maximum effective continuous period of the first controlled signal and the second controlled signal.
A gating method, characterized in that it includes:

Receive the system clock signal whose clock period is T clk ;

Receive the first controlled signal;

Receive the second controlled signal;

Output a gating signal that gates the input of the first controlled signal and the input of the second controlled signal;

Based on the system clock signal, counting the number of effective controlled signal clock cycles that the first controlled signal and the second controlled signal are simultaneously valid within the current gating cycle of the gating signal, based on the effective The number of clock cycles of the controlled signal is used to adjust the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal.
The gating method according to claim 6, further comprising:

Receive public gating enable signal;

It is used to perform and operate the common gating enable signal and the first controlled signal, and output the gated first controlled signal;

It is used to perform and operate the common gating enable signal and the second controlled signal, and output the gated second controlled signal;

Multiplexing the first controlled signal and the gated first controlled signal;

Multiplexing the second controlled signal and the gated second controlled signal,

Wherein, when the common gating enable signal is valid, the gated first controlled signal and the gated second controlled signal are output separately, and the common gate control is enabled When the signal is invalid, the first controlled signal and the second controlled signal are output separately.
The gating method according to claim 6, wherein the first controlled signal is a data transmission ready signal of the TPU, and the second controlled signal is a data calculation ready signal of the TPU.
The gating method according to claim 6, further comprising: adjusting the number of clock cycles of the next valid gating signal within the next gating cycle of the gating signal by the following steps:

Determine the total number of clock cycles included in the gating cycle;

Determining the step size and the number of levels n of clock cycle adjustments, taking the step size of the clock cycle adjustments as the basic unit, dividing the gating cycle into n levels in which the number of clock cycles increases in sequence;

If the number of clock cycles of the effective controlled signal is equal to the number of clock cycles of the current effective gate signal, the number of clock cycles of the next effective gate signal is adjusted to the clock cycle corresponding to the next stage with a larger number number;

If the number of clock cycles of the effective controlled signal is less than the number of clock cycles of the current effective gating signal, the number of clock cycles of the next effective gating signal is adjusted to the number of clock cycles corresponding to the corresponding level with a lower number of cycles ,

Wherein, the number of clock cycles of the next valid gating signal is less than or equal to the total number of clock cycles of the gating cycle.
The gating method according to claim 9, wherein the clock period of the next gating signal is evenly distributed within the maximum effective continuous period of the first controlled signal and the second controlled signal.