WO2020087730A1 - 一种h-3碳化硅pn型同位素电池及其制造方法 - Google Patents

一种h-3碳化硅pn型同位素电池及其制造方法 Download PDF

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WO2020087730A1
WO2020087730A1 PCT/CN2018/123949 CN2018123949W WO2020087730A1 WO 2020087730 A1 WO2020087730 A1 WO 2020087730A1 CN 2018123949 W CN2018123949 W CN 2018123949W WO 2020087730 A1 WO2020087730 A1 WO 2020087730A1
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type sic
epitaxial layer
ohmic contact
sic epitaxial
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张�林
王晓艳
朱礼亚
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长安大学
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    • G—PHYSICS
    • G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
    • G21H—OBTAINING ENERGY FROM RADIOACTIVE SOURCES; APPLICATIONS OF RADIATION FROM RADIOACTIVE SOURCES, NOT OTHERWISE PROVIDED FOR; UTILISING COSMIC RADIATION
    • G21H1/00—Arrangements for obtaining electrical energy from radioactive sources, e.g. from radioactive isotopes, nuclear or atomic batteries
    • G21H1/06—Cells wherein radiation is applied to the junction of different semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0312—Inorganic materials including, apart from doping materials or other impurities, only AIVBIV compounds, e.g. SiC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table

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  • the invention belongs to the technical field of semiconductor devices and semiconductor processes, and particularly relates to an H-3 silicon carbide PN type isotope battery and a manufacturing method thereof.
  • An isotope battery is an energy conversion device that converts nuclear radiant energy into electrical energy using the radiant volt effect produced by charged particles generated by radioactive isotope decay in a semiconductor device.
  • isotope batteries are regarded as the most ideal long-term energy sources for MEMS systems due to their advantages of high reliability, easy integration, and strong anti-interference.
  • High output power is a prerequisite for the wide application of micronuclear batteries.
  • micronuclear batteries due to the self-absorption effect and cost of isotope sources, it is difficult for micronuclear batteries to increase the output power by increasing the activity of the irradiation source. In order to obtain a sufficiently high and long-term stable output power to accelerate its practical application, it is necessary to optimize the design from both aspects of the transducing element and the radiation source.
  • the purpose of the present invention is to provide an H-3 silicon carbide PN type isotope battery and a manufacturing method thereof to solve the above problems.
  • the present invention adopts the following technical solutions:
  • the total thickness of the N-type SiC epitaxial layer and the P-type SiC epitaxial layer is 0.8 ⁇ m to 2.0 ⁇ m.
  • the thickness of the P-type SiC epitaxial layer is 0.05 ⁇ m to 0.20 ⁇ m.
  • the doping concentration of the P-type SiC epitaxial layer is 1 ⁇ 10 14 cm -3 to 1 ⁇ 10 17 cm -3 .
  • the doping concentration of the N-type SiC epitaxial layer is 1 ⁇ 10 17 cm -3 to 1 ⁇ 10 18 cm -3 .
  • the doping concentration of the P-type SiC ohmic contact doping region is 5 ⁇ 10 18 cm -3 ⁇ 2 ⁇ 10 19 cm -3 ; the thickness is 0.20 ⁇ m ⁇ 0.50 ⁇ m.
  • the thickness of the SiO 2 passivation layer is 5 nm to 20 nm.
  • a method for manufacturing an H-3 silicon carbide PN-type isotope battery is characterized in that the H-3 silicon carbide PN-type isotope battery based on the above includes the following steps:
  • Step 1 Provide a substrate composed of N-type doped SiC substrate
  • Step 2 Use chemical vapor deposition to epitaxially grow N on the upper surface of the substrate in step 1 with a doping concentration of 1 ⁇ 10 17 cm -3 ⁇ 1 ⁇ 10 18 cm -3 and a thickness of 0.75 ⁇ m to 1.8 ⁇ m Type SiC epitaxial layer;
  • Step 3 Use chemical vapor deposition to epitaxially grow on the upper surface of the N-type SiC epitaxial layer with a doping concentration of 1 ⁇ 10 14 cm -3 ⁇ 1 ⁇ 10 17 cm -3 and a thickness of 0.05 ⁇ m to 0.20 ⁇ m P-type SiC epitaxial layer;
  • Step 4 Use chemical vapor deposition to epitaxially grow on the upper surface of the P-type SiC epitaxial layer with a doping concentration of 5 ⁇ 10 18 cm -3 to 2 ⁇ 10 19 cm -3 and a thickness of 0.2 ⁇ m to 0.5 ⁇ m P-type SiC ohmic contact doped region;
  • Step 5 Use reactive ion etching to etch away some P-type SiC ohmic contact doped regions; expose the P-type SiC epitaxial layer;
  • Step 6 Use dry oxygen oxidation to form an oxide layer on the surface of the P-type ohmic contact doped region and the surface of the P-type SiC epitaxial layer; use wet etching to remove the oxide layer;
  • Step 7 Use dry oxygen oxidation to form a SiO 2 passivation layer with a thickness of 5 nm to 20 nm in a region outside the P-type SiC ohmic contact doping region on the upper surface of the P-type SiC epitaxial layer
  • Step 8 Deposit metal Ni with a thickness of 200 nm to 400 nm and metal Pt with a thickness of 100 to 200 nm in sequence above the P-type SiC ohmic contact doped region;
  • Step 9 Deposit metal Ni with a thickness of 200 nm to 400 nm and metal Pt with a thickness of 100 to 200 nm in sequence below the substrate;
  • Step 10 Perform thermal annealing at a temperature of 950 ° C to 1050 ° C for 2 minutes in an N 2 atmosphere to form a P-type ohmic contact electrode above the P-type SiC ohmic contact doped region; form an N-type below the substrate Ohmic contact electrode;
  • Step 11 An H-3 radioisotope source is provided on the top of the SiO 2 passivation layer.
  • the present invention has the following technical effects:
  • the H-3 silicon carbide PN type isotope battery of the present invention adopts a new type of transducing element to replace the conventional PIN junction or PN junction.
  • the surface recombination rate is reduced, which is helpful to reduce the current generation caused by irradiation
  • the composite loss of the surface on the surface increases the output power of the battery.
  • the high built-in barrier of the battery of the present invention can bring high open circuit voltage, thereby obtaining high conversion efficiency.
  • the depletion region should be used instead of the diffusion region to collect irradiated carriers. Since the high built-in barrier and the width of the wide depletion region are contradictory, this brings difficulties to the design of the battery.
  • the manufacturing method of the invention has simple process, convenient implementation and low cost.
  • the design of the invention is novel and reasonable, and the realization is convenient, which is conducive to improving the energy conversion efficiency and packaging density of the H-3 silicon carbide PN-type isotope battery.
  • FIG. 1 is a front view of the H-3 silicon carbide PN type isotope battery of the present invention.
  • FIG. 2 is a flow chart of a method for manufacturing a H-3 silicon carbide PN-type isotope battery of the present invention.
  • Figure 3 is a background art drawing.
  • 1-N type doped SiC substrate 2-N type SiC epitaxial layer; 3-P type SiC epitaxial layer; 4-SiO2 passivation layer; 5-P type SiC ohmic contact doped region; 6-P type ohmic contact Electrode; 7-N ohmic contact electrode; 8-H-3 radioisotope source.
  • an H-3 silicon carbide PN-type isotope battery including an N-type conductive SiC substrate 1, an N-type SiC epitaxial layer 2, a P-type SiC epitaxial layer 3, and a SiO 2 passivation layer 4.
  • the total thickness of the N-type SiC epitaxial layer 2 and the P-type SiC epitaxial layer 3 is 0.8 ⁇ m to 2.0 ⁇ m.
  • the thickness of the P-type SiC epitaxial layer 3 is 0.05 ⁇ m to 0.20 ⁇ m.
  • the doping concentration of the P-type SiC epitaxial layer 3 is 1 ⁇ 10 14 cm -3 ⁇ 1 ⁇ 10 17 cm -3 ; the higher the concentration of the P-type SiC epitaxial layer 3, the smaller the thickness, the more the concentration of the P-type SiC epitaxial layer 3 The greater the lower thickness.
  • the doping concentration of the N-type SiC epitaxial layer 2 is 1 ⁇ 10 17 cm -3 to 1 ⁇ 10 18 cm -3 ; the higher the concentration of the N-type SiC epitaxial layer 2, the smaller the thickness of the N-type SiC epitaxial layer 2.
  • the doping concentration of the P-type SiC ohmic contact doped region 5 is 5 ⁇ 10 18 cm -3 ⁇ 2 ⁇ 10 19 cm -3 ; the thickness is 0.20 ⁇ m ⁇ 0.50 ⁇ m.
  • the thickness of the SiO 2 passivation layer 4 is 5 nm to 20 nm.
  • a method for manufacturing H-3 silicon carbide PN type isotope battery includes the following steps:
  • Step 1 Provide a substrate 1 composed of an N-type doped SiC substrate;
  • Step 2 Use chemical vapor deposition to epitaxially grow N on the upper surface of the substrate in step 1 with a doping concentration of 1 ⁇ 10 17 cm -3 ⁇ 1 ⁇ 10 18 cm -3 and a thickness of 0.75 ⁇ m to 1.8 ⁇ m Type SiC epitaxial layer 2;
  • Step 3 Use chemical vapor deposition to epitaxially grow the upper surface of the N-type SiC epitaxial layer 2 with a doping concentration of 1 ⁇ 10 14 cm -3 ⁇ 1 ⁇ 10 17 cm -3 and a thickness of 0.05 ⁇ m to 0.20 ⁇ m Of P-type SiC epitaxial layer 3;
  • Step 4 The chemical vapor deposition method is used to epitaxially grow the upper surface of the P-type SiC epitaxial layer 3 with a doping concentration of 5 ⁇ 10 18 cm -3 to 2 ⁇ 10 19 cm -3 and a thickness of 0.2 ⁇ m to 0.5 ⁇ m P-type SiC ohmic contact doped region 5;
  • Step 5 Use reactive ion etching to etch away part of the P-type SiC ohmic contact doped region 5; expose the P-type SiC epitaxial layer 3;
  • Step 6 Use dry oxygen oxidation to form an oxide layer on the surface of the P-type SiC ohmic contact doped region 5 and the surface of the P-type SiC epitaxial layer 3; use wet etching to remove the oxide layer;
  • Step 7 Use dry oxygen oxidation to form a SiO 2 passivation layer 4 with a thickness of 5 nm to 20 nm in a region other than the P-type SiC ohmic contact doping region 5 on the upper surface of the P-type SiC epitaxial layer 3;
  • Step 8 Deposit metal Ni with a thickness of 200 nm to 400 nm and metal Pt with a thickness of 100 to 200 nm in sequence above the P-type SiC ohmic contact doped region 5;
  • Step 9 Deposit metal Ni with a thickness of 200 nm to 400 nm and metal Pt with a thickness of 100 to 200 nm in sequence under the substrate 1;
  • Step 10 Perform thermal annealing at a temperature of 950 ° C to 1050 ° C for 2 minutes in an N 2 atmosphere to form a P-type ohmic contact electrode 6 above the P-type SiC ohmic contact doped region 5; below the substrate 1 Forming an N-type ohmic contact electrode 7;
  • Step 11 H-3 radioisotope source 8 is provided on top of the SiO 2 passivation layer 7.
  • a method for manufacturing H-3 silicon carbide PN type isotope battery includes the following steps:
  • Step 1 Provide a substrate 1 composed of an N-type doped SiC substrate;
  • Step 2 The chemical vapor deposition method is used to epitaxially grow an N-type SiC epitaxial layer 2 with a doping concentration of 4 ⁇ 10 17 cm -3 and a thickness of 1.8 ⁇ m on the upper surface of the substrate in step one;
  • Step 3 Use chemical vapor deposition to epitaxially grow the P-type SiC epitaxial layer 3 with a doping concentration of 3 ⁇ 10 16 cm -3 and a thickness of 0.10 ⁇ m on the upper surface of the N-type SiC epitaxial layer 2;
  • Step 4 P-type SiC ohmic contact doping region 5 with a doping concentration of 1 ⁇ 10 19 cm -3 and a thickness of 0.2 ⁇ m is epitaxially grown on the upper surface of the P-type SiC epitaxial layer 3 by chemical vapor deposition;
  • Step 5 Use reactive ion etching to etch away part of the P-type SiC ohmic contact doped region 5; expose the P-type SiC epitaxial layer 3;
  • Step 6 Use dry oxygen oxidation to form an oxide layer on the surface of the P-type SiC ohmic contact doped region 5 and the surface of the P-type SiC epitaxial layer 3; use wet etching to remove the oxide layer;
  • Step 7 Use dry oxygen oxidation to form an SiO 2 passivation layer 4 with a thickness of 10 nm on the upper surface of the P-type SiC epitaxial layer 3 except for the P-type SiC ohmic contact doping region 5;
  • Step 8 Deposit metal Ni with a thickness of 400 nm and metal Pt with a thickness of 200 nm in sequence above the P-type SiC ohmic contact doped region 5;
  • Step 9 Deposit metal Ni with a thickness of 400 nm and metal Pt with a thickness of 200 nm under the substrate 1 in sequence;
  • Step 10 Perform thermal annealing at a temperature of 1000 ° C. for 2 minutes in an N 2 atmosphere to form a P-type ohmic contact electrode 6 above the P-type SiC ohmic contact doped region (5); below the substrate 1 N-type ohmic contact electrode 7;
  • Step 11 H-3 radioisotope source 8 is provided on top of the SiO 2 passivation layer 7.

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Abstract

一种H-3碳化硅PN型同位素电池及其制造方法，该同位素电池的结构自下而上包括N型欧姆接触电极（7），N型高掺杂SiC衬底（1），N型SiC外延层（2），P型SiC外延层（3），在P型SiC外延层（3）上部的部分区域设有P型SiC欧姆接触掺杂区（5），在P型SiC欧姆接触掺杂区（5）的顶部设有P型欧姆接触电极（6），在P型SiC外延层（3）上部除去P型SiC欧姆接触掺杂区（5）以外的区域设有SiO 2钝化层（4），在SiO 2钝化层（4）的上方设有H-3放射性同位素源（8）。该方法设计新颖合理，可以有效解决H-3在表面的辐照生载流子复合损耗问题，有效提高了同位素电池的输出功率、能量转换效率。

Description

一种H-3碳化硅PN型同位素电池及其制造方法 技术领域
本发明属于半导体器件以及半导体工艺技术领域，特别涉及一种H-3碳化硅PN型同位素电池及其制造方法。
背景技术
同位素电池是一种采用放射性同位素衰变产生的带电粒子在半导体器件中产生的辐射伏特效应将核放射能转换成电能的一种能量转换装置。在诸多类型的微型能源中，同位素电池由于具有可靠性高、易集成、抗干扰性强等优点，被视为MEMS系统最理想的长期能源。高的输出功率是微型核电池可以广泛实用的前提，但由于同位素源的自吸收效应及成本等原因，微型核电池难以通过提升辐照源活度的方法来提升输出功率。为了获得足够高且长期稳定的输出功率以加快推进其实用，需要从换能元件和放射源两个方面同时进行优化设计。
在放射源方面，目前大都采用低能β放射源(如 63Ni，粒子平均能量17.3KeV)作为能量源，其电子通量密度较低；同时由于放射源的自吸收效应，单纯的靠提高放射源的强度来提升输出功率的意义有限。因此，提升能量转换效率是目前研究的重点。在诸多的同位素源中，H-3(氚， 3H)的半衰期长(12.3年)、比活度高，同时易于获得、价格低廉，被视为微型核电池最理想的能源之一。H-3发射的电子能量较低(5.7keV)，在半导体材料中的射程浅(低于2μm)，电离能容易被充分收集，但同时也导致其性能更容易受换能元件表面结构和表面复合等因素的影响。图1是H-3在SiC材料中产生的电离能分布。
以SiC、GaN为代表的宽禁带半导体材料，具有禁带宽度大﹑抗辐射能力强等优点，用其制成的同位素电池换能元件的内建电势高﹑漏电流小，理论上可以得到比硅基电池更 高的开路电压和能量转换效率；同时，也具有在高温强辐射等恶劣环境下长期工作的能力。相比于SiC肖特基二极管，SiC PN或者PIN型二极管具有内建电势高、漏电流小等优点，用其制成的同位素电池具有开路电压高、转换效率高等优点。
但是目前采用H-3的碳化硅PN型同位素电池的研究也存在很多的问题，其中最大的问题是如何避免辐照生载流子在器件表面的复合损耗。如图3所示，H-3产生的电子射程较浅，且峰值靠近器件表面，表面复合造成的辐照生载流子损失难以避免。由于SiC材料高硬度和高化学稳定性的特性，其加工工艺远不如Si材料成熟，降低表面复合对于微型核电池输出特性的影响是目前研究的热点和难点。
发明内容
本发明的目的在于提供一种H-3碳化硅PN型同位素电池及其制造方法，以解决上述问题。
为实现上述目的，本发明采用以下技术方案：
一种H-3碳化硅PN型同位素电池，包括N型导通型SiC衬底、N型SiC外延层、P型SiC外延层、SiO 2钝化层、P型SiC欧姆接触掺杂区、P型欧姆接触电极、N型欧姆接触电极和H-3放射性同位素源；衬底下方设置N型欧姆接触电极，衬底上部设置N型SiC外延层，N型SiC外延层上部设置P型SiC外延层，P型SiC欧姆接触掺杂区和SiO 2钝化层相邻设置在P型SiC外延层的上表面，在P型SiC欧姆接触掺杂区的正上方设置P型欧姆接触电极，在SiO 2钝化层的正上方设置H-3放射性同位素源。
进一步的，N型SiC外延层和P型SiC外延层的总厚度为0.8μm～2.0μm。
进一步的，P型SiC外延层的厚度为0.05μm～0.20μm。
进一步的，P型SiC外延层的掺杂浓度为1×10 14cm -3～1×10 17cm -3。
进一步的，N型SiC外延层的掺杂浓度为1×10 17cm -3～1×10 18cm -3。
进一步的，P型SiC欧姆接触掺杂区的掺杂浓度为5×10 18cm -3～2×10 19cm -3；厚度为0.20μm～0.50μm。
进一步的，SiO 2钝化层的厚度为5nm～20nm。
进一步的，一种H-3碳化硅PN型同位素电池的制造方法，其特征在于，基于上述的一种H-3碳化硅PN型同位素电池，包括以下步骤：
步骤一、提供由N型掺杂SiC基片构成的衬底；
步骤二、采用化学气相沉积法在步骤一所述衬底的上表面上外延生长掺杂浓度为1×10 17cm -3～1×10 18cm -3、厚度为0.75μm～1.8μm的N型SiC外延层；
步骤三、采用化学气相沉积法在所述N型SiC外延层的上表面上外延生长掺杂浓度为1×10 14cm -3～1×10 17cm -3、厚度为0.05μm～0.20μm的P型SiC外延层；
步骤四、采用化学气相沉积法在所述P型SiC外延层的上表面上外延生长掺杂浓度为5×10 18cm -3～2×10 19cm -3、厚度为0.2μm～0.5μm的P型SiC欧姆接触掺杂区；
步骤五、采用反应离子刻蚀法刻蚀掉部分P型SiC欧姆接触掺杂区；露出P型SiC外延层；
步骤六、采用干氧氧化在P型SiC欧姆接触掺杂区表面和P型SiC外延层的表面形成氧化层；采用湿法腐蚀去除掉氧化层；
步骤七、采用干氧氧化在所述P型SiC外延层的上表面P型SiC欧姆接触掺杂区以外的区域形成厚度为5nm～20nm厚的SiO 2钝化层；
步骤八、在P型SiC欧姆接触掺杂区的上方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
步骤九、在衬底的下方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
步骤十、在N 2气氛下进行温度为950℃～1050℃的热退火2分钟，在P型SiC欧姆接触掺杂区的上方形成P型欧姆接触电极；在所述衬底的下方形成N型欧姆接触电极；
步骤十一、在所述SiO 2钝化层顶部设置有H-3放射性同位素源。
与现有技术相比，本发明有以下技术效果：
本发明H-3碳化硅PN型同位素电池，采用新型换能元件代替常规的PIN结或者PN 结，通过将降低器件表面的掺杂浓度，以降低表面复合率，有利于减少辐照生载流子在表面的复合损耗，从而提升电池的输出功率。
本发明的电池的高内建势垒可以带来高的开路电压，从而获得高的转换效率。同时，由于H-3的电子射程浅，应尽量采用耗尽区而非扩散区收集辐照生载流子。由于高的内建势垒与宽的耗尽区宽度是矛盾的，这给电池的设计带来困难。采用本发明提出的换能元件结构，既可以获得高的内建势垒，又易于得到较宽的耗尽区厚度，提升电池的性能
本发明的制造方法，工艺简单，实现方便且成本低。
本发明设计新颖合理，实现方便，有利于提高H-3碳化硅PN型同位素电池的能量转换效率和封装密度，有利于集成，实用性强，推广应用价值高。
附图说明
图1为本发明H-3碳化硅PN型同位素电池的主视图。
图2为本发H-3碳化硅PN型同位素电池的制造方法的方法流程图。
图3为背景技术附图。
附图标记说明:
1—N型掺杂SiC衬底；2—N型SiC外延层；3—P型SiC外延层；4—SiO2钝化层；5—P型SiC欧姆接触掺杂区；6—P型欧姆接触电极；7—N型欧姆接触电极；8—H-3放射性同位素源。
具体实施方式
以下结合附图对本发明进一步说明：
请参阅图1和图2，一种H-3碳化硅PN型同位素电池，包括N型导通型SiC衬底1、N型SiC外延层2、P型SiC外延层3、SiO 2钝化层4、P型SiC欧姆接触掺杂区5、P型欧姆接触电极6、N型欧姆接触电极7和H-3放射性同位素源8；衬底1下方设置N型欧姆接触电极7，衬底上部设置N型SiC外延层2，N型SiC外延层2上部设置P型SiC外 延层3，P型SiC欧姆接触掺杂区5和SiO 2钝化层4相邻设置在P型SiC外延层3的上表面，在P型SiC欧姆接触掺杂区5的正上方设置P型欧姆接触电极6，在SiO 2钝化层4的正上方设置H-3放射性同位素源8。
N型SiC外延层2和P型SiC外延层3的总厚度为0.8μm～2.0μm。
P型SiC外延层3的厚度为0.05μm～0.20μm。
P型SiC外延层3的掺杂浓度为1×10 14cm -3～1×10 17cm -3；P型SiC外延层3的浓度越高厚度越小，P型SiC外延层3的浓度越低厚度越大。
N型SiC外延层2的掺杂浓度为1×10 17cm -3～1×10 18cm -3；N型SiC外延层2的浓度越高，N型SiC外延层2的厚度越小。
P型SiC欧姆接触掺杂区5的掺杂浓度为5×10 18cm -3～2×10 19cm -3；厚度为0.20μm～0.50μm。
SiO 2钝化层4的厚度为5nm～20nm。
一种H-3碳化硅PN型同位素电池的制造方法，包括以下步骤：
步骤一、提供由N型掺杂SiC基片构成的衬底1；
步骤二、采用化学气相沉积法在步骤一所述衬底的上表面上外延生长掺杂浓度为1×10 17cm -3～1×10 18cm -3、厚度为0.75μm～1.8μm的N型SiC外延层2；
步骤三、采用化学气相沉积法在所述N型SiC外延层2的上表面上外延生长掺杂浓度为1×10 14cm -3～1×10 17cm -3、厚度为0.05μm～0.20μm的P型SiC外延层3；
步骤四、采用化学气相沉积法在所述P型SiC外延层3的上表面上外延生长掺杂浓度为5×10 18cm -3～2×10 19cm -3、厚度为0.2μm～0.5μm的P型SiC欧姆接触掺杂区5；
步骤五、采用反应离子刻蚀法刻蚀掉部分P型SiC欧姆接触掺杂区5；露出P型SiC外延层3；
步骤六、采用干氧氧化在P型SiC欧姆接触掺杂区5表面和P型SiC外延层3的表面形成氧化层；采用湿法腐蚀去除掉氧化层；
步骤七、采用干氧氧化在所述P型SiC外延层3的上表面P型SiC欧姆接触掺杂区5 以外的区域形成厚度为5nm～20nm厚的SiO 2钝化层4；
步骤八、在P型SiC欧姆接触掺杂区5的上方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
步骤九、在衬底1的下方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
步骤十、在N 2气氛下进行温度为950℃～1050℃的热退火2分钟，在P型SiC欧姆接触掺杂区5的上方形成P型欧姆接触电极6；在所述衬底1的下方形成N型欧姆接触电极7；
步骤十一、在所述SiO 2钝化层7顶部设置有H-3放射性同位素源8。
实施例1：
一种H-3碳化硅PN型同位素电池的制造方法，包括以下步骤：
步骤一、提供由N型掺杂SiC基片构成的衬底1；
步骤二、采用化学气相沉积法在步骤一所述衬底的上表面上外延生长掺杂浓度为4×10 17cm -3、厚度为1.8μm的N型SiC外延层2；
步骤三、采用化学气相沉积法在所述N型SiC外延层2的上表面上外延生长掺杂浓度为3×10 16cm -3、厚度为0.10μm的P型SiC外延层3；
步骤四、采用化学气相沉积法在所述P型SiC外延层3的上表面上外延生长掺杂浓度为1×10 19cm -3、厚度为0.2μm的P型SiC欧姆接触掺杂区5；
步骤五、采用反应离子刻蚀法刻蚀掉部分P型SiC欧姆接触掺杂区5；露出P型SiC外延层3；
步骤六、采用干氧氧化在P型SiC欧姆接触掺杂区5表面和P型SiC外延层3的表面形成氧化层；采用湿法腐蚀去除掉氧化层；
步骤七、采用干氧氧化在所述P型SiC外延层3的上表面P型SiC欧姆接触掺杂区5以外的区域形成厚度为10nm厚的SiO 2钝化层4；
步骤八、在P型SiC欧姆接触掺杂区5的上方依次淀积厚度为400nm的金属Ni和厚 度为200nm的金属Pt；
步骤九、在衬底1的下方依次淀积厚度为400nm的金属Ni和厚度为200nm的金属Pt；
步骤十、在N 2气氛下进行温度为1000℃的热退火2分钟，在P型SiC欧姆接触掺杂区(5)的上方形成P型欧姆接触电极6；在所述衬底1的下方形成N型欧姆接触电极7；
步骤十一、在所述SiO 2钝化层7顶部设置有H-3放射性同位素源8。

Claims (8)

  1. 一种H-3碳化硅PN型同位素电池，其特征在于，包括N型导通型SiC衬底(1)、N型SiC外延层(2)、P型SiC外延层(3)、SiO 2钝化层(4)、P型SiC欧姆接触掺杂区(5)、P型欧姆接触电极(6)、N型欧姆接触电极(7)和H-3放射性同位素源(8)；衬底(1)下方设置N型欧姆接触电极(7)，衬底上部设置N型SiC外延层(2)，N型SiC外延层(2)上部设置P型SiC外延层(3)，P型SiC欧姆接触掺杂区(5)和SiO 2钝化层(4)相邻设置在P型SiC外延层(3)的上表面，在P型SiC欧姆接触掺杂区(5)的正上方设置P型欧姆接触电极(6)，在SiO 2钝化层(4)的正上方设置H-3放射性同位素源(8)。
  2. 根据权利要求1所述的一种H-3碳化硅PN型同位素电池，其特征在于，N型SiC外延层(2)和P型SiC外延层(3)的总厚度为0.8μm～2.0μm。
  3. 根据权利要求1所述的一种H-3碳化硅PN型同位素电池，其特征在于，P型SiC外延层(3)的厚度为0.05μm～0.20μm。
  4. 根据权利要求3所述的一种H-3碳化硅PN型同位素电池，其特征在于，P型SiC外延层(3)的掺杂浓度为1×10 14cm -3～1×10 17cm -3。
  5. 根据权利要求2所述的一种H-3碳化硅PN型同位素电池，其特征在于，N型SiC外延层(2)的掺杂浓度为1×10 17cm -3～1×10 18cm -3。
  6. 根据权利要求1所述的一种H-3碳化硅PN型同位素电池，其特征在于，P型SiC欧姆接触掺杂区(5)的掺杂浓度为5×10 18cm -3～2×10 19cm -3；厚度为0.20μm～0.50μm。
  7. 根据权利要求1所述的一种H-3碳化硅PN型同位素电池，其特征在于，SiO 2钝化层(4)的厚度为5nm～20nm。
  8. 一种H-3碳化硅PN型同位素电池的制造方法，其特征在于，基于权利要求1至7所述的一种H-3碳化硅PN型同位素电池，包括以下步骤：
    步骤一、提供由N型掺杂SiC基片构成的衬底(1)；
    步骤二、采用化学气相沉积法在步骤一所述衬底的上表面上外延生长掺杂浓度为1×10 17cm -3～1×10 18cm -3、厚度为0.75μm～1.8μm的N型SiC外延层(2)；
    步骤三、采用化学气相沉积法在所述N型SiC外延层(2)的上表面上外延生长掺杂浓度为1×10 14cm -3～1×10 17cm -3、厚度为0.05μm～0.20μm的P型SiC外延层(3)；
    步骤四、采用化学气相沉积法在所述P型SiC外延层(3)的上表面上外延生长掺杂浓度为5×10 18cm -3～2×10 19cm -3、厚度为0.2μm～0.5μm的P型SiC欧姆接触掺杂区(5)；
    步骤五、采用反应离子刻蚀法刻蚀掉部分P型SiC欧姆接触掺杂区(5)；露出P型SiC外延层(3)；
    步骤六、采用干氧氧化在P型SiC欧姆接触掺杂区(5)表面和P型SiC外延层(3)的表面形成氧化层；采用湿法腐蚀去除掉氧化层；
    步骤七、采用干氧氧化在所述P型SiC外延层(3)的上表面P型SiC欧姆接触掺杂区(5)以外的区域形成厚度为5nm～20nm厚的SiO 2钝化层(4)；
    步骤八、在P型SiC欧姆接触掺杂区(5)的上方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
    步骤九、在衬底(1)的下方依次淀积厚度为200nm～400nm的金属Ni和厚度为100～200nm的金属Pt；
    步骤十、在N 2气氛下进行温度为950℃～1050℃的热退火2分钟，在P型SiC欧姆接触掺杂区(5)的上方形成P型欧姆接触电极(6)；在所述衬底(1)的下方形成N型欧姆接触电极(7)；
    步骤十一、在所述SiO 2钝化层(7)顶部设置有H-3放射性同位素源(8)。
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