WO2020087645A1 - 信号控制电路及包含信号控制电路的显示装置 - Google Patents

信号控制电路及包含信号控制电路的显示装置 Download PDF

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Publication number
WO2020087645A1
WO2020087645A1 PCT/CN2018/119020 CN2018119020W WO2020087645A1 WO 2020087645 A1 WO2020087645 A1 WO 2020087645A1 CN 2018119020 W CN2018119020 W CN 2018119020W WO 2020087645 A1 WO2020087645 A1 WO 2020087645A1
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circuit
signal
voltage
capacitor
display device
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PCT/CN2018/119020
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English (en)
French (fr)
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胡水秀
曾德康
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惠科股份有限公司
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Publication of WO2020087645A1 publication Critical patent/WO2020087645A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present application relates to the field of display technology, and in particular, to a signal control circuit and a display device including the signal control circuit.
  • GOA Gate Driver Array
  • the GOA circuit that implements the GOA technology generally needs to generate a control signal of a certain phase difference, and the control signal is used for the switching of a TFT (Thin Film Transistor, thin film transistor) to further control the writing of color data.
  • TFT Thin Film Transistor, thin film transistor
  • the phase difference between current control signals can only be adjusted together as a whole, and the phase difference between certain two signals cannot be adjusted separately. Therefore, the GOA circuit is not flexible enough to use.
  • a signal control circuit that can individually adjust a control signal is provided.
  • a display device is also provided.
  • a signal control circuit configured to provide a control signal for an array substrate grid drive integrated circuit, including:
  • a voltage detection circuit configured to detect the voltage of the first capacitor
  • a voltage adjustment circuit configured to output a voltage adjustment signal according to the detected voltage, and the voltage adjustment signal is set to adjust the time at which the rising edge of the control signal occurs;
  • the timing controller is set to provide a reference voltage signal
  • the delay output circuit is configured to receive the reference voltage signal and output the reference voltage signal when the rising edge arrives to provide a control signal.
  • the signal control circuit further includes:
  • a level shift circuit is electrically connected to the delay output circuit, and is configured to boost and transmit the voltage of the control signal to the array substrate gate drive integrated circuit.
  • the voltage regulating circuit is a sliding rheostat.
  • the voltage regulation circuit is a digital potentiometer.
  • a signal control circuit is provided to provide a control signal for an array substrate gate drive integrated circuit, wherein the signal control circuit includes:
  • a voltage detection circuit configured to detect the voltage of the first capacitor
  • a voltage adjustment circuit configured to output a voltage adjustment signal according to the detected voltage, the voltage adjustment signal being set to adjust the time at which the rising edge of the control signal occurs; wherein, the voltage adjustment circuit is a digital potentiometer;
  • Timing controller set to provide a reference voltage signal
  • a delay output circuit configured to receive the reference voltage signal and output the reference voltage signal when the rising edge arrives to provide a control signal
  • a level shift circuit is electrically connected to the delay output circuit, and is configured to boost and transmit the voltage of the control signal to the array substrate gate drive integrated circuit.
  • a display device includes a display panel and a drive circuit, the display panel includes a display area and a non-display area, the display area is provided with a plurality of data lines and a plurality of scan lines, wherein the drive circuit includes a signal control circuit ,
  • the signal control circuit includes:
  • a voltage detection circuit configured to detect the voltage of the first capacitor
  • a voltage adjustment circuit configured to output a voltage adjustment signal according to the detected voltage, and the voltage adjustment signal is set to adjust the time at which the rising edge of the control signal occurs;
  • the timing controller is set to provide a reference voltage signal
  • the delay output circuit is configured to receive the reference voltage signal and output the reference voltage signal when the rising edge arrives to provide a control signal.
  • the display device further includes:
  • a printed circuit board, the timing controller is provided on the printed circuit board.
  • the driving circuit further includes:
  • a flexible circuit board provided at the edge of the non-display area; the display panel is connected to the printed circuit board through the flexible circuit board;
  • a source driving circuit is provided on the flexible circuit board, and is configured to drive the data line on or off.
  • the material of the flexible circuit board is polyimide.
  • the flexible circuit board is made of polyester film.
  • the driving circuit further includes: an array substrate gate driving integrated circuit, disposed in the non-display area, and configured to drive the scanning line on or off.
  • the display area is further provided with a plurality of pixel circuits, and the pixel circuit includes a plurality of sub-pixel circuits; wherein, the sub-pixel circuit includes a switching unit, a second capacitor, and a third capacitor.
  • the switch unit is a thin film transistor.
  • the switch unit is a field effect transistor.
  • the second capacitor is a liquid crystal capacitor
  • the liquid crystal capacitor includes a pixel electrode, a common electrode, and a liquid crystal layer interposed between the pixel electrode and the common electrode.
  • the third capacitor is an energy storage capacitor, and the energy storage capacitor is connected in parallel with the liquid crystal capacitor.
  • the voltage regulating circuit is integrated on the printed circuit board.
  • the delay output circuit is integrated on the printed circuit board.
  • the voltage detection circuit is integrated on the printed circuit board.
  • the above signal control circuit and display device adjust the timing of the rising edge of the control signal by detecting the voltage of the first capacitor, and further, by setting a timing controller for providing the reference voltage signal and controlling the reference voltage signal to arrive at the rising edge
  • the time-delayed output module can adjust the output of the control signal. Furthermore, for multiple control signals, the control signal can have different rise time and different phase difference, so that the control signal The adjustment does not need to be adjusted overall, thereby increasing the flexibility of the circuit.
  • FIG. 1 is a schematic structural diagram of a signal control circuit in an embodiment
  • FIG. 2 is a schematic structural diagram of a signal control circuit in another embodiment
  • FIG. 3 is a schematic structural diagram of a display device in an embodiment
  • FIG. 4 is a schematic diagram of an arrangement of pixel circuits in an embodiment
  • FIG. 5 is a schematic diagram of a circuit structure of a pixel circuit in an embodiment
  • FIG. 6 is an enlarged schematic diagram of the circuit structure of the sub-pixel circuit in FIG. 5;
  • FIG. 7 is a waveform diagram of multiple control signals output by the signal control circuit in FIG. 1.
  • FIG. 7 is a waveform diagram of multiple control signals output by the signal control circuit in FIG. 1.
  • CK represents the reference voltage signal
  • CK1 represents the first control signal
  • CK2 represents the second control signal
  • CK3 represents the third control signal
  • CK4 represents the fourth control signal
  • t represents the phase difference between the first control signal and the reference voltage signal
  • t1 represents the phase difference between the second control signal and the first control signal
  • t2 represents the phase difference between the third control signal and the second control signal
  • t3 represents the phase difference between the fourth control signal and the third control signal.
  • the signal control circuit of the present application can effectively and flexibly adjust the timing of the rising edge of the control signal.
  • FIG. 1 is a schematic structural diagram of a signal control circuit in an embodiment.
  • the signal control circuit is configured to provide a control signal for an array substrate gate drive integrated circuit.
  • the signal control circuit may include a first capacitor 210 , Voltage detection circuit 220, voltage adjustment circuit 230, timing controller 240 and delay output circuit 250.
  • the first capacitor 210 is a high-precision capacitor
  • the voltage detection circuit 220 is configured to detect the voltage of the first capacitor 210
  • the voltage adjustment circuit 230 is configured to output a voltage adjustment signal according to the detected voltage of the first capacitor 210, wherein the voltage The adjustment signal is set to the moment when the rising edge of the adjustment control signal appears.
  • the control signal is mainly configured to control the on or off of the switching element in the array substrate grid drive integrated circuit, and then control the array substrate grid drive integrated circuit to output a scan driving voltage signal to drive the corresponding scan line to be turned on or off.
  • the timing controller 240 is configured to provide a reference voltage signal.
  • the delay output circuit 250 is configured to receive the reference voltage signal and cause the reference voltage signal to be output when a rising edge arrives to provide a control signal.
  • the rising time of the control signal is adjusted by detecting the voltage of the first capacitor. Further, by setting a timing controller that provides the reference voltage signal and a delay output circuit that controls the output of the reference voltage signal when the rising edge arrives The output of the control signal can be adjusted. Further, for multiple control signals, the control signals can have different rise time and different phase difference, so that the adjustment of the control signal does not need to be adjusted overall, which increases the circuit Flexibility.
  • the voltage regulating circuit 230 may be a sliding rheostat or a digital potentiometer.
  • the voltage adjustment circuit 230 is a digital potentiometer.
  • a digital potential control circuit for adjusting the resistance of the digital potentiometer can be integrated in the signal control circuit.
  • the digital potentiometer is a relatively accurate adjustable resistance.
  • the digital potential control circuit that controls the digital potentiometer is also a relatively simple control method.
  • the timing controller 40 is mainly configured to process the R (Red, Red) / G (Green) / B (Blue, Blue) compressed signals and control signals sent by the system motherboard, and then generate corresponding clock control signals. It can be understood that the clock control signal here is also a control signal output in the signal control circuit of the present application.
  • FIG. 2 is a schematic structural diagram of a signal control circuit in an embodiment.
  • the signal control circuit is configured to provide a control signal for an array substrate gate drive integrated circuit.
  • the signal control circuit may include a first capacitor 210 and a voltage detection circuit 220.
  • the first capacitor 210 is a high-precision capacitor
  • the voltage detection circuit 220 is configured to detect the voltage of the first capacitor 210
  • the voltage adjustment circuit 230 is configured to output a voltage adjustment signal according to the detected voltage of the first capacitor 210, wherein the voltage The adjustment signal is set to the moment when the rising edge of the adjustment control signal appears.
  • the control signal is mainly configured to control the on or off of the switching element in the array substrate grid drive integrated circuit, and then control the array substrate grid drive integrated circuit to output a scan driving voltage signal to drive the corresponding scan line to be turned on or off.
  • the timing controller 240 is configured to provide a reference voltage signal.
  • the delay output circuit 250 is configured to receive the reference voltage signal and output the reference voltage signal when the rising edge comes to provide a control signal.
  • the level shift circuit 260 is electrically connected to the delay output circuit 250, and is configured to boost the voltage of the control signal and transmit it to the array substrate gate drive integrated circuit.
  • the level shift circuit 260 may also be referred to as a level shift chip. Since the voltage of the control signal output from the delay output circuit 250 is a low voltage, the low voltage needs to be raised to the required high voltage, and the level shift circuit 260 is used to raise the low voltage to the high voltage.
  • the rise time of the control signal is adjusted by detecting the voltage of the first capacitor. Further, by setting a timing controller that provides the reference voltage signal and a delay output circuit that controls the output of the reference voltage signal when the rising edge arrives, The output of the control signal can be adjusted. Further, for multiple control signals, the control signals can have different rise time and different phase difference, so that the adjustment of the control signal does not need to be adjusted overall, which increases the circuit Flexibility. Furthermore, by setting the level shift circuit, the low voltage from the timing controller can be changed to the required high voltage.
  • the display device may include a display panel 10 and a drive circuit 20.
  • the display panel 10 includes a display area 110 and a non-display area 120.
  • the display area 110 is provided with multiple data lines and multiple scan lines.
  • the display area 110 is an area where image information is displayed, and may also be referred to as an active area.
  • the non-display area 120 usually refers to an area where no image is displayed. This part of the area is mainly used to press some circuits and some sensors. Fit in this area.
  • the data lines are represented by D1, D2, D3, ... Dn
  • the scanning lines are represented by S1, S2, ... Sn.
  • the drive circuit 20 includes the aforementioned signal control circuit.
  • the driving circuit 20 may include a first capacitor 210, a voltage detection circuit 220, a voltage adjustment circuit 230, a timing controller 240, a delay output circuit 250, and a level shift circuit 260. It can be understood that, for the specific description of the first capacitor 210, the voltage detection circuit 220, the voltage adjustment circuit 230, the timing controller 240, the delay output circuit 250, and the level shift circuit 260, reference may be made to the description of the foregoing signal control circuit embodiment. This will not be described further.
  • control signal output by the signal control circuit can be regarded as the clock control signal output by the timing controller, and the clock control signal is set to control the thin film transistor in the GOA (Gate driver on Array, gate driver integrated on the array substrate) circuit Turning it on or off, in other words, is to control the GOA unit to output the scan driving voltage signal.
  • GOA Gate driver on Array, gate driver integrated on the array substrate
  • a signal control circuit having a first capacitor, a voltage detection circuit, a voltage adjustment circuit, a timing controller, and a delay output circuit
  • the signal control circuit controls the rise of the control signal by detecting the voltage of the first capacitor Edge time, by setting a timing controller that provides a reference voltage signal and a delay output circuit that controls the output of the reference voltage signal when the rising edge comes, and further, by setting a voltage adjustment circuit to adjust the delay size of the delay output circuit.
  • the display device of the present application can realize the adjustment of the output of the control signal. Further, for multiple control signals, the control signals can have different rise time between each other, and thus have different phase differences, so that the adjustment of the control signal There is no need for overall adjustment, thereby increasing the flexibility of the circuit.
  • the display device may further include a printed circuit board 30.
  • the timing controller 240 is provided on the printed circuit board 30 and is provided to provide a clock control signal.
  • the printed circuit board 30 is abbreviated as PCB (Printed Circuit Board).
  • the printed circuit board 30 is an important electronic component, a support for electronic components, and a carrier for electrical connection of electronic components.
  • the first capacitor 210, the voltage detection circuit 220, the voltage adjustment circuit 230, the delay output circuit 250, and the level shift circuit 260 may be integrated on the printed circuit board 30.
  • the first capacitor 210 may be a capacitor related to the timing controller 240 on the printed circuit board 30.
  • the first capacitor 210, the voltage detection circuit 220, the voltage adjustment circuit 230, the timing controller 240, the delay output circuit 250 and the level shift circuit 260 on the printed circuit board 30 can reduce the non-display area 110 of the display panel 10 usage area.
  • the driving circuit 20 may further include a flexible circuit board 270, a source driving circuit 280 provided on the flexible circuit board 270, and an array substrate gate driving integrated circuit 290.
  • the flexible circuit board 270 is a highly reliable and excellent flexible printed circuit board made of polyimide or polyester film as a substrate, referred to as FPC (Flexible Printed Circuit).
  • FPC Flexible Printed Circuit
  • the flexible circuit board 270 is disposed at the edge of the non-display area 120, the flexible circuit board 270 is electrically connected to the printed circuit board 30, and the source driving circuit 280 is disposed on the flexible circuit board 270.
  • each flexible circuit board 270 is provided with only one source driving circuit 280, so the number of flexible circuit boards 270 corresponds to the number of source driving circuits 280.
  • the flexible circuit board 270 generally serves as a carrier for receiving the source driving circuit 280 and a bridge connecting the display panel 10 and the printed circuit board 30.
  • the source driving circuit 280 is electrically connected to the timing controller 40, and is configured to receive the clock signal output by the timing controller 40 and drive the corresponding data lines D1, D2, and D3 to turn on or off according to the clock signal.
  • the source driving circuit 280 is also called a source thin film driving chip, abbreviated as S-COF (Source-Chip on Film), which mainly generates a strobe signal based on a clock control signal, which is also a data line driving voltage signal, and its role Controls the writing of data signals.
  • Array substrate gate drive integrated circuit 290 referred to as GOA unit, array substrate gate drive integrated circuit 290 is to directly make the gate drive circuit around the display panel, usually located in the non-display area 120 of the display panel 10, this arrangement method can be reduced Production procedures, and can reduce product costs, improve panel integration, and achieve narrow borders.
  • the array substrate grid driving integrated circuit 290 mainly generates a strobe signal based on a clock control signal.
  • the strobe signal is also a scan driving voltage signal, and its role is to control the writing of color data.
  • a plurality of pixel circuits P1 are further provided in the display area 110 of the display panel 10, and the plurality of pixel circuits P1 are electrically connected to the data lines and the scanning lines, respectively.
  • the pixel circuit P1 includes a plurality of sub-pixel circuits p1, and the plurality of sub-pixel circuits are arranged in a matrix array, as shown in FIG. 5.
  • the pixel circuit P1 includes a plurality of sub-pixel circuits p1. In other words, one pixel circuit P1 is composed of a plurality of sub-pixel circuits p1.
  • one pixel circuit P1 is composed of three sub-pixel circuits p1, and the three sub-pixel circuits p1 correspond to R ( Red, red) G (Green, green) B (Blue, blue) three primary colors.
  • Each sub-pixel circuit p1 includes a switching unit T1, a second capacitor, and a third capacitor.
  • the switch unit T1 may be, for example, a thin film transistor or a field effect transistor; taking the switch unit T1 as a thin film transistor as an example, the gate of the thin film transistor T1 is connected to the scanning line S1, the source is connected to the data line D1, and the drain is connected in parallel with two The second capacitor and the third capacitor are connected. The other end of the parallel capacitor can be connected to the common voltage Vcom.
  • the second capacitor may be a liquid crystal capacitor Clc, also known as a parasitic capacitor, and may generally include a pixel electrode (not shown in FIG. 1), a common electrode (not shown in FIG. 1), and a liquid crystal layer (not shown in FIG. 1).
  • the pixel electrode is generally provided on the TFT (Thin Film Transistor) substrate of the display panel
  • the common electrode is generally provided on the CF (Color Filter) substrate of the display panel.
  • the pixel electrodes are also arranged in a matrix, and Connected to a switching element such as a thin film transistor that sequentially applies data voltages to pixels.
  • the common electrode is provided over the entire surface of the display panel, and provides a common voltage to the common electrode.
  • the third capacitor may be an energy storage capacitor Cs, and the third capacitor Cs is connected in parallel with the second capacitor Clc. In this application, the energy storage capacitor Cs is mainly set to a storage voltage.
  • FIG. 4 is a schematic diagram of the arrangement of pixel circuits in an embodiment
  • FIG. 5 is a schematic diagram of the circuit structure of the pixel circuit in an embodiment
  • FIG. 6 is an enlarged schematic diagram of the circuit structure of the sub-pixel circuit in FIG. Please refer to Figure 5 and Figure 6 for details.
  • the plurality of sub-pixel circuits p1 are arranged in an array, and scan signals Si (1 ⁇ i ⁇ m) are input in each row, and data signals Dj (1 ⁇ j ⁇ n) are input in each column. Among them, the scan signal Si is output according to the control signal output by the signal control circuit.
  • the scan signal Si is input line by line, that is, S1 to Sm are sequentially input high level in a fixed cycle, so that the sub-pixel circuit p1 of the line is input Data signal Dj.
  • the scan time of one frame is 1/60 second, that is, the refresh rate is 60 Hz.
  • FIG. 6 is an enlarged view of the circuit structure of the sub-pixel circuit p1 in FIG. 5.
  • the sub-pixel circuit p1 includes a three-terminal switching device, which can generally be a thin-film transistor T1, a scan signal Si is input to its gate, a data signal Dj is input to its source, and two parallel capacitors Cs, Clc are connected to the drain , Where capacitor Cs is the energy storage capacitor and capacitor Clc is the liquid crystal capacitor. The other end of the parallel capacitor can be connected to the common voltage Vcom.
  • the thin film transistor T1 When the scanning signal Si inputs a high level, the thin film transistor T1 is turned on and receives an input data signal Dj (voltage signal).
  • the voltage difference between the data signal Dj and the common voltage Vcom charges the capacitors Cs and Clc, and the voltage between 210 deflects the liquid crystal molecules in it, causing the backlight to transmit a corresponding degree of light according to the deflection of the liquid crystal molecules, thereby The sub-pixel has a corresponding brightness.
  • the capacitor Cs is set to maintain this voltage until the next scan comes.
  • the voltage of the data signal Dj may be higher than the common voltage Vcom or lower than the common voltage Vcom.
  • the absolute value of the voltage difference between the two is the same and the sign is opposite, the brightness displayed by the driving sub-pixels is the same.
  • the voltage of the data signal Dj is higher than the common voltage Vcom, in the following embodiments, it is called positive polarity driving, otherwise it is called negative polarity driving.
  • each sub-pixel structure it is set to drive and display one sub-pixel.
  • the sub-pixels are red sub-pixels (R), green sub-pixels (G), and blue sub-pixels (B); for a four-color pixel circuit, the sub-pixels are red sub-pixels ( R), green sub-pixel (G), blue sub-pixel (B), and white sub-pixel (W).

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Abstract

一种信号控制电路及显示装置，该信号控制电路包括：电压检测电路(220)，设置为检测第一电容(210)的电压；电压调节电路(230)，设置为根据检测到的电压输出控制信号，控制信号设置为控制控制信号的上升沿出现的时刻；时序控制器(240)，设置为提供一路基准电压信号；延时输出电路(250)，设置为接收基准电压信号、并使基准电压信号在上升沿到来时输出以提供控制信号。

Description

信号控制电路及包含信号控制电路的显示装置
相关申请的交叉引用
本申请要求于2018年10月29日提交中国专利局、申请号为201811269839.X申请名称为“信号控制电路及包含信号控制电路的显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种信号控制电路及包含信号控制电路的显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着显示技术的发展，显示装置因具有高画质、省电、机身薄、窄边框等优点而被广泛应用，其中，窄边框能让显示装置的显示画面面积更大，进而增加用户的体验感。为了让显示装置的边框变窄，出现了GOA(Gate driver on Array，阵列基板栅驱动集成)技术，GOA技术是一种可以直接将栅极驱动电路做在显示面板周围的技术，可以减少制作程序，而且可以降低产品成本，提高面板集成度，实现窄边框。
实现GOA技术的GOA电路一般需要产生一定相位差的控制信号，该控制信号用于TFT(Thin Film Transistor，薄膜晶体管)的开关，进而控制颜色数据的写入。但是目前的控制信号之间的相位差只能整体一起调节，不能单独进行某两个信号之间相位差的调节。从而使得GOA电路使用起来不够灵 活。
申请内容
根据本申请的各种实施例，提供一种可以单独调节控制信号的信号控制电路。
此外，还提供一种显示装置。
一种信号控制电路，设置为为阵列基板栅驱动集成电路提供控制信号，包括：
电压检测电路，设置为检测第一电容的电压；
电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述电压调节信号设置为调节所述控制信号的上升沿出现的时刻；
时序控制器，设置为提供一路基准电压信号；及
延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号。
在其中一个实施例中，所述信号控制电路还包括：
电平移位电路，与所述延时输出电路电连接，设置为将所述控制信号的电压提升、并传输至所述阵列基板栅驱动集成电路。
在其中一个实施例中，所述电压调节电路为滑动变阻器。
在其中一个实施例中，所述电压调节电路为数字电位器。
一种信号控制电路，设置为为阵列基板栅驱动集成电路提供控制信号，其中，所述信号控制电路包括：
电压检测电路，设置为检测第一电容的电压；
电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述 电压调节信号设置为调节所述控制信号的上升沿出现的时刻；其中，所述电压调节电路为数字电位器；
时序控制器，设置为提供一路基准电压信号；
延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号；及
电平移位电路，与所述延时输出电路电连接，设置为将所述控制信号的电压提升、并传输至所述阵列基板栅驱动集成电路。
一种显示装置，包括显示面板和驱动电路，所述显示面板包括显示区域和非显示区域，所述显示区域设置有多条数据线和多条扫描线，其中，所述驱动电路包括信号控制电路，所述信号控制电路包括：
电压检测电路，设置为检测第一电容的电压；
电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述电压调节信号设置为调节所述控制信号的上升沿出现的时刻；
时序控制器，设置为提供一路基准电压信号；及
延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号。
在其中一个实施例中，所述显示装置还包括：
印刷电路板，所述时序控制器设于所述印刷电路板上。
在其中一个实施例中，所述驱动电路还包括：
柔性电路板，设于所述非显示区域的边缘；所述显示面板通过所述柔性电路板与所述印刷电路板连接；
源极驱动电路，设于所述柔性电路板上，设置为驱动所述数据线的开启或关闭。
在其中一个实施例中，所述柔性电路板的材料为聚酰亚胺。
在其中一个实施例中，所述柔性电路板的材料为聚酯薄膜。
在其中一个实施例中，所述驱动电路还包括：阵列基板栅驱动集成电路，设置于所述非显示区域，设置为驱动所述扫描线的开启或关闭。
在其中一个实施例中，所述显示区域还设置有多个像素电路，所述像素电路包括多个子像素电路；其中，所述子像素电路包括开关单元、第二电容及第三电容。
在其中一个实施例中，所述开关单元为薄膜晶体管。
在其中一个实施例中，所述开关单元为场效应晶体管。
在其中一个实施例中，所述第二电容为液晶电容，所述液晶电容包括像素电极、共电极及夹设于所述像素电极与所述共电极之间的液晶层。
在其中一个实施例中，所述第三电容为储能电容，所述储能电容与所述液晶电容并联。
在其中一个实施例中，所述电压调节电路集成在所述印刷电路板上。
在其中一个实施例中，所述延时输出电路集成在所述印刷电路板上。
在其中一个实施例中，所述电压检测电路集成在所述印刷电路板上。
上述信号控制电路及显示装置，通过检测第一电容的电压来调节控制信号的上升沿出现的时刻，进一步地，通过设置用于提供基准电压信号的时序控制器和控制基准电压信号在上升沿到来时输出的延时输出模块，可以实现控制信号的输出调节，进一步地，针对多个控制信号可以实现控制信号相互之间具有不同的上升沿时间，进而具有不同的相位差，从而使得控制信号的调节不必整体调节，进而增加电路的灵活性。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的信号控制电路的结构示意图；
图2为另一实施例中的信号控制电路的结构示意图；
图3为一实施例中的显示装置的结构示意图；
图4为一实施例中的像素电路的排列方式示意图；
图5为一实施例中的像素电路的电路结构示意图；
图6为图5中的子像素电路的电路结构放大示意图；
图7为图1中信号控制电路输出的多个控制信号的波形图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的可选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参阅图7，为图1中信号控制电路输出的多个控制信号的波形图。其中，CK表示基准电压信号，CK1表示第一控制信号，CK2表示第二控制信号，CK3表示第三控制信号，CK4表示第四控制信号。t表示第一控制信号与基准电压信号之间的相位差，t1表示第二控制信号与第一控制信号之间的相位差，t2表示第三控制信号与第二控制信号之间的相位差，t3表示第四控制信号与第三控制信号之间的相位差。从图7中可以看出，t、t1、t2、t3四者之间并不相等，区别于示例性的控制信号的调节只能整体调节，也就是说，在示例性的控制信号的调节方法中，t、t1、t2、t3四者是相等的。而采用本申请的信号控制电路可以有效、并且灵活的对控制信号的上升沿出现的时刻进行调整。
具体地，请参阅图1，图1为一实施例中的信号控制电路的结构示意图，该信号控制电路设置为为阵列基板栅驱动集成电路提供控制信号，该信号控制电路可以包括第一电容210，电压检测电路220，电压调节电路230，时序控制器240及延时输出电路250。其中，第一电容210为高精度的电容，电压检测电路220设置为检测第一电容210的电压，电压调节电路230设置为根据检测到的第一电容210的电压输出电压调节信号，其中，电压调节信号设置为调节控制信号的上升沿出现的时刻。控制信号主要设置为控制阵列基板栅驱动集成电路中开关元件的开启或关闭，进而控制阵列基板栅驱动集成电路输出扫描驱动电压信号，以驱动对应的扫描线开启或关闭。时序控制器240设置为提供一路基准电压信号。延时输出电路250设置为接收基准电压信号、并使基准电压信号在上升沿到来时输出以提供控制信号。
上述实施例，通过检测第一电容的电压来调节控制信号的上升沿时间， 进一步地，通过设置提供基准电压信号的时序控制器和控制基准电压信号在上升沿到来时输出的延时输出电路，可以实现控制信号的输出调节，进一步地，针对多个控制信号可以实现控制信号相互之间具有不同的上升沿时间，进而具有不同的相位差，从而使得控制信号的调节不必整体调节，进而增加电路的灵活性。
电压调节电路230可以为滑动变阻器或者数字电位器。可选地，电压调节电路230为数字电位器，相应地，信号控制电路里就可以集成用于调整数字电位器的阻值的数字电位控制电路，数字电位器是比较精确的可调电阻，同时控制数字电位器的数字电位控制电路也是比较简单的控制方式。
时序控制器40主要设置为将系统主板发送的R(Red,红色)/G(Green，绿色)/B(Blue，蓝色)压缩信号、控制信号进行处理，然后生成相应的时钟控制信号。可以理解，此处的时钟控制信号也即是本申请的信号控制电路中输出的控制信号。
请参照图2，为一实施例中的信号控制电路的结构示意图，该信号控制电路设置为阵列基板栅驱动集成电路提供控制信号，该信号控制电路可以包括第一电容210，电压检测电路220，电压调节电路230，时序控制器240，延时输出电路250及电平移位电路260。其中，第一电容210为高精度的电容，电压检测电路220设置为检测第一电容210的电压，电压调节电路230设置为根据检测到的第一电容210的电压输出电压调节信号，其中，电压调节信号设置为调节控制信号的上升沿出现的时刻。控制信号主要设置为控制阵列基板栅驱动集成电路中开关元件的开启或关闭，进而控制阵列基板栅驱动集成电路输出扫描驱动电压信号，以驱动对应的扫描线开启或关闭。时序控制器240设置为提供一路基准电压信号。延时输出电 路250设置为接收基准电压信号、并使基准电压信号在上升沿到来时输出以提供控制信号。电平移位电路260，与延时输出电路250电连接，设置为将控制信号的电压提升、并传输至阵列基板栅驱动集成电路。
可以理解，对于第一电容210，电压检测电路220，电压调节电路230，时序控制器240，延时输出电路250的描述可以参照前述信号控制电路实施例的有关描述，在此不再进一步赘述。
电平移位电路260，也可以称为电平移位(level shift)芯片。由于从延时输出电路250输出的控制信号的电压为低电压，所以需要将低电压提升到需要的高电压，而电平移位电路260就是用来将低电压提升至高电压。
上述实施例，通过检测第一电容的电压来调节控制信号的上升沿时间，进一步地，通过设置提供基准电压信号的时序控制器和控制基准电压信号在上升沿到来时输出的延时输出电路，可以实现控制信号的输出调节，进一步地，针对多个控制信号可以实现控制信号相互之间具有不同的上升沿时间，进而具有不同的相位差，从而使得控制信号的调节不必整体调节，进而增加电路的灵活性。更进一步地，通过设置电平移位电路可以使得从时序控制器出来的低电压变成需要的高电压。
请参阅图3，为一实施例中的显示装置的结构示意图。该显示装置可以包括显示面板10和驱动电路20。其中显示面板10包括显示区域110和非显示区域120，显示区域110设置有多条数据线和多条扫描线。显示区域110也即是有图像信息显示的一块区域，也可以称为显示区(active area)；非显示区域120通常指没有图像显示的区域，该部分区域主要用于将一些线路和部分传感器压合在这个区域。其中，数据线用D1、D2、D3、…Dn表示，扫描线用S1、S2、…Sn表示。驱动电路20包括前述信号控制电路。 具体地，驱动电路20可以包括第一电容210、电压检测电路220、电压调节电路230、时序控制器240、延时输出电路250及电平移位电路260。可以理解，对于第一电容210、电压检测电路220、电压调节电路230、时序控制器240、延时输出电路250及电平移位电路260的具体描述可以参照前述信号控制电路实施例的描述，在此不再进一步进行赘述。可以理解，可将信号控制电路输出的控制信号看作是时序控制器输出的时钟控制信号，而时钟控制信号设置为控制GOA(Gate driver on Array，阵列基板上栅驱动集成)电路中薄膜晶体管的开启或关闭，换句话说，就是控制GOA单元输出扫描驱动电压信号。
上述实施例，通过采用具有第一电容、电压检测电路、电压调节电路、时序控制器和延时输出电路的信号控制电路，其中，信号控制电路通过检测第一电容的电压来控制控制信号的上升沿时间，通过设置提供基准电压信号的时序控制器和控制基准电压信号在上升沿到来时输出的延时输出电路，更进一步地，通过设置电压调节电路来调节延时输出电路的延时大小，可以使得本申请的显示装置可实现控制信号的输出调节，进一步地，针对多个控制信号可以实现控制信号相互之间具有不同的上升沿时间，进而具有不同的相位差，从而使得控制信号的调节不必整体调节，进而增加电路的灵活性。
在一个实施例中，请继续参阅图3，显示装置还可以包括印刷电路板30。其中，时序控制器240设于印刷电路板30上，设置为提供时钟控制信号。印刷电路板30，简称PCB(Printed Circuit Board)。印刷电路板30是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的载体。具体地，在本申请中，可将第一电容210、电压检测电路220、电压调 节电路230及延时输出电路250、电平移位电路260均集成在印刷电路板30上。具体地，第一电容210可以为印刷电路板30上的与时序控制器240相关的电容。将第一电容210、电压检测电路220、电压调节电路230、时序控制器240、延时输出电路250及电平移位电路260在印刷电路板30上可以减小显示面板10的非显示区域110的使用面积。
在一个实施例中，请继续参阅图3，驱动电路20还可以包括柔性电路板270，设于柔性电路板270上的源极驱动电路280，阵列基板栅驱动集成电路290。柔性电路板270是以聚酰亚胺或聚酯薄膜为基材制成的一种具有高度可靠性，绝佳的可挠性印刷电路板，简称FPC(Flexible Printed Circuit)。柔性电路板270设置在非显示区域120的边缘位置，柔性电路板270与印刷电路板30电性连接，源极驱动电路280设置在柔性电路板270上。可以理解，柔性电路板270的数量为多个，并且每一个柔性电路板270上只设置一个源极驱动电路280，所以，柔性电路板270的数量与源极驱动电路280的数量相对应。柔性电路板270通常作为承放源极驱动电路280的载体以及连接显示面板10和印刷电路板30的桥梁。源极驱动电路280与时序控制器40电连接，设置为接收时序控制器40输出的时钟信号、并根据时钟信号驱动对应的数据线D1、D2、D3开启或关闭。源极驱动电路280又称为源极薄膜驱动芯片，简称S-COF(Source-Chip on Film)，主要基于时钟控制信号产生选通信号，选通信号也即是数据线驱动电压信号，其作用是控制数据信号的写入。阵列基板栅驱动集成电路290，简称GOA单元，阵列基板栅驱动集成电路290是直接将栅极驱动电路做在显示面板周围，通常设于显示面板10的非显示区域120，这种设置方法可以减少制作程序，而且可以降低产品成本，提高面板集成度，实现窄边框。阵列基 板栅驱动集成电路290主要基于时钟控制信号产生选通信号，选通信号也即是扫描驱动电压信号，其作用是控制颜色数据的写入。
进一步地，请继续参阅图3，在显示面板10的显示区域110还设置有多个像素电路P1，多个像素电路P1分别与数据线和扫描线电气连接。具体地，像素电路P1包括多个子像素电路p1，并且多个子像素电路呈矩阵阵列排布，如图5所示。像素电路P1包括多个子像素电路p1，换句话说，一个像素电路P1由多个子像素电路p1构成，典型地，一个像素电路P1由三个子像素电路p1构成，三个子像素电路p1分别对应R(Red，红色)G(Green，绿色)B(Blue，蓝色)三原色。每一个子像素电路p1包括一个开关单元T1，第二电容，第三电容。其中，开关单元T1可例如薄膜晶体管或者场效应晶体管；以开关单元T1为薄膜晶体管为例，薄膜晶体管T1的栅极与扫描线S1连接，源极与数据线D1连接，漏极与两个并联的第二电容、第三电容连接。并联电容的另一端可以连接公共电压Vcom。
进一步地，第二电容可以为液晶电容Clc，也称作寄生电容，一般可以包括像素电极(图1未示)、共电极(图1未示)和液晶层(图1未示)。像素电极一般设置于显示面板的TFT(Thin Film Transistor，薄膜晶体管)基板上，而共电极一般设置于显示面板的CF(Color Filter，彩色滤光片)基板上，像素电极亦按照矩阵布置，并连接到将数据电压顺序地施加到像素的开关元件如薄膜晶体管。共电极被设置在显示面板的整个表面的上方，并对共电极提供共电压。第三电容可以为储能电容Cs，第三电容Cs与第二电容Clc并联，本申请中，储能电容Cs主要设置为储存电压。
综上，结合附图简要说明像素电路的驱动原理。图4为一实施例中的像素电路的排列方式示意图；图5为一实施例中的像素电路的电路结构示 意图；图6为图5中的子像素电路的电路结构放大示意图。具体请参阅图5和图6。多个子像素电路p1呈阵列排布，在每一行会输入扫描信号Si(1≤i≤m)，在每一列会输入数据信号Dj(1≤j≤n)。其中，扫描信号Si根据信号控制电路输出的控制信号进行输出，一般地，扫描信号Si逐行输入，即S1到Sm以固定的周期依序输入高电平，使该行的子像素电路p1输入数据信号Dj。当扫描信号Si输入完成后，完成一帧图形的显示。通常地，一帧扫描时间为1/60秒，即刷新频率为60赫兹。
图6为图5中的子像素电路p1的电路结构放大图。该子像素电路p1包括一个三端开关器件，一般可以为薄膜晶体管T1，在其栅极输入扫描信号Si，在其源极输入数据信号Dj，并在漏极连接两个并联的电容Cs、Clc，其中电容Cs为储能电容，电容Clc为液晶电容。并联电容的另一端可以连接公共电压Vcom。
当扫描信号Si输入高电平时，薄膜晶体管T1开通，接收输入数据信号Dj(电压信号)。数据信号Dj与公共电压Vcom之间的电压差使电容Cs、Clc充电，其中210之间的电压使处于其中的液晶分子发生偏转，使背光根据液晶分子的偏转程度透射出相应程度的光，从而使该子像素呈现相应的亮度。电容Cs设置为保持该电压直到下次扫描来临。
数据信号Dj的电压可以高于公共电压Vcom，也可以低于公共电压Vcom。当二者的电压差的绝对值相同，而符号相反时，驱动子像素显示的亮度相同。当数据信号Dj的电压高于公共电压Vcom时，在以下实施例中，称为正极性驱动，否则称为负极性驱动。
对每一个子像素结构，其设置为驱动显示一个子像素。例如，对于三色像素电路，其中的子像素为红色子像素(R)、绿色子像素(G)以及蓝 色子像素(B)；对于四色像素电路，其中的子像素为红色子像素(R)、绿色子像素(G)、蓝色子像素(B)以及白色子像素(W)。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种信号控制电路，设置为为阵列基板栅驱动集成电路提供控制信号，其中，包括：
    电压检测电路，设置为检测第一电容的电压；
    电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述电压调节信号设置为调节所述控制信号的上升沿出现的时刻；
    时序控制器，设置为提供一路基准电压信号；及
    延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号。
  2. 根据权利要求1所述的信号控制电路，其中，还包括：
    电平移位电路，与所述延时输出电路电连接，设置为将所述控制信号的电压提升、并传输至所述阵列基板栅驱动集成电路。
  3. 根据权利要求1所述的信号控制电路，其中，所述电压调节电路为滑动变阻器。
  4. 根据权利要求1所述的信号控制电路，其中，所述电压调节电路为数字电位器。
  5. 一种信号控制电路，设置为为阵列基板栅驱动集成电路提供控制信号，其中，所述信号控制电路包括：
    电压检测电路，设置为检测第一电容的电压；
    电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述电压调节信号设置为调节所述控制信号的上升沿出现的时刻；其中，所述电压调节电路为数字电位器；
    时序控制器，设置为提供一路基准电压信号；
    延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号；及
    电平移位电路，与所述延时输出电路电连接，设置为将所述控制信号的电压提升、并传输至所述阵列基板栅驱动集成电路。
  6. 一种显示装置，包括显示面板和驱动电路，所述显示面板包括显示区域和非显示区域，所述显示区域设置有多条数据线和多条扫描线，其中，所述驱动电路包括信号控制电路，所述信号控制电路包括：
    电压检测电路，设置为检测第一电容的电压；
    电压调节电路，设置为根据检测到的所述电压输出电压调节信号，所述电压调节信号设置为调节所述控制信号的上升沿出现的时刻；
    时序控制器，设置为提供一路基准电压信号；及
    延时输出电路，设置为接收所述基准电压信号、并使所述基准电压信号在所述上升沿到来时输出以提供控制信号。
  7. 根据权利要求6所述的显示装置，其中，还包括：
    印刷电路板，所述时序控制器设于所述印刷电路板上。
  8. 根据权利要求7所述的显示装置，其中，所述驱动电路还包括：
    柔性电路板，设于所述非显示区域的边缘；所述显示面板通过所述柔性电路板与所述印刷电路板连接；
    源极驱动电路，设于所述柔性电路板上，设置为驱动所述数据线的开启或关闭。
  9. 根据权利要求8所述的显示装置，其中，所述柔性电路板的材料为聚酰亚胺。
  10. 根据权利要求8所述的显示装置，其中，所述柔性电路板的材料为 聚酯薄膜。
  11. 根据权利要求6所述的显示装置，其中，所述驱动电路还包括：阵列基板栅驱动集成电路，设置于所述非显示区域，设置为驱动所述扫描线的开启或关闭。
  12. 根据权利要求8所述的显示装置，其中，所述显示区域还设置有多个像素电路，所述像素电路包括多个子像素电路；其中，所述子像素电路包括开关单元、第二电容及第三电容。
  13. 根据权利要求12所述的显示装置，其中，所述开关单元为薄膜晶体管。
  14. 根据权利要求12所述的显示装置，其中，所述开关单元为场效应晶体管。
  15. 根据权利要求12所述的显示装置，其中，所述第二电容为液晶电容，所述液晶电容包括像素电极、共电极及夹设于所述像素电极与所述共电极之间的液晶层。
  16. 根据权利要求15所述的显示装置，其中，所述第三电容为储能电容，所述储能电容与所述液晶电容并联。
  17. 根据权利要求8所述的显示装置，其中，所述电压调节电路集成在所述印刷电路板上。
  18. 根据权利要求8所述的显示装置，其中，所述延时输出电路集成在所述印刷电路板上。
  19. 根据权利要求8所述的显示装置，其中，所述电压检测电路集成在所述印刷电路板上。
PCT/CN2018/119020 2018-10-29 2018-12-03 信号控制电路及包含信号控制电路的显示装置 WO2020087645A1 (zh)

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