WO2020087396A1

WO2020087396A1 - Circuit board, chip layout method, and computing device

Info

Publication number: WO2020087396A1
Application number: PCT/CN2018/113181
Authority: WO
Inventors: 修洪雨
Original assignee: 北京比特大陆科技有限公司
Priority date: 2018-10-31
Filing date: 2018-10-31
Publication date: 2020-05-07
Also published as: CN109643705A

Abstract

Embodiments of the present disclosure provide a circuit board, a chip layout method, and a computing device. The circuit board comprises a PCB and two sets of chips disposed on the PCB. The first set of chips is disposed on a first surface of the PCB, and the second set of chips is disposed on a second surface opposite to the first surface of the PCB, wherein the first set of chips is provided with a first heat sink, and the second set of chips is provided with a second heat sink. Embodiments of the present disclosure achieve the rational planning and layout of chips on the PCB, such that the effective heat dissipation area of the circuit board is expanded from only the area on the front side of a single board to the front and back sides thereof, thereby reducing the power density of the circuit board and improving the overall heat dissipation efficiency of the circuit board.

Description

Circuit board and chip layout method, computing equipment

Technical field

The present disclosure relates to the technical field of heat dissipation of computing devices, and in particular, to a circuit board and chip layout method, and computing devices.

Background technique

In the existing artificial intelligence (referred to as AI) solutions, in order to meet the accelerated processing needs of large-scale data operations, technicians use multiple sets of processing chips to form a tandem structure to build a computing board, and use one or more computing boards to form high performance Computing equipment has greatly improved the computing and processing capabilities for artificial intelligence.

As shown in FIGS. 1A, 1B, and 1C, the existing computing board 1 of the multi-chip series structure generally arranges multiple sets of chips 3 evenly on one side of the PCB board 2, and dissipates heat by arranging the two sides of the PCB board For heat dissipation. The heat dissipation space formed by the front radiator 4A located on the side of the PCB board chip is an effective heat dissipation path of the chip, and the back radiator 4B located on the opposite side of the PCB board plays an auxiliary heat dissipation role. However, the inventor of the present disclosure found that in the current layout of the computing board, so many chips are concentrated on the front of the PCB board, and the layout of the power devices is concentrated, resulting in a large volume power density in the front space of the PCB board and limited heat dissipation paths. The heat dissipation efficiency of the computing board.

Summary of the invention

The embodiments of the present disclosure provide a circuit board, a chip layout method, and a computing device to solve the problem of low heat dissipation efficiency of a computing board in the prior art.

In a first aspect, an embodiment of the present disclosure provides a circuit board, including: a PCB board and two sets of chips disposed on the PCB board;

The first group of chips is arranged on the first side of the PCB board, and the second group of chips is arranged on the second side opposite to the first side of the PCB board;

Wherein, the first group of chips is provided with a first heat sink, and the second group of chips is provided with a second heat sink.

In an optional embodiment, the first group of chips and the second group of chips are arranged in an array on the PCB.

In an optional embodiment, the first group of chips and the second group of chips are arranged in an array on the PCB board and include:

The mapping position of the first group of chips on the PCB board does not overlap with the mapping position of the second group of chips on the PCB board.

In an optional implementation manner, each chip in the first group of chips is provided with a third heat sink at a mapping position on the second surface of the PCB board;

Each chip in the second group of chips is provided with a fourth heat sink at a mapping position on the first surface of the PCB board.

In an optional implementation manner, the connection manner of the third heat sink and the fourth heat sink to the PCB board is a solder connection.

The mapping position of the first group of chips on the PCB board overlaps or partially overlaps with the mapping position of the second group of chips on the PCB board.

In an alternative embodiment, the connection between the first heat sink and the second heat sink and the chip includes one or more of fixing, gluing, and soldering the structural member.

In a second aspect, an embodiment of the present disclosure proposes a chip layout method, which is applied to a PCB. The method includes:

A first group of chips is arranged on the first surface of the PCB board;

A second group of chips is provided on a second side of the PCB board opposite to the first side; and,

A first heat sink and a second heat sink are provided on the first group of chips and the second group of chips, respectively.

In an alternative embodiment, the method includes: arranging the first group of chips and the second group of chips in an array on the PCB.

In a third aspect, an embodiment of the present disclosure provides a computing device, including at least one circuit board as described in any of the implementation manners of the first aspect.

The embodiments of the present disclosure realize the reasonable planning and layout of the chips on the PCB board by arranging the chips on the PCB board, so that the effective heat dissipation space of the circuit board is expanded from the space on the front of the single board to the front and back sides, which reduces the circuit board. The volumetric power density improves the overall heat dissipation efficiency of the circuit board.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments of the present disclosure or the technical solutions in the prior art, the following will briefly introduce the drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description These are some embodiments of the present disclosure. For those of ordinary skill in the art, without paying creative labor, other drawings may be obtained based on these drawings.

FIG. 1A is a schematic side view of a computing board in the prior art along the length direction;

1B is a schematic front view of a computing board in the prior art;

FIG. 1C is a schematic top plan view of a computing board in the prior art;

2A is a schematic side view of the circuit board in the width direction of the first embodiment of the present disclosure;

2B is a schematic front plan view of the circuit board of the first embodiment of the present disclosure;

2C is a schematic top plan view of the circuit board of the first embodiment of the present disclosure;

2D is a schematic side view of the circuit board in the width direction of the second embodiment of the present disclosure;

3A is a schematic side view of the circuit board according to the third embodiment of the present disclosure along the length direction;

3B is a schematic front plan view of the circuit board of the third embodiment of the present disclosure;

3C is a schematic top plan view of a circuit board of a third embodiment of the present disclosure;

3D is a schematic side view of the circuit board according to the fourth embodiment of the present disclosure along the length direction;

4 is a schematic longitudinal cross-sectional view of a heat sink of a circuit board according to an embodiment of the present disclosure;

5 is a flowchart of a chip layout method according to an embodiment of the present disclosure;

6 is a schematic structural diagram of a computing device according to an embodiment of the present disclosure.

detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

2A is a schematic side view of the circuit board in the width direction of the first embodiment of the present disclosure. As shown in FIG. 2A, the circuit board 10 of the embodiment of the present disclosure includes: a PCB board 11, a first group of chips 12A mounted on the first side (front side) of the PCB board 11, and an AND mounted on the PCB board 11 A second group of chips 12B on a second side (reverse side) opposite to the first side, wherein a first heat sink 13A is mounted on the upper surface of the first group of chips 12A, and a second heat sink is mounted on the upper surface of the second group of chips 12B 13B.

In this embodiment, it can be known that by arranging the front and back sides of the chips on the PCB board, a reasonable planning and layout of the chips on the PCB board is realized, so that the effective heat dissipation space of the circuit board is expanded from the space on the front side of the board to the front and back On both sides, the volume power density of the circuit board is reduced, and the overall heat dissipation efficiency of the circuit board is improved.

In some embodiments, the first group of chips 12A and the second group of chips 12B may be integrated circuit IC chips, specifically ASIC-specific integrated circuit chips for performing various data processing operations, for example, may include but It is not limited to the execution of artificial intelligence operations with super high computing power. The circuit board 10 may be a circuit board in a computing device that performs data processing operations, such as an operation board or a computing power board.

FIG. 2B is a schematic front plan view of the circuit board of the first embodiment of the present disclosure, and FIG. 2C is a schematic plan top view of the circuit board of the first embodiment of the present disclosure. As shown in FIGS. 2B and 2C, considering the wiring specifications of the power supply circuit and the signal circuit on the PCB board, the first group of chips 12A located on the front side of the PCB board 11 of the circuit board and the second group located on the back side of the PCB board 11 The chips 12B are arranged in a regular array on the PCB board 11.

The array arrangement of the first group of chips 12A and the second group of chips 12B may be an array arrangement of multiple rows and multiple columns, for example, a uniform array arrangement with equal intervals between rows and equal intervals between columns, or between rows Equal spacing and unequal spacing between columns, or unequal spacing between rows and equidistant spacing between columns, or unequal spacing between rows and columns, etc., are not limited herein.

In a preferred embodiment, as shown in FIG. 2A, the mapping position of the first group of chips 12A on the front of the PCB board 11 on the PCB board 11 and the second group of chips 12B on the opposite side of the PCB board 11 are on the PCB board Does not overlap.

In this embodiment, the staggered arrangement of the front and back chips makes the heat dissipation space on the front and back sides of the PCB more balanced, which further improves the heat dissipation efficiency of the circuit board.

Wherein, the mapping position of the first group of chips 12A on the PCB board 11 and the mapping position of the second group of chips 12B on the PCB board do not overlap include: the mapping position of the single column of the second group of chips 12B on the PCB board is located at the first Between the mapping positions of adjacent columns on the PCB board 11 in the chip group 12A, for example, the mapping may be equidistant mapping between columns, or the mapping may be unequal spacing between columns.

In an alternative embodiment, the mapping position of the first group of chips 12A on the front side of the PCB board 11 on the PCB board 11 and the mapping position of the second group of chips 12B on the opposite side of the PCB board 11 on the PCB board It can also overlap or partially overlap.

Among them, the overlap refers to the mapping position of each chip in the first group of chips 12A on the PCB board 11 corresponds to the mapping position of each chip in the second group of chips 12B on the PCB board, partial overlap refers to the first group The mapping positions of some chips in the chip 12A on the PCB board 11 exactly correspond to the mapping positions of some chips in the second group of chips 12B on the PCB board. This partially overlapping layout can be related to the electrical connection relationship and heat dissipation efficiency. For example, at the fan air inlet, overlap can be used, and at the air outlet, non-overlapping staggered settings can be used.

2D is a schematic side view of the circuit board in the width direction of the second embodiment of the present disclosure. As shown in FIG. 2D, each chip in the first group of chips 12A is provided with a third heat sink 14A at a mapping position on the second surface of the PCB board;

Each chip in the second group of chips 12B is provided with a fourth heat sink 14B at a mapping position on the first surface of the PCB board.

In this embodiment, on the basis of the embodiment described in FIG. 2A, an additional auxiliary heat sink is provided at a position on each side where there is no chip, thereby further improving the heat dissipation efficiency of the circuit board.

FIG. 3A is a schematic side view of a circuit board according to a third embodiment of the present disclosure along the length direction. FIG. 3B is a schematic front plan view of the circuit board of the third embodiment of the present disclosure; FIG. 3C is a schematic plan top view of the circuit board of the third embodiment of the present disclosure. As shown in FIGS. 3A-3C, the mapping position of the first group of chips 12A on the PCB board 11 and the mapping position of the second group of chips 12B on the PCB board do not overlap, and their arrangement is as follows: The mapping position of a single row on the PCB board is located between the mapping positions of adjacent rows in the first group of chips 12A on the PCB board 11, for example, it may be an equal-space mapping between rows or an unequal-space mapping between rows.

FIG. 3D is a schematic side view of the circuit board according to the fourth embodiment of the present disclosure along the length direction. As shown in FIG. 3D, each chip in the first group of chips 12A is provided with a third heat sink 14A at a mapping position on the second surface of the PCB board;

In this embodiment, on the basis of the embodiment described in FIG. 3A, an additional auxiliary heat sink is provided at a position on each side where there is no chip, thereby further improving the heat dissipation efficiency of the circuit board.

In an alternative embodiment, as shown in FIG. 4, the first heat sink 13A, the second heat sink 13B, the third heat sink 14A, and the fourth heat sink 14B may be implemented by using fins of the same size, Of course, different heat sinks are used for implementation, and the disclosure does not limit the implementation form of the radiator. Specifically, if fins of the same size are used, the fins can have the same number and height of fins.

In an alternative embodiment, the heat sink may include a bottom sheet 131 and a plurality of fins 132. The negative film 131 may further include a first portion 131A located in the middle and a second portion 131B and a third portion 131C respectively inclined upward from both sides of the first portion. The bottom surface of the first portion 131A is used for the upper surface of the

chips

12A and 12B Surface fixed connection. The plurality of fins 132 are respectively connected to the top surfaces of the first portion 131A, the second portion 131B, and the third portion 131C of the bottom sheet. The plurality of fins 132 may be arranged in parallel or at equal intervals. In order to facilitate the machine or manual lifting of the heat sink, a gripper 133 can also be provided on the top of one of the fins. The grip 133 may be a sheet-shaped or ring-shaped body connected to the tip of the fin.

In an optional embodiment, the connection between the first heat sink 13A and the second heat sink 13B and the chip includes one or more of fixing, gluing, and welding of structural members. Specifically, the adhesive may use thermally conductive adhesive to connect the bottom surface of the heat sink to the upper surface of the chip. The welding method may be a soldering method.

In some embodiments, the first radiator 13A and the second radiator 13B may use different connection methods, or may use the same connection method.

In an alternative embodiment, the connection between the third heat sink 14A and the fourth heat sink 14B and the PCB board includes soldering. Specifically, it may be a soldering method.

5 is a flowchart of a chip layout method according to an embodiment of the present disclosure. The method is applied to a PCB. As shown in FIG. 5, the chip layout method of the embodiment of the present disclosure includes:

Step S101, setting a first group of chips on the first surface of the PCB board;

Step S102, setting a second group of chips on a second surface of the PCB opposite to the first surface;

In step S103, a first heat sink and a second heat sink are provided on the first group of chips and the second group of chips, respectively.

In this embodiment, the chips on the PCB of the circuit board are laid out on the front and back sides to achieve a reasonable layout of the chips on the PCB board, so that the effective heat dissipation space of the circuit board is expanded from the space on the front of the single board to the front and back sides. , Reduce the volume power density of the circuit board, improve the overall heat dissipation efficiency of the circuit board.

In some embodiments, the first group of chips and the second group may be integrated circuit IC chips, specifically ASIC-specific integrated circuit chips for performing various data processing operations, such as but not limited to execution Artificial intelligence computing. The circuit board may be a circuit board in a computing device that performs data processing operations, such as an operation board or a computing power board.

In an optional embodiment, the method further includes: arranging the first group of chips and the second group of chips in an array on the PCB.

In an optional embodiment, arranging the first group of chips and the second group of chips on the PCB in an array includes:

The mapping position of the first group of chips on the PCB board and the mapping position of the second group of chips on the PCB board do not overlap.

In an optional embodiment, the method further includes: setting a third heat sink at a mapping position on the second side of the PCB of each chip in the first group of chips; Each chip in the second group of chips is provided with a fourth heat sink at a mapped position on the first side of the PCB board.

The mapping positions of the first group of chips on the PCB board and the mapping positions of the second group of chips on the PCB board overlap or partially overlap.

In an optional embodiment, the connection between the first heat sink, the second heat sink and the chip includes one or more of fixing, gluing and soldering of the structural member.

In an optional embodiment, the connection between the third heat sink and the fourth heat sink and the PCB board is a solder connection.

6 is a schematic structural diagram of a computing device according to an embodiment of the present disclosure. As shown in FIG. 6, in the embodiment of the present disclosure, the computing device 100 includes at least one circuit board 10. The embodiments of the circuit board 10 include any embodiments of the present disclosure, and will not be repeated here.

It should be noted that FIG. 5 only schematically illustrates the case where the computing device 100 includes one circuit board. In actual applications, the number of circuit boards in the computing device can be configured as needed according to the demands of computing performance.

In this embodiment, the computing device may generally be any computer or other terminal device capable of performing computing tasks, which is not limited in any way.

The circuit board, the chip layout method and the computing device disclosed in the embodiments of the present disclosure realize the reasonable planning and layout of the chips on the PCB board by arranging the front and back sides of the chips on the PCB board, so that the effective heat dissipation space of the circuit board can be reduced The space on the front is extended to both sides, which reduces the volume power density of the circuit board and improves the overall heat dissipation efficiency of the circuit board.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, but not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features thereof may be equivalently replaced; and these modifications or replacements do not deviate from the essence of the corresponding technical solutions of the technical solutions of the embodiments of the present disclosure range.

Claims

A circuit board, characterized by comprising a PCB board and two groups of chips arranged on the PCB board;

The first group of chips is arranged on the first side of the PCB board, and the second group of chips is arranged on the second side opposite to the first side of the PCB board;

Wherein, the first group of chips is provided with a first heat sink, and the second group of chips is provided with a second heat sink.
The circuit board according to claim 1, wherein the first group of chips and the second group of chips are arranged in an array on the PCB board.
The circuit board according to claim 2, wherein the first group of chips and the second group of chips are arranged in an array on the PCB board including:

The mapping position of the first group of chips on the PCB board does not overlap with the mapping position of the second group of chips on the PCB board.
The circuit board according to claim 3, wherein each chip in the first group of chips is provided with a third heat sink at a mapping position on the second surface of the PCB board;

Each chip in the second group of chips is provided with a fourth heat sink at a mapping position on the first surface of the PCB board.
The circuit board according to claim 4, wherein the connection between the third heat sink and the fourth heat sink and the PCB board is a solder connection.
The circuit board according to claim 2, wherein the first group of chips and the second group of chips are arranged in an array on the PCB board including:

The mapping position of the first group of chips on the PCB board overlaps or partially overlaps with the mapping position of the second group of chips on the PCB board.
The circuit board according to claim 1, wherein the connection manners of the first heat sink, the second heat sink and the chip include one or more of fixing, gluing and soldering of structural parts.
A chip layout method, applied to a PCB board, characterized by including:

A first group of chips is arranged on the first surface of the PCB board;

A second group of chips is provided on a second side of the PCB board opposite to the first side; and,

A first heat sink and a second heat sink are provided on the first group of chips and the second group of chips, respectively.
The chip layout method according to claim 8, further comprising: arranging the first group of chips and the second group of chips in an array on the PCB.
A computing device, characterized by comprising at least one circuit board according to any one of claims 1-7.