WO2020083019A1 - 一种基于多核处理器的解码方法、终端设备及存储介质 - Google Patents

一种基于多核处理器的解码方法、终端设备及存储介质 Download PDF

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Publication number
WO2020083019A1
WO2020083019A1 PCT/CN2019/109895 CN2019109895W WO2020083019A1 WO 2020083019 A1 WO2020083019 A1 WO 2020083019A1 CN 2019109895 W CN2019109895 W CN 2019109895W WO 2020083019 A1 WO2020083019 A1 WO 2020083019A1
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Prior art keywords
decoding
core
decoded
cores
image
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PCT/CN2019/109895
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English (en)
French (fr)
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汤增宏
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百富计算机技术（深圳）有限公司
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Publication of WO2020083019A1 publication Critical patent/WO2020083019A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/10—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation
    • G06K7/10544—Methods or arrangements for sensing record carriers, e.g. for reading patterns by electromagnetic radiation, e.g. optical sensing; by corpuscular radiation by scanning of the records by radiation in the optical part of the electromagnetic spectrum

Definitions

  • the present application belongs to the technical field of decoding, and particularly relates to a decoding method based on a multi-core processor, a terminal device, and a computer-readable storage medium.
  • QR code scanning functions such as certain browser software clients and instant messaging software clients.
  • the embodiments of the present application provide a decoding method based on a multi-core processor, a terminal device, and a computer-readable storage medium to solve the problems of slow decoding process and long time in the current decoding process.
  • a first aspect of the embodiments of the present application provides a decoding method based on a multi-core processor, including:
  • N cores from the multi-core processor are decoding cores, where N is less than or equal to the number of cores of the multi-core processor;
  • a second aspect of the embodiments of the present application provides a terminal device, including:
  • An image acquisition unit configured to select a core from the multi-core processor as a main core, and obtain an image to be decoded through the main core;
  • a decoding core selection unit configured to select N cores from the multi-core processor as decoding cores, where N is less than or equal to the number of cores of the multi-core processor;
  • the decoding unit is configured to simultaneously decode the image to be decoded by N decoding cores.
  • a third aspect of the embodiments of the present application provides a terminal device, including a memory, a multi-core processor, and a computer program stored in the memory and executable on the multi-core processor, the multi-core processor executing the The computer program implements the steps of the method provided in the first aspect of the embodiments of the present application.
  • a fourth aspect of the embodiments of the present application provides a computer-readable storage medium that stores a computer program that is executed by one or more multi-core processors to implement the first In one aspect, the steps of the method are provided.
  • a fifth aspect of the embodiments of the present application provides a computer program product.
  • the computer program product includes a computer program, and the computer program is executed by one or more multi-core processors. Describe the steps of the method.
  • An embodiment of the present application provides a decoding method based on a multi-core processor.
  • a core is selected from the multi-core processor as a main core, and an image to be decoded is obtained through the main core, and N is selected from the multi-core processor.
  • Each core serves as a decoding core, where N is less than or equal to the number of cores of the multi-core processor, and the image to be decoded is simultaneously decoded by N decoding cores.
  • FIG. 1 is a schematic flowchart of a decoding method based on a multi-core processor provided by an embodiment of the present application
  • FIG. 2 is a schematic flowchart of another decoding method based on a multi-core processor provided by an embodiment of the present application
  • FIG. 3 is a schematic flowchart of another decoding method based on a multi-core processor provided by an embodiment of the present application
  • FIG. 4 is a schematic block diagram of a terminal device provided by an embodiment of the present application.
  • FIG. 5 is a schematic block diagram of another terminal device provided by an embodiment of the present application.
  • the term “if” may be interpreted as “when” or “once” or “in response to determination” or “in response to detection” depending on the context .
  • the phrase “if determined” or “if [described condition or event] is detected” may be interpreted in the context to mean “once determined” or “in response to a determination” or “once detected [described condition or event ] “Or” In response to detection of [the described condition or event] ".
  • FIG. 1 is a schematic flowchart of an implementation of a decoding method based on a multi-core processor provided by an embodiment of the present application. As shown in the figure, the method may include the following steps:
  • step S101 a core is selected from the multi-core processor as the main core, and the image to be decoded is obtained through the main core.
  • one core in the multi-core processor may be defined as the main core.
  • any core may be selected as the main core.
  • the camera is usually called to collect the image to be decoded, so the image to be decoded can be obtained from the camera.
  • the camera can be stored in the preset storage after the image to be decoded Therefore, the main core can also obtain the image to be decoded from the preset storage space.
  • Step S102 Select N cores from the multi-core processor as decoding cores, where N is less than or equal to the number of cores of the multi-core processor.
  • a part of cores in the multi-core processor may be selected for running decoding tasks, or all cores in the multi-core processor may be used for running decoding tasks.
  • a 4-core processor may use All the cores run the decoding task.
  • the embodiment of the present application records the core running the decoding task as the decoding core.
  • Step S103 Decode the image to be decoded simultaneously by N decoding cores.
  • the decoding kernel used to run the decoding task can decode the image to be decoded at the same time.
  • multiple encoding codes are stored in the system, and the selected N decoding cores can sequentially select the encoding codes to decode the image to be decoded.
  • the system stores the code system A1, A2, A3, A4, A5, A6, A7, A8, A9, A10.
  • N 4, the four decoding cores respectively select the coding system in order to decode the image to be decoded, the first decoding core selects A1, decodes the image to be decoded based on A1, the second decoding core selects A2, based on A2 To decode the image to be decoded, the third decoding core selects A3, decodes the image to be decoded based on A3, and the fourth decoding core selects A4, and decodes the image to be decoded based on A4.
  • the four decoding cores after any one of the selected coding system fails to decode the image to be decoded, continue to select an unselected coding system from the coding system queue to continue decoding the image to be decoded.
  • the decoding result is generated; or until all the encoding code systems are selected, the decoded image is not successfully decoded, which means that the decoding fails.
  • one core is selected from the multi-core processor as the main core, and the image to be decoded is obtained through the main core, and N cores are selected from the multi-core processor as the decoding core, where N is less than or equal to The number of cores of the multi-core processor simultaneously decodes the image to be decoded through N decoding cores. Since multiple cores decode the image to be decoded at the same time, the decoding speed can be improved.
  • FIG. 2 is a schematic diagram of an implementation process of another decoding method based on a multi-core processor provided by an embodiment of the present application. As shown in the figure, the method may include the following steps:
  • step S201 a core is selected from the multi-core processor as the main core, and the image to be decoded is obtained through the main core.
  • step S101 This step is consistent with the content of step S101. For details, reference may be made to the description of step S101, and details are not described herein again.
  • Step S202 Select N cores from the multi-core processor as decoding cores, where N is less than or equal to the number of cores of the multi-core processor.
  • the selected decoding core includes a main core.
  • a multi-core processor is a 4-core processor, from which one core is selected as the main core, and all four cores are used as decoding cores.
  • Step S203 Acquire a plurality of pre-stored coding systems, and divide the multiple coding systems into N groups, where each decoding core corresponds to a set of coding codes.
  • a plurality of encoding code systems pre-stored in the system can be acquired, and the plurality of encoding code systems can be divided into N groups, and the plurality of decoding code systems can be sorted according to historical use frequency from high to bottom ; Divide the sorted multiple decoded code systems into N groups, where the sequence number of the i-th decoded code system is i + aN, a is a natural number greater than or equal to 0, i ⁇ [1, N].
  • the first group is the coding system of the sequence number 1 + 4a, namely the first (A1), fifth (B1), ninth (C1), ....
  • the second group is the coding system of the sequence number 2 + 4a, namely the 2nd (A2), 6th (B2), 10th (C2), ...
  • the third group is the coding system of the sequence number 3 + 4a, namely the 3rd (A3), 7th (B3), 11th (C3), ....
  • the fourth group is the coding system of the sequence number 4 + 4a, namely the 4th (A4), 8th (B4), 12th (C4), ....
  • each decoding core corresponds to a set of coding system.
  • step S204 N decoding kernels simultaneously decode the image to be decoded based on their respective sorted encoded code values.
  • the encoding code values corresponding to each decoding core may also be sorted according to historical use frequency from high to low.
  • the historical use frequency may be found first, or the number of successful decodings according to history may be used.
  • each decoding core decodes based on the corresponding set of coding codes, and one decoding core decodes the image to be decoded based on each corresponding coding code, Either succeed or fail. If successful, the entire decoding task will be ended in advance; if it fails, then select the next encoding system in order to decode the image to be decoded.
  • Step S205 If the master core successfully decodes the image to be decoded, the master core stops decoding, and sends an instruction to stop decoding to a decoding core other than the master core.
  • Step S206 if the decoding core other than the main core successfully decodes the image to be decoded, the decoding core that currently decodes successfully stops decoding, and sends a successful decoding instruction to the main core.
  • step S207 after receiving the successful decoding instruction, the master core sends an instruction to stop decoding to the decoding core outside the master core.
  • Step S208 if the decoding core other than the main core fails to decode the image to be decoded by each corresponding decoding code system, an instruction that the decoding fails is sent to the main core.
  • the decoding is stopped, and the decoding cores other than the main core are notified to stop decoding, so that all the cores All decoding is stopped, and the current decoding task is successful.
  • the decoding core other than the main core decodes the image to be decoded successfully based on the corresponding decoding code system
  • the decoding is stopped, and the decoding by the main core is successful.
  • the other cores (the main core and the decoding core that successfully decodes) External decoding core) to send an instruction to stop decoding.
  • FIG. 3 is a schematic diagram of an implementation process of another decoding method based on a multi-core processor provided by an embodiment of the present application. As shown in the figure, the method may include the following steps:
  • Step S301 Select a core from the multi-core processor as the main core, and obtain the image to be decoded through the main core.
  • step S101 This step is consistent with the content of step S101. For details, reference may be made to the description of step S101, and details are not described herein again.
  • Step S302 Select N cores from the multi-core processor as decoding cores, where N is less than or equal to the number of cores of the multi-core processor.
  • a multi-core processor is a 4-core processor, from which one core is selected as the main core, and the other three cores are all used as decoding cores.
  • Step S303 Acquire a plurality of pre-stored coding systems and divide the multiple coding systems into N groups, where each decoding core corresponds to a group of coding codes.
  • step S304 the coding code values corresponding to each decoding kernel are sorted according to historical use frequency from high to low.
  • step S305 the N decoding cores simultaneously decode the image to be decoded based on their respective sorted encoded code values.
  • a plurality of pre-stored coding systems may be divided into three groups, and each decoding core corresponds to a group of coding systems. Each group of coding systems can be sorted according to historical use frequency or historical decoding success times.
  • the three decoding cores simultaneously run the decoding task, and each decoding core decodes the image to be decoded based on the corresponding encoding code system. Of course, it is the same as the embodiment shown in FIG.
  • the corresponding coding system decodes the image to be decoded.
  • Step S306 if any decoding core successfully decodes the image to be decoded, the decoding core that has successfully decoded currently stops decoding, and sends a successful decoding instruction to the main core.
  • step S307 after receiving the decoding successful instruction, the master core sends an instruction to stop decoding to the decoding kernel.
  • step S308 if the decoding core fails to decode the image to be decoded by each corresponding decoding code system, an instruction of decoding failure is sent to the main core.
  • the main core since the main core does not participate in the decoding process based on the encoding and coding system, after any decoding core successfully decodes the image to be decoded, the decoding core that has successfully decoded stops decoding and sends The core sends an instruction for successful decoding, and after receiving the instruction for successful decoding, the master core sends an instruction to stop decoding to all decoding cores or other decoding cores that are currently successfully decoded.
  • FIG. 4 is a schematic block diagram of a terminal device provided by an embodiment of the present application. For ease of description, only parts related to the embodiment of the present application are shown.
  • the terminal device 4 may be a software unit, a hardware unit, or a combination of software and hardware on terminal devices such as mobile phones and computers, and may be integrated into the terminal devices such as mobile phones and computers as independent pendants.
  • the terminal device 4 includes:
  • the image obtaining unit 41 is configured to select a core from the multi-core processor as a main core, and obtain an image to be decoded through the main core;
  • the decoding unit 43 is configured to simultaneously decode the image to be decoded by N decoding cores.
  • the terminal device 4 further includes:
  • the encoding code system grouping unit 44 is configured to acquire a plurality of encoding code systems stored in advance, and divide the plurality of encoding code systems into N groups, where each decoding core corresponds to a group of encoding code values.
  • the coding code grouping unit 44 includes:
  • the first sorting module 441 is used to sort the multiple decoding code systems according to historical usage frequency from high to low;
  • the grouping module 442 is used to divide the sorted multiple decoded code systems into N groups, in which the sequence number of the i-th decoded code system is i + aN, a is a natural number greater than or equal to 0, i ⁇ [1, N].
  • the decoding unit 43 includes:
  • the second sorting module 431 is used to sort the code value corresponding to each decoding core according to historical use frequency from high to low;
  • the decoding module 432 is used for N decoding cores to simultaneously decode the image to be decoded based on the corresponding sorted encoding code values.
  • the decoding unit 43 is further configured to:
  • the master core If the master core successfully decodes the image to be decoded, the master core stops decoding, and sends an instruction to stop decoding to a decoding kernel other than the master core;
  • the decoding core other than the main core decodes the image to be decoded successfully, the decoding core that currently decodes successfully stops decoding, and sends a successful decoding instruction to the main core;
  • the master core After receiving the instruction for successful decoding, the master core sends an instruction to stop decoding to the decoding core outside the master core;
  • the decoding unit 43 is further configured to:
  • the decoding core that currently decodes successfully stops decoding, and sends a successful decoding instruction to the main core;
  • the master core After receiving the successful decoding instruction, the master core sends an instruction to stop decoding to the decoding core;
  • the decoding core fails to decode the image to be decoded by each corresponding decoding code system, an instruction that the decoding fails is sent to the main core.
  • the N is equal to the number of cores of the multi-core processor.
  • each functional unit and module is used as an example for illustration.
  • the above-mentioned functions can be allocated by different functional units
  • the module is completed, that is, the internal structure of the terminal device is divided into different functional units or modules to complete all or part of the functions described above.
  • the functional units and modules in the embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above integrated unit may use hardware It can also be implemented in the form of software functional units.
  • the specific names of each functional unit and module are only for the purpose of distinguishing each other, and are not used to limit the protection scope of the present application.
  • For specific working processes of the units and modules in the foregoing terminal device reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described herein again.
  • FIG. 5 is a schematic block diagram of a terminal device provided by another embodiment of the present application.
  • the terminal device 5 may include: one or more multi-core processors 50, a memory 51, and a computer program 52 stored in the memory 51 and executable on the multi-core processor 50.
  • the steps in the above method embodiments are implemented, for example, steps S101 to S103 shown in FIG. 1.
  • the multi-core processor 50 executes the computer program 52, the functions of each module / unit in the foregoing embodiment of the terminal device are realized, for example, the functions of the modules 41 to 43 shown in FIG. 4.
  • the computer program 52 may be divided into one or more modules / units, and the one or more modules / units are stored in the memory 51 and executed by the multi-core processor 50 to Complete this application.
  • the one or more modules / units may be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 52 in the terminal device 5.
  • the computer program 52 may be divided into an image acquisition unit, a decoding kernel selection unit, and a decoding unit.
  • An image acquisition unit configured to select a core from the multi-core processor as a main core, and obtain an image to be decoded through the main core;
  • a decoding core selection unit configured to select N cores from the multi-core processor as decoding cores, where N is less than or equal to the number of cores of the multi-core processor;
  • the decoding unit is configured to simultaneously decode the image to be decoded by N decoding cores.
  • the terminal device includes but is not limited to a multi-core processor 50 and a memory 51.
  • FIG. 5 is only an example of the terminal device 5 and does not constitute a limitation on the terminal device 5, and may include more or less components than the illustration, or a combination of certain components, or different Components, for example, the terminal device may further include an input device, an output device, a network access device, a bus, and the like.
  • the multi-core processor 50 may be a central processing unit (Central Processing Unit (CPU), can also be other general-purpose multi-core processors, digital signal multi-core processors (Digital Signal Processor, DSP), application-specific integrated circuits (Application Specific Integrated Circuit (ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose multi-core processor may be a micro-multi-core processor or the multi-core processor may also be any conventional multi-core processor.
  • the memory 51 may be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5.
  • the memory 51 may also be an external storage device of the terminal device 5, for example, a plug-in hard disk equipped on the terminal device 5, a smart memory card (Smart Media Card, SMC), and secure digital (SD) Flash card Card) etc.
  • the memory 51 may also include both an internal storage unit of the terminal device 5 and an external storage device.
  • the memory 51 is used to store the computer program and other programs and data required by the terminal device.
  • the memory 51 can also be used to temporarily store data that has been or will be output.
  • the disclosed terminal device and method may be implemented in other ways.
  • the embodiments of the terminal device described above are only schematic.
  • the division of the module or unit is only a division of logical functions.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or software function unit.
  • the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the present application can implement all or part of the processes in the methods of the above embodiments, or it can be completed by a computer program instructing relevant hardware.
  • the computer program can be stored in a computer-readable storage medium.
  • the steps of the foregoing method embodiments may be implemented.
  • the computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file, or some intermediate form, etc.
  • the computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disc, a computer memory, a read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signals, telecommunication signals, and software distribution media.
  • ROM Read-Only Memory
  • RAM Random Access Memory

Abstract

本申请适用于解码技术领域，提供了一种基于多核处理器的解码方法、终端设备及计算机可读存储介质，所述方法包括：从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量，通过N个解码内核同时对所述待解码图像进行解码，通过本申请可以提高解码过程的速度，降低解码时间。

Description

一种基于多核处理器的解码方法、终端设备及存储介质 技术领域
本申请属于解码技术领域，尤其涉及一种基于多核处理器的解码方法、终端设备及计算机可读存储介质。
 背景技术
目前，随着二维码图片在各个领域的广泛应用，用户通过手机扫描二维码图片获取信息的方式也得到广泛应用。为了便于扫描二维码，很多应用的客户端程序中集成了二维码扫描功能，例如某些浏览器软件客户端、即时通讯软件客户端等。
实际应用中，不仅存在二维码图片，还存在一维码等其他类型的待解码图片；并且，由于存在不同的编码码制，在扫描待解码图片获取信息时需要手机等终端设备一侧通过本身存储的每一种编码码制对扫描的二维码图像进行解码，这样，造成解码过程速度慢、时间长的问题。
 技术问题
有鉴于此，本申请实施例提供了一种基于多核处理器的解码方法、终端设备及计算机可读存储介质，以解决目前解码过程速度慢、时间长的问题。
 技术解决方案
本申请实施例的第一方面提供了一种基于多核处理器的解码方法，包括：
从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
通过N个解码内核同时对所述待解码图像进行解码。
本申请实施例的第二方面提供了一种终端设备，包括：
图像获取单元，用于从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
解码内核选取单元，用于从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
解码单元，用于通过N个解码内核同时对所述待解码图像进行解码。
本申请实施例的第三方面提供了一种终端设备，包括存储器、多核处理器以及存储在所述存储器中并可在所述多核处理器上运行的计算机程序，所述多核处理器执行所述计算机程序时实现本申请实施例第一方面提供的所述方法的步骤。
本申请实施例的第四方面提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被一个或多个多核处理器执行时实现本申请实施例第一方面提供的所述方法的步骤。
本申请实施例的第五方面提供了一种计算机程序产品，所述计算机程序产品包括计算机程序，所述计算机程序被一个或多个多核处理器执行时实现本申请实施例第一方面提供的所述方法的步骤。
 有益效果
本申请实施例提供了一种基于多核处理器的解码方法，从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量，通过N个解码内核同时对所述待解码图像进行解码。通过本申请可以提高解码速度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种基于多核处理器的解码方法的流程示意图；
图2是本申请实施例提供的另一种基于多核处理器的解码方法的流程示意图；
图3是本申请实施例提供的另一种基于多核处理器的解码方法的流程示意图；
图4是本申请实施例提供的一种终端设备的示意框图；
图5是本申请实施例提供的另一种终端设备的示意框图。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
为了说明本申请所述的技术方案，下面通过具体实施例来进行说明。
图1是本申请实施例提供的一种基于多核处理器的解码方法的实现流程示意图，如图所示该方法可以包括以下步骤：
步骤S101，从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像。
在本申请实施例中，可以定义所述多核处理器中的一个内核为主核，实际应用中，可以选择任意一个内核作为主核，在确定主核后，通过主核从摄像头或预设的存储空间中获取待解码图像，在进行扫码时，通常会调用摄像头采集待解码图像，因此可以从摄像头获取待解码图像，另外，由于摄像头在采集待解码图像后，可以存储在预设的存储空间，因此，主核也可以从预设的存储空间获取待解码图像。
步骤S102，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量。
在本申请实施例中，可以从所述多核处理器中选取一部分内核用于运行解码任务，也可以将所述多核处理器中的全部内核用于运行解码任务，例如，4核处理器可以将全部内核运行解码任务，8核处理器中可以选择其中4个或6个内核用于运行解码任务。为了方便区别不同的内核，本申请实施例将运行解码任务的内核记为解码内核。
步骤S103，通过N个解码内核同时对所述待解码图像进行解码。
在本申请实施例中，用于运行解码任务的解码内核可以同时对待解码图像进行解码。在实际应用中，系统中存储了多个编码码制，选取的N个解码内核可以依次选取编码码制对待解码图像进行解码。例如，系统中存储了编码码制A1、A2、A3、A4、A5、A6、A7、A8、A9、A10。N=4，4个解码内核按照次序分别选取编码码制，用于对待解码图像进行解码，第一个解码内核选取A1，基于A1对待解码图像进行解码，第二个解码内核选取A2，基于A2对待解码图像进行解码，第三个解码内核选取A3，基于A3对待解码图像进行解码，第四个解码内核选取A4，基于A4对待解码图像进行解码。在4个解码内核中，任意一个通过选取的编码码制对待解码图像解码失败后，继续从编码码制的队列中选取未被选取的一个编码码制继续对待解码图像进行解码。直到其中一个解码内核通过选取的编码码制对待解码图像解码成功，这样就生成解码结果；或者直到将所有的编码码制选取完毕，依然未对待解码图像解码成功，这样就表示解码失败。
本申请实施例从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量，通过N个解码内核同时对所述待解码图像进行解码。由于，通过多个内核同时对待解码图像进行解码，因此可以提高解码速度。
图2是本申请实施例提供的另一种基于多核处理器的解码方法的实现流程示意图，如图所示，该方法可以包括以下步骤：
步骤S201，从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像。
该步骤与步骤S101内容一致，具体可参照步骤S101的描述，在此不再赘述。
步骤S202，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量。
在本申请实施例中，以N等于所述多核处理器的内核数量为例，那么选取的解码内核包括主核。例如，多核处理器为4核处理器，从其中选取一个内核作为主核，4个内核均作为解码内核。
步骤S203，获取预先存储的多个编码码制，并将多个编码码制划分为N组，其中，每个解码内核对应一组编码码值。
在本申请实施例中，可以获取系统中预先存储的多个编码码制，并将多个编码码制划分为N组，可以对所述多个解码码制按照历史使用频率从高到底进行排序；将排序后的多个解码码制划分为N组，其中，第i组解码码制的排序序号为i+aN，a为大于或等于0的自然数，i∈[1,N]。
作为举例，按照历史使用频率从高到低对系统中存储的多个编码码制进行排序：A1,A2,A3,A4,B1,B2,B3,B4,C1,C2,C3,C4,D1,D2,D3,D4,E1......。
第一组为排序序号1+4a的编码码制，即第1个（A1）、第5个（B1）、第9个（C1）、……。
第二组为排序序号2+4a的编码码制，即第2个（A2）、第6个（B2）、第10个（C2）、……。
第三组为排序序号3+4a的编码码制，即第3个（A3）、第7个（B3）、第11个（C3）、……。
第四组为排序序号4+4a的编码码制，即第4个（A4）、第8个（B4）、第12个（C4）、……。
分组后，每个解码内核对应一组编码码制。
步骤S204，N个解码内核同时基于各自对应的排序后的编码码值对所述待解码图像进行解码。
在本申请实施例中，在进行解码前，也可以对每个解码内核对应的编码码值按照历史使用频率从高到低进行排序。
需要说明，在对所述编码码制进行排序时，可以先找历史使用频率，也可以按照历史解码成功的次数。
在多个解码内核同时对待解码图像进行解码时，每个解码内核都是基于各自对应的一组编码码制进行解码，其中一个解码内核在基于对应的每一个编码码制对待解码图像进行解码，要么成功，要么失败，成功则提前结束整个解码任务；失败接着按照顺序选取下一个编码码制对待解码图像进行解码。
在实际应用中，需要多个内核之间相互知晓是否有其他内核解码成功，在有其他内核解码成功时，停止解码任务，如步骤S205至步骤S208的描述。
步骤S205，若所述主核对所述待解码图像解码成功，则所述主核停止解码，并向所述主核之外的解码内核发送停止解码的指令。
步骤S206，若主核之外的解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令。
步骤S207，所述主核在接收到解码成功的指令后，向所述主核之外解码内核发送停止解码的指令。
步骤S208，若所述主核之外的解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
在本申请实施例中，预先选取的主核通过对应的编码码制对所述待解码图像解码成功后，停止解码，并通知所述主核之外的解码内核停止解码，这样，所有的内核均停止解码，当前解码任务成功。
主核之外的解码内核基于对应的解码码制对所述待解码图像解码成功后，停止解码，并通过主核解码成功，主核向的其他解码内核（主核和解码成功的解码内核之外的解码内核）发送停止解码的指令。
如果所有的解码内核均未接收到解码成功或者停止解码的指令，则需要按照顺序依次选取各自对应的编码码制对所述待解码图像进行解码，直到全部解码失败或者通过一个编码码制对所述待解码图像解码成功。若是全部解码失败，需要通知主核解码失败。
图3是本申请实施例提供的另一种基于多核处理器的解码方法的实现流程示意图，如图所示，该方法可以包括以下步骤：
步骤S301，从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像。
该步骤与步骤S101内容一致，具体可参照步骤S101的描述，在此不再赘述。
步骤S302，从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量。
在本申请实施例中，以N小于所述多核处理器的内核数量为例，且选取的解码内核不包括主核。例如，多核处理器为4核处理器，从其中选取一个内核作为主核，另外3个内核均作为解码内核。
步骤S303，获取预先存储的多个编码码制，并将多个编码码制划分为N组，其中，每个解码内核对应一组编码码值。
步骤S304，对每个解码内核对应的编码码值按照历史使用频率从高到低进行排序。
步骤S305，N个解码内核同时基于各自对应的排序后的编码码值对所述待解码图像进行解码。
在本申请实施例中，可以将预先存储的多个编码码制划分为3组，每一个解码内核对应一组编码码制。每一组编码码制可以根据历史使用频率或者历史解码成功次数进行排序。3个解码内核同时运行解码任务，其中每一个解码内核都是基于各自对应的编码码制对所述待解码图像进行解码，当然，与图2所示实施例相同，也需要按照顺序依次选取各自对应的编码码制对待解码图像进行解码。
步骤S306，若任意一个解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令。
步骤S307，所述主核在接收到解码成功的指令后，向所述解码内核发送停止解码的指令。
步骤S308，若所述解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
在本申请实施例中，由于主核不参与基于编码码制解码的过程，任意的解码内核在对所述待解码图像解码成功后，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令，主核在接收到解码成功的指令后，向所有解码内核或者当前解码成功的其它解码内核发送停止解码的指令。
当然，若所述解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
图4是本申请一实施例提供的终端设备的示意框图，为了便于说明，仅示出与本申请实施例相关的部分。
该终端设备4可以是手机、计算机等终端设备上的软件单元、硬件单元或者软硬结合的单元，可以作为独立的挂件集成到所述手机、计算机等终端设备中。
所述终端设备4包括：
图像获取单元41，用于从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
解码内核选取单元42，用于从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
解码单元43，用于通过N个解码内核同时对所述待解码图像进行解码。
作为本申请另一实施例，所述终端设备4还包括：
编码码制分组单元44，用于获取预先存储的多个编码码制，并将多个编码码制划分为N组，其中，每个解码内核对应一组编码码值。
作为本申请另一实施例，所述编码码制分组单元44包括：
第一排序模块441，用于对所述多个解码码制按照历史使用频率从高到底进行排序；
分组模块442，用于将排序后的多个解码码制划分为N组，其中，第i组解码码制的排序序号为i+aN，a为大于或等于0的自然数，i∈[1,N]。
作为本申请另一实施例，所述解码单元43包括：
第二排序模块431，用于对每个解码内核对应的编码码值按照历史使用频率从高到低进行排序；
解码模块432，用于N个解码内核同时基于各自对应的排序后的编码码值对所述待解码图像进行解码。
作为本申请另一实施例，当所述解码内核包括主核时，所述解码单元43还用于：
若所述主核对所述待解码图像解码成功，则所述主核停止解码，并向所述主核之外的解码内核发送停止解码的指令；
若主核之外的解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令；
所述主核在接收到解码成功的指令后，向所述主核之外解码内核发送停止解码的指令；
若所述主核之外的解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
作为本申请另一实施例，当所述解码内核不包括主核时，所述解码单元43还用于：
若任意一个解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令；
所述主核在接收到解码成功的指令后，向所述解码内核发送停止解码的指令；
若所述解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
作为本申请另一实施例，所述N等于所述多核处理器的内核数量。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述终端设备的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述终端设备中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
图5是本申请又一实施例提供的终端设备的示意框图。如图5所示，该终端设备5可以包括：一个或多个多核处理器50、存储器51以及存储在所述存储器51中并可在所述多核处理器50上运行的计算机程序52。所述多核处理器50执行所述计算机程序52时实现上述各个方法实施例中的步骤，例如图1所示的步骤S101至S103。或者，所述多核处理器50执行所述计算机程序52时实现上述终端设备实施例中各模块/单元的功能，例如图4所示模块41至43的功能。
示例性的，所述计算机程序52可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器51中，并由所述多核处理器50执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序52在所述终端设备5中的执行过程。例如，所述计算机程序52可以被分割成图像获取单元、解码内核选取单元、解码单元。
图像获取单元，用于从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
解码内核选取单元，用于从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
解码单元，用于通过N个解码内核同时对所述待解码图像进行解码。
其它单元或模块可参照图4所示的实施例中的描述，在此不再赘述。
所述终端设备包括但不仅限于多核处理器50、存储器51。本领域技术人员可以理解，图5仅仅是终端设备5的一个示例，并不构成对终端设备5的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述终端设备还可以包括输入设备、输出设备、网络接入设备、总线等。
所述多核处理器50可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用多核处理器、数字信号多核处理器 (Digital Signal Processor，DSP)、专用集成电路 (Application Specific Integrated Circuit，ASIC)、现成可编程门阵列 (Field-Programmable Gate Array，FPGA) 或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用多核处理器可以是微多核处理器或者该多核处理器也可以是任何常规的多核处理器等。
所述存储器51可以是所述终端设备5的内部存储单元，例如终端设备5的硬盘或内存。所述存储器51也可以是所述终端设备5的外部存储设备，例如所述终端设备5上配备的插接式硬盘，智能存储卡（Smart Media Card, SMC），安全数字（Secure Digital, SD）卡，闪存卡（Flash Card）等。进一步地，所述存储器51还可以既包括所述终端设备5的内部存储单元也包括外部存储设备。所述存储器51用于存储所述计算机程序以及所述终端设备所需的其他程序和数据。所述存储器51还可以用于暂时地存储已经输出或者将要输出的数据。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的终端设备和方法，可以通过其它的方式实现。例如，以上所描述的终端设备实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的模块/单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被多核处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器（ROM，Read-Only Memory）、随机存取存储器（RAM，Random Access Memory）、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括是电载波信号和电信信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种基于多核处理器的解码方法，其特征在于，包括：
    从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
    从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
    通过N个解码内核同时对所述待解码图像进行解码。
  2. 如权利要求1所述的基于多核处理器的解码方法，其特征在于，所述通过N个解码内核同时对所述待解码图像进行解码之前，还包括：
    获取预先存储的多个编码码制，并将多个编码码制划分为N组，其中，每个解码内核对应一组编码码值。
  3. 如权利要求2所述的基于多核处理器的解码方法，其特征在于，所述将多个编码码制划分为N组包括：
    对所述多个解码码制按照历史使用频率从高到底进行排序；
    将排序后的多个解码码制划分为N组，其中，第i组解码码制的排序序号为i+aN，a为大于或等于0的自然数，i∈[1,N]。
  4. 如权利要求2所述的基于多核处理器的解码方法，其特征在于，所述通过N个解码内核同时对所述待解码图像进行解码包括：
    对每个解码内核对应的编码码值按照历史使用频率从高到低进行排序；
    N个解码内核同时基于各自对应的排序后的编码码值对所述待解码图像进行解码。
  5. 如权利要求1所述的基于多核处理器的解码方法，其特征在于，当所述解码内核包括主核时，在N个解码内核同时对所述待解码图像进行解码时，还包括：
    若所述主核对所述待解码图像解码成功，则所述主核停止解码，并向所述主核之外的解码内核发送停止解码的指令；
    若主核之外的解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令；
    所述主核在接收到解码成功的指令后，向所述主核之外解码内核发送停止解码的指令；
    若所述主核之外的解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
  6. 如权利要求1所述的基于多核处理器的解码方法，其特征在于，当所述解码内核不包括主核时，在N个解码内核同时对所述待解码图像进行解码时，还包括：
    若任意一个解码内核对所述待解码图像解码成功，则当前解码成功的解码内核停止解码，并向所述主核发送解码成功的指令；
    所述主核在接收到解码成功的指令后，向所述解码内核发送停止解码的指令；
    若所述解码内核通过每一个对应的解码码制均对所述待解码图像解码失败，则向所述主核发送解码失败的指令。
  7. 如权利要求1至6任一项所述的基于多核的解码方法，其特征在于，所述N等于所述多核处理器的内核数量。
  8. 一种终端设备，其特征在于，包括：
    图像获取单元，用于从所述多核处理器中选取一个内核作为主核，并通过所述主核获取待解码图像；
    解码内核选取单元，用于从所述多核处理器中选取N个内核作为解码内核，其中，N小于或等于所述多核处理器的内核数量；
    解码单元，用于通过N个解码内核同时对所述待解码图像进行解码。
  9. 一种终端设备，包括存储器、多核处理器以及存储在所述多核存储器中并可在所述多核处理器上运行的计算机程序，其特征在于，所述多核处理器执行所述计算机程序时实现如权利要求1至7任一项所述方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序被一个或多个处理器执行时实现如权利要求1至7任一项所述方法的步骤。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109544439B (zh) * 2018-10-23 2021-06-08 百富计算机技术（深圳）有限公司 一种基于多核处理器的解码方法、终端设备及存储介质
CN110263895B (zh) * 2019-06-25 2023-02-17 北京慧眼智行科技有限公司 一种码图生成方法及系统
CN111881698A (zh) * 2020-06-11 2020-11-03 上海祥承通讯技术有限公司 一种基于安卓系统的扫码头模组多线程扫码处理方法
CN115146664B (zh) * 2022-09-06 2022-12-23 无锡盈达聚力科技有限公司 图像采集方法及装置
CN116489380A (zh) * 2023-04-20 2023-07-25 上海先楫半导体科技有限公司 一种微控制处理器及视频码流的解码方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246431A (zh) * 2008-03-10 2008-08-20 中兴通讯股份有限公司 加载多核不同操作系统映像的管理方法
CN101901207A (zh) * 2010-07-23 2010-12-01 中国科学院计算技术研究所 异构共享存储多处理机系统的操作系统及其工作方法
CN106095536A (zh) * 2016-06-22 2016-11-09 福建联迪商用设备有限公司 基于多核mpu的多线程解码方法及系统
CN107203987A (zh) * 2017-06-07 2017-09-26 云南师范大学 一种红外图像和低照度图像实时融合系统
CN109544439A (zh) * 2018-10-23 2019-03-29 百富计算机技术（深圳）有限公司 一种基于多核处理器的解码方法、终端设备及存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9131240B2 (en) * 2007-08-23 2015-09-08 Samsung Electronics Co., Ltd. Video decoding method and apparatus which uses double buffering
US8587595B2 (en) * 2009-10-01 2013-11-19 Hand Held Products, Inc. Low power multi-core decoder system and method
CN101840492B (zh) * 2010-05-25 2013-11-06 福建新大陆电脑股份有限公司 一种支持多码制并行处理的条码解码装置
CN103034147B (zh) * 2011-09-29 2015-11-25 展讯通信（上海）有限公司 媒体文件的播放处理方法、多处理器系统与设备
US9513910B2 (en) * 2012-12-18 2016-12-06 International Business Machines Corporation Requesting shared variable directory (SVD) information from a plurality of threads in a parallel computer
CN105407356B (zh) * 2015-11-27 2018-08-10 西安电子科技大学 高速实时jpeg2000解码方法
CN105992008B (zh) * 2016-03-30 2019-08-30 南京邮电大学 一种在多核处理器平台上的多层次多任务并行解码方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101246431A (zh) * 2008-03-10 2008-08-20 中兴通讯股份有限公司 加载多核不同操作系统映像的管理方法
CN101901207A (zh) * 2010-07-23 2010-12-01 中国科学院计算技术研究所 异构共享存储多处理机系统的操作系统及其工作方法
CN106095536A (zh) * 2016-06-22 2016-11-09 福建联迪商用设备有限公司 基于多核mpu的多线程解码方法及系统
CN107203987A (zh) * 2017-06-07 2017-09-26 云南师范大学 一种红外图像和低照度图像实时融合系统
CN109544439A (zh) * 2018-10-23 2019-03-29 百富计算机技术（深圳）有限公司 一种基于多核处理器的解码方法、终端设备及存储介质

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