WO2020082820A1 - 一种加密与解密系统及其操作方法 - Google Patents

一种加密与解密系统及其操作方法 Download PDF

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Publication number
WO2020082820A1
WO2020082820A1 PCT/CN2019/095682 CN2019095682W WO2020082820A1 WO 2020082820 A1 WO2020082820 A1 WO 2020082820A1 CN 2019095682 W CN2019095682 W CN 2019095682W WO 2020082820 A1 WO2020082820 A1 WO 2020082820A1
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key
chip
data
ciphertext
read
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French (fr)
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李祎
缪向水
程龙
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits

Definitions

  • the invention belongs to the field of information security, and more specifically, relates to an encryption and decryption system and an operation method thereof.
  • the encryption process refers to encoding the plaintext data by means of encoding.
  • the method used in the encoding process is the key, and the encoded data is the ciphertext data.
  • the decryption process is the inverse operation of the encryption process.
  • the key is used to decode the ciphertext, and the output is plaintext.
  • the key In the process of encryption and decryption, the key must be unique and can be repeated, otherwise the ciphertext can be easily cracked, or cannot be cracked at all, so that the original data cannot be obtained.
  • the key is the key to the entire encryption and decryption process, so its security determines how easy the ciphertext can be cracked.
  • the object of the present invention is to provide an encryption and decryption system and an operation method thereof, which aim to improve the problems of low security and low energy efficiency in the encryption method based on the data algorithm.
  • the invention provides an encryption and decryption system, including: a key chip, a ciphertext chip, a random number generator and a peripheral circuit; the random number generator is used to randomly generate a series of binary codes according to instructions; the peripheral circuit and The key chip and the ciphertext chip are both connected and used to read the key data in the key chip and perform logical operations on the plaintext data in the ciphertext chip to generate a ciphertext, that is, data encryption.
  • the key chip and the ciphertext chip have the same structure, and both include: a resistive crossbar array composed of N resistive change units and N transistors, and an address selection circuit corresponding to the array.
  • Each resistance change unit is connected in series with a transistor; the gate of the transistor is connected to the selection line (SL), the source of the transistor is connected to the word line (WL), the drain of the transistor is connected to the anode of the resistance change unit, and the anode of the resistance Line (BL) is connected.
  • the resistance changing unit when a positive voltage pulse exceeding the first threshold is applied to the positive and negative electrodes of the resistance changing unit, the resistance changing unit becomes a low resistance state; when a negative voltage exceeding the second threshold is applied to the positive and negative electrodes of the resistance changing unit When a voltage pulse is applied, the resistance change unit becomes a high resistance state; the low resistance state of the resistance change unit is recorded as a logic value 1, and the high resistance state of the resistance change unit is recorded as a logic value 0.
  • the peripheral circuit includes: a controller, a key read-write circuit, a ciphertext read-write circuit, a signal amplifier, and an address encoding circuit; the first input terminal of the key read-write circuit is connected to the random number generator , The second input of the key read-write circuit is connected to the first output of the controller, and the output of the key read-write circuit is connected to the first input of the key chip ; The first input of the ciphertext read-write circuit is connected to the first output of the signal amplifier, and the second input of the ciphertext read-write circuit is connected to the second output of the controller.
  • the output end of the ciphertext read-write circuit is connected to the first input end of the ciphertext chip; the first input end of the signal amplifier is connected to the output end of the key chip, and the first input of the signal amplifier Connected to the third output of the controller; the input of the address encoding circuit is connected to the second output of the signal amplifier, and the first output of the address encoding circuit is connected to the key chip The second input, The second output terminal of the address encoding circuit is connected to the second input terminal of the ciphertext chip; the controller is used for the key read-write circuit, the ciphertext read-write circuit, the signal amplifier and The address encoding circuit provides various operating voltages; the key read-write circuit is used to read or write data in the key chip; the cipher text read-write circuit is used to read or write the cipher text chip The data amplifier; the signal amplifier is used to convert the current signal read in the key chip into a voltage signal that meets the need; the address encoding circuit is used to associate and encode the address of
  • the invention also provides an operation method based on the above encryption and decryption system, which can perform the data encryption function, including the following steps:
  • S11 Generate a random pulse sequence by the random number generator, and control the key read-write circuit to write random data to the key chip by the controller;
  • S12 The controller controls the ciphertext read-write circuit to write plaintext data to the ciphertext chip;
  • the address encoding circuit associates the address of the plaintext data in the ciphertext chip with the address of part of the data in the key chip, and this part of the data is the key;
  • the logic operation is XOR logic.
  • the present invention also provides an operation method based on the above encryption and decryption system, which can perform the data decryption function, including the following steps:
  • the number of bits of some data in the key chip is defined by the user.
  • the buffer area in the address coding circuit is used to store information relating to the key address in the key chip and the cipher text address in the cipher text chip.
  • the key can be stored for a long time due to the use of the resistance state of the device as the key; the characteristics of random generation and offline storage of the key enhance the security of key storage
  • the encryption and decryption method of integration of storage and logical operation power consumption and delay are saved, the ciphertext is protected from brute force cracking, and the security of information storage is improved.
  • Figure 1 is a schematic diagram of the volt-ampere characteristic curve of a resistive device
  • Figure 2 is a schematic diagram of the structure of the encryption and decryption system
  • Figure 3 is a schematic diagram of the structure of the resistance change unit chip
  • Figure 4 is a schematic diagram of the data encryption process
  • Figure 5 is a schematic diagram of the data decryption process
  • Figure 6 is a schematic diagram of a signal amplifier circuit
  • Figure 7 is a schematic diagram of XOR logic operation
  • Figure 8 is the XOR logic truth map
  • FIG. 9 is a schematic diagram of the first embodiment of the present invention: data encryption operation
  • FIG. 10 is a schematic diagram of the second embodiment of the present invention: data decryption operation.
  • FIG. 1 is a schematic diagram of the volt-ampere characteristic curve of the bipolar resistance change device. It can be seen from the figure that when the forward voltage applied across the resistive device is greater than or equal to the first threshold, such as V Set , the device changes from a high resistance state to a low resistance state; when the negative voltage applied to the resistive device is less than or equal to When it is equal to the second threshold, such as V Reset , the device changes from low resistance to high resistance.
  • the first threshold such as V Set
  • V Reset the second threshold
  • the voltage across the resistive switching device is controlled to achieve the purpose of controlling the resistance state of the device, and binary data "0" and "1" are written through the change in the resistance state of the resistive switching device.
  • binary data "0" and "1" are written through the change in the resistance state of the resistive switching device.
  • the resistance change device is low resistance
  • data 1 is written
  • the resistance change device is high resistance
  • data 0 is written.
  • data 0 can also be written when the resistance change device is low resistance
  • data 1 can be written when the resistance change device is high resistance.
  • the high resistance state of the resistance change device is logic 0
  • the low resistance state is logic 1.
  • Figure 1 also shows the size of the read voltage V Read , the amplitude of the V Read voltage is much smaller than the first threshold and the second threshold, and will not have a large impact on the resistance state of the resistive device.
  • FIG. 2 is a schematic diagram of an encryption and decryption system of the present invention, specifically including: a key chip and a ciphertext chip, a random number generator and a peripheral circuit, wherein the peripheral circuit is composed of a controller, a key read-write circuit, a ciphertext read-write circuit, and a signal
  • the amplifier and the address coding circuit are composed.
  • the output of the random number generator is connected to the input of the key reading and writing circuit, the output of the key reading and writing circuit is connected to the key chip, the key chip is connected to the input of the signal amplifier, and the output of the signal amplifier is connected to the secret
  • the input end of the text read-write circuit is connected, and the output end of the cipher text read-write circuit is connected to the cipher text chip.
  • the output end of the controller is connected with the key read-write circuit, the ciphertext read-write circuit and the input end of the address encoding circuit, and the output end of the address encoding circuit is connected with the key
  • the random number generator can randomly generate a series of binary codes according to the instructions
  • the controller provides various operating voltages for the read-write circuit, signal amplifier and address encoding circuit
  • the key reading and writing circuit is used to read or write data in the key chip
  • the ciphertext read-write circuit is used to read or write data in the ciphertext chip
  • the signal amplifier is connected to the key chip and the ciphertext read-write circuit, and its function is to convert the current signal read in the key chip into a voltage signal that meets the needs;
  • the address encoding circuit associates and encodes the addresses of the cells in the key chip and the ciphertext chip.
  • FIG. 3 is a schematic diagram of a chip structure of a resistance change unit, specifically including a resistance crossbar array and a corresponding on-chip address selection circuit.
  • each resistive unit is connected in series with a transistor, the gate of the transistor is connected to the selection line (SL), the source of the transistor is connected to the word line (WL), and the drain of the transistor is connected to the positive electrode of the resistive unit, The negative electrode of the resistance change unit is connected to the bit line (BL).
  • SL selection line
  • WL word line
  • BL bit line
  • FIG. 4 is a schematic diagram of an encryption operation flow based on the system structure, specifically including the following operation steps:
  • the random number generator generates a binary code
  • S104 Associate the address of the plaintext data in the ciphertext chip with the address of the user-defined data in the key chip; this part of the user-defined data is the key data;
  • S105 Perform XOR logic operation on the key data in the key chip and the plain text data in the cipher text chip;
  • FIG. 5 is a schematic diagram of a decryption operation flow based on the system structure, specifically including the following operation steps:
  • FIG. 6 is a schematic diagram of a signal amplifier.
  • the result of reading part of the data from the key chip is input in the form of current I IN .
  • V OUT I IN ⁇ R
  • the resistance value of R is much larger than the low resistance state of the resistance variable device, the specific resistance value Can be determined according to the actual situation.
  • Figure 7 is a schematic diagram of XOR logic operation.
  • the key data in the key chip be p
  • the plaintext data / ciphertext data in the ciphertext chip be q.
  • the p and q variables are expressed in the form of resistance states; for the transistor gate, source, and ports of the resistance change unit negative electrode, the p and q variables are expressed in the form of voltages.
  • Figure 8 is the XOR logic truth map
  • FIG. 9 is a schematic diagram of the first embodiment of the present invention: data encryption operation.
  • the random number generator generates a binary code of "10101001" and has written it into the key chip.
  • the plaintext "01011010” has been written into the ciphertext chip.
  • the user selects the first 4 bits of data in the key chip as the key, and associates the address of the 8 bits of data in the ciphertext chip with the key data address in the key chip, that is, the key data in the key chip is "1010 ".
  • the key “1010” When encrypting, first of all, the key “1010” performs the XOR logic operation with the first 4 bits of data "0101" in the ciphertext chip, the calculation result is "1111”, overwrites the plaintext data and stores it directly in the ciphertext chip; then the key “ 1010 "performs XOR logic operation with the last 4 digits of data” 1010 "in the ciphertext chip, the calculation result is” 0000 ", overwrites the plaintext data and stores it directly in the ciphertext chip.
  • "11110000" is the cipher text, and the encryption process is completed;
  • the address encoding circuit first determines the key address corresponding to the ciphertext "11110000" in the ciphertext chip, and obtains the key "1010".

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Abstract

本发明公开了一种加密与解密系统及其操作方法；包括密钥芯片、密文芯片、随机数产生器和外围电路，其中外围电路由控制器、读写电路、信号放大器和地址编码电路组成。加密前，随机数产生器产生随机信号写入密钥芯片中。加密时，先把明文数据写入密文芯片中，然后将明文数据与密钥芯片中作为密钥的部分单元地址关联，将密钥信号施加在明文数据单元上进行加密计算，即完成数据加密。解密时，读取密钥芯片中密钥，与密文芯片中密文进行解密计算，即完成数据解密。整个过程中，密钥芯片始终保持离线状态。本发明以电阻状态作为密钥，在硬件的基础上对明文数据加密，并覆盖原始数据，离线存储密钥，提高了信息保存的安全性并节约了功耗和延时。

Description

一种加密与解密系统及其操作方法 【技术领域】
本发明属于信息安全领域，更具体的，涉及一种加密与解密系统及其操作方法。
【背景技术】
数据的加密与解密在信息化时代有着重要的应用。加密过程是指将明文数据通过编码手段进行编码，编码过程中使用的方法即为密钥，编码后的数据即为密文数据。解密过程是加密过程的逆运算，通过密钥对密文进行解码操作，输出即为明文。加密和解密的过程中，密钥必须是唯一而且可以被重复的，否则密文很容易被破解，或者根本无法破解，从而得不到原始数据。密钥是整个加密和解密过程的关键，因此，它的安全性决定了密文被破解的难易程度。
传统加密方法如中国发明专利《基于SM3算法和随机挑战码的登录验证方法及系统》(申请号：CN108347335A)中提出的设计，对目前广泛使用的MD5等国际算法进行了优化，增加了摘要信息位数和登录挑战码。这种设计是基于数据算法、在软件层面进行的加密过程，虽然在已有技术上进行了改进，但是本质上还是基于算法，易被监听，进而被破解；而且，复杂的操作步骤虽然增加了安全性，但同时也使得整个系统消耗大量的功耗、操作时间和存储空间；另外，对存储原始数据的存储器进行暴力破解，也可以直接避开加密解密算法而获得其中的数据。因此，基于数据算法的加密过程依然存在安全性不高、能效低的问题。
发明内容
针对现有技术的缺陷，本发明的目的在于提供一种加密与解密系统及其操作方法，旨在提高基于数据算法的加密方法中存在的低安全性、低能 效的问题。
本发明提供了一种加密与解密系统，包括：密钥芯片、密文芯片、随机数产生器和外围电路；所述随机数产生器用于根据指令随机产生一系列二进制码；所述外围电路与所述密钥芯片和所述密文芯片均连接，用于读取所述密钥芯片中的密钥数据，并对所述密文芯片中的明文数据进行逻辑运算生成密文，即实现数据加密。
更进一步地，所述密钥芯片和所述密文芯片结构相同，均包括：由N个阻变单元和N个晶体管构成的阻变交叉杆阵列，以及与阵列对应的地址选择电路，阵列中的每个阻变单元都与一个晶体管串联；晶体管栅极与选择线(SL)相连，晶体管源极与字线(WL)相连，晶体管漏极与阻变单元正极相连，阻变单元负极与位线(BL)相连。
其中，所有阻变单元、晶体管的材料、参数均一致。
其中，当给阻变单元正负极两端施加超过第一阈值的正向电压脉冲时，阻变单元变为低阻态；当给阻变单元正负极两端施加超过第二阈值的负向电压脉冲时，阻变单元变为高阻态；阻变单元的低阻态记为逻辑值1，阻变单元的高阻态记为逻辑值0。
更进一步地，外围电路包括：控制器、密钥读写电路、密文读写电路、信号放大器和地址编码电路；所述密钥读写电路的第一输入端连接至所述随机数产生器的输出端，所述密钥读写电路的第二输入端连接至所述控制器的第一输出端，所述密钥读写电路的输出端连接至所述密钥芯片的第一输入端；所述密文读写电路的第一输入端连接至所述信号放大器的第一输出端，所述密文读写电路的第二输入端连接至所述控制器的第二输出端，所述密文读写电路的输出端连接至所述密文芯片的第一输入端；所述信号放大器的第一输入端连接至所述密钥芯片的输出端，所述信号放大器的第一输入端连接至所述控制器的第三输出端；所述地址编码电路的输入端连接至所述信号放大器的第二输出端，所述地址编码电路的第一输出端连接 至所述密钥芯片的第二输入端，所述地址编码电路的第二输出端连接至所述密文芯片的第二输入端；所述控制器用于为所述密钥读写电路、所述密文读写电路、所述信号放大器和所述地址编码电路提供各种操作电压；所述密钥读写电路用于读取或写入密钥芯片中的数据；所述密文读写电路用于读取或写入密文芯片中的数据；所述信号放大器用于将密钥芯片中读取的电流信号转化为符合需要的电压信号；所述地址编码电路用于将密钥芯片和密文芯片中单元的地址关联并编码。
本发明还提供了一种基于上述的加密与解密系统的操作方法，可执行数据加密功能，包括下述步骤：
S11：通过所述随机数产生器产生随机脉冲序列，由所述控制器控制所述密钥读写电路对所述密钥芯片进行随机数据写入；
S12：通过所述控制器控制所述密文读写电路将明文数据写入所述密文芯片中；
S13：通过所述地址编码电路将所述密文芯片中明文数据的地址与所述密钥芯片中部分数据的地址关联，这部分数据即为密钥；
S14：读取所述密钥芯片中的密钥数据，并通过所述信号放大器及所述密文读写电路对所述密文芯片中的明文数据进行逻辑运算生成密文，即实现数据加密。
其中，逻辑运算为XOR逻辑。
本发明还提供了一种基于上述的加密与解密系统的操作方法，可执行数据解密功能，包括下述步骤：
S21：通过所述地址编码电路选取与所述密文芯片中密文数据地址对应的所述密钥芯片中的密钥；
S22：读取所述密钥芯片中的密钥数据，并通过所述信号放大器及所述密文读写电路对所述密文芯片中的密文进行逻辑运算生成明文数据，即实现数据解密。
其中，密钥芯片中的部分数据的位数由用户自定义。
其中，址编码电路中的缓存区用于存储关联所述密钥芯片中密钥地址和所述密文芯片中密文地址的信息。
通过本发明所构思的以上技术方案，与现有技术相比，由于使用器件的电阻状态作为密钥，密钥能够长久保存；随机产生以及离线存储密钥的特点，增强了密钥存储的安全性；在硬件的基础上，通过存储与逻辑运算一体化的加密解密方式，节约了功耗和延时，保障了密文不被暴力破解，提高了信息存储的安全性。
【附图说明】
图1为阻变器件的伏安特性曲线示意图；
图2为加密与解密系统的结构示意图；
图3为阻变单元芯片结构示意图；
图4为数据加密流程示意图；
图5为数据解密流程示意图；
图6为信号放大器电路示意图；
图7为XOR逻辑操作示意图；
图8为XOR逻辑真值图；
图9为本发明实施例一：数据的加密操作示意图；
图10为本发明实施例二：数据的解密操作示意图。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在介绍本发明的技术方案之前，首先介绍阻变器件的一些特性，图1为双极性阻变器件的伏安特性曲线示意图。由图可知，当加在阻变器件两端的正向电压大于或等于第一阈值时，例如V Set，器件从高阻态变为低阻 态；当加在阻变器件的负向电压小于或等于第二阈值时，例如V Reset，器件从低阻态变为高阻态。
基于上述阻变器件的特性，本发明中通过控制阻变器件两端的电压，达到控制器件阻态的目的，通过阻变器件阻态的变化来写入二进制数据“0”和“1”。例如当阻变器件为低阻时，即写入数据1；当阻变器件为高阻时，即写入数据0。当然，也可以在阻变器件为低阻时，写入数据0；当阻变器件为高阻时，写入数据1。在本发明中，记阻变器件的高阻态为逻辑0，低阻态为逻辑1。
图1还标出了读取电压V Read的大小，V Read电压幅值远小于第一阈值和第二阈值，不会对阻变器件的阻态产生较大影响。
图2为本发明加密与解密系统示意图，具体包括：密钥芯片和密文芯片、随机数产生器和外围电路，其中外围电路由控制器、密钥读写电路、密文读写电路、信号放大器和地址编码电路组成。随机数产生器的输出端与密钥读写电路的输入端相连，密钥读写电路的输出端与密钥芯片相连，密钥芯片与信号放大器的输入端相连，信号放大器的输出端与密文读写电路的输入端相连，密文读写电路的输出端与密文芯片相连。控制器的输出端与密钥读写电路、密文读写电路和地址编码电路的输入端相连，地址编码电路的输出端与密钥芯片和密文芯片相连。
随机数产生器能根据指令随机产生一系列二进制码；
控制器为读写电路、信号放大器和地址编码电路提供各种操作电压；
密钥读写电路用于读取或写入密钥芯片中的数据；
密文读写电路用于读取或写入密文芯片中的数据；
信号放大器连接密钥芯片及密文读写电路，其功能为将密钥芯片中读取的电流信号转化为符合需要的电压信号；
地址编码电路将密钥芯片和密文芯片中单元的地址关联并编码。
图3为阻变单元芯片结构示意图，具体包括一块阻变交叉杆阵列，以 及对应的芯片内地址选择电路。在阻变交叉杆阵列中，每个阻变单元与一个晶体管串联，晶体管栅极与选择线(SL)相连，晶体管源极与字线(WL)相连，晶体管漏极与阻变单元正极相连，阻变单元负极与位线(BL)相连。所有阻变单元、晶体管的材料、参数均一致。
当给阻变单元正负极两端施加超过第一阈值的正向电压脉冲时，阻变单元会变为低阻态；当给阻变单元正负极两端施加超过第二阈值的负向电压脉冲时，阻变单元会变为高阻态。将阻变单元的低阻态记为逻辑值1，将阻变单元的高阻态记为逻辑值0。其中，第一阈值和第二阈值是阻变单元的固有参数，不同的阻变单元所对应的阈值不同，当阻变单元确定后，本领域普通技术人员可以根据现有技术中提供的方法测出上述阈值。图4为基于该系统结构的加密操作流程示意图，具体包括下述操作步骤：
S101：随机数产生器产生二进制码；
S102：将二进制码数据写入密钥芯片中；
S103：将明文数据写入密文芯片中；
S104：将密文芯片中明文数据的地址与密钥芯片中用户自定义的数据的地址相关联；用户自定义的这部分数据即为密钥数据；
S105：将密钥芯片中密钥数据与密文芯片中的明文数据进行XOR逻辑运算；
S106：所有数据计算完毕，数据加密完成。
图5为基于该系统结构的解密操作流程示意图，具体包括下述操作步骤：
S201：读取密钥芯片中的密钥数据；
S202：将密钥数据与密文芯片中的密文数据进行XOR逻辑运算；
S203：所有数据计算完毕，数据解密完成。
图6为一种信号放大器示意图。从密钥芯片中读取部分数据的结果以电流I IN的形式输入进来，根据电路知识可得V OUT＝I IN·R，R的阻值远大于 阻变器件的低阻态，具体阻值可根据实际情况确定。
当密钥芯片中单元存储的数据为1时，该单元为低阻态，读取的电流较大，因此V OUT为高电平，高电平记为逻辑1；当密钥芯片中单元存储的数据为0时，该单元为高阻态，读取的电流较小，因此V OUT为低电平，低电平记为逻辑0；综上，信号放大器将电流输入转换成了对应的电压输出；
图7为XOR逻辑操作示意图。为方便描述，令密钥芯片中密钥数据为p，密文芯片中明文数据/密文数据为q。对于阻变单元，p和q变量以阻态的形式表示；对于晶体管栅极、源极和阻变单元负极的端口，p和q变量以电压的形式表示。
当密文芯片中数据为0时，即q＝0，若p＝0，栅极电压小于晶体管开启电压，晶体管夹断，阻变单元的阻态不会发生变化，计算结果为0；若p＝1，栅极电压大于晶体管开启电压，晶体管导通，此时阻变单元正极为高电平，负极为低电平，使得阻变单元变为低阻态，计算结果为1。当芯片B中数据为1时，即q＝1，若p＝0，栅极电压小于晶体管开启电压，晶体管夹断，阻变单元的阻态不会发生变化，计算结果为1；若p＝1，栅极电压大于晶体管开启电压，晶体管导通，此时阻变单元正极为低电平，负极为高电平，使得阻变单元变为高阻态，计算结果为0；
图8为XOR逻辑真值图；
图9为本发明实施例一：数据的加密操作示意图。随机数产生器产生“10101001”的二进制码，并且已经写入密钥芯片中。密文芯片中已写入明文“01011010”。用户选取密钥芯片中前4位数据作为密钥，将密文芯片中的8位数据的地址与密钥芯片中的密钥数据地址相关联，即密钥芯片中的密钥数据为“1010”。
加密时，首先是密钥“1010”与密文芯片中前4位数据“0101”进行XOR逻辑运算，计算结果为“1111”，覆盖明文数据并直接存储在密文芯片中； 然后密钥“1010”与密文芯片中后4位数据“1010”进行XOR逻辑运算，计算结果为“0000”，覆盖明文数据并直接存储在密文芯片中。“11110000”即为密文，加密过程完成；
图10为本发明实施例二：数据的解密操作示意图。由地址编码电路先确定与密文芯片中密文“11110000”对应的密钥地址，获取密钥“1010”。
解密时，首先是密钥“1010”与密文芯片中前4位数据“1111”进行XOR逻辑运算，计算结果为“0101”，覆盖密文数据并直接存储在密文芯片中；然后密钥“1010”与密文芯片中后4位数据“0000”进行XOR逻辑运算，计算结果为“1010”，覆盖密文数据并直接存储在密文芯片中。“01011010”即为明文，解密过程完成。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种加密与解密系统，其特征在于，包括：密钥芯片、密文芯片、随机数产生器和外围电路；
    所述随机数产生器用于根据指令随机产生一系列二进制码；
    所述外围电路与所述密钥芯片和所述密文芯片均连接，用于读取所述密钥芯片中的密钥数据，并对所述密文芯片中的明文数据进行逻辑运算生成密文，即实现数据加密。
  2. 如权利要求1所述的加密与解密系统，其特征在于，所述密钥芯片和所述密文芯片结构相同，均包括：由N个阻变单元和N个晶体管构成的阻变交叉杆阵列，以及与阵列对应的地址选择电路，
    阵列中的每个阻变单元都与一个晶体管串联；晶体管栅极与选择线相连，晶体管源极与字线相连，晶体管漏极与阻变单元正极相连，阻变单元负极与位线相连。
  3. 如权利要求2所述的加密与解密系统，其特征在于，所有阻变单元、晶体管的材料、参数均一致。
  4. 如权利要求2所述的加密与解密系统，其特征在于，当给阻变单元正负极两端施加超过第一阈值的正向电压脉冲时，阻变单元变为低阻态；当给阻变单元正负极两端施加超过第二阈值的负向电压脉冲时，阻变单元变为高阻态；阻变单元的低阻态记为逻辑值1，阻变单元的高阻态记为逻辑值0。
  5. 如权利要求1-4任一项所述的加密与解密系统，其特征在于，所述外围电路包括：控制器、密钥读写电路、密文读写电路、信号放大器和地址编码电路；
    所述密钥读写电路的第一输入端连接至所述随机数产生器的输出端， 所述密钥读写电路的第二输入端连接至所述控制器的第一输出端，所述密钥读写电路的输出端连接至所述密钥芯片的第一输入端；
    所述密文读写电路的第一输入端连接至所述信号放大器的第一输出端，所述密文读写电路的第二输入端连接至所述控制器的第二输出端，所述密文读写电路的输出端连接至所述密文芯片的第一输入端；
    所述信号放大器的第一输入端连接至所述密钥芯片的输出端，所述信号放大器的第一输入端连接至所述控制器的第三输出端；
    所述地址编码电路的输入端连接至所述信号放大器的第二输出端，所述地址编码电路的第一输出端连接至所述密钥芯片的第二输入端，所述地址编码电路的第二输出端连接至所述密文芯片的第二输入端；
    所述控制器用于为所述密钥读写电路、所述密文读写电路、所述信号放大器和所述地址编码电路提供各种操作电压；
    所述密钥读写电路用于读取或写入密钥芯片中的数据；
    所述密文读写电路用于读取或写入密文芯片中的数据；
    所述信号放大器用于将密钥芯片中读取的电流信号转化为符合需要的电压信号；
    所述地址编码电路用于将密钥芯片和密文芯片中单元的地址关联并编码。
  6. 一种基于权利要求1所述的加密与解密系统的操作方法，其特征在于，可执行数据加密功能，包括下述步骤：
    S11：通过所述随机数产生器产生随机脉冲序列，由所述控制器控制所述密钥读写电路对所述密钥芯片进行随机数据写入；
    S12：通过所述控制器控制所述密文读写电路将明文数据写入所述密文芯片中；
    S13：通过所述地址编码电路将所述密文芯片中明文数据的地址与所述密钥芯片中部分数据的地址关联，这部分数据即为密钥；
    S14：读取所述密钥芯片中的密钥数据，并通过所述信号放大器及所述密文读写电路对所述密文芯片中的明文数据进行逻辑运算生成密文，即实现数据加密。
  7. 一种基于权利要求6所述的加密与解密系统的操作方法，其特征在于，所述逻辑运算为XOR逻辑。
  8. 一种基于权利要求1所述的加密与解密系统的操作方法，其特征在于，可执行数据解密功能，包括下述步骤：
    S21：通过所述地址编码电路选取与所述密文芯片中密文数据地址对应的所述密钥芯片中的密钥；
    S22：读取所述密钥芯片中的密钥数据，并通过所述信号放大器及所述密文读写电路对所述密文芯片中的密文进行逻辑运算生成明文数据，即实现数据解密。
  9. 如权利要求6或8所述的操作方法，其特征在于，所述密钥芯片中的部分数据的位数由用户自定义。
  10. 如权利要求8或9所述的操作方法，其特征在于，所述地址编码电路中的缓存区用于存储关联所述密钥芯片中密钥地址和所述密文芯片中密文地址的信息。
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