WO2020076236A1

WO2020076236A1 - A power management module

Info

Publication number: WO2020076236A1
Application number: PCT/SG2019/050492
Authority: WO
Inventors: Jianming Zhao; Yuan Gao
Original assignee: Agency For Science, Technology And Research
Priority date: 2018-10-10
Filing date: 2019-09-27
Publication date: 2020-04-16

Abstract

This document describes a module and method for boosting and managing the boosted output power of a system. In particular, the module comprises an active rectifier circuit and at least one charge pump module, whereby the charge pump module is controlled by a logic circuit to boost the output power of the system. When a plurality of the charge pump modules are used in a multi-phase configuration, the system then ensures that the boosted output power remains constant throughout.

Description

A POWER MANAGEMENT MODULE

Field of the Invention

This invention relates to a module and method for boosting and managing the boosted output power of a system. In particular, the invention comprises an active rectifier circuit and at least one charge pump module, whereby the charge pump module is controlled by a logic circuit to boost the output power of the system. When a plurality of the charge pump modules are used in a multi-phase configuration, the system then ensures that the boosted output power remains constant throughout.

Summary of the Prior Art

Power management circuits play a crucial and indispensable role in biomedical devices such as implantable biomedical devices that are used for neural recording and nerve/muscle stimulation. Examples of such biomedical devices would be retinal prostheses and cochlear implant products. For these types of applications, the implants’ size has to be kept as small as possible as implants located within body tissue typically causes the tissue to become inflamed over time. As a result, in order to minimize the size of these implants, they usually do not include batteries or trailing wires.

Hence, it has been proposed that these implants be powered via near field coupling coils whereby the power source is located outside the implanted tissue. In such an approach, wireless power is received by the near field coupling coils and subsequently boosted to the required power level using charge pumps. Charge pumps obtain an output voltage that is higher than a source voltage primarily by means of capacitive transfer from an input source to its output whereby the energy transfer capacitors used in charge pumps for the capacitive transfers are typically known as“flying capacitors”. Due to advances in Complementary Metal-Oxide-Semiconductor (CMOS) processes, high density on-chip capacitors and smaller switch transistors have been developed, making fully on-chip charge pumps well suited for various integrated circuits.

Presently, charge/discharge losses occurring in existing on-chip charge pumps are caused by the parasitic capacitances associated with an on-chip flying capacitor’s parasitic capacitance and the switch transistors’ gate capacitance. To alleviate the loss caused by these parasitic capacitances, it has been proposed by those skilled in the art that a Metal- Insulator-Metal (MIM) type capacitor or a Metal-Oxide-Metal (MOM) type capacitor be adopted instead. The main disadvantage of this approach is that MIM and MOM type capacitors are not efficient capacitors. As such, it has also been proposed that the capacitors be fabricated on Silicon-on-lnsulator (SOI) substrates to produce Metal-Oxide- Semiconductor (MOS) gate capacitors with low parasitic capacitance. In addition to the above, in order to achieve high power efficiencies, it has also been proposed that existing capacitors be replaced with deep trench capacitors. However, this approach is quite costly as it is not as commonplace as capacitors made using classic CMOS processes. Those skilled in the art have also proposed applying special gate capacitor connections to existing capacitors with the objective of reducing its parasitic capacitance. However, this method is difficult to implement as it causes some internal nodes in the module to be in an“electrical floating stage” thereby rendering the design unstable.

In order to address the loss caused by the switch transistors’ gate capacitance, it has been proposed that a soft charging technique be applied to reuse the electrical quantities between the switches, thereby letting current flow from the high-voltage switch gates to the low-voltage switch gates in more than one step. However, to get a significant improvement on power efficiency, the charge pump structure then becomes overly complex and requires a significant amount of intermediate clocks to finish a complete charge/discharge cycle.

Apart from power loss due to capacitive losses, the switches’ Equivalent Series Resistance (ESR) plays an equally important role in determining the power efficiency of the system. When current flows through the switches, a voltage drop occurs across the ESRs and causes power to dissipate as heat. As a result, the sizes of the switches have to be carefully selected so that a balance may be achieved between the capacitive loss and ESR heat loss. It is hard to reduce the ESR of a switch when the voltage supply and the CMOS process used to make the components are fixed, thus, a way of optimizing the system’s power efficiency involves reducing the loss due to capacitive loss.

For the above reasons, those skilled in the art are constantly striving to come up with a system and method for reducing the capacitive loss in a charge pump module while maintaining a constant boosted output power. By doing so, the power management system would be able to achieve high power efficiency and high power density.

Summary of the Invention

The above and other problems are solved and an advance in the art is made by systems and methods provided by embodiments in accordance with the invention. A first advantage of embodiments of systems and methods in accordance with the invention is that the power management module is able to generate boosted output power when driven with an alternating current (AC) signal and that the module is highly power efficient.

A second advantage of embodiments of systems and methods in accordance with the invention is that when the charge pumps in the power management module are used in a multi-phase configuration, the resulting boosted output power remains at a constant level throughout and the module still retains its high power efficiency.

The above advantages are provided by embodiments of a system in accordance with the invention operating in the following manner.

According to a first aspect of the invention, a power management module is disclosed whereby the module comprises: an active rectifier circuit configured to rectify a first alternating current (AC) signal to a first pulse signal and to rectify a second AC signal to a second pulse signal; a first logic circuit configured to utilize the first and second pulse signals to control a first group of transmission gates to generate, from one of the AC signals, a first set of clock signals; and a first charge pump module being biased by a bias voltage V _DD, and comprising a first flying capacitor, a first set of switch transistors and an output, wherein the first charge pump module is configured to charge and discharge the first flying capacitor by controlling the first set of switch transistors using the first set of clock signals, whereby the discharging of the first flying capacitor boosts the output of the first charge pump module above the bias voltage V_DD.

With reference to the first aspect, the first pulse signal is generated based on a valley of the first AC signal and the second pulse signal is generated based on a valley of the second AC signal.

With reference to the first aspect, the first logic circuit comprises: a plurality of D-type Flip Flops having outputs that are coupled to a plurality of AND logic gates, wherein the first and second pulse signals are provided to the D-type Flip Flops for causing control signals to be produced at outputs of the AND logic gates, whereby the control signals are used to control the first group of transmission gates.

With reference to the first aspect, the module further comprises: a second logic circuit configured to utilize the first and second pulse signals to control a second group of transmission gates to generate, from one of the AC signals, a second set of clock signals; and a second charge pump module being biased by the bias voltage V_DD, and comprising a second flying capacitor, a second set of switch transistors and an output, wherein the second charge pump module is configured to charge and discharge the second flying capacitor by controlling the second set of switch transistors using the second set of clock signals, whereby the discharging of the second flying capacitor boosts the output of the second charge pump module, whereby the output of the first charge pump module is connected to the same load as the output of the second charge pump module, and whereby a clock signal in the second set of clock signals is out of phase with a clock signal in the first set of clock signals by at least one clock cycle of the AC signal used to generate the first and second set of clock signals.

With reference to the first aspect, the module further comprises: an inductor- capacitor resonator circuit configured to generate the first and second AC signals based on received wireless power.

According to a second aspect of the invention, a method for managing a power management module is disclosed, the method comprising: rectifying, using an active rectifier circuit, a first alternating current (AC) signal to a first pulse signal and a second AC signal to a second pulse signal; utilizing, using a first logic circuit provided in the management module, the first and second pulse signals to control a first group of transmission gates to generate, from one of the AC signals, a first set of clock signals; and charging and discharging a first flying capacitor provided in a first charge pump module, the first charge pump module being provided in the management module, being biased by a bias voltage V _DD, and comprising a first set of switch transistors and an output, wherein the first flying capacitor is charged and discharged by controlling the first set of switch transistors using the first set of clock signals, whereby the discharging of the first flying capacitor boosts the output of the first charge pump module above the bias voltage V _DD.

With reference to the second aspect, the first pulse signal is generated based on a valley of the first AC signal and the second pulse signal is generated based on a valley of the second AC signal.

With reference to the second aspect, the first logic circuit comprises: a plurality of D- type Flip Flops having outputs that are coupled to a plurality of AND logic gates, wherein the first and second pulse signals are provided to the D-type Flip Flops for causing control signals to be produced at outputs of the AND logic gates, whereby the control signals are used to control the first group of transmission gates. With reference to the second aspect, the method further comprises: utilizing, using a second logic circuit provided in the management module, the first and second pulse signals to control a second group of transmission gates to generate, from one of the AC signals, a second set of clock signals; and charging and discharging a second flying capacitor provided in a second charge pump module, the second charge pump module being provided in the management module, being biased by the bias voltage V_DD, and comprising a second set of switch transistors and an output, wherein the second flying capacitor is charged and discharged by controlling the second set of switch transistors using the second set of clock signals, whereby the discharging of the second flying capacitor boosts the output of the first charge pump module, whereby the output of the first charge pump module is connected to the same load as the output of the second charge pump module, and whereby a clock signal in the second set of clock signals is out of phase with a clock signal in the first set of clock signals by at least one clock cycle of the AC signal used to generate the first and second set of clock signals.

With reference to the second aspect, the method further comprises an inductor- capacitor resonator circuit configured to generate the first and second AC signals based on received wireless power.

Brief Description of the Drawings

The above advantages and features in accordance with this invention are described in the following detailed description and are shown in the following drawings:

Figure 1 illustrating a block diagram representative of a power management module in accordance with embodiments of the invention;

Figure 2 illustrating a detailed block diagram representative of a LC tank, a rectifier, a logic circuit, a plurality of transmission gates, and a charge pump of the power management module in accordance with embodiments of the invention;

Figure 3 illustrating a representative rectifier circuit in accordance with embodiments of the invention;

Figure 4 illustrating alternating current waveforms and the resulting pulse signals generated by the rectifier circuit illustrated in Figure 3;

Figure 5 illustrating a representative logic circuit in accordance with embodiments of the invention; Figure 6 illustrating waveforms generated by the logic circuit illustrated in Figure 5 when the logic circuit is provided with the two pulse signals as inputs;

Figure 7 illustrating representative transmission gates that are configured to generate a set of clock signals based on control signals provided by a logic circuit in accordance with embodiments of the invention;

Figure 8 illustrating the waveforms previously shown in Figure 6 together with a sample clock waveform as generated by the transmission gates;

Figure 9 illustrating a representative charge pump circuit in accordance with embodiments of the invention;

Figure 10 illustrating a timing diagram showing the charge and discharge cycles of a flying capacitor of the charge pump illustrated in Figure 9 when the charge pump is driven by a set of clock signals;

Figure 1 1 illustrating a power management module comprising a plurality of multi phase charge pumps and their associated logic circuits in accordance with embodiments of the invention; and

Figure 12 illustrating a timing diagram showing the various charge and discharge cycles of flying capacitors of each of the charge pumps illustrated in Figure 1 1 when the charge pumps are driven by multi-phase clock signals.

Detailed Description

This invention relates to a module and method for boosting and managing the boosted output power of a system. In particular, the invention comprises an active rectifier circuit coupled to at least one charge pump module, whereby the charge pump module is controlled by a logic circuit to boost the output power of the system. When a plurality of the charge pump modules and their associated logic circuits are used in a multi-phase configuration, the system is configured to provide a constant boosted output power throughout. In further embodiments of the invention, the power management system may be driven by alternating current (AC) signals obtained from wireless signals.

Figure 1 illustrates a power management module 100 in accordance with embodiments of the invention. Power management module 100 comprises an active rectifier circuit 1 10; a logic circuit 1 15; a plurality of transmission gates 120 and a charge pump 125. As illustrated in Figure 1 , AC signals 102 and 104 are provided as inputs to active rectifier circuit 1 10 and the plurality of transmission gates 120. Active rectifier circuit 1 10 is configured to rectify the AC signals 102 and 104 into pulse signals 1 1 1 a and 1 1 1 b respectively. The pulse signals 1 1 1 a and 1 1 1 b are then utilized by logic circuit 1 15 to generate control signals 1 16. The control signals 1 16 are then used to control the plurality of transmission gates 120 such that a first set of clock signals 121 a, 121 b and 121c may be generated from AC signals 102 and/or 104. The first set of clock signals 121 a, 121 b and 121c are then used to control the switching rate of a set of switch transistors in charge pump 125 such that when the switch transistors are switching on and off, this in turn causes a flying capacitor in charge pump 125 to charge and discharge accordingly, thereby boosting the output power of charge pump 125 beyond a biasing voltage of charge pump 125.

Figure 2 illustrates a detailed view of the various components / modules located in an embodiment of power management module 100. In this embodiment of the invention, AC signals 102 and 104 are obtained from an Inductor-Capacitor (L-C) tank, with the values of these components chosen such that the L-C tank has the same resonance frequency as active rectifier circuit 1 10. The AC signals 102 and 104 are then rectified by the active rectifier circuit 1 10 to generate pulse singals 1 1 1 a and 1 1 1 b. The generated pulse signals 1 1 1 a and 1 1 1 b (illustrated as“red” and“rec2” respectively in Figure 2) are then provided to logic circuit 1 15. In this embodiment, logic circuit 1 15 then uses the rectified signals“red” and“rec2” to generate six control signals 1 16. The six control signals 1 16 are then used by the corresponding six pairs of transmission gates 120 to generate the first set of clock signals from AC signals 102 or 104. As illustrated in Figure 2, the first set of clock signals comprise clock signal CLK1 , DRIVE2 and CLK3 and these clock signals are used by charge pump 125 to control the switching rate of the switch transistors M1 -M4 provided in charge pump 125 such that flying capacitor 205 may charge and discharge in a controlled manner to boost the output voltage at a load at the output of charge pump 125 beyond the biasing voltage of the charge pump 125.

If another charge pump (not shown) is to be used in power management module 100, another logic circuit would then have to be configured to use the rectified signals“red” and “rec2” to generate a new set of six control signals. The new set of six control signals will then be used by a new set of six pairs of transmission gates to generate a second set of clock signals from the AC signals. The second set of clock signals may then be used to drive another charge pump to boost the voltage at the load of this charge pump. It should be noted that a continuous boosted output voltage may be maintained at the load by varying the phases of the clock signals used to drive the respective charge pumps. The detailed workings of the various components that make up power management module 100 will be described in detail in the following paragraphs.

An exemplary circuit of active rectifier circuit 1 10 is illustrated in Figure 3. One skilled in the art will recognize that other types of circuit configurations or layouts may be used to perform the rectification function performed by active rectifier circuit 1 10 and that rectifier circuit 1 10 is not limited to the circuit illustrated in Figure 3 only. In general, active rectifier 1 10 comprises four switch transistors and two comparators. In embodiments of the invention, the comparator compares signal 102 with a reference voltage such as ground voltage (0V). When signal 102 becomes lower than the reference voltage, the comparator generates a corresponding HIGH voltage. As a result, when signal 102 becomes lower than the reference voltage and rises above the reference voltage, a pulse signal 1 1 1 a is generated by the comparator. The comparator performs in the same manner for AC signal 104 to generate pulse 1 1 1 b..

In operation, active rectifier circuit 1 10 will generate the pulse signals 1 1 1 a and 1 1 1 b from AC signal 102 and 104 as described above. As illustrated in Figure 4, it can be seen that active rectifier 1 10 samples the rising edge of AC signal 102 and causes pulse signal 1 1 1 a to be generated, i.e. the pulse is generated at a valley of AC signal 102. Similarly, it can be seen that active rectifier 1 10 samples the rising edge of AC signal 104 and causes pulse signal 1 1 1 b to be generated, i.e. the pulse is generated at a valley of AC signal 104.

The pulse signals 1 1 1 a and 1 1 1 b are then provided to logic circuit 1 15 to generate the control signals 1 16 that are used to control the plurality of transmission gates 120. Figure 5 illustrates an exemplary circuit 500 that uses the received pulse signals 1 1 1 a and 1 1 1 b to generate a pair of control signals that are in turn used to control two pairs of transmission gates to generate the clock signal 121 a. Logic circuit 500 comprises four D- type flip-flops 505a-d, a NOR logic gate and two AND logic gates 510a and 510b. As can be seen from this figure, the received pulse signals 1 1 1 a and 1 1 1 b are used as inputs at the CLOCK input of D-type flip-flop 505a and 505b respectively. Table 1 below illustrates the truth table of a D-type flip-flop while the truth table of the NOR and AND logic gates are omitted for brevity as these two logic gates are well known to those skilled in the art.

Table 1

As shown in Figure 5, it can be seen that the outputs from the D-type flip-flops 505a- d are provided to the AND logic gates 51 1 and 512 and some of the outputs from the flip- flops are also used as inputs for some of the flip-flops themselves. One skilled in the art will recognize that the exact configuration of the inputs and outputs of the D-type flip-flops, the NOR and AND logic gates are left as a design choice to one skilled in the art and the objective of logic circuit 500 is to generate the required control signals 51 1 and 512. In other words, circuit 500 may be reconfigured as required so that other types of control signals may be generated as required.

Figures 6c, d, e and f illustrate the timing diagrams of the signals“pole”,“one”,“two” and“three” that are provided to AND logic gates 510a and 510b to generate control signals 51 1 and 512 in accordance with embodiments of this invention. The waveform for pole is not shown in Figure 6 as one skilled in the art will understand that this waveform is the complement of the“pole” signal waveform illustrated in Figure 6c. The signals“pole”, "pole" , “one”,“two” and“three” are produced by the outputs of the D-type flip-flops in circuit 500 when the pulse signals 1 1 1 a and 1 1 1 b (as illustrated in Figures 6a and b) are provided to circuit 500. The resulting outputs from the AND logic gates are the control signals 51 1/control and 512/control2 as illustrated in Figures 6g and h.

The control signal 51 1 from circuit 500 is then provided to one of the transmission gates in the plurality of transmission gates 120. In this example, it is assumed that signal 51 1 is provided to transmission gate 701 of transmission gates 120. This is illustrated in Figure 7. It is understood that a transmission gate is defined as an electronic element that will selectively block or pass a signal level from its input to its output and typically comprises a pair of control gate transistors that are biased in a complementary manner so that both control gate transistors of the transmission gate will be both either on or off at the same time. This means that when the“control” signal at a control gate of transmission gate 701 is at Logic 1 , a complementary Logic 0 will be applied to the other“complementary-control” node at the other control gate of transmission gate 701 allowing both control gate transistors to conduct and pass the signal through. Conversely, when the“control” signal at the control gate of transmission gate 701 is at a Logic 0, the complementary Logic 1 will be applied to the “complementary-control” node at the other control gate of transmission gate 701 , effectively turning both control gate transistors off and forcing an overall high-impedance condition at transmission gate 701 thereby blocking the signal from passing through.

It should be noted that when Logic 1 and Logic 0 are referred to in this description, reference is being made to the two voltage levels or states that are commonly used in digital circuit design. For completeness, these two states may also be known as HIGH and LOW, or TRUE and FALSE as identified in Boolean algebra and standard truth tables.

In view of the above, it may then be understood that when Logic 1 is applied to transmission gate 701 in accordance with the waveform shown in Figure 8g at stage 802 (i.e. the“control” signal 51 1 is Logic 1 when the AC signal 102 is rising), the AC signal 102 will be allowed to pass through transmission gate 701 making signal 121 a a“high” as shown in corresponding Figure 8i. When Logic 0 is subsequently applied to transmission gate 701 , as shown in Figure 8g, the AC signal 102 is then blocked from passing through transmission gate 701 causing the output at transmission gate 701 to remain at the same“high” logic level. Similarly, when Logic 1 is applied to transmission gate 702 in accordance with the waveform shown in Figure 8h at stage 804 (i.e. the“control2” signal 512 is Logic 1 when the AC signal 102 is falling), the AC signal 102 is allowed to pass through transmission gate 701 making signal 121 a a“low” as shown in corresponding Figure 8i. When Logic 0 is then applied to transmission gate 702, as shown in Figure 8h, the AC signal 102 is then blocked from passing through transmission gate 702 causing the output at transmission gate 702 to remain at the same“low” logic level. The steps set out above then repeat themselves when control signal 51 1 becomes Logic 1 again. Flence, from the above, it can be seen that clock signal 121 a may be generated in accordance with the waveforms of control signals 51 1 and 512.

Although the timing diagrams in Figure 8 only illustrate how clock signal 121 a is generated based on control signals 51 1 and 512, one skilled in the art will recognize that the similar concept may be applied to generate other clock signals such as clock signal 121 b and c and this is done by varying the control signal waveforms that are applied to the other pairs of transmission gates. In other words, clock signals 121 b and 121c will be generated when control signals“control3”,“control4”,“control5” and“control6” as generated from the associated logic gates are provided to the corresponding pairs of control gate transistors in transmission gates 120 as shown in Figure 7. One skilled in the art will also recognize that if AC signal 102 were to be replaced with AC signal 104, this will cause different clock signals 121 a-c to be produced without departing from this invention.

Once the clock signals 121 a, 121 b and 121c have been generated by the plurality of transmission gates 120, the clock signals 121 a-c are then provided to charge pump 125. As illustrated in Figure 9, charge pump 125 comprises two P-type Metal-Oxide-Semiconductor (PMOS) transistors M1 and M4, two N-type Metal-Oxide-Semiconductor (NMOS) transistors M2 and M3, flying capacitor 902 and two assistant capacitors C_ai and C_a2.

The function of the two assistant capacitors C_a1 and C_a2 are to boost the voltage level of the clock signals 121 a and 121c that are provided to the gates of NMOS transistor M4 and PMOS transistors M2. In operation, flying capacitor 902 will be charged and discharged based on the switching rate of transistors M1 -M4 and when flying capacitor 902 discharges, the voltage level at the output of charge pump 125 will increase, beyond the biasing voltage, VDD, of charge pump 125. One skilled in the art will recognize that transistors M1 -M4 may comprise either PMOS or NMOS transistors without departing from this invention, provided that the clock signals used to switch these transistors on and off are amended accordingly as well.

The operation of charge pump 125 is described in this section with reference to the timing diagrams illustrated in Figure 10. At phase 1 (as shown in Figure 10), clock signal 121 a is at Logic 1 , signal 121 b is at a falling edge and signal 121 c is at Logic 0. As a result, transistors M1 -M4 are all off at this phase and node 904a of capacitor 902 is pulled to a low voltage.

At phase 2, clock signal 121 a is still maintained at Logic 1 while clock signal 121c is at a rising edge. As clock signal 121c is rising, this causes transistors M2 and M3 to gradually switch on. With node 904a being maintained at Logic 0 due to clock signal 121 b and with transistor M3 switching on, and with the bias voltage VDD being gradually provided to node 904b through transistor M2, this causes charge to gradually build up across capacitor 902.

In order to fully charge capacitor 902 to the bias voltage VDD, clock signal 121 c is held at Logic 0 over one complete charging phase. In this charging phase, clock signal 121 b is held at Logic 0 and clock signal 121 a is maintained at Logic 1 for one complete cycle of AC signal 102. At phase 3, clock signal 121 a is still maintained at Logic 1 and clock signal 121 b is maintained at Logic 0. However, at this phase, clock signal 121c begins falling thereby causing transistors M2 and M3 to gradually switch off.

At phase 4, clock signal 121 a is still maintained at Logic 1 , clock signal 121c is maintained at Logic 0 and clock signal 121 b begins rising, gradually pulling up the voltage at node 904a. It should be noted that at phase 4, transistors M1 -M4 are all switched off.

Transistors M1 and M4 gradually switch on at phase 5 as clock signal 121 a begins falling. In this phase, clock signal 121c is maintained at Logic 0 while clock signal 121 b maintains the voltage at node 904a at a high level.

At the discharge phase, transistors M1 and M4 are fully switched on by clock signal 121 a while node 904a is kept at a high level by clock signal 121 b. The series combination of the bias voltage VDD and the discharging capacitor 902 causes the output voltage 910 across the load of charge pump 125 to gradually increase to twice the biasing voltage VDD, i.e. 2VDD.

At phase 6, flying capacitor 902 would have been fully discharged across the load at the output of charge pump 125. The clock signal 121 a then begins rising causing transistors M1 and M4 to gradually switch off while clock signals 121 b and 121 c remain unchanged, at Logic 1 and Logic 0 respectively. At the end of phase 6, all transistors M1 -M4 would be switched off.

Based on the above, it can be seen that it takes at least five complete cycles of AC signal 102 in order to complete one charge pump cycle and that the charging phase and discharging phase each takes one complete cycle of the AC signal. In embodiments of the invention, if required, the number of cycles of AC signal 102 to complete one charge pump cycle may be increased by introducing additional delay cycles into clock signals 121 a-c accordingly.

As described above, transistors M1 and M4 are configured to switch on simultaneously when Logic 0 is provided to the gates of these two transistors via clock signal 121 a. However, it should be noted that the signal used to switch on the gate of transistor M4 is different from the signal provided to the gate of transistor M1 . The clock signal 121 a at the gate of transistor M1 is at a CLK1 level while the signal provided to the gate of transistor M4 is at a CLK1 H level and this is due to assistant capacitor C_ai discharging when transistors M1 and M4 switch on. In particular, when transistors M1 and M4 are not switched on, IB switches SW3 and SW4 will switch on momentarily, thereby gradually charging up assistant capacitor C_ai and when M1 and M4 are switching on, assistant capacitor C_ai will couple with the AC signal thereby creating the voltage differential between the signal CLK1 (as applied to the gate of transistor M1 ) and the signal CLK1 H (as applied to the gate of transistor M4) One skilled in the art will recognize that various clock generating circuits (not shown) may be used to generate the clock signals with the necessary timings to drive switches SW3 and SW4 without departing from this invention.

Similarly, transistors M2 and M3 are configured to switch on simultaneously when Logic 1 is provided to the gates of these two transistors via clock signal 121c. However, it should be noted that the signal used to switch on the gate of transistor M3 is different from the signal provided to the gate of transistor M2. The clock signal 121 c at the gate of transistor M3 is at a CLK3 level while the signal provided to the gate of transistor M2 is at a CLK3H level and this is due to assistant capacitor C_a2 discharging when transistors M2 and M3 are switching on. In particular, when transistors M2 and M3 are not switched on, switches SW1 and SW2 will switch on momentarily, thereby gradually charging up assistant capacitor and when M2 and M3 are switching on, assistant capacitor C_a2 will couple with the AC signal thereby creating the voltage differential between the signal CLK3 (as applied to the gate of transistor M3) and the signal CLK3H (as applied to the gate of transistor M2). As mentioned in the previous paragraph, one skilled in the art will recognize that various clock generating circuits (not shown) may be used to generate the clock signals used to drive switches SW1 and SW2 without departing from this invention.

In embodiments of the invention, switches SW1 , SW3 and SW4 may comprise PMOS transistors configured to operate as switches which switch on when Logic 0 is applied to the gates of these transistors while switch SW2 may comprise an NMOS transistor configured to operate as a switch that switches on when Logic 1 is applied to the gate of this transistor. One skilled in the art will recognize that SW1 -SW4 are not limited to these types of transistors and other types of transistors or switches may be utilized to achieve the same functions without departing from this invention.

In accordance with embodiments of the invention, in order to ensure that the boosted output at the load of charge pump 125 remains constant throughout and as at least five complete cycles of an AC signal are required in order to complete one charge pump cycle, five charge pump branches may be utilized with one of the AC signals, e.g. AC signal 104, as illustrated in Figure 1 1 . This means that each charge pump branch will comprise its own plurality of transmission gates 120 that are controlled by its associated logic circuits 1 15 whereby the corresponding clock signals produced by these transmission gates are used to control the corresponding charge pump 125 in the charge pump branch. Further, in order to ensure that the boosted output at the load remains constant, the phases of the clock signals utilized in each charge pump branch will have to differ from each other. This is shown in Figure 12 with regard to the first clock signal as generated by each of the plurality of transmission gates in each charge pump branch. In other words, at phase 1202, the 1 ^st clock signal will be at Logic 0, at phase 1204 the 2^nd clock signal will be at Logic 0, at phase 1206 the 3^rd clock signal will be at Logic 0, at phase 1208 the 4^th clock signal will be at Logic 0, and at phase 1210 the 5^th clock signal will be at Logic 0. Thereafter, the clock signals will repeat accordingly. By doing so, the power management system 100 is able to ensure that the boosted voltage at the load of charge pump 125 as driven by AC signal 104 remains constant throughout. It should be noted that the phase difference between the clock signals may be selected by changing the timing diagram of the control signals produced by the corresponding logic circuits in each of the charge pump branches.

Similarly, in order to simultaneously utilize AC signal 102, additional five charge pump branches 1 105 may be used. Each one of these charge pump branches will comprise its own plurality of transmission gates 120 that are controlled by its associated logic circuits 1 15 whereby the corresponding clock signals produced by these transmission gates are used to control the corresponding charge pump 125 in the charge pump branch. Further, in order to ensure that the boosted output at the load remains constant, the phases of the clock signals utilized in each charge pump branch will have to differ from each other as shown in the timing diagrams of Figure 12.

In embodiments of the invention, in order to maintain the L-C tank (as illustrated in Figure 2) of power management system 100 in perfect resonating condition, the equivalent capacitance C in the L-C tank should be maintained at a constant value at all time. One way to achieve this is by dividing the AC signal into five identical clock drive signals to drive the corresponding capacitors in each charge pump branch. As a result, the flying capacitor in each of the charge pump branches are treated as if it is always connected to the L-C tank because the five charge pump branches work in a perfect cycle and they are identical. In this manner, the L-C tank’s constant resonance may be maintained. In particular, the equivalent capacitance C in the L-C tank should be maintained at constant values at all time. If only one charge pump branch is used, then the L-C tank’s equivalent capacitance would fluctuate through phases 1 to 6. Figure 10 illustrates that the equivalent capacitance changed in each of phases 1 to 6 when the various circuit nodes are driven to a low level or a high level between phases 1 to 6 as different circuit nodes have different capacitances. Flence, when five charge pump branches are used, as illustrated in Figure 12, the corresponding signals 121 a, 121 b and 121 c will form non-stop rising-falling edges. In other words, this means that there will always be a 121 a signal (i.e. a CLK1 signal) that is either rising or falling in each of these phases. Further, as the 5 charge pump branches are identical, the 121 a signal will contribute the same capacitance C for the L-C tank in every phase. The explanation above may also be applied for signals 121 b and 121c and as a result, the capacitance C in the L-C tank remains constant throughout.

Embodiment

As an exemplary embodiment of the invention, the design as illustrated in the drawings and as described in the sections above was fabricated using a Complementary Metal-Oxide-Semiconductor (CMOS) 0.18pm process. The AC signal that was provided to the power management module comprised a 13.56 MFIz AC signal which when provided to the active rectifier circuit produced rectified outputs having a VDD voltage level. The rectified outputs together with the AC signal were then provided to the respective charge pump branches and as a result, produced a voltage level of 2VDD at the load of the charge pump branches. It was also found that the power management module achieved a power efficiency of 85.8%.

Table 2 Table 2 above illustrates the power efficiency of the fabricated module 100 as compared to the power efficiencies of power management modules produced by others skilled in the art.

The above is a description of embodiments of a system and method in accordance with the present invention as set forth in the following claims. It is envisioned that others may and will design alternatives that fall within the scope of the following claims.

Claims

CLAIMS:

1. A power management module comprising:

an active rectifier circuit configured to rectify a first alternating current (AC) signal to a first pulse signal and to rectify a second AC signal to a second pulse signal;

a first logic circuit configured to utilize the first and second pulse signals to control a first group of transmission gates to generate, from one of the AC signals, a first set of clock signals; and

a first charge pump module being biased by a bias voltage V_DD, and comprising a first flying capacitor, a first set of switch transistors and an output, wherein the first charge pump module is configured to charge and discharge the first flying capacitor by controlling the first set of switch transistors using the first set of clock signals, whereby the discharging of the first flying capacitor boosts the output of the first charge pump module above the bias voltage V_DD.

2. The module according to claim 1 wherein the first pulse signal is generated based on a valley of the first AC signal and the second pulse signal is generated based on a valley of the second AC signal.

3. The module according to any one of claims 1 or 2, whereby the first logic circuit comprises:

a plurality of D-type Flip Flops having outputs that are coupled to a plurality of AND logic gates, wherein the first and second pulse signals are provided to the D-type Flip Flops for causing control signals to be produced at outputs of the AND logic gates, whereby the control signals are used to control the first group of transmission gates.

4. The module according to any one of claims 1 to 4 further comprising:

a second logic circuit configured to utilize the first and second pulse signals to control a second group of transmission gates to generate, from one of the AC signals, a second set of clock signals; and a second charge pump module being biased by the bias voltage V _DD, and comprising a second flying capacitor, a second set of switch transistors and an output, wherein the second charge pump module is configured to charge and discharge the second flying capacitor by controlling the second set of switch transistors using the second set of clock signals, whereby the discharging of the second flying capacitor boosts the output of the second charge pump module,

whereby the output of the first charge pump module is connected to the same load as the output of the second charge pump module, and

whereby a clock signal in the second set of clock signals is out of phase with a clock signal in the first set of clock signals by at least one clock cycle of the AC signal used to generate the first and second set of clock signals.

5. The module according to any one of claims 1 to 3 further comprising:

an inductor-capacitor resonator circuit configured to generate the first and second AC signals based on received wireless power.

6. A method for managing a power management module, the method comprising:

rectifying, using an active rectifier circuit, a first alternating current (AC) signal to a first pulse signal and a second AC signal to a second pulse signal;

utilizing, using a first logic circuit provided in the management module, the first and second pulse signals to control a first group of transmission gates to generate, from one of the AC signals, a first set of clock signals; and

charging and discharging a first flying capacitor provided in a first charge pump module, the first charge pump module being provided in the management module, being biased by a bias voltage V _DD, and comprising a first set of switch transistors and an output,

wherein the first flying capacitor is charged and discharged by controlling the first set of switch transistors using the first set of clock signals, whereby the discharging of the first flying capacitor boosts the output of the first charge pump module above the bias voltage V_DD.

7. The method according to claim 6 wherein the first pulse signal is generated based on a valley of the first AC signal and the second pulse signal is generated based on a valley of the second AC signal.

8. The method according to any one of claims 6 or 7, whereby the first logic circuit comprises:

9. The method according to any one of claims 6 to 8 further comprising:

utilizing, using a second logic circuit provided in the management module, the first and second pulse signals to control a second group of transmission gates to generate, from one of the AC signals, a second set of clock signals; and

charging and discharging a second flying capacitor provided in a second charge pump module, the second charge pump module being provided in the management module, being biased by the bias voltage V_DD, and comprising a second set of switch transistors and an output,

wherein the second flying capacitor is charged and discharged by controlling the second set of switch transistors using the second set of clock signals, whereby the discharging of the second flying capacitor boosts the output of the first charge pump module,

10. The method according to any one of claims 6 to 9 further comprising: