WO2020072867A1

WO2020072867A1 - Methods, apparatus, and systems for remote epitaxy using stitched graphene

Info

Publication number: WO2020072867A1
Application number: PCT/US2019/054639
Authority: WO
Inventors: Kyusang Lee; Wei Kong; Jeehwan Kim
Original assignee: Massachusetts Institute of Technology
Current assignee: Massachusetts Institute of Technology
Priority date: 2018-10-05
Filing date: 2019-10-04
Publication date: 2020-04-09
Anticipated expiration: 2021-04-05

Abstract

Apparatus, systems, and methods for remote epitaxy using multiple 2D layers comprising disposing a first two-dimensional (2D) layer onto a target substrate, disposing a second 2D layer onto the target substrate and adjacent to the first 2D layer so as to form at least a portion of a release layer, forming a first epitaxial layer on the release layer, and removing the first epitaxial layer from the release layer.

Description

METHODS, APPARATUS, AND SYSTEMS FOR REMOTE EPITAXY USING

STITCHED GRAPHENE

REUATED APPUI CATIONS

This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 62/741,992, filed October 5, 2018, and entitled“Methods, Apparatus, and Systems for Remote Epitaxy Using Stitched Graphene,” which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND

Advanced GaN-based electronics rely heavily on the material quality of GaN templates as the initial building blocks. The characteristics of a GaN template, such as the dislocation density and surface roughness, affect the performance of active devices epitaxially grown on top of the GaN template. However, due to the limited availability and the cost of high quality bulk GaN templates, heteroepitaxy of GaN on foreign substrates, such as sapphire and Si, is common practice. Even though these foreign substrates (e.g., sapphire and Si) are available in large diameters, the lattice and thermal expansion coefficient mismatch of these substrates to GaN can lead to complexity in the growth process and excess dislocation density. In addition, the removal of epitaxial GaN thin films from bulk/foreign substrates is usually very challenging. Existing liftoff processes involving

photoelectrochemical etching, mechanical spalling, and laser interface melting suffer from either slow processing speed or significant surface roughening/cracking, thereby limiting the process yield and practicality of reusing the substrate.

Growth of GaN on a monolayer graphene coated high quality GaN template through remote epitaxy allows for the reuse of costly GaN templates. However, the processing wafer area is usually equal to or smaller than the diameter of epitaxial graphene area, since the reuse of the substrate is prohibited if homoepitaxy of GaN directly on GaN without graphene occurs. Wafer size scaling is therefore limited by the available SiC substrate that is used to fabricate epitaxial graphene.

SUMMARY

Embodiments of the present invention include apparatus, systems, and methods for remote epitaxy using stitched graphene. In one aspect, a method of fabricating a semiconductor device is provided. In one example, the method comprises disposing a first two-dimensional (2D) layer onto a target substrate, disposing a second 2D layer onto the target substrate and adjacent to the first 2D layer so as to form at least a portion of a release layer, forming a first epitaxial layer on the release layer, and removing the first epitaxial layer from the release layer.

In another example, a method of fabricating a semiconductor device includes forming a first 2D layer on a first substrate and transferring the first 2D layer onto a target substrate. The method also includes forming a second 2D layer on a second substrate and disposing the second 2D layer onto the target substrate and adjacent to the first 2D layer so as to form at least a portion of a release layer. The method further includes forming a first epitaxial layer on the release layer removing the first epitaxial layer from the release layer.

It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and/or structurally similar elements).

FIGS. 1A-1D illustrate a method of forming a release layer for fabricating

semiconductor devices, in accordance with certain embodiments.

FIGS. 2A-2C illustrate a method of fabricating semiconductor devices using a stitched release layer, in accordance with some embodiments.

FIG. 3A shows a schematic of a release layer that can be used for fabricating semiconductors via remote epitaxy, in accordance with certain embodiments. FIG. 3B shows a schematic of a stitched release layer including round 2D layers, in accordance with some embodiments.

FIGS. 4A-4E illustrate a method of fabricating semiconductor devices on a reusable platform including a stitched release layer, in accordance with certain embodiments.

DETAILED DESCRIPTION

Methods, apparatus, and systems described herein can be used to address the challenges in conventional semiconductor fabrication using remote epitaxy techniques via a stitched release layer. In one embodiment, a growth substrate (also referred to as a target substrate) is coated with a release layer including monolayer graphene by stitching graphene. The stitched graphene can be transferred from a different SiC substrate. The release layer therefore can have a larger diameter compared to graphene grown on a single SiC substrate. Remote epitaxy can then be performed on the release layer. Due to the large diameter of the release layer, a large-area epitaxial layer (e.g., GaN) can be fabricated.

Because of the van der Waals interaction at the interface between the release layer and the epitaxial thin film, the epitaxial thin film can be precisely and rapidly exfoliated from the substrate, with the atomic flatness at the released surface mimicking the morphology of the release layer. Such a high quality interface allows for the reuse of the substrate without post processing, as well as the bonding of the epitaxial thin film to any foreign substrate having a flat surface. This technique also allows for novel device design, including the bonding of an active device to an electrically and/or thermally conductive substrate for improved thermal dissipation, serial electrical conductance, and/or current spreading characteristics.

In some examples, epitaxial graphene can be used as the material for the release layer and can be produced by sublimation of Si with SiC substrates. In some examples, hexagonal boron nitride can be used as the material for the release layer. In some embodiments, the release layer comprises a transition metal dichalcogenide (TMD), for example, having the formula MX₂, where M is a transition metal atom (e.g., Mo, W, etc.) and X is a chalcogen atom (e.g., S, Se, or Te). In some embodiments, the release layer comprises M0S2 or WSe₂.

The substrates can be diced into an appropriate size and/or shape. In some embodiments, each graphene layer is individually transferred and stitched onto a high quality GaN template, thereby covering the entire GaN template surface. In some embodiments, epitaxial GaN thin films are then deposited on the stitched graphene coated GaN template. The thin film GaN is subsequently, in certain embodiments, exfoliated and transferred to a foreign substrate. In some embodiments, the stitched graphene coated GaN template is reused for the next cycle of GaN growth, thereby reducing the fabrication cost.

FIGS. 1A-1D illustrate a method 100 of forming a release layer 135 for fabricating semiconductor devices. The method 100 includes, as illustrated in FIG. 1A, forming a first two-dimensional (2D) layer 110 on a first substrate (underneath first 2D layer 110, not shown in FIG. 1A). In some examples, first 2D layer 110 as formed has a round shape. In some other examples, first 2D layer 110 can have any other appropriate shape (e.g., the same shape as the first substrate).

FIG. 1B shows an optional step of cleaving first 2D layer 110 into a different shape, referred to as a cleaved first 2D layer 120. For example, first 2D layer 110 as fabricated can have a round shape and cleaved first 2D layer 120 can have a rectangular shape (including square shape). Cleaved first 2D layer 120 can have any other appropriate shape, such as diamond and hexagon. First 2D layer 110 can be processed into different shapes via various methods, such as laser cutting, water jet cutting, and die saw cutting, among others.

In FIG. 1C, cleaved first 2D layer 120 is transferred to a target substrate 140 (now referred to as 2D layer 120(1)). Additional 2D layers 120(2)-120(9) are also fabricated and transferred to target substrate 140. For example, a second 2D layer 120(2) can be fabricated on a second substrate, transferred to target substrate 140, and disposed adjacent to first 2D layer 120(1). Alternatively or additionally, the same substrate can be used to fabricate multiple 2D layers. These 2D layers 120(1)-120(9) are disposed adjacent to each other to form a preliminary release layer 130, i.e., these 2D layers 120(1)-120(9) are stitched together to form a single piece of 2D layer.

In one example, 2D layers 120(1)-120(9) can have the same shape (e.g., rectangular, square, hexagon, etc.). In another example, 2D layers 120(1)- 120(9) can have different shapes. In one example, 2D layers 120(1)-120(9) can form a 2D array. In another example, 2D layers 120(1)-120(9) can form a 1D sequence. The total number of 2D layers 120 can be, for example, 2 to 100, including any values and sub ranges in between.

In one example, each 2D layer in the array of 2D layers 120(1)-120(9) are coupled to an adjacent 2D layer at the edge. In another example, at least some of the 2D layers are overlapping with adjacent 2D layers to reinforce the stitching.

FIG. 1D shows another optional step of modifying the shape of preliminary release layer 130 into a release layer 135. For example, preliminary release layer 130 can be rectangular or square, and release layer 135 can be round. The shape of release layer 135 can depend on, for example, the desired shape of epitaxial layers to be fabricated on release layer 135.

As described herein, first 2D layer 110 can be made of graphene, in which case first 2D layer 110 is also referred to as graphene layer 110. Graphene layer 110 can be fabricated on the first substrate via various methods. In one example, graphene layer 110 can include an epitaxial graphene with a single-crystalline orientation and the substrate can include a (0001) 4H-SiC wafer with a silicon surface. The fabrication of graphene layer 110 can include multistep annealing steps. A first annealing step can be performed in H₂ gas for surface etching and vicinalization, and a second annealing step can be performed in Ar for graphitization at high temperature (e.g., about 1,575 °C).

In another example, graphene layer 110 can be grown on the first substrate via a chemical vapor deposition (CVD) process. The first substrate can include a nickel substrate or a copper substrate. Alternatively, the substrate can include an insulating substrate of Si0₂, Hf0₂, Al₂0₃, Si₃N₄, and practically any other high temperature compatible planar material by CVD.

In yet another example, the first substrate can be any substrate that can hold graphene layer 110 and the fabrication can include a mechanical exfoliation process. In this example, the first substrate can function as a temporary holder for graphene layer 110.

Various methods can also be used to transfer graphene layer 110 from the first substrate to target substrate 140. In one example, a carrier film can be attached to graphene layer 110. The carrier film can include a thick film of Poly(methyl methacrylate) (PMMA) or a thermal release tape and the attachment can be achieved via a spin-coating process. After the combination of the carrier film and graphene layer 110 is disposed on target substrate 140, the carrier film can be dissolved (e.g., in acetone) for further fabrication of the epilayer on graphene layer 110.

In another example, a stamp layer including an elastomeric material such as polydimethylsiloxane (PDMS) can be attached to graphene layer 110 and the first substrate can be etched away, leaving the combination of the stamp layer and graphene layer 110.

After the stamp layer and graphene layer 110 are placed on target substrate 140, the stamp layer can be removed by mechanical detachment, producing a clean surface of graphene layer 110 for further processing.

In yet another example, a self-release transfer method can be used to transfer graphene layer 110 to target substrate 140. In this method, a self-release layer is first spun- cast over the graphene layer 110. An elastomeric stamp is then placed in conformal contact with the self-release layer. The first substrate can be etched away to leave the combination of the stamp layer, the self-release layer, and the graphene layer. After this combination is placed on target substrate 140, the stamp layer can be removed mechanically and the self release layer can be dissolved under mild conditions in a suitable solvent. The release layer can include polystyrene (PS), poly(isobutylene) (PIB), and/or Teflon AF (poly[4,5-difluoro- 2,2-bis(trifluoromethyl)-l,3-dioxole-co-tetrafluoroethylene]).

FIGS. 2A-2C illustrate an example of a method 200 of fabricating an epitaxial layer 230 using a stitched release layer 220. The epitaxial layer can comprise, for example, a semiconductor material. Examples of such semiconductor materials include, but are not limited to III-V semiconductors (which can be, for example, III-N semiconductors, III-P semiconductors, or III-As semiconductors, examples of which include GaN, A1N, InN, GaP, A1P, InP, AlAs, and GaAs); II- VI semiconductors; and Ge. In some embodiments, the semiconductor comprises GaN.

In FIG. 2A, release layer 220 is disposed on a target substrate 210. In some examples, epitaxial layer 230 is fabricated via remote epitaxy, in which the epitaxial growth of epitaxial layer 230 is seeded by target substrate 210. For example, target substrate 210 and epitaxial layer 230 can include the same material, such as GaN or any other appropriate material. In some embodiments, target substrate 210 comprises GaN, such as GaN fabricated via hydride vapor phase epitaxy (HVPE). In some embodiments, release layer 220 comprises a plurality of sheets of graphene. In certain embodiments, epitaxial layer 230 comprises GaN, optionally epitaxial GaN such as GaN formed by remote epitaxy.

The seeding of epitaxial layer 230 by target substrate 210 (e.g., to produce an epitaxial layer 230 that is epitaxially matched with target substrate 210) can occur, in accordance with certain embodiments, even when there is not direct contact between epitaxial layer 230 and target substrate 210. (Such contact might occur, for example, when there are holes in release layer 220.) For example, in accordance with certain embodiments, target substrate 210 may have a potential field (e.g., created by van der Waals forces and/or other atomic or molecular forces) and release layer 220 may be so thin (e.g., in cases where the release layer comprises laterally stitched portions of monolayer graphene) that the potential field of target substrate 210 reaches beyond release layer 220 an interacts with the region within which epitaxial layer 230 is formed. As a result, in some embodiments, the potential field from target substrate 210 affects the growth of epitaxial layer 230. In some such embodiments, the crystallographic orientations of target substrate 210 and epitaxial layer 230 can be matched. As described above, release layer 220 can have various shapes. FIG. 2B shows a release layer 220a having a round shape. FIG. 2C shows a release layer 220b having a pseudo-square shape.

FIG. 3A shows a schematic of an example of a stitched release layer 300 for fabricating semiconductor devices via remote epitaxy. In FIG. 3A, release layer 300 includes a collection of 2D layers 310, and adjacent 2D layers are overlapping with each other to reinforce the stitching. For example, a first 2D layer 310(1) (which can be, in some embodiments, a monolayer of graphene) is overlapping, on the edge, with a second 2D layer 310(2) (which can be, in some embodiments, a second monolayer of graphene) to form an overlap region 315 (in which, in some embodiments, two monolayers of graphene overlap). The ratio of the area of the overlap region 315 with respect to the area of the first 2D layer 310(1) can be, for example, about 1% to about 90% (e.g., about 1%, about 2%, about 5%, about 10%, about 20%, about 30%, about 40%, about 50%, about 60%, about 70%, about 80%, or about 90%, including any values and sub ranges in between).

FIG. 3B shows a schematic of a release layer 301 including round 2D layers 330a- 330d. Another round 2D layer 340 is disposed on the gap formed by the array of the four 2D layers 330a-330d. Additional 2D layers can be added similarly to increase the area of the resulting release layer 301. In one example, the 2D layer 340 is also round. In another example, the 2D layer 340 can have any other shape, as long as the 2D layer 340 can substantially cover the gap between adjacent 2D layers 330a-330d.

FIGS. 4A-4E illustrate one example of a method 400 of fabricating semiconductor devices using a reusable platform including a stitched release layer. The method 400 starts with a substrate 410 (e.g., a GaN template) as illustrated in FIG. 4A, followed by forming a release layer 420 (e.g., comprising stitched graphene) on substrate 410 as illustrated in FIG. 4B. For example, substrate 410 can include GaN fabricated via hydride vapor phase epitaxy (HVPE). In one example, release layer 420 can be formed directly on substrate 410 (e.g., via the method 100 illustrated in FIGS. 1A-1D). In another example, release layer 420 can be formed on another substrate and then transferred to substrate 410.

In FIG. 4C, an epitaxial layer 430 is fabricated on the release layer 420 via remote epitaxy, i.e., seeded by substrate 410. For example, in some embodiments, epitaxial layer 430 can include a GaN thin film, and substrate 410 includes GaN as well.

In FIG. 4D, in accordance with some embodiments, a handler layer 440 is formed on epitaxial layer 430 to facilitate the removal and transfer of epitaxial layer 430. After the removal of epitaxial layer 430, the platform including substrate 410 and release layer 420 can be reused to grow another epitaxial layer (e.g., via reuse step 460 in FIGS. 4C-4D). In some embodiments, the removed epitaxial layer 430 is disposed on a host substrate 450 for further processing, such as in forming a functional device, such as LEDs, lasers, transistors, and/or solar cells, among others. More information about layer transfer technique can be found in PCT Patent Application No. PCT/US2016/050701, filed September 8, 2016, published as International Patent Application Publication No. WO 2017/044577 on March 16, 2017, and entitled“SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER,” which is incorporated herein by reference in its entirety.

While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

The above-described embodiments can be implemented in any of numerous ways.

For example, embodiments of designing and making the technology disclosed herein may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible format.

Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.

The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

The terms“program” or“software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.

Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.

Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationships between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationships between data elements.

Also, various inventive concepts may be embodied as one or more methods, of which examples have been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

The indefinite articles“a” and“an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean“at least one.”

The phrase“and/or,” as used herein in the specification and in the claims, should be understood to mean“either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with“and/or” should be construed in the same fashion, i.e.,“one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the“and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

As used herein in the specification and in the claims,“or” should be understood to have the same meaning as“and/or” as defined above. For example, when separating items in a list,“or” or“and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as“only one of’ or“exactly one of,” or, when used in the claims,“consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term“or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e.,“one or the other but not both”) when preceded by terms of exclusivity, such as“either,”“one of,”“only one of,” or “exactly one of.”“Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

As used herein in the specification and in the claims, the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example,“at least one of A and B” (or, equivalently,“at least one of A or B,” or, equivalently“at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another

embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one,

B (and optionally including other elements); etc.

In the claims, as well as in the specification above, all transitional phrases such as “comprising,”“including,”“carrying,”“having,”“containing,”“involving,”“holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases“consisting of’ and“consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

disposing a first two-dimensional (2D) layer and a second 2D layer onto a target substrate, the second 2D layer being adjacent to the first 2D layer, so as to form at least a portion of a release layer;

forming a first epitaxial layer on the release layer; and

removing the first epitaxial layer from the release layer.

2. The method of claim 1, wherein disposing the first 2D layer onto the target substrate comprises forming the first 2D layer on a first substrate and transferring the first 2D layer from the first substrate onto the target substrate.

3. The method of any one of claims 1-2, wherein disposing the second 2D layer onto the target substrate comprises forming the second 2D layer on a second substrate and transferring the second 2D layer from the second substrate onto the target substrate.

4. The method of any one of claims 2-3, wherein forming the first 2D layer comprises forming the first 2D layer on a SiC substrate.

5. The method of any one of claims 2-4, wherein forming the first 2D layer comprises forming the first 2D layer via epitaxial growth.

6. The method of any one of claims 1-5, wherein the first 2D layer comprises graphene.

7. The method of any one of claims 1-6, wherein disposing the second 2D layer comprises disposing at least a portion of the second 2D layer on the first 2D layer so as to form an overlap region.

8. The method of any one of claims 1-7, wherein the target substrate comprises a semiconductor and the first epitaxial layer comprises the semiconductor.

9. The method of claim 8, wherein the semiconductor comprises GaN.

10. The method of any one of claims 1-9, wherein the target substrate comprises GaN, and further comprising:

forming the target substrate comprising GaN via hydride vapor phase epitaxy (HVPE).

11. The method of any one of claims 1-10, further comprising:

after removing the first epitaxial layer from the release layer, forming a second epitaxial layer on the release layer.

12. The method of any one of claims 2-11, further comprising:

cleaving the first 2D layer into a rectangular shape before transferring the first 2D layer onto the target substrate.

13. The method of any one of claims 1-12, wherein, during the forming of the first epitaxial layer, the first epitaxial layer is not in direct contact with the target substrate.

14. The method of any one of claims 1-12, wherein, during the forming of the first epitaxial layer, a potential field from the target substrate reaches beyond the release layer and affects the growth of the first epitaxial layer.