WO2020072871A1 - Methods, apparatus, and systems for manufacturing gan templates via remote epitaxy - Google Patents

Methods, apparatus, and systems for manufacturing gan templates via remote epitaxy

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Publication number
WO2020072871A1
WO2020072871A1 PCT/US2019/054646 US2019054646W WO2020072871A1 WO 2020072871 A1 WO2020072871 A1 WO 2020072871A1 US 2019054646 W US2019054646 W US 2019054646W WO 2020072871 A1 WO2020072871 A1 WO 2020072871A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gan
forming
gan layer
substrate
Prior art date
Application number
PCT/US2019/054646
Other languages
French (fr)
Inventor
Kyusang Lee
Eugene Fitzgerald
Wei Kong
Jeehwan Kim
Original Assignee
Massachusetts Institute Of Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Massachusetts Institute Of Technology filed Critical Massachusetts Institute Of Technology
Publication of WO2020072871A1 publication Critical patent/WO2020072871A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B21/00—Nitrogen; Compounds thereof
    • C01B21/06—Binary compounds of nitrogen with metals, with silicon, or with boron, or with carbon, i.e. nitrides; Compounds of nitrogen with more than one metal, silicon or boron
    • C01B21/0632—Binary compounds of nitrogen with metals, with silicon, or with boron, or with carbon, i.e. nitrides; Compounds of nitrogen with more than one metal, silicon or boron with gallium, indium or thallium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02499—Monolayers
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02485—Other chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • Advanced GaN-based electronics rely heavily on the material quality of GaN templates as the initial building blocks.
  • the characteristics of a GaN template such as the dislocation density and surface roughness, affect the performance of active devices epitaxially grown on top of the GaN template.
  • heteroepitaxy of GaN on foreign substrates such as sapphire and Si, is common practice. Even though these foreign substrates (e.g., sapphire and Si) are available in large diameters, the lattice and thermal expansion coefficient mismatch of these substrates to GaN can lead to complexity in the growth process and excess dislocation density.
  • the removal of epitaxial GaN thin films from bulk/foreign substrates is usually very challenging. Existing liftoff processes involving
  • photoelectrochemical etching, mechanical spalling, and laser interface melting suffer from either slow processing speed or significant surface roughening/cracking, thereby limiting the process yield and practicality of reusing the substrate.
  • Embodiments of the present invention include apparatus, systems, and methods for manufacturing GaN templates via remote epitaxy.
  • a method of fabricating a semiconductor device includes forming a first GaN layer on a first substrate and removing the first substrate. The method also includes forming a release layer on the first GaN layer so as to form a GaN template, and the release layer includes a two-dimensional (2D) material. The method further includes forming a second GaN layer on the GaN template via epitaxial growth and transferring the second GaN layer from the GaN template to a second substrate.
  • FIGS. 1A-1C illustrate a method of fabricating a GaN template including a release layer, in accordance with certain embodiments.
  • FIGS. 2A-2C illustrate a method of fabricating and transferring a GaN layer using the GaN template fabricated via the method illustrated in FIGS. 1A-1C, in accordance with some embodiments.
  • FIGS. 3A-3D illustrate a method of fabricating semiconductor devices using a jet sprayed substrate handler, in accordance with certain embodiments.
  • FIGS. 4A-4D illustrate a method of fabricating semiconductor devices using a GaN template and sputtered GaN or A1N as a handler, in accordance with some embodiments.
  • FIGS. 5A-5D illustrate a method of fabricating semiconductor devices using sputtered GaN or A1N as a host substrate, in accordance with certain embodiments.
  • FIG. 6 shows a schematic of a substrate handler for fabricating semiconductor devices, in accordance with some embodiments.
  • Homoepitaxial growth can be performed remotely through a single-atom- thickness gap, with the dislocation density of the epitaxial thin film at the same level as the high-quality substrate.
  • the single-atom-thickness gap can be achieved using a layer of two-dimensional (2D) material, such as graphene. This layer is referred to as a release layer throughout this application. Because of the van der Waals interaction at the interface between the release layer and the epitaxial thin film, the epitaxial thin film can be precisely and rapidly exfoliated from the substrate, with the atomic flatness at the released surface mimicking the morphology of the release layer.
  • Such a high quality interface allows the reuse of substrate without post processing, as well as the bonding of the epitaxial thin film to any foreign substrate having a flat surface.
  • this technique also allows novel device design, including the bonding of active devices to electrically and thermally conductive substrates for improved thermal dissipation, serial electrical conductance, and/or current spreading characteristics.
  • FIGS. 1A-1C illustrate a method 100 of fabricating a GaN template 140.
  • Method 100 includes forming a GaN layer 110 (also referred to as a first GaN layer, which can be, in some embodiments, a GaN buffer layer) on a substrate 120 (e.g., a silicon substrate, a sapphire substrate, or a SiC substrate, etc.) as shown in FIG. 1 A.
  • GaN layer 110 can be formed using, for example, hydride vapor phase epitaxy (HVPE) in a chamber 105.
  • HVPE hydride vapor phase epitaxy
  • HVPE hydride vapor phase epitaxy
  • hydrogen chloride is reacted at elevated temperature with group-III metals to produce gaseous metal chlorides, which then react with ammonia to produce the group-III nitrides.
  • Carrier gasses commonly used include ammonia, hydrogen, and various chlorides.
  • FIG. 1B shows that substrate 120 for growing GaN layer 110 is removed via, for example, mechanical polishing, grinding, or laser lift-off.
  • a release layer 130 is formed on GaN layer 110, thereby forming a GaN template 140.
  • the lateral dimension of GaN template 140 can depend on the dimension of substrate 120.
  • at least one lateral dimension (e.g., a diameter) of GaN template 140 can be about 0.5 inch to about 18 inches (e.g., about 0.5 inch, about 1 inch, about 2 inches, about 3 inches, about 5 inches, about 10 inches, about 12 inches, about 14 inches, or about 18 inches, including any values and sub ranges in between).
  • Release layer 130 can include a two-dimensional (2D) material, such as graphene.
  • 2D two-dimensional
  • hexagonal boron nitride can be used as the material for the release layer.
  • the release layer comprises a transition metal dichalcogenide (TMD), for example, having the formula MX 2 , where M is a transition metal atom (e.g., Mo, W, etc.) and X is a chalcogen atom (e.g., S, Se, or Te).
  • TMD transition metal dichalcogenide
  • MX a transition metal atom
  • X a chalcogen atom
  • the release layer comprises MoS 2 or WSe 2 .
  • release layer 130 is prepared on another substrate and then disposed on GaN layer 110.
  • release layer 130 can be formed directly on GaN layer 110.
  • the 2D material can be a single layer of graphene (e.g., a single layer of crystalline graphene)
  • the 2D material can be continuous across its lateral dimensions. More information about forming releaser layer 130 can be found, for example, in PCT Patent Application No. PCT/US2016/050701, filed September 8, 2016, published as International Patent Application Publication No. WO 2017/044577 on March 16, 2017, and entitled“SYSTEMS AND METHODS FOR
  • FIGS. 2A-2C illustrate a method 200 of fabricating GaN layers using a GaN template.
  • the GaN template includes a first GaN layer 210 and a release layer 220 (which can comprise graphene) disposed on first GaN layer 210.
  • This template can be the same or substantially similar to GaN template 140 shown in FIG. 1C and fabricated via method 100 illustrated in FIGS. 1A-1C.
  • a second GaN layer 230 is formed on release layer 220 via remote epitaxy. The epitaxial growth of second GaN layer 230 can be seeded by first GaN layer 210 underneath release layer 220.
  • the seeding of second GaN layer 230 by first GaN layer 210 can occur, in accordance with certain embodiments, even when there is not direct contact between second GaN layer 230 and first GaN layer 210.
  • first GaN layer 210 may have a potential field (e.g., created by van der Waals forces and/or other atomic or molecular forces) and release layer 220 may be so thin (e.g., in the case of a monolayer of continuous graphene) that the potential field of first GaN layer 210 reaches beyond release layer 220 an interacts with the region within which second GaN layer 230 is formed.
  • the potential field from first GaN layer 210 affects the growth of second GaN layer 230.
  • the crystallographic orientations of first GaN layer 210 and second GaN layer 230 can be matched.
  • a handler layer 240 (also referred to as a mechanical handler) is formed on second GaN layer 230.
  • Handler layer 240 is employed, in some embodiments, to exfoliate second GaN layer 230 precisely at the interface between second GaN layer 230 and release layer 220.
  • handler layer 240 can include, for example, a metal stressor (e.g., a nickel stressor).
  • an optional tape layer can be formed on the metal stressor to facilitate the transfer process.
  • handler layer 240 can include poly A1N.
  • handler layer 240 can include various other materials, such as glass, tape (e.g., heat release tape), polymer, and/or a silicon substrate, among others.
  • the exfoliated second GaN layer 230 is disposed on a second substrate 250 (also referred to as a substrate handler) for further processing, such as forming a functional device.
  • Second substrate 250 can be employed for various functions.
  • second substrate 250 can be used to as a vehicle to transport GaN layer 230.
  • second substrate 250 can be used as a temporary holder of GaN layer 230.
  • Second substrate 250 can be either flexible or rigid.
  • Handler layer 240 can also be removed, exposing the surface of second GaN layer 230 for further processing.
  • the GaN template i.e., the platform including the first GaN layer 210 and the release layer 220
  • the GaN template can be reused to fabricate additional GaN layers (e.g., a third GaN layer, a fourth GaN layer, and so on), as illustrated by reuse step 260 in FIGS. 2A-2B.
  • FIGS. 3A-3D illustrate a method 300 of fabricating semiconductor devices using a jet sprayed substrate handler 350.
  • Method 300 includes, in accordance with certain
  • a second GaN layer 330 (e.g., epitaxially, such as via remote epitaxy) on a release layer 320 (e.g., graphene), which is disposed on a first GaN layer 310, as shown in FIG. 3A.
  • a handler layer 340 is formed on second GaN layer 330 to exfoliate second GaN layer 330 from release layer 320.
  • the GaN template including first GaN layer 310 and release layer 320, can be reused to fabricate additional GaN layers, as illustrated by reuse step 360 in FIGS. 3A-3B.
  • FIG. 3C shows handler layer 340 and the exfoliated second GaN layer 330 disposed on a substrate handler 350.
  • Substrate handler 350 can include, for example, GaN or A1N that is formed via a jet spray. In practice, this jet spray method can be convenient because the jet spray method can create a thick layer within a short period of time. In addition, substrate handler 350 formed by jet spray can have good heat conduction.
  • FIG. 3D shows that handler layer 340 is removed from second GaN layer 330, thereby exposing the surface of second GaN layer 330 for further processing.
  • FIGS. 4A-4D illustrate a method 400 of fabricating semiconductor devices using a GaN template and sputtered GaN or A1N as a handler.
  • Method 400 includes, in accordance with certain embodiments, forming a second GaN layer 430 (e.g., epitaxially, such as via remote epitaxy) on a release layer 420 (e.g., graphene), which is disposed on a first GaN layer 410, as shown in FIG. 4A.
  • a second GaN layer 430 e.g., epitaxially, such as via remote epitaxy
  • a release layer 420 e.g., graphene
  • an interfacial layer 460 is formed on second GaN layer 430
  • a first handler layer 440a is formed on interfacial layer 460.
  • Interfacial layer 460 can include, for example, sputtered GaN or A1N.
  • First handler layer 440a and interfacial layer 460 can facilitate the exfoliation of second GaN layer 430 from release layer 420.
  • the GaN template including first GaN layer 410 and release layer 420, can be reused to fabricate additional GaN layers, as illustrated by reuse step 480 in FIGS. 4A-4B.
  • a second handler layer 440b is formed on second GaN layer 430 and is employed to transfer interfacial layer 460 and second GaN layer 430 to a foreign substrate 450, which can be the same as or similar to the substrate handlers described herein.
  • Interfacial layer 460 is, in some embodiments, in contact with foreign substrate 450 to facilitate bonding between second GaN layer 430 and foreign substrate 450.
  • second handler layer 440b is removed, exposing second GaN layer 430 for further processing.
  • handler layer 440a can include poly A1N
  • interfacial layer 460 can include amorphous A1N so as to bond second GaN layer 430 with handler layer 440a.
  • FIGS. 5A-5D illustrate a method 500 of fabricating semiconductor devices using sputtered GaN or A1N as a host substrate.
  • Method 500 includes, in accordance with certain embodiments, and as shown in FIG. 5A, forming a second GaN layer 530 (e.g., epitaxially, such as via remote epitaxy) on a release layer 520 (e.g., graphene), which is disposed on a first GaN layer 510.
  • a host substrate 540 is formed on second GaN layer 530.
  • Host substrate 540 can include sputtered GaN or A1N.
  • the thickness of host substrate 540 can be about 1 pm to about 300 pm (e.g., about 1 pm, about 2 pm, about 3 pm, about 5 pm, about 10 pm, about 20 pm, about 30 pm, about 50 pm, about 100 pm, about 200 pm, or about 300 pm, including any values and sub ranges in between).
  • a handler layer 550 is formed on host substrate 540 and is employed to exfoliate second GaN layer 530 from release layer 520. After the exfoliation, the GaN template, including first GaN layer 510 and release layer 520, can be reused to fabricate additional GaN layers, as illustrated by reuse step 580 in FIGS. 5A-5C.
  • handler layer 550 is removed, leaving second GaN layer 530 attached to host substrate 540 to form a platform 560 for further processing.
  • FIG. 6 shows a schematic of a substrate handler 600 for fabricating semiconductor devices.
  • Handler 600 includes a substrate 610 and an optional intermediate layer 620.
  • Substrate 610 can include, for example, silicon, sapphire, glass, stainless steel, sputtered A1N, porous Si0 2 , and/or electroplate metal, among others.
  • the intermediate layer 620 can include, for example, sputtered A1N.
  • Intermediate layer 620 can be employed to manage the strain force between substrate 610 and any GaN layer disposed on handler 600.
  • intermediate layer 620 can have a good surface quality so as to receive the GaN layer disposed thereon.
  • Substrate handler 600 can be used for mechanical handling of GaN layers fabricated via remote epitaxy (e.g., second GaN layers 230, 330, 430, and/or 530).
  • Substrate handler 600 can also be used as a heat and/or electrical conductor.
  • Optional intermediate layer 620 can be used for strain management, as a back diffusion barrier, and/or for surface planarization.
  • inventive embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed.
  • inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein.
  • embodiments of designing and making the technology disclosed herein may be implemented using hardware, software or a combination thereof.
  • the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
  • a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.
  • PDA Personal Digital Assistant
  • a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible format.
  • Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet.
  • networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.
  • the various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.
  • inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above.
  • the computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.
  • program or“software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.
  • Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices.
  • program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • functionality of the program modules may be combined or distributed as desired in various embodiments.
  • data structures may be stored in computer-readable media in any suitable form.
  • data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationships between the fields.
  • any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationships between data elements.
  • inventive concepts may be embodied as one or more methods, of which examples have been provided.
  • the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
  • a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
  • “or” should be understood to have the same meaning as“and/or” as defined above.
  • “or” or“and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as“only one of’ or“exactly one of,” or, when used in the claims,“consisting of,” will refer to the inclusion of exactly one element of a number or list of elements.
  • the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
  • This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified.
  • “at least one of A and B” can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another

Abstract

Apparatus, systems, and methods for manufacturing GaN templates via remote epitaxy comprising forming a first GaN layer on a first substrate and removing the first substrate, forming a release layer on the first GaN layer so as to form a GaN template, and the release layer includes a two-dimensional (2D) material, forming a second GaN layer on the GaN template via epitaxial growth and transferring the second GaN layer from the GaN template to a second substrate.

Description

METHODS, APPARATUS, AND SYSTEMS FOR MANUFACTURING GAN
TEMPUATES VIA REMOTE EPITAXY
REUATED APPUI CATIONS
This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional
Application No. 62/742,123, filed October 5, 2018, and entitled“Methods, Apparatus, and Systems for Manufacturing GaN Templates Via Remote Epitaxy,” which is incorporated herein by reference in its entirety for all purposes.
BACKGROUND
Advanced GaN-based electronics rely heavily on the material quality of GaN templates as the initial building blocks. The characteristics of a GaN template, such as the dislocation density and surface roughness, affect the performance of active devices epitaxially grown on top of the GaN template. However, due to the limited availability and the cost of high quality bulk GaN templates, heteroepitaxy of GaN on foreign substrates, such as sapphire and Si, is common practice. Even though these foreign substrates (e.g., sapphire and Si) are available in large diameters, the lattice and thermal expansion coefficient mismatch of these substrates to GaN can lead to complexity in the growth process and excess dislocation density. In addition, the removal of epitaxial GaN thin films from bulk/foreign substrates is usually very challenging. Existing liftoff processes involving
photoelectrochemical etching, mechanical spalling, and laser interface melting suffer from either slow processing speed or significant surface roughening/cracking, thereby limiting the process yield and practicality of reusing the substrate.
SUMMARY
Embodiments of the present invention include apparatus, systems, and methods for manufacturing GaN templates via remote epitaxy. In one example, a method of fabricating a semiconductor device includes forming a first GaN layer on a first substrate and removing the first substrate. The method also includes forming a release layer on the first GaN layer so as to form a GaN template, and the release layer includes a two-dimensional (2D) material. The method further includes forming a second GaN layer on the GaN template via epitaxial growth and transferring the second GaN layer from the GaN template to a second substrate.
It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.
BRIEF DESCRIPTION OF THE DRAWINGS
The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and/or structurally similar elements).
FIGS. 1A-1C illustrate a method of fabricating a GaN template including a release layer, in accordance with certain embodiments.
FIGS. 2A-2C illustrate a method of fabricating and transferring a GaN layer using the GaN template fabricated via the method illustrated in FIGS. 1A-1C, in accordance with some embodiments.
FIGS. 3A-3D illustrate a method of fabricating semiconductor devices using a jet sprayed substrate handler, in accordance with certain embodiments.
FIGS. 4A-4D illustrate a method of fabricating semiconductor devices using a GaN template and sputtered GaN or A1N as a handler, in accordance with some embodiments.
FIGS. 5A-5D illustrate a method of fabricating semiconductor devices using sputtered GaN or A1N as a host substrate, in accordance with certain embodiments.
FIG. 6 shows a schematic of a substrate handler for fabricating semiconductor devices, in accordance with some embodiments.
DETAILED DESCRIPTION
Homoepitaxial growth can be performed remotely through a single-atom- thickness gap, with the dislocation density of the epitaxial thin film at the same level as the high-quality substrate. The single-atom-thickness gap can be achieved using a layer of two-dimensional (2D) material, such as graphene. This layer is referred to as a release layer throughout this application. Because of the van der Waals interaction at the interface between the release layer and the epitaxial thin film, the epitaxial thin film can be precisely and rapidly exfoliated from the substrate, with the atomic flatness at the released surface mimicking the morphology of the release layer. Such a high quality interface allows the reuse of substrate without post processing, as well as the bonding of the epitaxial thin film to any foreign substrate having a flat surface. In accordance with certain embodiments, this technique also allows novel device design, including the bonding of active devices to electrically and thermally conductive substrates for improved thermal dissipation, serial electrical conductance, and/or current spreading characteristics.
FIGS. 1A-1C illustrate a method 100 of fabricating a GaN template 140. Method 100 includes forming a GaN layer 110 (also referred to as a first GaN layer, which can be, in some embodiments, a GaN buffer layer) on a substrate 120 (e.g., a silicon substrate, a sapphire substrate, or a SiC substrate, etc.) as shown in FIG. 1 A. GaN layer 110 can be formed using, for example, hydride vapor phase epitaxy (HVPE) in a chamber 105. In this technique, hydrogen chloride is reacted at elevated temperature with group-III metals to produce gaseous metal chlorides, which then react with ammonia to produce the group-III nitrides. Carrier gasses commonly used include ammonia, hydrogen, and various chlorides.
FIG. 1B shows that substrate 120 for growing GaN layer 110 is removed via, for example, mechanical polishing, grinding, or laser lift-off. In FIG. 1C, a release layer 130 is formed on GaN layer 110, thereby forming a GaN template 140. The lateral dimension of GaN template 140 can depend on the dimension of substrate 120. For example, in some embodiments, at least one lateral dimension (e.g., a diameter) of GaN template 140 can be about 0.5 inch to about 18 inches (e.g., about 0.5 inch, about 1 inch, about 2 inches, about 3 inches, about 5 inches, about 10 inches, about 12 inches, about 14 inches, or about 18 inches, including any values and sub ranges in between).
Release layer 130 can include a two-dimensional (2D) material, such as graphene. In some examples, hexagonal boron nitride can be used as the material for the release layer. In some embodiments, the release layer comprises a transition metal dichalcogenide (TMD), for example, having the formula MX2, where M is a transition metal atom (e.g., Mo, W, etc.) and X is a chalcogen atom (e.g., S, Se, or Te). In some embodiments, the release layer comprises MoS2 or WSe2.
In one example, release layer 130 is prepared on another substrate and then disposed on GaN layer 110. In another example, release layer 130 can be formed directly on GaN layer 110. In some embodiments, the 2D material can be a single layer of graphene (e.g., a single layer of crystalline graphene) In certain embodiments, the 2D material can be continuous across its lateral dimensions. More information about forming releaser layer 130 can be found, for example, in PCT Patent Application No. PCT/US2016/050701, filed September 8, 2016, published as International Patent Application Publication No. WO 2017/044577 on March 16, 2017, and entitled“SYSTEMS AND METHODS FOR
GRAPHENE BASED LAYER TRANSFER,” which is incorporated herein by reference in its entirety.
FIGS. 2A-2C illustrate a method 200 of fabricating GaN layers using a GaN template. The GaN template includes a first GaN layer 210 and a release layer 220 (which can comprise graphene) disposed on first GaN layer 210. This template can be the same or substantially similar to GaN template 140 shown in FIG. 1C and fabricated via method 100 illustrated in FIGS. 1A-1C. In FIG. 2A, a second GaN layer 230 is formed on release layer 220 via remote epitaxy. The epitaxial growth of second GaN layer 230 can be seeded by first GaN layer 210 underneath release layer 220. The seeding of second GaN layer 230 by first GaN layer 210 (e.g., to produce a second GaN layer 230 that is epitaxially matched with first GaN layer 210) can occur, in accordance with certain embodiments, even when there is not direct contact between second GaN layer 230 and first GaN layer 210. (Such contact might occur, for example, when there are holes in release layer 220.) For example, in accordance with certain embodiments, first GaN layer 210 may have a potential field (e.g., created by van der Waals forces and/or other atomic or molecular forces) and release layer 220 may be so thin (e.g., in the case of a monolayer of continuous graphene) that the potential field of first GaN layer 210 reaches beyond release layer 220 an interacts with the region within which second GaN layer 230 is formed. As a result, in some embodiments, the potential field from first GaN layer 210 affects the growth of second GaN layer 230. In some such embodiments, the crystallographic orientations of first GaN layer 210 and second GaN layer 230 can be matched.
In FIG. 2B, in accordance with some embodiments, a handler layer 240 (also referred to as a mechanical handler) is formed on second GaN layer 230. Handler layer 240 is employed, in some embodiments, to exfoliate second GaN layer 230 precisely at the interface between second GaN layer 230 and release layer 220. In one example, handler layer 240 can include, for example, a metal stressor (e.g., a nickel stressor). In addition, an optional tape layer can be formed on the metal stressor to facilitate the transfer process. In another example, handler layer 240 can include poly A1N. In yet another example, handler layer 240 can include various other materials, such as glass, tape (e.g., heat release tape), polymer, and/or a silicon substrate, among others.
In FIG. 2C, in accordance with certain embodiments, the exfoliated second GaN layer 230 is disposed on a second substrate 250 (also referred to as a substrate handler) for further processing, such as forming a functional device. Second substrate 250 can be employed for various functions. For example, second substrate 250 can be used to as a vehicle to transport GaN layer 230. In another example, second substrate 250 can be used as a temporary holder of GaN layer 230. Second substrate 250 can be either flexible or rigid.
Handler layer 240 can also be removed, exposing the surface of second GaN layer 230 for further processing. After second GaN layer 230 is removed from the GaN template (i.e., the platform including the first GaN layer 210 and the release layer 220), the GaN template can be reused to fabricate additional GaN layers (e.g., a third GaN layer, a fourth GaN layer, and so on), as illustrated by reuse step 260 in FIGS. 2A-2B.
FIGS. 3A-3D illustrate a method 300 of fabricating semiconductor devices using a jet sprayed substrate handler 350. Method 300 includes, in accordance with certain
embodiments, forming a second GaN layer 330 (e.g., epitaxially, such as via remote epitaxy) on a release layer 320 (e.g., graphene), which is disposed on a first GaN layer 310, as shown in FIG. 3A. In FIG. 3B, a handler layer 340 is formed on second GaN layer 330 to exfoliate second GaN layer 330 from release layer 320. After the exfoliation, the GaN template, including first GaN layer 310 and release layer 320, can be reused to fabricate additional GaN layers, as illustrated by reuse step 360 in FIGS. 3A-3B.
FIG. 3C shows handler layer 340 and the exfoliated second GaN layer 330 disposed on a substrate handler 350. Substrate handler 350 can include, for example, GaN or A1N that is formed via a jet spray. In practice, this jet spray method can be convenient because the jet spray method can create a thick layer within a short period of time. In addition, substrate handler 350 formed by jet spray can have good heat conduction. FIG. 3D shows that handler layer 340 is removed from second GaN layer 330, thereby exposing the surface of second GaN layer 330 for further processing.
FIGS. 4A-4D illustrate a method 400 of fabricating semiconductor devices using a GaN template and sputtered GaN or A1N as a handler. Method 400 includes, in accordance with certain embodiments, forming a second GaN layer 430 (e.g., epitaxially, such as via remote epitaxy) on a release layer 420 (e.g., graphene), which is disposed on a first GaN layer 410, as shown in FIG. 4A. In FIG. 4B, in accordance with some embodiments, an interfacial layer 460 is formed on second GaN layer 430, and a first handler layer 440a is formed on interfacial layer 460. Interfacial layer 460 can include, for example, sputtered GaN or A1N. First handler layer 440a and interfacial layer 460 can facilitate the exfoliation of second GaN layer 430 from release layer 420. After the exfoliation, the GaN template, including first GaN layer 410 and release layer 420, can be reused to fabricate additional GaN layers, as illustrated by reuse step 480 in FIGS. 4A-4B. In FIG. 4C, in accordance with certain embodiments, a second handler layer 440b is formed on second GaN layer 430 and is employed to transfer interfacial layer 460 and second GaN layer 430 to a foreign substrate 450, which can be the same as or similar to the substrate handlers described herein.
Interfacial layer 460 is, in some embodiments, in contact with foreign substrate 450 to facilitate bonding between second GaN layer 430 and foreign substrate 450. In FIG. 4D, in accordance with some embodiments, second handler layer 440b is removed, exposing second GaN layer 430 for further processing.
In some examples, handler layer 440a can include poly A1N, and interfacial layer 460 can include amorphous A1N so as to bond second GaN layer 430 with handler layer 440a.
FIGS. 5A-5D illustrate a method 500 of fabricating semiconductor devices using sputtered GaN or A1N as a host substrate. Method 500 includes, in accordance with certain embodiments, and as shown in FIG. 5A, forming a second GaN layer 530 (e.g., epitaxially, such as via remote epitaxy) on a release layer 520 (e.g., graphene), which is disposed on a first GaN layer 510. In FIG. 5B, in accordance with some embodiments, a host substrate 540 is formed on second GaN layer 530. Host substrate 540 can include sputtered GaN or A1N. The thickness of host substrate 540 can be about 1 pm to about 300 pm (e.g., about 1 pm, about 2 pm, about 3 pm, about 5 pm, about 10 pm, about 20 pm, about 30 pm, about 50 pm, about 100 pm, about 200 pm, or about 300 pm, including any values and sub ranges in between). In FIG. 5C, in accordance with certain embodiments, a handler layer 550 is formed on host substrate 540 and is employed to exfoliate second GaN layer 530 from release layer 520. After the exfoliation, the GaN template, including first GaN layer 510 and release layer 520, can be reused to fabricate additional GaN layers, as illustrated by reuse step 580 in FIGS. 5A-5C. In FIG. 5D, in accordance with some embodiments, handler layer 550 is removed, leaving second GaN layer 530 attached to host substrate 540 to form a platform 560 for further processing.
FIG. 6 shows a schematic of a substrate handler 600 for fabricating semiconductor devices. Handler 600 includes a substrate 610 and an optional intermediate layer 620.
Substrate 610 can include, for example, silicon, sapphire, glass, stainless steel, sputtered A1N, porous Si02, and/or electroplate metal, among others. The intermediate layer 620 can include, for example, sputtered A1N. Intermediate layer 620 can be employed to manage the strain force between substrate 610 and any GaN layer disposed on handler 600. In addition, intermediate layer 620 can have a good surface quality so as to receive the GaN layer disposed thereon. Substrate handler 600 can be used for mechanical handling of GaN layers fabricated via remote epitaxy (e.g., second GaN layers 230, 330, 430, and/or 530). Substrate handler 600 can also be used as a heat and/or electrical conductor. Optional intermediate layer 620 can be used for strain management, as a back diffusion barrier, and/or for surface planarization.
While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.
The above-described embodiments can be implemented in any of numerous ways.
For example, embodiments of designing and making the technology disclosed herein may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.
Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.
Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in another audible format.
Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.
The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.
In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media can be transportable, such that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.
The terms“program” or“software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.
Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.
Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationships between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationships between data elements.
Also, various inventive concepts may be embodied as one or more methods, of which examples have been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
The indefinite articles“a” and“an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean“at least one.”
The phrase“and/or,” as used herein in the specification and in the claims, should be understood to mean“either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with“and/or” should be construed in the same fashion, i.e.,“one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the“and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to“A and/or B”, when used in conjunction with open-ended language such as“comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims,“or” should be understood to have the same meaning as“and/or” as defined above. For example, when separating items in a list,“or” or“and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as“only one of’ or“exactly one of,” or, when used in the claims,“consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term“or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e.,“one or the other but not both”) when preceded by terms of exclusivity, such as“either,”“one of,”“only one of,” or “exactly one of.”“Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.
As used herein in the specification and in the claims, the phrase“at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase“at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example,“at least one of A and B” (or, equivalently,“at least one of A or B,” or, equivalently“at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another
embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one,
B (and optionally including other elements); etc.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,”“including,”“carrying,”“having,”“containing,”“involving,”“holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases“consisting of’ and“consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

1. A method of fabricating a semiconductor device, the method comprising:
forming a first GaN layer on a first substrate;
removing the first substrate;
forming a release layer on the first GaN layer so as to form a GaN template, the release layer comprising a two-dimensional (2D) material;
forming a second GaN layer on the GaN template via epitaxial growth; and transferring the second GaN layer from the GaN template to a second substrate.
2. The method of claim 1, wherein forming the first GaN layer comprises forming the first GaN layer via hydride vapor phase epitaxy (HVPE).
3. The method of any one of claims 1-2, wherein forming the release layer comprises disposing the release layer on the first GaN layer.
4. The method of any one of claims 1-3, wherein forming the release layer comprises forming a graphene layer.
5. The method of any one of claims 1-4, wherein transferring the second GaN layer comprises:
forming a handler layer on the second GaN layer;
exfoliating the second GaN layer from the GaN template using the handler layer; disposing the handler layer and the second GaN layer on the second substrate; and removing the handler layer from the second GaN layer.
6. The method of claim 5, further comprising:
forming an interfacial layer between the handler layer and the second GaN layer so as to bond the second GaN layer with the handler layer.
7. The method of claim 6, wherein forming the interfacial layer comprises forming an A1N layer, and the handler layer comprises poly A1N.
8. The method of claim 6, wherein forming the interfacial layer comprises forming an amorphous A1N layer via sputtering.
9. The method of claim 6, wherein forming the interfacial layer comprises depositing a GaN layer or an A1N layer on the second GaN layer before forming the handler layer on the interfacial layer.
10. The method of any one of claims 1-9, further comprising:
forming the second substrate using a jet spray, the second substrate comprising at least one of GaN or A1N.
11. The method of any one of claims 1-10, further comprising:
after transferring the second GaN layer, forming a third GaN layer on the GaN template.
12. The method of any one of claims 1-11, wherein, during the forming of the second GaN layer on the GaN template via epitaxial growth, the second GaN layer is not in direct contact with the first GaN layer.
13. The method of any one of claims 1-11, wherein, during the forming of the second
GaN layer on the GaN template via epitaxial growth, a potential field from the first GaN layer reaches beyond the release layer and affects the growth of second GaN layer.
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