WO2020065535A1 - Integrated plasmons with thin film transistor (tft) device for molecular biosensing - Google Patents

Abstract

Embodiments of the invention are directed to a device that combines Localized Surface Plasmon Resonance (LSPR) nanostructures with transduction methods, such as an integrated thin film transistor (TFT), enabling direct detection and efficient amplification of plasmon energy for biomolecular sensing.

Description

INTEGRATED PLASMONS WITH THIN FILM TRANSISTOR (TFT) DEVICE

FOR MOLECULAR BIOSENSING

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 62/735,326 filed September 24, 2018, which is hereby incorporated by reference in its entirety

BACKGROUND

Field of the Invention

[0002] The invention generally concerns thin film transistors for use in biosensors. In particular the biosensor is configured to amplify localized surface plasmon.

Description of the Related Art

[0003] The detection of biomolecular interactions is critical for medical and wellness monitoring applications. Optical detection methods such as fluorescence and localized surface plasmon resonance (LSPR) techniques are used to detect biomolecular binding to a sensor. Localized Surface Plasmon Resonance (LSPR) can emanate from the interaction of light with nanosized noble metallic nanostructures in which confined free electrons oscillate with the same frequency as the incident radiation and eventually enter resonance, giving rise to intense, highly localized electromagnetic fields. Such nanostructures have been proposed as efficient light manipulating components that can be integrated into different devices including light emitting diodes and photovoltaic cells to increase the efficiency of conventional architectures considerably.

[0004] Recent investigations have shown that plasmonic nanostructures can also be utilized to convert collected light directly into electrical energy by generating hot electrons. After light interacts with metallic nanostructures generating LSPR excitation, the resulting plasmons can decay, transferring their accumulated energy to electrons in the conduction band of an adjacent semiconducting material. This process produces highly energetic electrons, also known as‘hot electrons’ that can escape from the plasmonic nanostructures and be collected by, for example, a semiconductor in a photocatalytic solar cell device. This novel approach for solar energy conversion opens up a way to realize photocatalytic devices whose performances may rival, or even exceed, those of conventional devices. However, there are difficulties and limitations to integrating this technology into other emerging technologies for biosensing, such as sufficient efficiency and costs of devices. The structural and chemical properties of the materials employed need to be developed in order to achieve better efficiencies while keeping fabrication costs low.

[0005] Furthermore, in optical detection systems the observed transmittance or reflection is usually affected by the medium surrounding the nanostructures, which can lead to a false read- out. Noteworthy to mention for the use optical detection systems is also the complexity of required optical components, which makes the cost of utilizing optical sensors not cost- effective when compared with other available technologies.

[0006] There remains a need for devices and materials designed to provide an efficient device capable of detecting biomolecules and the like.

SUMMARY

[0007] Embodiments of the invention introduce a combination of Localized Surface Plasmon Resonance (LSPR) nanostructures with transduction methods such as an integrated thin film transistor (TFT) that enables direct detection and efficient amplification of plasmon energy for biomolecular sensing. In particular aspects a single integrated thin film flexible sensor device is described that uses electrical current operation mode for its readout. Aspects of the invention addresses a major technical challenge inherent to the use of optical based methods for trace molecular detection of biomarkers: the facile integration the Localized Surface Plasmon Resonance (LSPR) sensor into a nanofabricated chip. The integrated plasmon-TFT sensor system described herein solves the above described problems providing a platform for next generation biosensing technologies and providing for at least: (i) the use of label free sensing mechanism with high sensitivity to detect molecular binding of any specimen in real-time and at very low concentration; (ii) the detection of the plasmon shift electronically, due to optoelectronic amplification systems used in conjunction with ultra-high speed data processing; (iii) the facile integration of device fabrication to the current bioelectronics and optical technologies; and (iv) the realization of miniaturized sensor for Point of Care (POC) needs.

[0008] Embodiments of the invention are directed to an integrated plasmonic Thin Film Transistor (TFT) device for biosensing applications and the method of producing the same. The device described herein can effectively detect targets and enhance the sensitivity of the biosensor by amplifying the localized surface plasmon. The device can be fabricated at low processing temperature, making it amenable to be easily integrated on both rigid and flexible plastic substrates. It also allows the deployment of aptly surface functionalized plasmonic nanostructures for broader molecular materials detection capability with enhanced selectivity and sensitivity of the proposed biosensor. Using microfluidics and selective surface functionalization, these devices can be used for multiple biomarker sensing applications.

[0009] Certain embodiments are directed to a sensor or a device comprising a sensor, the sensor having (a) a substrate layer; (b) a gate electrode layer deposited on the substrate layer; (c) a gate insulator layer deposited on the gate electrode layer covering at least a portion of the gate electrode layer; (d) a channel or semiconductor layer deposited on the gate insulator layer; (e) a source-drain electrode layer deposited on the channel layer, wherein the source-drain electrode layer covers a portion of the semiconductor layer; (f) an encapsulation layer forming a well between source and drain portions, with the well having a floor formed by the channel layer and the well configured to receive or contain plasmonic nanostructures; and (g) plasmonic nanostructures operatively positioned on or integrated with the semiconductor layer in the well formed in the source-drain layer.

[0010] Certain embodiments are directed to a sensor or a device comprising a sensor, the sensor having (a) a substrate layer; (b) a gate electrode layer deposited on the substrate layer; (c) a gate insulator layer deposited on the gate electrode layer covering at least a portion of the gate electrode layer; (d) a channel or semiconductor layer deposited on the gate insulator layer; (e) a source-drain electrode layer deposited on the channel layer, wherein the source-drain electrode layer covers a portion of the semiconductor layer; (f) plasmonic nanostructures operatively positioned or integrated on a portion of the semiconductor layer; (g) an encapsulation layer material deposited onto the source drain electrode layer forming an encapsulation layer forming a well having a floor formed by the plasmonic nanostructure and a wall formed by the encapsulation layer.

[0011] The substrate can be a plastic substrate, a glass substrate, or a silicon substrate. In certain aspects the substrate is a flexible substrate, a flexible substrate is understood to be a substrate that can be bent without breaking or cracking upon application of a bending force, e.g., 1 to 10 Newtons. The deformation or bend can be reversible and of a plastic nature. The flexibility of the substrate can be the result of choice of material and/or by geometry of the substrate, for example, a thin elongate substrate. In certain aspects the substrate is or includes PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PEI (polyethylenimine), PDMS (polydimethylsiloxane), PMMA (polymethylmethacrylate), PC (polycarbonate), COC (cyclic olefin copolymer), PA (polyamide), PE (polyethylene), PP (polypropylene), PPE (polyphenylene ether), PS (polystyrene), POM (polyoxymethylene), PEEK (polyetheretherketone), PTFE (polytetrafluoroethylene), PVC (polyvinylchloride), PVDF (polyvinylidene fluoride), PBT (polybutyleneterephthalate), FEP (fluorinated ethylenepropylene), or PFA (perfluoralkoxyalkane).

[0012] In certain aspects, the gate electrode layer can be a metal film, a conducting polymer film, a doped silicon conducting film, or a transparent conducting oxide, such as Al-ZnO, Ga- ZnO, ITO, Sn02, F-Sn02. The gate layer can be or include aluminum, gold, molybdenum, titanium, chromium, indium tin oxide, conductive polymers, or combinations thereof.

[0013] In certain aspects, the gate insulator layer is or can include an inorganic material film, an organic polymer film, or an organic-inorganic composite film. The insulator layer can be or includes silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, barium titanate, barium zirconium titanate, polyesters, polycarbonates, poly(vinyl phenol), polyimides, polystyrene, polymethacrylates, polyacrylates, epoxy resin, or combinations thereof. In certain aspects, the gate insulator layer is or is about 25, 50, 75, or 100 to, 100, 125, 150, or 200 nm thick. In particular aspects the insulator layer is 25 to 200 nm thick, 50 to 200 nm thick, 75 to 200 nm thick, 100 to 200 nm thick, 25 to 100 nm thick, 25 to 125 nm thick, 25 to 150 nm thick, 50 to 100 nm thick, 50 to 125 nm thick, 50 to 150 nm thick, 75 to 100 nm thick, 75 to 125 nm thick, 75 to 150 nm thick, 100 to 125 nm thick, or 100 to 150 nm thick, including all values and ranges there between.

[0014] In certain aspects, the channel or semiconductor layer is an inorganic or organic semiconducting material. The semiconducting material is or can include a zinc oxide (ZnO), zinc indium oxide (IZO) or indium gallium zinc oxide (IGZO), zinc tin oxide, or any oxide semiconducting material having at least In, Zn, Sn, and Ga, acene, perylene, fullerene, oligothiophenes, polythiophenes, polypyrrole, poly-p-phenylenes, poly-p-phenylvinylidenes, naphthalenedicarboxylic dianhydrides, naphthalene-bisimides, polynaphthalenes, phthalocyanines, or substituted derivatives thereof. The semiconducting layer can be about 5, 10, 15, 20, or 25 to 30, 35, 40, 45, or 50 nm thick. In particular aspects the semiconducting layer is or is about 5 to 50 nm thick, 5 to 45 nm thick, 5 to 40 nm thick, 5 to 35 nm thick, 5 to 30 nm thick, 10 to 50 nm thick, 10 to 45 nm thick, 10 to 40 nm thick, 10 to 35 nm thick, 10 to

30 nm thick, 15 to 50 nm thick, 15 to 45 nm thick, 15 to 40 nm thick, 15 to 35 nm thick, 15 to

30 nm thick, 20 to 50 nm thick, 20 to 45 nm thick, 20 to 40 nm thick, 20 to 35 nm thick, 20 to

30 nm thick, 25 to 50 nm thick, 25 to 45 nm thick, 25 to 40 nm thick, 25 to 35 nm thick, or 25 to 30 nm thick, including all values and ranges there between. [0015] In certain aspects, the source-drain layer is or can include titanium, gold, nickel, aluminum, chromium, molybdenum, platinum, a combination of them, transparent conducting oxides or a conducting polymer(s). In particular aspects, the source-drain layer is or is about 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 to 110, 120, 130, 140, 150, 160, 170, 180, 190, or 200 nm thick. In particular aspects the source-drain layer is 20 to 110, 20 to 120, 20 to 130, 20 to 140, 20 to 150, 20 to 160, 20 to 170, 20 to 180, 20 to 190, 20 to 200, 30 to 110, 30 to 120, 30 to 130, 30 to 140, 30 to 150, 30 to 160, 30 to 170, 30 to 180, 30 to 190, 30 to 200, 40 to 110, 40 to 120, 40 to 130, 40 to 140, 40 to 150, 40 to 160, 40 to 170, 40 to 180, 40 to 190, 40 to 200, 50 to 110, 50 to 120, 50 to 130, 50 to 140, 50 to 150, 50 to 160, 50 to 170, 50 to 180, 50 to 190, 50 to 200, 60 to 110, 60 to 120, 60 to 130, 60 to 140, 60 to 150, 60 to 160, 60 to 170, 60 to 180, 60 to 190, 60 to 200, 70 to 110, 70 to 120, 70 to 130, 70 to 140, 70 to 150, 70 to 160, 70 to 170, 70 to 180, 70 to 190, 70 to 200, 80 to 110, 80 to 120, 80 to 130, 80 to 140, 80 to 150, 80 to 160, 80 to 170, 80 to 180, 80 to 190, 80 to 200, 90 to 110, 90 to 120, 90 to 130, 90 to 140, 90 to 150, 90 to 160, 90 to 170, 90 to 180, 90 to 190, 90 to 200, 100 to 1 10, 100 to 120, 100 to 130, 100 to 140, 100 to 150, 100 to 160, 100 to 170, 100 to 180, 100 to 190, 100 to 200 nm thick, including all values and ranges there between.

[0016] In certain aspects, the plasmonic nanostructures are nanowires, nanorods, nano- triangles, nanocubes, nanoprisms and/or nanosponges. The plasmonic nanostructures can include or be made of a metal or transparent conducting oxide nano structures. In certain aspects, the plamonsic nanostructure includes silver, gold, aluminum, copper, platinum, palladium, and/or nickel Al-doped ZnO, Ga-doped ZnO, indium tin oxide nanoparticles or nanostructures. The plasmonic nanostructure(s) can have a thickness in at least one dimension of about 1, 10, 15, 20, 25 to 30, 35, 40, 45, 50 nm in diameter. In particular aspects the plasmonic nanostructure(s) have a thickness in at one dimension of 1 to 10, 10 to 30, 15 to 35, 20 to 40, 25 to 45, 30 to 50, 15 to 30, 15 to 35, 15 to 40, 15 to 45, 15 to 50, 20 to 30, 20 to 35, 20 to 40, 20 to 45, 20 to 50, 25 to 30, 25 to 35, 25 to 40, 25 to 45, or 25 to 50 nm in diameter.

[0017] A method of making a plasmonic thin film transistor sensor comprising: (a) depositing a layer of gate electrode material onto a substrate forming a gate electrode layer; (b) depositing a layer of gate insulator material onto the gate electrode layer forming a gate insulator layer; (c) depositing a layer of semiconducting material on the gate insulator layer forming a channel layer; (d) depositing source drain layer materials on the channel layer forming a source drain electrode layer; (e) depositing an encapsulation layer material onto the source drain electrode layer forming an encapsulation layer; and (f) forming or attaching plasmonic nanostructures in the well on or integrated into the semiconductor layer. The plasmonic thin film transistor structure can be configured to provide an electrical read out mode. Use and delivery of nanoparticles to TFT structure enhanced overall device stability, lower- cost, and lower processing temperatures. An integrated micro-fluid channel can be included for sample delivery/consumption and device sensitivity. Final flexible sensor can be configured to provide for a disposable patch type biosensor.

[0018] A method of making a plasmonic thin film transistor sensor comprising: (a) depositing a layer of gate electrode material onto a substrate forming a gate electrode layer; (b) depositing a layer of gate insulator material onto the gate electrode layer forming a gate insulator layer; (c) depositing a layer of semiconducting material on the gate insulator layer forming a channel layer; (d) depositing source drain layer materials on the channel layer forming a source drain electrode layer; (e) forming or attaching or integrating the plasmonic nanostructures on a portion of the semiconductor layer; and (f) depositing an encapsulation layer material onto the source drain electrode layer forming an encapsulation layer forming a well having a floor formed by the plasmonic nanostructure and a wall formed by the encapsulation layer. In some aspects, the method can include a step of depositing a protection layer material over at least a portion of a surface of the semiconductor layer to form a protection layer, prior to the plasmonic nanostructure formation, and forming or attaching or integrating the plasmonic nanostructures on a portion of the protection layer.

[0019] One embodiment, embodiment 1, is directed to a sensor comprising: (a) a substrate layer; (b) a gate electrode layer deposited on the substrate layer; (c) a gate insulator layer deposited on the gate electrode layer covering at least a portion of the gate electrode layer; (d) a channel or semiconductor layer deposited on the gate insulator layer; (e) a source-drain electrode layer deposited on the channel layer, wherein the source-drain electrode layer covers a portion of the semiconductor layer; (f) an encapsulation layer forming a well between source and drain portions, with the well having a floor formed by the channel layer and the well configured to receive or contain plasmonic nanostructures; and (g) plasmonic nanostructures operatively positioned on or integrated with the semiconductor layer in the well formed in the source-drain layer.

[0020] Embodiment 2 is directed to a sensor of embodiment 1, wherein the substrate is a plastic substrate, a glass substrate, or a silicon substrate. [0021] Embodiment 3 is directed to the sensor of embodiment 1, wherein the substrate is a flexible substrate.

[0022] Embodiment 4 is directed to any one of embodiments 1 to 3, wherein the substrate comprises PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PEI (polyethylenimine), PDMS (poly dimethyl siloxane), PMMA (polymethylmethacrylate), PC (polycarbonate), COC (cyclic olefin copolymer), PA (polyamide), PE (polyethylene), PP (polypropylene), PPE (polyphenylene ether), PS (polystyrene), POM (polyoxymethylene), PEEK (polyetheretherketone), PTFE (polytetrafluoroethylene), PVC (polyvinylchloride), PVDF (polyvinylidene fluoride), PBT (polybutyleneterephthalate), FEP (fluorinated ethylenepropylene), or PFA (perfluoralkoxyalkane).

[0023] Embodiment 5 is directed to any one of embodiments 1 to 4, wherein the gate electrode layer is a metal film, a conducting polymer film, a doped silicon conducting film, or a transparent conducting oxide, such as Al-ZnO, Ga-ZnO, Hf-ZnO, ITO, Sn02, F-Sn02.

[0024] Embodiment 6 is directed to any one of embodiments 1 to 5, wherein the gate layer comprises aluminum, gold, chromium, titanium, molybdenum, indium tin oxide, conductive polymers or combination thereof.

[0025] Embodiment 7 is directed to any one of embodiments 1 to 6, wherein the gate insulator layer is an inorganic material film, an organic polymer film, or an organic-inorganic composite film.

[0026] Embodiment 8 is directed to any one of embodiments 1 to 7, wherein the insulator layer comprises silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, barium titanate, barium zirconium titanate, polyesters, polycarbonates, poly(vinyl phenol), polyimides, polystyrene, polymethacrylates, polyacrylates, epoxy resin, or combinations thereof.

[0027] Embodiment 9 is directed to any one of embodiments 1 to 8, wherein the gate insulator layer is about 25 to 200 nm thick.

[0028] Embodiment 10 is directed to any one of embodiments 1 to 9, wherein the channel or semiconductor layer is an inorganic or organic semiconducting material.

[0029] Embodiment 11 is directed to any one of embodiments 1 to 10, wherein the semiconducting material is typically inorganic materials usch as zinc oxide (ZnO), zinc indium oxide (IZO) or indium gallium zinc oxide (IGZO), zinc tin oxide, or any oxide semiconducting material having at least In, Zn, Sn, and Ga, or organics such as acene, perylene, fullerene, oligothiophenes, polythiophenes, polypyrrole, poly-p-phenylenes, poly-p-phenylvinylidenes, naphthalenedicarboxylic dianhydrides, naphthalene-bisimides, polynaphthalenes, phthalocyanines, or substituted derivatives thereof.

[0030] Embodiment 12 is directed to any one of embodiments 1 to 11, wherein the semiconducting layer is about 5 to 50 nm.

[0031] Embodiment 13 is directed to any one of embodiments 1 to 12, wherein the source- drain layer is chromium, titanium, gold, nickel, aluminum, molybdenum, platinum, a combination of them, transparent conducting oxides or a conducting polymer(s).

[0032] Embodiment 14 is directed to any one of embodiments 1 to 13, wherein the source- drain layer is about 20 to 200 nm thick.

[0033] Embodiment 15 is directed to any one of embodiments 1 to 14, wherein the plasmonic nanostructures are nanowires, nanorods, nano-triangles, nanocubes, nanoprisms and/or nanosponges.

[0034] Embodiment 16 is directed to any one of embodiments 1 to 15, wherein the plasmonic nanostructures comprise a metal or transparent conducting oxide nanostructures.

[0035] Embodiment 17 is directed to any one of embodiments 1 to 16, wherein the plasmosic nanostructure comprise silver, gold, aluminum, copper, platinum, palladium, and/or nickel Al-doped ZnO, Ga-doped ZnO, indium tin oxide nanoparticles or nanostructures.

[0036] Embodiment 18 is directed to any one of embodiments 1 to 17, wherein the plasmonic nanostructure have a thickness in at least one dimension of about 1 to 50 nm, or 1 to 15 nm, or 1 to 25 nm, or 10 to 50 nm in diameter.

[0037] Embodiment 19 is directed to any one of embodiments 1 to 18, further comprising one or more microfluidic channels fluidically coupled to the encapsulation well.

[0038] Embodiment 20 is directed to any one of embodiments 1 to 19, wherein the encapsulation layer is formed of encapsulation layer material and the encapsulation layer material contains AI2O3, HFO2, silicon nitride, silicon dioxide, SU-8, parylene, PVP, PVDF or any combination thereof.

[0039] Embodiment 21 is directed to any one of embodiments 1 to 20, wherein the sensor further includes a protection layer over at least a portion of a surface of the semiconductor layer in the well and the plasmonic nanostructures are operatively positioned on or integrated with the protection layer.

[0040] Embodiment 22 is directed to embodiment 21, wherein the plasmonic nanostructures contact a surface of the protection layer.

[0041] Embodiment 23 is directed to any one of embodiments 21 or 22, wherein the protection layer is formed of protection layer material and the protection layer material contains AI2O3, Fifth, silicon nitride, silicon dioxide, parylene, PVP, PVDF or any combination thereof.

[0042] Embodiment 24 is directed to embodiment 23, wherein the encapsulation layer material contains different material than the protection layer material.

[0043] Embodiment 25 is directed to a method of making a plasmonic thin film transistor sensor comprising: (a) depositing a layer of gate electrode material onto a substrate forming a gate electrode layer; (b) depositing a layer of gate insulator material onto the gate electrode layer forming a gate insulator layer; (c) depositing a layer of semiconducting material on the gate insulator layer forming a channel layer; (d) depositing source drain layer materials on the channel layer forming a source drain electrode layer; (e) forming or attaching or integrating the plasmonic nanostructures on a portion of the semiconductor layer; and (f) depositing an encapsulation layer material onto the source drain electrode layer forming an encapsulation layer forming a well having a floor formed by the plasmonic nanostructure and a wall formed by the encapsulation layer.

[0044] Embodiment 26 is directed to embodiment 25, further including a step of depositing a protection layer material over at least a portion of a surface of the semiconductor layer to form a protection layer, prior to the plasmonic nanostructure formation, and forming or attaching or integrating the plasmonic nanostructures on a portion of the protection layer.

[0045] Other embodiments of the invention are discussed throughout this application. Any embodiment discussed with respect to one aspect of the invention applies to other aspects of the invention as well and vice versa. Each embodiment described herein is understood to be embodiments of the invention that are applicable to all aspects of the invention. It is contemplated that any embodiment discussed herein can be implemented with respect to any method or composition of the invention, and vice versa. Furthermore, compositions and kits of the invention can be used to achieve methods of the invention. [0046] The use of the word“a” or“an” when used in conjunction with the term“comprising” in the claims and/or the specification may mean“one,” but it is also consistent with the meaning of“one or more,”“at least one,” and“one or more than one.”

[0047] Throughout this application, the term“about” is used to indicate that a value includes the standard deviation of error for the device or method being employed to determine the value.

[0048] The use of the term“or” in the claims is used to mean“and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and“and/or.”

[0049] As used in this specification and claim(s), the words“comprising” (and any form of comprising, such as“comprise” and“comprises”),“having” (and any form of having, such as “have” and“has”),“including” (and any form of including, such as“includes” and“include”) or“containing” (and any form of containing, such as“contains” and“contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps.

Other objects, features and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and the specific examples, while indicating specific embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

DESCRIPTION OF THE DRAWINGS

[0050] The following drawings form part of the present specification and are included to further demonstrate certain aspects of the present invention. The invention may be better understood by reference to one or more of these drawings in combination with the detailed description of the specification embodiments presented herein.

[0051] FIGS. 1A-1B illustrates the schematic structure of a thin film transistor integrated with plasmonic nanostructure, where all the components are deposited on top of a suitable substrate using thin film deposition techniques.

[0052] FIGS. 2A-2B illustrates an expected response of Plasmonic-TFT integrated device structure with respect to biomarker interactions.

[0053] FIGS. 3A-3B illustrates plasmon nanoparticle fabrication and their integration into the TFT device. [0054] FIGS. 4A- 4B illustrates optical image of a TFT before and after gold nano-island formation. FIG. 4C illustrates SEM image of the selected region in the channel area of the TFT, which clearly shows the formation of gold nano-islands after annealing the 3nm gold film at 160 °C for 2 hours in air environment.

[0055] FIGS. 5 illustrates measured drain current for IGZO TFTs with and without gold nano-islands in the channel area under dark and red light illumination.

[0056] FIG. 6 illustrates schematic of IGZO TFTs (A) with and (B) without protection layer on top of the semiconductor layer. FIG. 6C illustrates performance of a gold nano-island and SU-8 integrated IGZO TFT without FKO2 protection layer on top of the IGZO semiconductor layer. FIG. 6C illustrates performance of a gold nano-island and SU-8 integrated IGZO TFT with ALD deposited 1 nm HTCte protection layer on top of the IGZO semiconductor layer.

[0057] FIG. 7A illustrates optical image of a gold nano-island integrated TFT device with SU-8 protection layer and MPBA treatment. FIG. 7B illustrates Raman spectra obtained from different locations as indicated in FIG. 7A.

[0058] FIG. 8A illustrates output characteristic of gold nano-island and 4-MPBA integrated TFT based sensor device with different glucose concentrations. FIG. 10B illustrates plot of extracted drain current (at VD=2V) versus glucose concentration.

DESCRIPTION

[0059] The following discussion is directed to various embodiments of the invention. The term“invention” is not intended to refer to any particular embodiment or otherwise limit the scope of the disclosure. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

[0060] Surface plasmon resonance (SPR) sensors are widely used in biomedical research offering extreme sensitives and robust operation. For example, GE’s Biacore for healthcare is a versatile system for high-quality characterization of molecular interactions, from ions to viruses. SPR platforms have been used for comprehensive characterization of molecular interactions in terms of kinetics, affinity, specificity, comparability, concentration, immunogenicity, and thermodynamics. [0061] Ligand binding is used to study the interactions of molecules. If the plasmonic coupling occurs in a confined zero dimensional structure ( e.g ., nanoparticles), it is called as localized surface plasmon resonance (LSPR) and this type of plasmon has been widely studied in a broad range of applications. The distinct property of such LSPR is the tunability and sharp absorption/scattering peaks depending on the shape and sizes of the metal nanostructures. Moreover, LSPR shows stable optical property under temperature fluctuations, which makes LSPR a better candidate for specific applications such as biosensors and nanoscale spectroscopy based technologies. These examples employ conventional calorimetric LSPR design, which involves optical detection via monitoring changes of reflectance or transmittance of the plasmonic nanostructures. Recently, a plethora of fabrication techniques and characterization methods have been reported to successfully couple plasmonic effects for use as metamaterials, photovoltaic devices, light modulation, localized heat generation as well as in quantum optics. However, such efforts are lacking coupling of electronic excitations of optical energy via plasmon resonances in conjunction with thin film transistors (TFT) to improve gain in sensitivity and selectivity of the resulting devices in various optoelectronic applications and specifically for biomolecular interactions in biosensors.

[0062] To date surface plasmon resonance is only detected via optical methods such as Raman spectroscopy. Nonetheless, for practical applications, the use of such systems makes their integration into amenable form factors complicated (e.g., wearable devices). Furthermore, the sensing mechanism relies on comparative data analysis (spectra comparison) which is inherently subjective. The lack of a direct sensing mechanism (such as a direct electrical measurement) makes this technique to rely on complicated statistical data analysis and pattern identification.

I. Plasmonic-Thin Film Transistor (TFT)

[0063] A plasmonic-TFT (100) includes a number of layers configured to produce an electronic signal. The layers include (a) a substrate layer (101), (b) a gate electrode layer (102), (c) a gate insulator (103), (d) a semiconductor (104), (e) a source drain electrode layer (105), and (f) an encapsulation layer (106) (for an example see FIG. 1 A and FIG. 1B). In some aspects, the plasmonic-TFT can optionally include a protection layer (108).

A. Substrate Layer

[0064] In certain embodiments a gate electrode layer will be disposed on all or a portion of a substrate surface. The substrate may be formed of a transparent material that allows light to be transmitted. For instance, the substrate may include a plastic substrate, a glass substrate, a ceramic substrate, quartz substrate, and/or a silicon substrate. In particular aspects the substrate is a flexible substrate. In certain aspects, the substrate may be formed of a polymer such as PDMS (polydimethylsiloxane), PMMA (polymethylmethacrylate), PC (polycarbonate), COC (cyclic olefin copolymer), PA (polyamide), PE (polyethylene), PP (polypropylene), PPE (polyphenylene ether), PS (polystyrene), POM (polyoxymethylene), PEEK (polyetheretherketone), PTFE (polytetrafluoroethylene), PVC (polyvinylchloride), PVDF (polyvinylidene fluoride), PBT (polybutyleneterephthalate), FEP (fluorinated ethylenepropylene), and PFA (perfluoralkoxy alkane).

B. Gate Electrode Layer

[0065] A gate electrode layer can be deposited or formed on the surface of a substrate. The gate electrode is composed of an electrically conductive material and can be a thin metal film, a conducting polymer film, a doped silicon conducting film, or the like. Examples of gate electrode materials include but are not restricted to aluminum (Al), gold (Au), chromium (Cr), indium tin oxide (ITO), and conductive polymers such as polystyrene sulfonate-doped poly(3,4-ethylenedioxythiophene) (PSS-PEDOT). A gate electrode layer can be a single-layer or multilayer structure including one or more conductive films of conductive material. In other aspects the conductive material can be molybdenum (Mo), copper (Cu), chromium (Cr), tungsten (W), titanium (Ti), manganese (Mn), tantalum (Ta), niobium (Nb), silver (Ag), platinum (Pt), palladium (Pd), indium (In), nickel (Ni), neodymium (Nd), or an alloy of metals or conductive metal oxide thereof. The gate electrode layer can be deposited or formed on the substrate in a predetermined shape or geometry.

[0066] The gate electrode layer can be formed, deposited, or prepared by one or more of vacuum evaporation, sputtering of metals or conductive metal oxides, conventional lithography and etching, chemical vapor deposition, spin coating, casting or printing, or other deposition processes. The thickness of the gate electrode can range from or from about 10 to about 500 nanometers for metal films and from about 0.5 to about 10 micrometers for conductive polymers. In certain aspects the gate layer is about 20 to 200 nm thick.

C. Gate Insulator Layer

[0067] A gate insulator layer can be deposited or formed on the surface of the gate electrode layer and configured to be in contact with the gate electrode layer, at least a portion of a semiconductor layer, and in some configurations a portion of a source drain electrode. In certain instances the gate insulator layer can also cover or overlay the gate electrode and be in contact with the substrate layer. The gate insulator layer can comprise an inorganic material film, an organic polymer film, or an organic-inorganic composite film. Examples of inorganic materials suitable as the gate insulator/dielectric layer include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, barium titanate, barium zirconium titanate and the like. Examples of suitable organic polymers include polyesters, polycarbonates, poly(vinyl phenol), polyimides, polystyrene, polymethacrylates, polyacrylates, epoxy resin and the like. The thickness of the layer depends on the dielectric constant of the material used and can be, for example, from about 5 nm to about 500 nm or about 10 nm to about 500 nm. The layer may have a conductivity that is, for example, less than about 10-12 Siemens per centimeter (S/cm). The layer can be formed using conventional processes known in the art, including those processes described in forming the gate electrode ( e.g ., vacuum evaporation, sputtering of metals or conductive metal oxides, conventional lithography and etching, chemical vapor deposition, spin coating, casting or printing, or other deposition processes).

D. Channel or Semiconductor Layer

[0068] A semiconductor layer can be deposited or formed on the surface of the gate insulator layer and configured to be in contact with the source-drain electrode layer, at least a portion of an encapsulation layer and nanoparticle structures. The semiconductor layer generally is an inorganic or organic semiconducting material. Examples of inorganic semiconducting materials are zinc oxide (ZnO), tin oxide, indium oxide, zinc indium oxide (IZO) or indium gallium zinc oxide (IGZO), zinc tin oxide, or any oxide semiconducting material having at least In, Zn, Sn, and Ga. Examples of organic semiconductors include but are not limited to acenes, such as anthracene, tetracene, pentacene, and their substituted derivatives, perylenes, fullerenes, oligothiophenes, polythiophenes and their substituted derivatives, polypyrrole, poly-p-phenylenes, poly-p-phenylvinylidenes, naphthalenedicarboxylic dianhydrides, naphthalene-bisimides, polynaphthalenes, phthalocyanines such as copper phthalocyanines or zinc phthalocyanines and their substituted derivatives. In particular, polythiophenes may be used. The polythiophene may be selected from the group consisting of regioregular and regiorandom poly(3-alkylthiophene)s, polythiophenes comprising substituted and unsubstituted thienylene groups, polythiophenes comprising optionally substituted thieno[3,2-b]thiophene and/or optionally substituted thieno[2,3-b]thiophene groups, and polythiophenes comprising non-thiophene based aromatic groups. In one non-limiting aspect, the semiconductor used is a p-type semiconductor. In another exemplary embodiment, the semiconductor is a liquid crystalline semiconductor. The semiconductor layer is from about 5 nm to about 1000 nm or about 5 nm to about 100 nm or about 5 nm to about 50 nm thick. The semiconductor layer can be formed by molecular beam deposition, vacuum evaporation, sublimation, sputtering, atomic layer deposition, blade coating, rod coating, screen printing, stamping, ink jet printing, spin-on coating, dip coating, and the like, and other conventional processes known in the art, including those processes described in forming the gate electrode layer.

E. Source-Drain Electrode

[0069] A source-drain electrode layer can be deposited or formed on the surface of the semiconductor layer and configured to be in contact with an encapsulation layer. The source- drain electrode layer can be configured to allow access to underlying semiconductor layer that can be contacted or coupled to nanostructures. The source and drain (source-drain) electrodes can be fabricated from materials which provide a low resistance ohmic contact to the semiconductor layer. Typical materials suitable for use as source and drain electrodes include those of the gate electrode materials such as gold, nickel, molybdenum, chromium, titanium, aluminum, platinum, transparent conducting oxides, conducting polymers, and conducting inks. The source-drain electrode layer can be or can be about 40 nm to about 1 pm with a more specific thickness being about 100 to about 400 nm. The TFTs of the present disclosure contain a semiconductor channel, e.g., a channel in the source-drain layer providing access to the semiconductor layer. The semiconductor channel width may be, for example, from about 10 pm to about 5 mm with a specific channel width being about 1 pm to about 1 mm. The semiconductor channel length may be, for example, from about 1 pm to about 1 mm with a more specific channel length being from about 5 pm to about 100 pm.

F. Protection layer

[0070] In some aspects, an optional protection layer can be formed or deposited over all or part of a semiconductor layer surface. The protection layer material can be AI2O3, HfCfe, zirconium oxide, titanium oxide, silicon nitride, silicon dioxide, or any other organic materials such as parylene, PVP and PVDF. In some aspects, the protection layer material can be different than the encapsulation layer material. In some aspects, the protection layer can have a thickness of 0.1 nm to 10 nm or 0.1 nm to 1 nm, or at least any one of, equal to any one of, or between any two of 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm and 10 nm. G. Plasmonic Nanostructures

[0071] The semiconductor channels and/or the protection layer over the semiconductor channels can harbor plasmonic nanostructures (107) that are embedded and/or coupled, covalently or non-covalently, and/or directly or indirectly to the semiconductor layer and/or the protection layer over the semiconductor layer and are configured to bind or interact with various target moieties to be detected. “Plasmonic nanostructures” are objects of nanostructured material that support the formation of plasmons, or waves produced by the collective effects of large numbers of electrons disturbed from equilibrium. The geometry and the locations of the plasmonic nanostructures relative to the neighboring semiconductor material can be important. It is envisioned that the photocurrent generated by an active plasmonic element can be significantly enhanced by embedding it in the semiconductor layer and/or in the protection layer over the semiconductor layer , as this permits more efficient transfer between the plasmon-TFT structures. The plasmon-TFT devices are not affected by the solution diffusion factors that might limit the efficiencies of conventional semiconductor- based devices. The size, shape and composition of the plasmonic nanostructures can be adapted, modified, or designed to obtain broad absorption across energy wavelength relevant to biological specimens. The high absorption cross-section of anisotropically diverse plasmonic nanostructures (nanowires, nanorods, and nanosponges) allows the thickness of the active zone to be reduced while maintaining a high plasmon efficiency.

[0072] The terms“nanostructures,”“nanoparticles,”“particles,” and“resonators,” are used interchangeably. The term“irradiate” is used to mean that an object is receiving or is exposed to irradiation. Thus, when a nanostructure is described as being“irradiated” at or with a certain wavelength or frequency, the nanostructure is receiving or is exposed to irradiation with that wavelength or frequency. In addition, the terms“plasmonic resonance” or“plasmon resonance” are used to refer to the wavelength or frequency value at which a nanostructure achieves maximum absorption. Further, when a nanostructure is described as being“neutral,” the nanostructure may be in a state of equilibrium undisturbed by irradiation, or the nanostructure may be neutral during irradiation, if the incident radiation frequency is exactly resonant with the nanostructure.

[0073] The plasmonic nanostructures can be formed by using physical vapor deposition (PVD) techniques, including but not limited to evaporation, sputtering, molecular beam deposition, pulsed LASER deposition. Thin films of conducting metals including but not limited to aluminum, copper, gold, nickel, silver, palladium, platinum can be deposited using PVD techniques. About 1 nm to 25 nm thick metals films can be deposited using PVD techniques and a post formation annealing step in can be used to form the plasmonic nano structures. The plasmonic nanostructures can also be formed in-situ using PVD techniques.

[0074] Solution-drop evaporation approach can be used to fabricate monodisperse close- packed gold nanotriangles (AuNT) or gold nanorods (AuNR) monolayer onto the semiconductor layer and/or protection layer over the semiconductor layer of a device structure. In one non-limiting example, the synthesis of anisotropic gold nanotriangles involve three consecutive steps as described in the literature: first step entails the generation of cetyltriammomium chloride (CTAC) coated Au seeds, followed by fast addition of generated seeds into a final growth solution, and ultimately the purification of the desired products. It is anticipated to produce anisotropic gold nanotriangles (AuNT and gold nanorods (AuNR) with significant tunable sizes and hence improved SERS performance. Both AuNT and AuNR are stable in aqueous solution, and their surface activity can be tailored through surface functionalization with appropriate polymers. For example, polyvinyl pyrrolidone (PVP) coating of plasmonic materials allows the formation of single-nanoparticle monolayer at the air-liquid interface extended over a large surface area. Due to versatility of plasmonic nanostructures in wavelength tunability, this device architecture offers an ultra-wide spectral range that can be used in various applications. Subsequent self-assembly and or binding of label free moieties onto the top TFT gate surface will accelerate for the first time, the realization of the plasmonic-TFT bench-top sensor technology into a portable, miniaturized and in-situ electrical read-out, offering wide-range of relevant biomedical applications.

[0075] Plasmonic nanostructures include, but are not limited to rectangles, circles, ellipses, polygons, or other shapes. The individual structures of the nanostructures can be made of metal, such as silver, gold, aluminum, copper, platinum, palladium, and/or nickel. The metal can be arranged in a grid, series of pillars, series of gratings or holes, a particle array or a random distribution. In some embodiments, the individual nanostructures range from approximately 5, 25, 50, 75, 100, 125, 150, 175, 200, 225, 250 to 275, 300, 325, 350, 375, 400, 425, 450, 475, 500 nm in width, and neighboring nanostructures are spaced apart by approximately 5, 50, 100, 150, 200, 250 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, to 1000 nm.

[0076] Microfluidic channels can be created or formed using standard lithography to provide for the transport biomarker containing samples to different sensors or regions on or within a device. H. Encapsulation layer

[0077] An encapsulation layer can be formed or deposited on all or part of the source-drain electrode layer and can form wells in conjunction with the semiconductor channel(s). A suitable encapsulation layer with a well structure will be created on top of the semiconductor and the source drain electrodes. The encapsulation layer material can be AI2O3, HfCh, silicon nitride, silicon dioxide, or any other organic materials such as SU-8, parylene, PVP and PVDF. In some aspects, the encapsulation layer can have a thickness of 0.01 pm to 10 pm or 0.01 pm to 1 pm, or at least any one of, equal to any one of, or between any two of 0.01 pm, 0.02 pm, 0.03 pm, 0.04 pm, 0.05 pm, 0.06 pm, 0.07 pm, 0.08 pm, 0.09 pm, 0.1 pm, 0.2 pm, 0.3 pm, 0.4 pm, 0.5 pm, 0.6 pm, 0.7 pm, 0.8 pm, 0.9 pm, 1 pm, 2 pm, 3 pm, 4 pm, 5 pm, 6 pm, 7 pm, 8 pm, 9 pm and 10 pm, above the source drain electrode layer.

II. Methods of Fabricating a Plasmonic TFT

[0078] One or more of the following steps can be used in the fabrication of a plasmonic TFT described herein.

[0079] Step 1: Substrate preparation. A suitable rigid or flexible material such as glass, silicon or plastic, which can withstand the TFT fabrication process temperature, can be used as the substrate.

[0080] Step 2: Gate electrode deposition and patterning. A conducting thin film of a metal with suitable work function or transparent conducting oxides can be deposited on top of the substrate. This conducting thin film layer of thickness 20 to 200 nm can be used as the gate electrode of the TFT. The gate electrode can be patterned by using standard photolithography technique, wet/dry etching, or similar processes.

[0081] Step 3: Gate insulator layer deposition. A suitable gate insulator layer of thickness 25 nm to 200 nm can be deposited on top of the gate electrode layer by using atomic layer deposition, PECVD, sputtering techniques or similar processes.

[0082] Step 4: Semiconductor layer deposition and patterning. A suitable semiconductor layer such as zinc oxide (ZnO), zinc indium oxide (IZO) or indium gallium zinc oxide (IGZO) can be deposited by sputtering, atomic layer depositions, or similar processes. The semiconductor layer can have a thickness 10 to 50 nm and can be patterned using standard photolithography technique, wet/dry etching, or similar processes. [0083] Step 5: Gate via patterning. To create access to the gate electrode through gate insulator layer, holes can be formed by standard photolithography, dry/wet etching, or similar processes.

[0084] Step 6: Source-drain contact deposition and patterning. A suitable conducting layer of metal or transparent conducting oxide with appropriate work function can be used as the source-drain electrodes. The source-drain electrode layer can be deposited by using atomic layer deposition, e-beam/thermal evaporation, sputtering techniques, or similar processes. The source-drain electrodes can be patterned using standard photolithography technique, wet/dry etching, lift-off method, or similar processes. After fabrication, TFTs can be annealed at a suitable temperature < 200 °C for appropriate durations in air or other gas ambient to get better performance and stability.

[0085] Step 7: Protection layer. A suitable insulating material of thickness O. lnm to lOnm can be used as a protection layer. The optional protection layer can be deposited on a portion of the semiconductor layer using atomic layer deposition. The protection layer can be of hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, silicon oxide or a combination of them.

[0086] Step 8: Integration of plasmonic layer. The geometry and the locations of the plasmonic nanostructures relative to the neighboring semiconductor material can be important. The photocurrent generated by an active plasmonic element can be significantly enhanced by embedding it in the adjoining semiconductor layer or in the protection layer over the semiconductor layer, as this permits more efficient transfer channels between the plasmon-TFT structures with robust sensing capability. The plasmon-TFT devices are not affected by the solution diffusion factors that might limit the efficiencies of conventional semiconductor-based devices, and they thus open a new horizon of possibilities in the field of molecular biosensing. The size, shape and composition of the plasmonic nanostructures can be adapted to obtain broad absorption across energy wavelength relevant to biological specimen. The high absorption cross-section of anisotropically diverse plasmonic nanostructures (nanowires, nanorods, and nanosponges) allows the thickness of the active zone to be reduced while maintaining a high plasmon efficiency.

[0087] Step 9: Well-structure encapsulation layer. An encapsulation layer can form a well structure and can be created on top of the plasmonic layer, semiconductor and the source drain electrodes. The encapsulation layer material can be AI2O3, HfC , silicon nitride, silicon dioxide, or any other organic materials such as SU-8, parylene, PVP and PVDF.

[0088] Step 10: Surface functionalization of plasmonic layer. Depending on the sensing biomarker, the surface of the plasmonic layer can be functionalized with any materials of interst.

[0089] Step 11: Microfluidic channels. Microfluidic channels can be created using standard lithography to provide for transporting biomarker containing samples to different sensors or different regions on or in a sensor.

EXAMPLES

[0090] As part of the disclosure of the present invention, specific examples are included below. The examples are for illustrative purposes only and are not intended to limit the invention. Those of ordinary skill in the art will readily recognize parameters that can be changed or modified to yield essentially the same results.

Example 1

Thin film transistor (TFT)

A. Device Fabrication

[0091] Substrate preparation: Glass substrates of thickness 1.1 mm were used to build the TFT devices. The glass substrates were sonicated in acetone, isopropanol and deionized water separately and then lastly blown-dried by a high purity nitrogen (N2) gas gun.

[0092] Gate electrode deposition: Aluminum doped zinc oxide (AZO) thin-film of thickness about 170 nm was used as the gate electrode. The AZO films were deposited on cleaned glass substrates by atomic layer deposition (ALD) at l60°C using diethylzinc (DEZ) and trimethylaluminum (TMA) from Sigma Aldrich as the Zn and Al precursors and DIW as the oxygen precursor.

[0093] Gate electrode patterning: The AZO thin films were patterned by standard photolithography and wet etching. The AZO film was etched using 0.5% v/v hydrochloric acid .

[0094] Gate insulator deposition: Hafnium oxide (Hf02) was used as the thin-film gate insulator layer. The thin-film gate insulator layer was deposited on top of the AZO gate electrodes by ALD technique using tetrakis(dimethylamido)hafnium(IV) from (Sigma Aldrich) as the Hf precursor and ozone as the oxygen precursor and Nitrogen gas (e.g., N2 gas) was used as the process gas. Five hundred cycles of HfC (~54 nm) was deposited on top AZO gate electrodes.

[0095] Semiconductor layer deposition: Indium gallium zinc oxide (IGZO) thin film was used as the semiconductor layer. The IGZO layer was deposited on top of the FKO2 layer by radiofrequency sputtering under the deposition conditions as mentioned in Table 1.

Table 1 : Semiconductor layer deposition conditions

[0096] Semiconductor patterning: The IGZO semiconductor film was patterned by standard photolithography and wet etching using diluted (2% v/v) hydrochloric acid.

[0097] Gate via creation: To create access to the gate electrode through FHO2 gate insulator, via holes were formed by standard photolithography and dry etching. The FHO2 layer from the gate via pattern was etched by dry etching using CHF3 (20 seem) and Ar gas (4 ssem) plasma with an etching rate of about 55nm/minute.

[0098] Source-drain electrode deposition: A bi-layer of 10 nm titanium and 60 nm gold source and drain electrodes were patterned using conventional photolithography techniques and electron-beam evaporation deposition.

[0099] Post annealing of TFTs: After the whole fabrication process, the TFTs were annealed at l60°C for 2hours in air ambient to get better performance and stability.

[0100] Plasmonic nano structure formation: A 4 um-thick A Z ECI3027 positive photoresist (PR) was first spin coated on the substrate having TFTs. The PR layer was then exposed with a broadband UV light source at a dose of 200 mJcm ² and a photomask to transfer the desired features. The PR was then developed for 60 seconds using A Z 726 MIF developer. Gold films of 3 nm thickness was then deposited using e-beam evaporation deposition at room temperature with a deposition rate of 0.2 A/sec. Lift-off using acetone was performed to remove the unwanted areas and cleaned in isopropanol and DIW to complete the patterning process. The samples were finally dried using N2 gas. The TFT samples with gold thin film in the channel area were subjected to annealing at 160 °C for 2 hours to form the gold nano-islands.

[0101] SU8 based encapsulation layer and well formation: SU8 photo resist of thickness 2 pm (SU8-2002, Microchem) was used as the encapsulation layer to isolate the source-drain electrodes and to form a well structure within the gold nano-island region. The SU8 layer was deposited by spin coating (spin speed ~3000rpm) and the well structure was formed by standard photolithography.

[0102] Surface functionalization of gold nano-island layer within TFT device: The TFT samples after gold-nano island and SU8 layer formation were immersed in 25mM of 4- mercaptophenylboronic acid (4-MPBA) containing ethanol solution for 15 minutes. The samples were then rinsed several times in ethanol and dried using N2 gas.

B. Device testing:

[0103] The current and voltage characteristics of TFTs were measured using an Agilent B1500A semiconductor device parameter analyzer and Cascade Summit 1100 probe station. Transfer characteristic curves of the TFTs were obtained by sweeping the voltage applied to the gate electrode at a fixed voltage applied to the drain electrode while the source electrode was maintained as the common electrode (grounded). Output characteristic curves of the TFTs were obtained by sweeping the voltage applied to the drain electrode at a fixed voltage applied to the gate electrode while the source electrode was maintained as the common electrode (grounded).

[0104] Pictorial representation of plasmon integrated TFT device fabricated in this example is shown in (FIG. 1). The geometry and the locations of the plasmonic nanostructures relative to the neighboring semiconductor material are very important. It is envisioned that the photocurrent generated by an active plasmonic element can be significantly enhanced by embedding it in the adjoining semiconductor, as this permits more efficient transfer channels between the plasmon-TFT structures with robust sensing capability. The size, shape and composition of the plasmonic nanostructures can be adapted to obtain broad absorption across energy wavelength relevant to biological specimen (FIG. 3).

[0105] FIG. 4A and B shows the optical image of a TFT before and after gold nano-island formation. FIG. 4C shows the SEM image of the selected region in the channel area of the TFT, which clearly shows the formation of gold nano-islands after annealing the 3nm gold film at 160 °C for 2 hours in air environment.

[0106] FIG. 5 shows the measured drain current for IGZO TFTs with and without gold nano-islands in the channel area. The drain current was measured at a fixed voltage of 2V applied to the drain electrode and 3 V applied to the gate electrode. During the measurements, the channel area of the TFT was periodically illuminated by red light using a white light source and red color filter. FIG. 5 shows that irrespective of red light illumination, the drain current remains unchanged in case of the IGZO TFT without gold nano-islands. However, a clear enhancement the enhancement of drain current in case of the IGZO TFT with gold nano-islands due to plasmonic effect.

Example 2

Thin film transistor (TFT)

A. Device Fabrication

[0107] Substrate preparation: Glass substrates of thickness 1.1 mm were used to build the TFT devices. The glass substrates were sonicated in acetone, isopropanol and deionized water separately and then lastly blown-dried by a high purity nitrogen (N2) gas gun.

[0108] Gate electrode deposition: Aluminum doped zinc oxide (AZO) thin-film of thickness about 170 nm was used as the gate electrode. The AZO films were deposited on cleaned glass substrates by atomic layer deposition (ALD) at l60°C using diethylzinc (DEZ) and trimethylaluminum (TMA) from Sigma Aldrich as the Zn and Al precursors and DIW as the oxygen precursor.

[0109] Gate electrode patterning: The AZO thin films were patterned by standard photolithography and wet etching. The AZO film was etched using 0.5% v/v hydrochloric acid .

[0110] Gate insulator deposition: Hafnium oxide (Hf02) was used as the thin-film gate insulator layer. The thin-film gate insulator layer was deposited on top of the AZO gate electrodes by ALD technique using tetrakis(dimethylamido)hafnium(IV) from (Sigma Aldrich) as the Hf precursor and ozone as the oxygen precursor and Nitrogen gas (e.g., N2 gas) was used as the process gas. Five hundred cycles of Hf02 (~54 nm) was deposited on top AZO gate electrodes. [0111] Semiconductor layer deposition: Indium gallium zinc oxide (IGZO) thin film was used as the semiconductor layer. The IGZO layer was deposited on top of the Hf02 layer by radiofrequency sputtering under the deposition conditions as mentioned in Table 2.

Table 2: Semiconductor layer deposition conditions

[0112] Semiconductor patterning: The IGZO semiconductor film was patterned by standard photolithography and wet etching using diluted (2% v/v) hydrochloric acid.

[0113] Gate via creation: To create access to the gate electrode through Hf02 gate insulator, via holes were formed by standard photolithography and dry etching. The Hf02 layer from the gate via pattern was etched by dry etching using CHEri (20 seem) and Ar gas (4 ssem) plasma with an etching rate of about 55nm/minute.

[0114] Source-drain electrode deposition: A bi-layer of 10 nm titanium and 60 nm gold source and drain electrodes were patterned using conventional photolithography techniques and electron-beam evaporation deposition.

[0115] Formation of Hf0₂ based protection layer: About 1 nm of hafnium oxide was deposited by atomic layer deposition at 75 °C using tetrakis(dimethylamido)hafnium(IV) from (Sigma Aldrich) as the Hf precursor and ozone as the oxygen precursor and Nitrogen gas (e.g., N2 gas) was used as the process gas.

[0116] Post annealing of TFTs: After HTO2 protection layer deposition, the TFTs were annealed at l60°C for 2hours in air ambient to get better performance and stability.

[0117] Plasmonic nano structure formation: A 4 um-thick A Z ECI3027 positive photoresist (PR) was first spin coated on the substrate having TFTs. The PR layer was then exposed with a broadband UV light source at a dose of 200 mJcm ² and a photomask to transfer the desired features. The PR was then developed for 60 seconds using A Z 726 MIF developer. Gold films of 3 nm thickness was then deposited using e-beam evaporation deposition at room temperature with a deposition rate of 0.2 A/sec. Lift-off using acetone was performed to remove the unwanted areas and cleaned in isopropanol and DIW to complete the patterning process. The samples were finally dried using N2 gas. The TFT samples with gold thin film in the channel area were subjected to annealing at 160 °C for 2 hours to form the gold nano-islands.

[0118] SU8 based encapsulation layer and well formation: SU8 photo resist of thickness 2 pm (SU8-2002, Microchem) was used as the encapsulation layer to isolate the source-drain electrodes and to form a well structure within the gold nano-island region. The SU8 layer was deposited by spin coating (spin speed ~3000rpm) and the well structure was formed by standard photolithography.

[0119] Surface functionalization of gold nano-island layer within TFT device: The TFT samples after gold-nano island, SU8 layer formation and protection layer formation were immersed in 25mM of 4-mercaptophenylboronic acid (4-MPBA) containing ethanol solution for 15 minutes. The samples were then rinsed several times in ethanol and dried using N2 gas. The use of 4-MPBA enables selective molecular detection of glucose.

B. Device testing:

[0120] The current and voltage characteristics of TFTs were measured using an Agilent B1500A semiconductor device parameter analyzer and Cascade Summit 1100 probe station. Transfer characteristic curves of the TFTs were obtained by sweeping the voltage applied to the gate electrode at a fixed voltage applied to the drain electrode while the source electrode was maintained as the common electrode (grounded). Output characteristic curves of the TFTs were obtained by sweeping the voltage applied to the drain electrode at a fixed voltage applied to the gate electrode while the source electrode was maintained as the common electrode (grounded).

[0121] Pictorial representation of plasmon integrated TFT device fabricated in this example is shown in (FIG. 6B).

[0122] The oxide semiconductor based TFTs are sensitive to humidity, ambient atmosphere, light, and the storage time. As illustrated in (FIG. 6A and 6C), the performance of gold nano island integrated IGZO TFTs with SU-8 protection layer showed unstable behavior with ageing. These problems could be solved with the use of an ultra-thin (lnm) ALD deposited Hf02 layer on top of the IGZO semiconductor layer as shown in the figures FIG. 6B and 6D. [0123] Glucose detection based on using 4-mercaptophenyl boronic acid (4-MPBA) as a molecular probe: Optimal Conditions for (MPBA) templating into nanoplasmonic cavity of TFT device prior glucose determination were identified. Crucial environmental factors influencing not only the self-assembled monolayers of (4-MPBA) but also the orientation of (4-MPBA) onto the planar gold nanoislands (MPBA) in the TFT device were taken into account. Amongst these parameters, include the pH and incubation period of (4-MPBA) in the sensing system. FIG. 7(A) shows the optical image of a gold nano-island integrated TFT with SU-8 protection layer and treated with 4-MPBA. FIG. 7 B shows Raman spectra obtained from different locations as indicated in FIG. 7A. The 4-MPBA has characteristic peaks at 1574, 1074 and 1074 cm ¹ attributed to symmetric vibrational modes of the benzene ring, asymmetric vibrational modes of the benzene ring, and C-C in-plane bending coupled with C-S stretching respectively. The Raman spectra obtained from different locations clearly shows that the 4- MPBA molecules are only selectively attached to the gold nano-islands present in the well area of the TFT channel layer.

[0124] Glucose sensing measurements: Glucose solutions of concentrations 0.01 mg/dl, 0.1 mg/dl, lmg/dl, 10 mg/dl and 50 mg/dl were prepared by dissolving D(+) glucose >99.55 (Sigma Aldrich) in phosphate buffer saline (PBS). The buffer solution was prepared first by dissolving ready PBS powder (Sigma Aldrich) in Millipore water, thus resulting in pH of 7.4 and ionic strength of 0.154 M, both parameters matching the pH and ionic strength of human blood. A PDMS well was created and placed on the 4-MPBA treated channel area of the gold nano-island integrated TFT with SU-8 layer well. The output characteristics of the TFTs were obtained after adding different concentrations of glucose in the PDMS well as shown in FIG. 8 A. FIG. 8 A clearly shows the decrease in drain current with increasing glucose concentration. FIG. 8B shows the extracted drain current (at VD=2V) versus glucose concentration, which exhibits a linearly decrease in drain current with increasing glucose current. The results shown here, confirms that glucose concentrations of as low as O.Olmg/dl can be detected using our approach.

Claims

1. A sensor comprising:

(a) a substrate layer;

(b) a gate electrode layer deposited on the substrate layer;

(c) a gate insulator layer deposited on the gate electrode layer covering at least a

portion of the gate electrode layer;

(d) a channel or semiconductor layer deposited on the gate insulator layer;

(e) a source-drain electrode layer deposited on the channel layer, wherein the source- drain electrode layer covers a portion of the semiconductor layer;

(f) an encapsulation layer forming a well between source and drain portions, with the well having a floor formed by the channel layer and the well configured to receive or contain plasmonic nanostructures; and

(g) plasmonic nanostructures operatively positioned on or integrated with the

semiconductor layer in the well formed in the source-drain electrode layer.

2. The sensor of claim 1, wherein the substrate is a plastic substrate, a glass substrate, or a silicon substrate.

3. The sensor of claim 1, wherein the substrate is a flexible substrate.

4. The sensor of any one of claim 1 to 3, wherein the substrate comprises PET

(polyethylene terephthalate), PEN (polyethylene naphthalate), PEI

(polyethylenimine), PDMS (polydimethylsiloxane), PMMA

(polymethylmethacrylate), PC (polycarbonate), COC (cyclic olefin copolymer), PA (polyamide), PE (polyethylene), PP (polypropylene), PPE (polyphenylene ether), PS (polystyrene), POM (polyoxymethylene), PEEK (polyetheretherketone), PTFE (polytetrafluoroethylene), PVC (polyvinylchloride), PVDF (polyvinylidene fluoride), PBT (polybutyleneterephthalate), FEP (fluorinated ethylenepropylene), or PFA (perfluoralkoxy alkane).

5. The sensor of any one of claim 1 to 4, wherein the gate electrode layer is a metal film, a conducting polymer film, a doped silicon conducting film, or a transparent conducting oxide, such as Al-ZnO, Ga-ZnO, ITO, Sn02, F-Sn02.

6. The sensor of any one of claim 1 to 5, wherein the gate layer comprises aluminum, gold, chromium, molybdenum, titanium, indium tin oxide, conductive polymers or combination thereof.

7. The sensor of any one of claim 1 to 6, wherein the gate insulator layer is an inorganic material film, an organic polymer film, or an organic-inorganic composite film.

8. The sensor of any one of claim 1 to 7, wherein the insulator layer comprises silicon oxide, silicon nitride, zirconium oxide, titanium oxide, hafnium oxide, aluminum oxide, barium titanate, barium zirconium titanate, polyesters, polycarbonates, poly(vinyl phenol), polyimides, polystyrene, polymethacrylates, polyacrylates, epoxy resin, or combinations thereof and/or wherein the gate insulator layer is about 25 to 200 nm thick.

9. The sensor of any one of claim 1 to 8, wherein the channel or semiconductor layer is an inorganic or organic semiconducting material.

10. The sensor of any one of claim 1 to 9, wherein the semiconducting material is a zinc oxide (ZnO), indium oxide, tin oxide, zinc indium oxide (IZO) or indium gallium zinc oxide (IGZO), zinc tin oxide, or any oxide semiconducting material having at least In, Zn, Sn, and Ga, acene, perylene, fullerene, oligothiophenes, polythiophenes, polypyrrole, poly-p-phenylenes, poly-p-phenylvinylidenes, naphthalenedicarboxylic dianhydrides, naphthalene-bisimides, polynaphthalenes, phthalocyanines, or substituted derivatives thereof and/or wherein the semiconducting layer is about 5 to 100 nm.

11. The sensor of any one of claim 1 to 10, wherein the source-drain layer is titanium, gold, nickel, aluminum, platinum, a combination of them, transparent conducting oxides or a conducting polymer(s).

12. The sensor of any one of claim 1 to 11, wherein the source-drain layer is about 20 to 200 nm thick.

13. The sensor of any one of claim 1 to 12, wherein the plasm onic nanostructures are nanowires, nanorods, nano-triangles, nanocubes, nanoprisms and/or nanosponges.

14. The sensor of any one of claim 1 to 13, wherein the plasmonic nanostructures

comprise a metal or transparent conducting oxide nano structures.

15. The sensor of any one of claim 1 to 14, wherein the plamonsic nanostructure comprise silver, gold, aluminum, copper, platinum, palladium, and/or nickel Al-doped ZnO, Ga-doped ZnO, indium tin oxide nanoparticles or nanostructures.

16. The sensor of any one of claim 1 to 15, wherein the plasmonic nanostructure have a thickness in at least one dimension of about 1 to 50 nm in diameter.

17. The sensor of any one of claim 1 to 16, further comprising one or more microfluidic channels fluidically coupled to the encapsulation well.

18. The sensor of any one of claim 1 to 17, wherein the sensor comprises a protection layer over at least a portion of a surface of the semiconductor layer in the well and the plasmonic nanostructures are operatively positioned on or integrated with the protection layer.

19. A method of making a plasmonic thin film transistor sensor comprising:

(a) depositing a layer of gate electrode material onto a substrate forming a gate electrode layer;

(b) depositing a layer of gate insulator material onto the gate electrode layer forming a gate insulator layer;

(c) depositing a layer of semiconducting material on the gate insulator layer forming a channel layer;

(d) depositing source-drain layer materials on the channel layer forming a source- drain electrode layer configured to form channels in the source-drain layer that can lined with encapsulation layer material;

(e) forming or attaching plasmonic nanostructures on a portion of the semiconductor layer; and

(f) depositing an encapsulation layer material onto the source drain electrode layer forming an encapsulation layer forming a well having a floor formed by the plasmonic nanostructures and a wall formed by the encapsulation layer.

20. The method of claim 19, comprising depositing a protection layer material over at least a portion of a surface of the semiconductor layer to form a protection layerbefore the plasmonic nanostructures formation and attaching or forming the plasmonic nanostructures on a portion of the protection layer.