WO2020062501A1

WO2020062501A1 - Goa circuit structure

Info

Publication number: WO2020062501A1
Application number: PCT/CN2018/116368
Authority: WO
Inventors: 陈帅
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2018-09-25
Filing date: 2018-11-20
Publication date: 2020-04-02
Also published as: CN109119041A; CN109119041B

Abstract

A GOA circuit structure. The GOA circuit structure comprises a pull-up control unit (2), a pull-up unit (3), a downloading unit (4), a pull-down unit (5), a pull-down holding unit (6) and an additional thin film transistor (T23). By means of providing the additional thin film transistor (T23) and electrically connecting a control signal end to a gate of the additional thin film transistor (T23), the situation of interference in an output waveform of a gate signal output end of the GOA circuit structure can be reduced.

Description

GOA circuit structure

Technical field

The present invention relates to a GOA circuit structure, and more particularly, to a GOA circuit structure for improving the Q (n) waveform of a signal point.

Background technique

The working principle of a liquid crystal panel is based on a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate) and a color filter substrate (Color Filter (CF) is filled with liquid crystal molecules, and a driving voltage is applied to the two substrates to control the rotation direction of the liquid crystal molecules, and the light of the backlight module is refracted to generate a picture.

The liquid crystal panel has a plurality of pixels arranged in an array. Each pixel is electrically connected to a thin film transistor (TFT), a gate of the thin film transistor is connected to a horizontal scanning line, and a source is connected to a vertical direction. The drain line is connected to the pixel electrode. Applying sufficient voltage on the horizontal scanning line will cause all TFTs electrically connected to the horizontal scanning line to be turned on, so that the signal voltage on the data line can be written into the pixel, controlling the transmittance of different liquid crystals to achieve color control With the effect of brightness. Gate Driver on Array, or GOA for short, is a method of integrating a gate line scan driving circuit on a TFT array substrate by using an existing Array process of a thin film transistor liquid crystal panel to realize a driving method for scanning a gate. The use of GOA driver circuits instead of traditional gate drive chips (ICs) has the opportunity to increase productivity and reduce product costs, and can make LCD panels more suitable for making narrow-frame or borderless display products.

As shown in FIG. 1, it is an existing GOA circuit. The main structure includes a pull-up control unit 11, a pull-up unit 12, a pass-through unit 13, a pull-down unit 14, a pull-down maintenance unit 15, and a bootstrap capacitor Cbt. . The pull-up unit 12 is mainly responsible for outputting a clock signal (Clock) as a gate signal; the pull-up control unit 11 is responsible for controlling the opening time of the pull-up unit 12, and the pull-down unit 14 is responsible for The pull-down sustaining unit 15 is responsible for maintaining the gate output signal and the gate signal of the pull-up unit 14 (usually referred to as the Q point) in an off state (ie, negative). Potential); the bootstrap capacitor Cbt is responsible for the second lifting of the Q point, which is beneficial to the G (n) output of the pull-up unit 12.

As shown in Figures 1 and 2, it is assumed that the stage signal output terminal ST (n-4) of the n-4th stage GOA circuit and the gate signal output terminal G (n-4) of the n-4th stage GOA circuit correspond. The clock signal CK1 and the gate signal point Q (n) of the n-th GOA circuit correspond to the clock signal CK5. In an ideal case, when the stage signal output terminal ST (n-4) and the gate signal output terminal G (n-4) of the n-4 stage GOA circuit change from a high potential to a low potential, the The thin film transistor T11 of the pull-up control unit 11 is immediately turned off, and the gate signal point Q (n) is pulled to a higher potential by the bootstrap capacitor Cbt. However, in a practical situation, the GOA circuit includes many resistor and capacitor structures, which may cause the stage signal output terminal ST (N-4) and the gate due to resistance and capacitor delay (RC delay). The signal output terminal G (N-4) does not decrease from a high potential to a low potential instantly, but becomes a slowly decreasing voltage. During this process, the thin film transistor T11 is still in a slightly on state, which will cause the gate The decrease in the potential of the pole signal point Q (n) affects the turning on of the thin film transistor T21 of the pull-up unit 12, and further affects the output waveform of the gate signal output terminal G (n) of the n-th GOA circuit.

technical problem

An object of the present invention is to provide a GOA circuit structure. By providing an additional thin film transistor and electrically connecting a control signal terminal (P (n-3)) to the gate of the additional thin film transistor, interference with the gate signal output can be reduced. Terminal (G (n)).

Technical solutions

To solve the above problems, the technical solution provided by the present invention is as follows:

To achieve the foregoing object of the present invention, an embodiment of the present invention provides a GOA circuit structure. The GOA circuit structure is a plurality of cascaded GOA circuits. The n-th GOA circuit includes a pull-up control unit, a Pull-down unit, pull-down unit, pull-down unit, pull-down sustain unit, and an additional thin-film transistor (T23); wherein the pull-up unit, the download unit, the pull-down unit, and the pull-down sustain unit and the nth The gate signal output terminal (G (n)) of the GOA circuit is electrically connected, where n is a natural number; the pull-up control unit, the download unit, the pull-down unit, and the pull-down sustain unit are connected to the n-th stage. The gate signal point (Q (n)) of the GOA circuit is electrically connected; a gate of the additional thin film transistor (T23) is electrically connected to a control signal terminal (P (nm)) of the nm-level GOA circuit, m Is a natural number; a drain of the additional thin film transistor (T23) is electrically connected to a working voltage (VSS); a source of the additional thin film transistor (T23) is electrically connected to a first-level signal of a nm-level GOA circuit Output terminal (ST (nm)); the pull-up control unit is electrically connected to the nq-level GOA circuit Gate signal output terminal (G (n-q)), q is a natural number; n-th stage of the charging circuit GOA n-th horizontal scanning line is controlled.

In an embodiment of the present invention, the gate of the additional thin film transistor (T23) is electrically connected to the control signal terminal (P (n-3)) of the n-3th GOA circuit; the additional thin film transistor (T23) ) The source is electrically connected to the stage signal output terminal (ST (n-3)) of the nm-level GOA circuit; the pull-up control unit is electrically connected to the gate signal output terminal of the n-4 level GOA circuit ( G (n-4)).

In an embodiment of the present invention, when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is at a high potential, the control signal terminal (P (n -3)) is a low potential, so that the additional thin film transistor (T23) is in an off state.

In an embodiment of the present invention, when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is a low potential, the control signal terminal (P (n -3)) First, a low potential is maintained for a period of time and then a high potential, so that the additional thin film transistor (T23) is in an on state.

In an embodiment of the present invention, the downstream unit includes: a second thin film transistor (T22), and a gate of the second thin film transistor (T22) is electrically connected to a gate of the n-th GOA circuit. A signal point (Q (n)), a source of the second thin film transistor (T22) is electrically connected to a stage signal output terminal (ST (n)) of the n-th GOA circuit, and the second thin film transistor A drain of (T22) is electrically connected to a clock signal (CK1 / CK5).

In an embodiment of the present invention, the pull-up unit includes a third thin film transistor (T21), and a gate of the third thin film transistor (T21) is electrically connected to a gate of the n-th GOA circuit. A signal point (Q (n)), a source of the third thin film transistor (T21) is electrically connected to a gate signal output terminal (G (n)) of the n-th GOA circuit, and the third A drain of the thin film transistor (T21) is electrically connected to a clock signal (CK1 / CK5).

In an embodiment of the present invention, the pull-down unit includes a fourth thin film transistor (T41), and a gate of the fourth thin film transistor (T41) is electrically connected to a gate of the n + q-level GOA circuit. A signal output terminal (G (n + 4)), a drain of the fourth thin film transistor (T41) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and the A source of the fourth thin film transistor (T41) is electrically connected to the working voltage (VSS); and a fifth thin film transistor (T31), a gate of the fifth thin film transistor (T31) is connected to the n + qth A gate signal output terminal (G (n + 4)) of the first-level GOA circuit, a drain of the fifth thin film transistor (T31) is electrically connected to the gate signal output terminal (G (n)), and A source of the fifth thin film transistor (T31) is electrically connected to the operating voltage (VSS).

In an embodiment of the present invention, the pull-down sustaining unit includes a sixth thin film transistor (T32), and a gate of the sixth thin film transistor (T32) is electrically connected to a node of the n-th GOA circuit ( P (n)), a source of the sixth thin film transistor (T32) is electrically connected to the gate signal output terminal (G (n)), and a drain of the sixth thin film transistor (T32) is electrically connected To the working voltage (VSS); a seventh thin film transistor (T42), a gate of the seventh thin film transistor (T42) is electrically connected to the node (P (n)), and the seventh thin film A source of the transistor (T42) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and a drain of the seventh thin film transistor (T42) is electrically connected to the operating voltage. (VSS); an eighth thin film transistor (T51), a gate of the eighth thin film transistor (T51) is electrically connected to a signal terminal (LC), and a source of the eighth thin film transistor (T51) is electrically To the signal terminal (LC), a drain of the eighth thin film transistor (T51) is electrically connected to a gate of a fourth thin film transistor (T53); a ninth thin film transistor (T53), the Ninth thin film crystal A source of the tube (T53) is electrically connected to the signal terminal (LC), a drain of the ninth thin film transistor (T53) is electrically connected to the node (P (n)); a tenth thin film transistor (T52), a gate of the tenth thin film transistor (T52) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and one of the tenth thin film transistor (T52) A source is electrically connected to the operating voltage (VSS), a drain of the tenth thin film transistor (T52) is electrically connected to a gate of the fourth thin film transistor (T53); and an eleventh thin film transistor ( T54), a gate of the eleventh thin film transistor (T54) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and the eleventh thin film transistor (T54) A source is electrically connected to the working voltage (VSS), and a drain of the eleventh thin film transistor (T54) is electrically connected to the node (P (n)).

In an embodiment of the present invention, the pull-up control unit includes a first thin-film transistor (T11), and a gate of the first thin-film transistor (T11) is electrically connected to a stage-level signal of the nm-level GOA circuit. An output terminal (ST (nm)), a drain of the first thin film transistor (T11) is electrically connected to a gate signal output terminal (G (nq)) of the nq-level GOA circuit, the first thin film transistor A source of (T11) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit.

To achieve the foregoing object of the present invention, an embodiment of the present invention provides a GOA circuit structure. The GOA circuit structure is a plurality of cascaded GOA circuits. The n-th GOA circuit includes a pull-up control unit, a Pull-down unit, pull-down unit, pull-down unit, pull-down sustain unit, and an additional thin-film transistor (T23); wherein the pull-up unit, the download unit, the pull-down unit, and the pull-down sustain unit and the nth The gate signal output terminal (G (n)) of the GOA circuit is electrically connected, where n is a natural number; the pull-up control unit, the download unit, the pull-down unit, and the pull-down sustain unit are connected to the n-th stage. The gate signal point (Q (n)) of the GOA circuit is electrically connected; a gate of the additional thin film transistor (T23) is electrically connected to a control signal terminal (P (nm)) of the nm-level GOA circuit, m Is a natural number; a drain of the additional thin film transistor (T23) is electrically connected to a working voltage (VSS); a source of the additional thin film transistor (T23) is electrically connected to a first-level signal of a nm-level GOA circuit Output terminal (ST (nm)); the pull-up control unit is electrically connected to the nq-level GOA circuit Gate signal output terminal of a natural number (G (n-q)), q is

In an embodiment of the present invention, the GOA circuit further includes a bootstrap capacitor, and the bootstrap capacitor is electrically connected to the gate signal point (Q (n)) and the nth of the n-th GOA circuit. Between the gate signal output terminals (G (n)) of the stage GOA circuit.

Beneficial effect

The beneficial effect of the present invention is: by providing the additional thin film transistor and electrically connecting the control signal terminal (P (n-3)) to the gate of the additional thin film transistor, the gate signal point can be avoided The decrease in (Q (n)) potential affects the turning on of the third thin film transistor, thereby reducing the interference with the output waveform of the gate signal output terminal (G (n)). In addition, the first thin film can also be maintained The transistor is effectively turned off, thereby improving the stability of the gate signal point (Q (n)) potential.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly explain the embodiments or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely inventions. For some embodiments, for those skilled in the art, other drawings can be obtained based on these drawings without paying creative labor.

FIG. 1 is a schematic diagram of a conventional GOA circuit.

FIG. 2 is a schematic diagram of related waveforms of a conventional GOA circuit.

FIG. 3 is a schematic diagram of a preferred embodiment of the GOA circuit structure of the present invention.

4 and 5 are schematic diagrams of related waveforms of the GOA circuit structure of the present invention.

Best Mode of the Invention

The liquid crystal display module provided by the embodiments of the present invention has been described in detail above. Specific examples are used herein to explain the principles and implementation of the present invention. The description of the above embodiments is only used to help understand the present invention. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation and scope of application. In summary, the content of this description should not be construed as a limitation on the present invention. The following descriptions of the embodiments are made with reference to additional illustrations to illustrate specific embodiments in which the present invention can be implemented. The directional terms mentioned in the present invention, such as [up], [down], [front], [rear], [left], [right], [in], [out], [side], etc., are for reference only. The direction of the attached schema. Therefore, the directional terms used are for explaining and understanding the present invention, but not for limiting the present invention. In the figure, similarly structured units are denoted by the same reference numerals.

Please refer to FIG. 3, which is a schematic diagram of a preferred embodiment of the GOA circuit structure of the present invention. The GOA circuit structure of the present invention is a plurality of cascaded GOA circuits, wherein the n-th GOA circuit controls the charging of the n-th horizontal scanning line, and the n-th GOA circuit includes a pull-up control unit 2 and a The pull-down unit 3, the pass-through unit 4, the pull-down unit 5, the pull-down maintenance unit 6, a bootstrap capacitor Cbt, and an additional thin film transistor T23. The present invention will explain in detail the detailed structure, the assembly relationship, and the operation principle of the above components of the embodiments.

Continuing to refer to FIG. 3, the pull-up unit 3, the download unit 4, the pull-down unit 5, and the pull-down maintaining unit 6 and the gate signal output terminal G (n) of the n-th GOA circuit are electrically connected. Sexual connection, where n is a natural number. In addition, the pull-up control unit 2, the download unit 4, the pull-down unit 5, and the pull-down sustain unit 6 are electrically connected to the gate signal point Q (n) of the n-th GOA circuit.

Continuing to refer to FIG. 3, a gate of the additional thin film transistor T23 is electrically connected to a control signal terminal P (nm) of the nm-level GOA circuit, where m is a natural number; a drain of the additional thin film transistor T23 An operating voltage VSS is electrically connected; a source of the additional thin film transistor (T23) is electrically connected to a first-stage signal output terminal ST (nm) of the nm-level GOA circuit. In addition, a first thin film transistor T11 of the pull-up control unit is electrically connected to a gate signal output terminal G (n-q) of the n-q-level GOA circuit, where q is a natural number. For example, the gate of the additional thin film transistor T23 is electrically connected to the control signal terminal P (n-3) of the n-3 level GOA circuit; the source of the additional thin film transistor T23 is electrically connected to the nm-level GOA circuit. The stage transmission signal output terminal ST (n-3); the first thin film transistor T11 of the pull-up control unit 2 is electrically connected to the gate signal output terminal G (n-4) of the n-4th stage GOA circuit.

Continuing to refer to FIG. 3, the pull-up control unit 2 includes the first thin film transistor T11, wherein a gate of the first thin film transistor T11 is electrically connected to the stage signal output terminal ST of the nm-level GOA circuit. (nm), a drain of the first thin film transistor T11 is electrically connected to a gate signal output terminal G (nq) of the nq-level GOA circuit, and a source of the first thin film transistor T11 is electrically connected to The gate signal point Q (n) of the n-th GOA circuit is described.

Continuing to refer to FIG. 3, the pull-up unit 3 includes a third thin film transistor T21, wherein a gate of the third thin film transistor T21 is electrically connected to a gate signal point Q of the n-th GOA circuit ( n), a source of the third thin film transistor T21 is electrically connected to a gate signal output terminal G (n) of the n-th GOA circuit, and a drain of the third thin film transistor T21 is electrically connected to a Clock signal CK1 / CK5.

Continuing to refer to FIG. 3, the download unit 4 includes a second thin film transistor T22, wherein a gate of the second thin film transistor T22 is electrically connected to a gate signal point Q of the n-th GOA circuit ( n), a source of the second thin film transistor T22 is electrically connected to the stage signal output terminal ST (n) of the n-th GOA circuit, and a drain of the second thin film transistor T22 is electrically connected to a clock signal CK1 / CK5.

Continuing to refer to FIG. 3, the pull-down unit 5 includes a fourth thin film transistor T41 and a fifth thin film transistor T31. A gate of the fourth thin film transistor T41 is electrically connected to the n + q-th GOA circuit. A gate signal output terminal G (n + 4), a drain of the fourth thin film transistor T41 is electrically connected to a gate signal point Q (n) of the n-th GOA circuit, and the fourth thin film transistor A source of T41 is electrically connected to the working voltage VSS. In addition, a gate of the fifth thin film transistor T31 is connected to a gate signal output terminal G (n + 4) of the n + q-th GOA circuit, and a drain of the fifth thin film transistor T31 is electrically connected to the gate. A gate signal output terminal G (n), a source of the fifth thin film transistor T31 is electrically connected to the working voltage VSS.

Continuing to refer to FIG. 3, the pull-down sustaining unit 6 includes a sixth thin film transistor T32, a seventh thin film transistor T42, an eighth thin film transistor T51, a ninth thin film transistor T53, a tenth thin film transistor T52, and a An eleventh thin film transistor T54; a gate of the sixth thin film transistor T32 is electrically connected to a node P (n) of the n-th GOA circuit, and a source of the sixth thin film transistor T32 is electrically connected to The gate signal output terminal G (n), a drain of the sixth thin film transistor T32 is electrically connected to the working voltage VSS, and a gate of the seventh thin film transistor T42 is electrically connected to the node P ( n), a source of the seventh thin film transistor T42 is electrically connected to a gate signal point Q (n) of the n-th GOA circuit, and a drain of the seventh thin film transistor T42 is electrically connected to the Operating voltage VSS; a gate of the eighth thin film transistor T51 is electrically connected to a signal terminal LC, a source of the eighth thin film transistor T51 is electrically connected to the signal terminal LC, and the eighth thin film transistor T51 A drain is electrically connected to a gate of a fourth thin film transistor T53; A source of the thin film transistor T53 is electrically connected to the signal terminal LC, a drain of the ninth thin film transistor T53 is electrically connected to the node P (n), and a gate of the tenth thin film transistor T52 is electrically connected to the signal terminal LC. A gate signal point Q (n) of the n-th GOA circuit is electrically connected, a source of the tenth thin film transistor T52 is electrically connected to the operating voltage (VSS), and one of the tenth thin film transistor T52 is A drain is electrically connected to the gate of the fourth thin film transistor T53; a gate of the eleventh thin film transistor T54 is electrically connected to a gate signal point Q (n) of the n-th GOA circuit; A source of the eleventh thin film transistor T54 is electrically connected to the working voltage VSS, and a drain of the eleventh thin film transistor T54 is electrically connected to the node P (n).

According to the above structure, the gate signal of the first thin film transistor T11 of the pull-up control unit 2 is changed from the existing stage signal output terminal ST (n-4) to the stage signal output terminal ST (n- 3), and the additional thin film transistor T23 is further provided, wherein the gate of the additional thin film transistor T23 is electrically connected to the control signal terminal P (n-3), and the source of the additional thin film transistor T23 is electrically Is connected to the stage signal output terminal ST (n-3), and the drain of the additional thin film transistor T23 is electrically connected to the operating voltage VSS, so that the gate signal point Q (n) potential drop can be prevented from affecting the first The turning on of the three thin film transistors T21 further reduces the interference with the output waveform of the gate signal output terminal G (n). In addition, the effective turning off of the first thin film transistor T11 can be maintained, thereby improving the gate signal The stability of the potential at point Q (n).

Further, as shown in FIG. 4, in order to avoid the current stage signal output terminal ST (n-4) and the gate signal output terminal G (n-4) of the n-4th stage GOA circuit being reduced at the same time, The potential of the gate signal point Q (n) decreases, so that the gate signal of the first thin film transistor T11 is changed from the existing stage signal output terminal ST (n-4) to the stage signal output terminal ST ( n-3), so that the stage signal output terminal ST (n-3) will be lowered before the gate signal output terminal G (n-4). At this time, the first thin film transistor T11 is completely turned off. The potential of the gate signal output terminal G (n-4) does not affect the potential of the gate signal point Q (n). When the gate signal point Q (n) is at a low potential, the stage signal output terminal ST (n) of the n-th GOA circuit is always in an uncontrolled state, and will be subject to capacitive coupling or leakage current from other signals. This will cause the potential of the stage signal output terminal ST (n) of the n-th GOA circuit to be abnormal, thereby affecting the stability of the Q-point waveform. To this end, the additional thin film transistor T23 is added, and as shown in FIG. 5, when the stage signal output terminal ST (n-3) is at a high potential, the control signal terminal P (n-3) is at a low potential, The additional thin film transistor T23 is in an off state. When the stage signal output terminal ST (n-3) is at a low potential, the control signal terminal P (N-3) will continue to be low for a period of time and then become high. Potential, the additional thin film transistor T23 is turned on, and the stage signal output terminal ST (n-3) is continuously pulled down by the operating voltage VSS, thereby maintaining the stability of the low-potential signal and further improving the gate signal point The stability of the potential of Q (n).

As described above, by providing the additional thin film transistor T23 and electrically connecting the control signal terminal P (n-3) to the gate of the additional thin film transistor T23, the gate signal point Q (n can be avoided ) The potential drop affects the turning on of the third thin film transistor T21, thereby reducing the situation that the output waveform of the gate signal output terminal G (n) is disturbed. In addition, the effective turning off of the first thin film transistor T11 can be maintained. Thereby, the stability of the potential of the gate signal point Q (n) is improved.

The present invention has been described by the above related embodiments, but the above embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equal arrangements included in the spirit and scope of the claims are all included in the scope of the present invention.

Claims

A GOA circuit structure, wherein the GOA circuit structure is a plurality of cascaded GOA circuits, and the n-th GOA circuit includes a pull-up control unit, a pull-up unit, a pass-through unit, a pull-down unit, and a A pull-up sustaining unit and an additional thin film transistor (T23); wherein the pull-up unit, the download unit, the pull-down unit and the pull-down sustain unit and a gate signal output terminal (G ( n)) Electrical connection, n is a natural number; the pull-up control unit, the download unit, the pull-down unit, and the pull-down sustain unit and the gate signal point (Q (n) of the n-th GOA circuit) ) Is electrically connected; a gate of the additional thin film transistor (T23) is electrically connected to a control signal terminal (P (nm)) of the nm-level GOA circuit, and m is a natural number; A drain is electrically connected to a working voltage (VSS); a source of the additional thin film transistor (T23) is electrically connected to a first-level signal output terminal (ST (nm)) of a nm-level GOA circuit; the above The control unit is electrically connected to a gate signal output terminal (G (nq)) of the nq-th GOA circuit, where q is a natural number; GOA n-th stage circuit of the charge level n horizontal scanning lines is controlled.
The GOA circuit structure according to claim 1, wherein: the gate of the additional thin film transistor (T23) is electrically connected to the control signal terminal (P (n-3)) of the n-3th GOA circuit; the additional The source of the thin film transistor (T23) is electrically connected to the stage signal output end (ST (n-3)) of the GOA circuit at the nm level; the pull-up control unit is electrically connected to the gate of the GOA circuit at the n-4 level. Signal output (G (n-4)).
The GOA circuit structure according to claim 2, wherein when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is a high potential, the control signal terminal of the n-3th stage GOA circuit (P (n-3)) is a low potential, so that the additional thin film transistor (T23) is in an off state.
The GOA circuit structure according to claim 2, wherein when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is a low potential, the control signal terminal of the n-3th stage GOA circuit (P (n-3)) lasts for a time, a low potential, and then becomes a high potential, so that the additional thin film transistor (T23) is in an on state.
The GOA circuit structure according to claim 1, wherein the download unit comprises: a second thin film transistor (T22), and a gate of the second thin film transistor (T22) is electrically connected to the nth stage A gate signal point (Q (n)) of the GOA circuit, a source of the second thin film transistor (T22) is electrically connected to a stage signal output terminal (ST (n)) of the n-th GOA circuit, A drain of the second thin film transistor (T22) is electrically connected to a clock signal (CK1 / CK5).
The GOA circuit structure according to claim 1, wherein the pull-up unit comprises: a third thin film transistor (T21), and a gate of the third thin film transistor (T21) is electrically connected to the nth stage A gate signal point (Q (n)) of the GOA circuit, a source of the third thin film transistor (T21) is electrically connected to a gate signal output terminal (G (n)) of the n-th GOA circuit, A drain of the third thin film transistor (T21) is electrically connected to a clock signal (CK1 / CK5).
The GOA circuit structure of claim 1, wherein the pull-down unit comprises:

A fourth thin film transistor (T41), a gate of the fourth thin film transistor (T41) is electrically connected to a gate signal output terminal (G (n + 4)) of the n + q level GOA circuit, and A drain of the fourth thin film transistor (T41) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and a source of the fourth thin film transistor (T41) is electrically connected to The operating voltage (VSS); and

A fifth thin film transistor (T31), a gate of the fifth thin film transistor (T31) is connected to a gate signal output terminal (G (n + 4)) of the n + q level GOA circuit, and the fifth thin film A drain of the transistor (T31) is electrically connected to the gate signal output terminal (G (n)), and a source of the fifth thin film transistor (T31) is electrically connected to the operating voltage (VSS).
The GOA circuit structure according to claim 1, wherein the pull-down maintaining unit comprises:

A sixth thin film transistor (T32), a gate of the sixth thin film transistor (T32) is electrically connected to a node (P (n)) of the n-th GOA circuit, and the sixth thin film transistor (T32) A source is electrically connected to the gate signal output terminal (G (n)), and a drain of the sixth thin film transistor (T32) is electrically connected to the operating voltage (VSS);

A seventh thin film transistor (T42), a gate of the seventh thin film transistor (T42) is electrically connected to the node (P (n)), and a source of the seventh thin film transistor (T42) is electrically Connected to a gate signal point (Q (n)) of the n-th GOA circuit, and a drain of the seventh thin film transistor (T42) is electrically connected to the operating voltage (VSS);

An eighth thin film transistor (T51), a gate of the eighth thin film transistor (T51) is electrically connected to a signal terminal (LC), and a source of the eighth thin film transistor (T51) is electrically connected to the A signal terminal (LC), a drain of the eighth thin film transistor (T51) is electrically connected to a gate of a fourth thin film transistor (T53);

A ninth thin film transistor (T53), a source of the ninth thin film transistor (T53) is electrically connected to the signal terminal (LC), and a ninth thin film transistor (T53) is electrically connected to a drain述 node (P (n));

A tenth thin film transistor (T52), a gate of the tenth thin film transistor (T52) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, the tenth thin film transistor A source of (T52) is electrically connected to the operating voltage (VSS), and a drain of the tenth thin film transistor (T52) is electrically connected to a gate of the fourth thin film transistor (T53); and

An eleventh thin film transistor (T54), a gate of the eleventh thin film transistor (T54) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and the tenth A source of a thin film transistor (T54) is electrically connected to the working voltage (VSS), and a drain of the eleventh thin film transistor (T54) is electrically connected to the node (P (n)).
The GOA circuit structure according to claim 1, wherein the pull-up control unit includes a first thin film transistor (T11), and a gate of the first thin film transistor (T11) is electrically connected to the nm-level GOA circuit A stage signal output terminal (ST (nm)), a drain of the first thin film transistor (T11) is electrically connected to a gate signal output terminal (G (nq)) of the nq-th GOA circuit, A source of the first thin film transistor (T11) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit.
The GOA circuit structure according to claim 1, wherein the GOA circuit further comprises a bootstrap capacitor, and the bootstrap capacitor is electrically connected to a gate signal point (Q (n) of the n-th GOA circuit). ) And the gate signal output terminal (G (n)) of the n-th GOA circuit.
A GOA circuit structure, wherein the GOA circuit structure is a plurality of cascaded GOA circuits, and the n-th GOA circuit includes a pull-up control unit, a pull-up unit, a pass-through unit, a pull-down unit, and a A pull-up sustaining unit and an additional thin film transistor (T23); wherein the pull-up unit, the download unit, the pull-down unit and the pull-down sustain unit and a gate signal output terminal (G ( n)) Electrical connection, n is a natural number; the pull-up control unit, the download unit, the pull-down unit, and the pull-down sustain unit and the gate signal point (Q (n) of the n-th GOA circuit) ) Is electrically connected; a gate of the additional thin film transistor (T23) is electrically connected to a control signal terminal (P (nm)) of the nm-level GOA circuit, and m is a natural number; A drain is electrically connected to a working voltage (VSS); a source of the additional thin film transistor (T23) is electrically connected to a first-level signal output terminal (ST (nm)) of a nm-level GOA circuit; the above The pull control unit is electrically connected to a gate signal output terminal (G (nq)) of the nq-th GOA circuit, where q is a natural number.
The GOA circuit structure according to claim 11, wherein: the gate of the additional thin film transistor (T23) is electrically connected to the control signal terminal (P (n-3)) of the n-3th GOA circuit; the additional The source of the thin film transistor (T23) is electrically connected to the stage signal output end (ST (n-3)) of the GOA circuit at the nm level; the pull-up control unit is electrically connected to the gate of the GOA circuit at the n-4 level. Signal output (G (n-4)).
The GOA circuit structure according to claim 12, wherein when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is a high potential, the control signal terminal of the n-3th stage GOA circuit (P (n-3)) is a low potential, so that the additional thin film transistor (T23) is in an off state.
The GOA circuit structure according to claim 12, wherein when the stage signal output terminal (ST (n-3)) of the nm-th stage GOA circuit is a low potential, the control signal terminal of the n-3th stage GOA circuit (P (n-3)) lasts for a time, a low potential, and then becomes a high potential, so that the additional thin film transistor (T23) is in an on state.
The GOA circuit structure according to claim 11, wherein the download unit includes: a second thin film transistor (T22), and a gate of the second thin film transistor (T22) is electrically connected to the nth stage A gate signal point (Q (n)) of the GOA circuit, a source of the second thin film transistor (T22) is electrically connected to a stage signal output terminal (ST (n)) of the n-th GOA circuit, A drain of the second thin film transistor (T22) is electrically connected to a clock signal (CK1 / CK5).
The GOA circuit structure according to claim 11, wherein the pull-up unit comprises: a third thin film transistor (T21), and a gate of the third thin film transistor (T21) is electrically connected to the nth stage A gate signal point (Q (n)) of the GOA circuit, a source of the third thin film transistor (T21) is electrically connected to a gate signal output terminal (G (n)) of the n-th GOA circuit, A drain of the third thin film transistor (T21) is electrically connected to a clock signal (CK1 / CK5).
The GOA circuit structure according to claim 11, wherein the pull-down unit comprises:

A fourth thin film transistor (T41), a gate of the fourth thin film transistor (T41) is electrically connected to a gate signal output terminal (G (n + 4)) of the n + q level GOA circuit, and A drain of the fourth thin film transistor (T41) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and a source of the fourth thin film transistor (T41) is electrically connected to The operating voltage (VSS); and

A fifth thin film transistor (T31), a gate of the fifth thin film transistor (T31) is connected to a gate signal output terminal (G (n + 4)) of the n + q level GOA circuit, and the fifth thin film A drain of the transistor (T31) is electrically connected to the gate signal output terminal (G (n)), and a source of the fifth thin film transistor (T31) is electrically connected to the operating voltage (VSS).
The GOA circuit structure according to claim 11, wherein the pull-down maintaining unit comprises:

A sixth thin film transistor (T32), a gate of the sixth thin film transistor (T32) is electrically connected to a node (P (n)) of the n-th GOA circuit, and the sixth thin film transistor (T32) A source is electrically connected to the gate signal output terminal (G (n)), and a drain of the sixth thin film transistor (T32) is electrically connected to the operating voltage (VSS);

A seventh thin film transistor (T42), a gate of the seventh thin film transistor (T42) is electrically connected to the node (P (n)), and a source of the seventh thin film transistor (T42) is electrically Connected to a gate signal point (Q (n)) of the n-th GOA circuit, and a drain of the seventh thin film transistor (T42) is electrically connected to the operating voltage (VSS);

An eighth thin film transistor (T51), a gate of the eighth thin film transistor (T51) is electrically connected to a signal terminal (LC), and a source of the eighth thin film transistor (T51) is electrically connected to the A signal terminal (LC), a drain of the eighth thin film transistor (T51) is electrically connected to a gate of a fourth thin film transistor (T53);

A ninth thin film transistor (T53), a source of the ninth thin film transistor (T53) is electrically connected to the signal terminal (LC), and a ninth thin film transistor (T53) is electrically connected to a drain述 node (P (n));

A tenth thin film transistor (T52), a gate of the tenth thin film transistor (T52) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, the tenth thin film transistor A source of (T52) is electrically connected to the operating voltage (VSS), and a drain of the tenth thin film transistor (T52) is electrically connected to a gate of the fourth thin film transistor (T53); and

An eleventh thin film transistor (T54), a gate of the eleventh thin film transistor (T54) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit, and the tenth A source of a thin film transistor (T54) is electrically connected to the working voltage (VSS), and a drain of the eleventh thin film transistor (T54) is electrically connected to the node (P (n)).
The GOA circuit structure according to claim 11, wherein the pull-up control unit comprises a first thin film transistor (T11), and a gate of the first thin film transistor (T11) is electrically connected to the nm-level GOA circuit A stage signal output terminal (ST (nm)), a drain of the first thin film transistor (T11) is electrically connected to a gate signal output terminal (G (nq)) of the nq-th GOA circuit, A source of the first thin film transistor (T11) is electrically connected to a gate signal point (Q (n)) of the n-th GOA circuit.
The GOA circuit structure according to claim 11, wherein the GOA circuit further comprises a bootstrap capacitor, and the bootstrap capacitor is electrically connected to a gate signal point (Q (n) of the n-th GOA circuit). ) And the gate signal output terminal (G (n)) of the n-th GOA circuit.