WO2020056958A1 - 显示面板线路结构及显示面板 - Google Patents

显示面板线路结构及显示面板 Download PDF

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Publication number
WO2020056958A1
WO2020056958A1 PCT/CN2018/122347 CN2018122347W WO2020056958A1 WO 2020056958 A1 WO2020056958 A1 WO 2020056958A1 CN 2018122347 W CN2018122347 W CN 2018122347W WO 2020056958 A1 WO2020056958 A1 WO 2020056958A1
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Prior art keywords
circuit
display panel
pin
line
connection terminal
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PCT/CN2018/122347
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English (en)
French (fr)
Inventor
欧阳峰
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US16/317,291 priority Critical patent/US20210327918A1/en
Publication of WO2020056958A1 publication Critical patent/WO2020056958A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel circuit structure and a display panel.
  • the wiring mode of the display panel circuit structure is to meet the requirements of narrow line widths. Due to the narrowing of the distance between them, short circuits are prone to occur.
  • the wiring pattern of the display panel circuit structure meets the requirements of a narrow line width, and adjacent lines are affected by the narrowing of the distance, which is prone to short circuit.
  • an object of the present disclosure is to provide a display panel circuit structure and a display panel, which can prevent the display panel circuit structure from occurring through the first circuit and at least one second circuit pin located on different planes. Short circuit, improve wiring yield.
  • the present disclosure provides a circuit structure of a display panel.
  • the display panel includes an array substrate.
  • the array substrate includes a display area and a peripheral area surrounding the display area.
  • the display panel circuit structure is disposed in the peripheral region of the array substrate and includes a first circuit and a second circuit.
  • the first line includes at least one first line pin and at least one first connection terminal connected to the at least one first line pin.
  • the second line includes at least one second line pin and at least one second connection terminal connected to the at least one second line pin.
  • the first line and the at least one second line pin are located on different layers. flat.
  • the first circuit and the at least one second circuit pin are located on planes parallel to each other.
  • the at least one second circuit pin is located on a lower plane, and the upper plane is located above the lower plane.
  • the at least one second line pin includes at least one foot and at least one connection section connected to the at least one foot. An angle is formed between the at least one foot and the at least one connection section.
  • the included angle is substantially equal to 90 degrees.
  • a length of the at least one connection segment is substantially equal to a distance between the first line and the at least one second line pin.
  • the at least one second connection terminal is connected to the at least one connection section.
  • the at least one first connection terminal and the at least one second connection terminal are located on the same plane.
  • the at least one first connection terminal and the at least one second connection terminal are staggered.
  • the disclosure also provides a display panel circuit structure.
  • the display panel includes an array substrate.
  • the array substrate includes a display area and a peripheral area surrounding the display area.
  • the display panel circuit structure is disposed in the peripheral region of the array substrate and includes a first circuit and a second circuit.
  • the first line includes at least one first line pin and at least one first connection terminal connected to the at least one first line pin.
  • the second line includes at least one second line pin and at least one second connection terminal connected to the at least one second line pin.
  • the first line and the at least one second line pin are located on different layers. flat.
  • the first circuit and the at least one second circuit pin are located on planes parallel to each other.
  • the first circuit is located on an upper plane
  • the at least one second circuit pin is located on a lower plane
  • the upper plane is located above the lower plane
  • the at least one second circuit pin includes at least one foot and at least one connection segment connected to the at least one foot, and the at least one foot is connected to the at least one An angle is formed between the segments.
  • the included angle is substantially equal to 90 degrees.
  • a length of the at least one connection segment is substantially equal to a distance between the first line and the at least one second line pin.
  • the at least one second connection terminal is connected to the at least one connection section.
  • the at least one first connection terminal and the at least one second connection terminal are located on the same plane.
  • the at least one first connection terminal and the at least one second connection terminal are staggered.
  • the present disclosure also provides a display panel including an array substrate and the above-mentioned display panel circuit structure.
  • the array substrate includes a display area and a peripheral area surrounding the display area.
  • the display panel circuit structure and the display panel in the embodiments of the present disclosure avoid the display panel circuit through the first circuit and at least one second circuit pin located on different planes Short circuit occurs in the structure, which improves the yield of wiring.
  • FIG. 1 is a schematic structural diagram of a display panel circuit structure according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a display panel circuit structure according to an embodiment of the disclosure.
  • a display panel 10 includes an array substrate 100 and a display panel circuit structure 200.
  • the array substrate 100 includes a display area 110 and a peripheral area 120 surrounding the display area 110.
  • the display panel circuit structure 200 is disposed in the peripheral region 120 of the array substrate 100 and includes a first circuit 210 and a second circuit 220.
  • the first circuit 210 includes at least one first circuit pin 212 and at least one first connection terminal 214 connected to the at least one first circuit pin 212.
  • the second line 220 includes at least one second line pin 222 and at least one second connection terminal 224 connected to the at least one second line pin 222.
  • the first line 210 and the at least one second line pin 222 are located on different planes. Since the display panel circuit structure 200 in the embodiment of the present disclosure uses the first circuit 210 and at least one second circuit pin 222 located on different planes, short circuit of the display panel circuit structure 200 is avoided, and the wiring yield is improved.
  • the first circuit 210 and the at least one second circuit pin 222 are located on planes parallel to each other.
  • the first circuit 210 is located on an upper plane
  • at least one second circuit pin 222 is located on a lower plane
  • the upper plane is located above the lower plane.
  • the at least one second circuit pin 222 includes at least one foot 2222 and at least one connecting section 2224 connected to the at least one foot 2222.
  • An angle is formed between the at least one foot 2222 and the at least one connecting section 2224. The included angle is, for example, approximately equal to 90 degrees.
  • the length of the at least one connection segment 2224 is substantially equal to the distance between the first line 210 and the at least one second line pin 222.
  • At least one second connection terminal 224 is connected to at least one connection section 2224.
  • the at least one first connection terminal 214 and the at least one second connection terminal 224 are located on the same plane.
  • At least one first connection terminal 214 and at least one second connection terminal 224 are staggered.
  • at least one first connection terminal 214 and at least one second connection terminal 224 are staggered in the first direction, and at least one first connection terminal 214 and at least one second connection terminal 224 are arranged back and forth in the second direction.
  • the first direction is perpendicular to the second direction.
  • the at least one first line pin 212 is a plurality of first line pins 212 and the at least one second line pin 222 is a plurality of second line pins 222. Since the first circuit 210 and the at least one second circuit pin 222 are located on different planes in the embodiment of the present disclosure, the at least one first circuit pin 212 is a plurality of first circuit pins 212, so the first circuit 210 and the At least one second line pin 222 is separated. Therefore, a distance between each first line pin 212 and an adjacent first line pin 212 can be increased and each second line pin 222 and an adjacent first line pin 222 can be increased. The distance between the two line pins 222 can be increased, thereby reducing the process capability requirements of the panel wiring equipment.
  • the display panel circuit structure in the embodiment of the present disclosure can be applied to a high-resolution display panel and a wiring requirement that meets a narrow line width, and the actual application demand is high.
  • the display panel in the embodiment of the present disclosure has high resolution and meets the wiring requirements of narrow line width, and has high practical application requirements.
  • the first circuit and the at least one second circuit are effectively connected by the first circuit and the at least one second circuit pin located on different planes.
  • the pins are separated to avoid short circuit of the display panel circuit structure and improve the wiring yield.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板线路结构（200）及显示面板（10）。显示面板（10）包括阵列基板（100）。阵列基板（100）包括显示区（110）与围绕显示区的周边区（120）。显示面板线路结构（200）设置于阵列基板（100）的周边区（120）内且包括第一线路（210）及第二线路（220）。第二线路（220）包括至少一第二线路引脚（222）及至少一第二连接端子（224）。第一线路（210）与至少一第二线路引脚（222）位于不同层平面。

Description

显示面板线路结构及显示面板 技术领域
本揭示涉及一种显示技术领域，特别涉及一种显示面板线路结构及显示面板。
 背景技术
随着显示技术发展，用户对产品分辨率要求越来越高，高分辨率要求布线更密，在现有技术中，显示面板线路结构的布线模式，为符合窄线宽的需求，相邻线路之间受间距缩窄影响，容易发生短路。
故，有需要提供一种显示面板线路结构及显示面板，以解决现有技术存在的问题。
 技术问题
在现有技术中，显示面板线路结构的布线模式，为符合窄线宽的需求，相邻线路之间受间距缩窄影响，容易发生短路。
 技术解决方案
为解决上述技术问题，本揭示的一种目的在于提供一种显示面板线路结构及显示面板，其能通过位于不同层平面的第一线路与至少一第二线路引脚，避免显示面板线路结构发生短路，提升布线良率。
为达成上述目的，本揭示提供一显示面板线路结构。显示面板包括阵列基板。所述阵列基板包括显示区与围绕所述显示区的周边区。所述显示面板线路结构设置于所述阵列基板的所述周边区内且包括第一线路以及第二线路。所述第一线路包括至少一第一线路引脚及连接所述至少一第一线路引脚的至少一第一连接端子。所述第二线路包括至少一第二线路引脚及连接所述至少一第二线路引脚的至少一第二连接端子，所述第一线路与所述至少一第二线路引脚位于不同层平面。所述第一线路与所述至少一第二线路引脚位于互相平行的平面。所述至少一第二线路引脚位于下层平面，以及所述上层平面位于所述下层平面的上方。所述至少一第二线路引脚包括至少一底脚及连接所述至少一底脚的至少一连接段，所述至少一底脚与所述至少一连接段之间形成夹角。
于本揭示其中的一实施例中，所述夹角大致等于90度。
于本揭示其中的一实施例中，所述至少一连接段的长度大致等于所述第一线路与所述至少一第二线路引脚之间的距离。
于本揭示其中的一实施例中，所述至少一第二连接端子连接所述至少一连接段。
于本揭示其中的一实施例中，所述至少一第一连接端子与所述至少一第二连接端子位于同一平面。
于本揭示其中的一实施例中，所述至少一第一连接端子与所述至少一第二连接端子交错排列。
本揭示还提供一显示面板线路结构。显示面板包括阵列基板。所述阵列基板包括显示区与围绕所述显示区的周边区。所述显示面板线路结构设置于所述阵列基板的所述周边区内且包括第一线路以及第二线路。所述第一线路包括至少一第一线路引脚及连接所述至少一第一线路引脚的至少一第一连接端子。所述第二线路包括至少一第二线路引脚及连接所述至少一第二线路引脚的至少一第二连接端子，所述第一线路与所述至少一第二线路引脚位于不同层平面。
于本揭示其中的一实施例中，所述第一线路与所述至少一第二线路引脚位于互相平行的平面。
于本揭示其中的一实施例中，所述第一线路位于上层平面，所述至少一第二线路引脚位于下层平面，以及所述上层平面位于所述下层平面的上方。
于本揭示其中的一实施例中，所述至少一第二线路引脚包括至少一底脚及连接所述至少一底脚的至少一连接段，所述至少一底脚与所述至少一连接段之间形成夹角。
于本揭示其中的一实施例中，所述夹角大致等于90度。
于本揭示其中的一实施例中，所述至少一连接段的长度大致等于所述第一线路与所述至少一第二线路引脚之间的距离。
于本揭示其中的一实施例中，所述至少一第二连接端子连接所述至少一连接段。
于本揭示其中的一实施例中，所述至少一第一连接端子与所述至少一第二连接端子位于同一平面。
于本揭示其中的一实施例中，所述至少一第一连接端子与所述至少一第二连接端子交错排列。
本揭示还提供一显示面板包括阵列基板以及上述的显示面板线路结构。所述阵列基板包括显示区与围绕所述显示区的周边区。
 有益效果
相较于现有技术，为解决上述技术问题，本揭示的实施例中的显示面板线路结构及显示面板，通过位于不同层平面的第一线路与至少一第二线路引脚，避免显示面板线路结构发生短路，提升布线良率。
 附图说明
图1显示根据本揭示的一实施例的显示面板线路结构的结构示意图；以及
图2显示根据本揭示的一实施例的显示面板线路结构的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为让本揭示的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1及图2，本揭示的实施例的显示面板10包括阵列基板100以及显示面板线路结构200。阵列基板100包括显示区110与围绕显示区110的周边区120。显示面板线路结构200设置于阵列基板100的周边区120内且包括第一线路210以及第二线路220。第一线路210包括至少一第一线路引脚212及连接至少一第一线路引脚212的至少一第一连接端子214。第二线路220包括至少一第二线路引脚222及连接至少一第二线路引脚222的至少一第二连接端子224，第一线路210与至少一第二线路引脚222位于不同层平面。由于本揭示的实施例中的显示面板线路结构200通过位于不同层平面的第一线路210与至少一第二线路引脚222，避免显示面板线路结构200发生短路，提升布线良率。
具体地，第一线路210与至少一第二线路引脚222位于互相平行的平面。例如第一线路210位于上层平面，至少一第二线路引脚222位于下层平面，以及上层平面位于下层平面的上方。
具体地，至少一第二线路引脚222包括至少一底脚2222及连接至少一底脚2222的至少一连接段2224，至少一底脚2222与至少一连接段2224之间形成夹角。所述夹角例如大致等于90度。
具体地，至少一连接段2224的长度大致等于第一线路210与至少一第二线路引脚222之间的距离。至少一第二连接端子224连接至少一连接段2224。至少一第一连接端子214与至少一第二连接端子224位于同一平面。至少一第一连接端子214与至少一第二连接端子224交错排列。详细而言，例如至少一第一连接端子214与至少一第二连接端子224在第一方向上交错排列，至少一第一连接端子214与至少一第二连接端子224在第二方向上前后排列，第一方向与第二方向垂直。
具体地，至少一第一线路引脚212为多个第一线路引脚212及至少一第二线路引脚222为多个第二线路引脚222。由于本揭示的实施例中的第一线路210与至少一第二线路引脚222位于不同层平面至少一第一线路引脚212为多个第一线路引脚212，有效将第一线路210与至少一第二线路引脚222分开，因此，每一第一线路引脚212与相邻的第一线路引脚212之间的间距可以增加及每一第二线路引脚222与相邻的第二线路引脚222之间的间距可以增加，从而降低面板布线设备的制程能力要求。
本揭示的实施例中的显示面板线路结构能应用于高分辨率的显示面板及符合窄线宽的布线要求，实际应用需求高。本揭示的实施例中的显示面板具有高分辨率及符合窄线宽的布线要求，实际应用需求高。
综上所述，由于本揭示的实施例中的显示面板线路结构及显示面板，通过位于不同层平面的第一线路与至少一第二线路引脚，有效将第一线路与至少一第二线路引脚分开，避免显示面板线路结构发生短路，提升布线良率。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种显示面板线路结构，显示面板包括阵列基板，所述阵列基板包括显示区与围绕所述显示区的周边区，所述显示面板线路结构设置于所述阵列基板的所述周边区内且包括：
    第一线路，包括至少一第一线路引脚及连接所述至少一第一线路引脚的至少一第一连接端子；以及
    第二线路，包括至少一第二线路引脚及连接所述至少一第二线路引脚的至少一第二连接端子，所述第一线路与所述至少一第二线路引脚位于不同层平面；
    其中所述第一线路与所述至少一第二线路引脚位于互相平行的平面；
    其中所述第一线路位于上层平面，所述至少一第二线路引脚位于下层平面，以及所述上层平面位于所述下层平面的上方；
    其中所述至少一第二线路引脚包括至少一底脚及连接所述至少一底脚的至少一连接段，所述至少一底脚与所述至少一连接段之间形成夹角。
  2. 根据权利要求1所述的显示面板线路结构，其中所述夹角大致等于90度。
  3. 根据权利要求2所述的显示面板线路结构，其中所述至少一连接段的长度大致等于所述第一线路与所述至少一第二线路引脚之间的距离。
  4. 根据权利要求1所述的显示面板线路结构，其中所述至少一第二连接端子连接所述至少一连接段。
  5. 根据权利要求4所述的显示面板线路结构，其中所述至少一第一连接端子与所述至少一第二连接端子位于同一平面。
  6. 根据权利要求5所述的显示面板线路结构，其中所述至少一第一连接端子与所述至少一第二连接端子交错排列。
  7. 一种显示面板线路结构，显示面板包括阵列基板，所述阵列基板包括显示区与围绕所述显示区的周边区，所述显示面板线路结构设置于所述阵列基板的所述周边区内且包括：
    第一线路，包括至少一第一线路引脚及连接所述至少一第一线路引脚的至少一第一连接端子；以及
    第二线路，包括至少一第二线路引脚及连接所述至少一第二线路引脚的至少一第二连接端子，所述第一线路与所述至少一第二线路引脚位于不同层平面。
  8. 根据权利要求7所述的显示面板线路结构，其中所述第一线路与所述至少一第二线路引脚位于互相平行的平面。
  9. 根据权利要求8所述的显示面板线路结构，其中所述第一线路位于上层平面，所述至少一第二线路引脚位于下层平面，以及所述上层平面位于所述下层平面的上方。
  10.     根据权利要求7所述的显示面板线路结构，其中所述至少一第二线路引脚包括至少一底脚及连接所述至少一底脚的至少一连接段，所述至少一底脚与所述至少一连接段之间形成夹角。
  11.      根据权利要求10所述的显示面板线路结构，其中所述夹角大致等于90度。
  12.     根据权利要求11所述的显示面板线路结构，其中所述至少一连接段的长度大致等于所述第一线路与所述至少一第二线路引脚之间的距离。
  13.     根据权利要求10所述的显示面板线路结构，其中所述至少一第二连接端子连接所述至少一连接段。
  14.     根据权利要求13所述的显示面板线路结构，其中所述至少一第一连接端子与所述至少一第二连接端子位于同一平面。
  15.     根据权利要求14所述的显示面板线路结构，其中所述至少一第一连接端子与所述至少一第二连接端子交错排列。
  16.     一种显示面板，包括：
    阵列基板，包括显示区与围绕所述显示区的周边区；以及
    显示面板线路结构，所述显示面板线路结构设置于所述阵列基板的所述周边区内且包括：
    第一线路，包括至少一第一线路引脚及连接所述至少一第一线路引脚的至少一第一连接端子；以及
    第二线路，包括至少一第二线路引脚及连接所述至少一第二线路引脚的至少一第二连接端子，所述第一线路与所述至少一第二线路引脚位于不同层平面。
  17.     根据权利要求16所述的显示面板，其中所述第一线路与所述至少一第二线路引脚位于互相平行的平面。
  18.     根据权利要求17所述的显示面板，其中所述第一线路位于上层平面，所述至少一第二线路引脚位于下层平面，以及所述上层平面位于所述下层平面的上方。
  19.     根据权利要求16所述的显示面板，其中所述至少一第二线路引脚包括至少一底脚及连接所述至少一底脚的至少一连接段，所述至少一底脚与所述至少一连接段之间形成夹角。
  20.     根据权利要求19所述的显示面板，其中所述夹角大致等于90度。
PCT/CN2018/122347 2018-09-17 2018-12-20 显示面板线路结构及显示面板 WO2020056958A1 (zh)

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KR20080098996A (ko) * 2007-05-08 2008-11-12 삼성전자주식회사 액정 표시 장치
CN101487937A (zh) * 2009-02-25 2009-07-22 友达光电股份有限公司 平面显示器
CN102290416A (zh) * 2011-07-23 2011-12-21 华映光电股份有限公司 平面显示面板的数组基板
CN206541551U (zh) * 2017-02-24 2017-10-03 厦门天马微电子有限公司 显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080098996A (ko) * 2007-05-08 2008-11-12 삼성전자주식회사 액정 표시 장치
CN101487937A (zh) * 2009-02-25 2009-07-22 友达光电股份有限公司 平面显示器
CN102290416A (zh) * 2011-07-23 2011-12-21 华映光电股份有限公司 平面显示面板的数组基板
CN206541551U (zh) * 2017-02-24 2017-10-03 厦门天马微电子有限公司 显示面板

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