WO2020056622A1 - 图像校验系数的读取方法、闪存控制器、系统及存储介质 - Google Patents

图像校验系数的读取方法、闪存控制器、系统及存储介质 Download PDF

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Publication number
WO2020056622A1
WO2020056622A1 PCT/CN2018/106472 CN2018106472W WO2020056622A1 WO 2020056622 A1 WO2020056622 A1 WO 2020056622A1 CN 2018106472 W CN2018106472 W CN 2018106472W WO 2020056622 A1 WO2020056622 A1 WO 2020056622A1
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Prior art keywords
flash memory
image check
subset
image
coefficients
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English (en)
French (fr)
Inventor
周俊
陈德坤
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2018/106472 priority Critical patent/WO2020056622A1/zh
Priority to CN201880001521.5A priority patent/CN109313608B/zh
Publication of WO2020056622A1 publication Critical patent/WO2020056622A1/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of data processing, and in particular, to a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium.
  • an image signal processor receives an image collected from an image sensor, and performs processing such as noise reduction and verification on the image.
  • the ISP needs to perform noise reduction and verification on the image through the image verification coefficient.
  • the process by which an ISP obtains an image check coefficient includes: usually the ISP reads the image check coefficient from a buffer (Buffer), and when the image check coefficient in the buffer has been read, the buffer generates an interrupt request. And sends the interrupt request to a central processing unit (CPU), and after receiving the interrupt request, the CPU controls the flash controller (Flash Controller) to read the next image check coefficient from the flash (Flash), The read image check coefficient is stored in the buffer.
  • the cache memory is limited, the internal image check coefficient can be easily read. Based on this, the cache generates interrupt requests very frequently. The CPU needs to process these interrupt requests in real time in order to control the flash memory controller to read the image check coefficient from the flash memory. This will consume a lot of time of the CPU and affect the CPU to process other transactions, that is, the transaction processing efficiency of the CPU.
  • the application provides a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium.
  • the present application provides a method for reading an image check coefficient, comprising: a flash memory controller obtaining an interrupt request sent by a cache; the flash memory controller reading a subset of image check coefficients currently required to be cached from the flash memory according to the interrupt request ; The flash controller stores a subset of the image check coefficients that currently need to be cached into the cache.
  • the CPU can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU.
  • the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • the flash memory controller before the flash memory controller obtains the interrupt request sent by the cache, the flash memory controller further includes: the flash memory controller receives the instruction information sent by the central processing unit; correspondingly, the flash memory controller reads the current cached image check from the flash memory according to the interrupt request
  • the subset of coefficients includes: the flash memory controller reads a subset of image check coefficients that need to be buffered from the flash memory according to the interrupt request and the instruction information.
  • the CPU sends only one instruction message to the flash memory controller, and subsequent flash memory controllers only need to read a subset of the image check coefficients that need to be cached from the flash memory according to the interrupt request and the instruction information.
  • the interrupt request can be prevented.
  • the CPU time is occupied so that the CPU can process other transactions, that is, the transaction processing efficiency of the CPU is improved.
  • the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time.
  • the total length of the factor is: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time.
  • the indication information further includes: a start address of each image check coefficient subset.
  • the flash memory controller reads the current subset of image check coefficients to be cached from the flash memory according to the interrupt request and the instruction information, including: the flash memory controller determines, based on the instruction information, that the current image buffer needs to be cached according to the instruction request.
  • the start address starts to read the data of the total length.
  • the interrupt request includes: a start address of a subset of image check coefficients that currently needs to be cached and a total length of image check coefficients included in the subset of image check coefficients that currently need to be cached; a subset of image check coefficients It is a subset of the image check coefficient set.
  • the image check coefficient set is composed of all the image check coefficients required in the image processing process.
  • the flash memory controller reads the currently checked cached image check from the flash memory according to the interrupt request.
  • the coefficient subset includes: the flash memory controller reads data of the total length from the flash memory, starting from the start address of the image verification coefficient subset that currently needs to be buffered.
  • the flash memory controller before the flash memory controller reads the total length of data from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered, the flash memory controller further includes: the flash memory controller determines the image check coefficients that currently need to be buffered.
  • the total length of data includes: If the start address of the subset of image check coefficients currently required to be cached is less than the end address of the image check coefficient set in the flash memory, the flash memory controller The start address of the subset of test coefficients starts to read the data of the total length.
  • the flash memory controller determines that the start address of the image check coefficient subset that needs to be cached is The starting address of the image check coefficient set in the flash memory.
  • the total length of the image check coefficient included in the image check coefficient subset that needs to be cached is the first image check coefficient subset included in the image check coefficient set.
  • the total length of the image check coefficients in the flash memory controller; starting from the flash memory, the data of the total length of the image check coefficient subsets that need to be buffered is read from the start address of the subset of the image check coefficients that currently need to be buffered. This ensures that when the image check coefficients required for a frame of image have been transmitted, the flash memory controller can still accurately obtain a subset of the image check coefficients that currently need to be cached, thereby improving the reliability of the flash memory controller.
  • the present application provides a flash memory controller, including: the flash memory controller is configured to: obtain an interrupt request sent by a cache; read a subset of image check coefficients that currently need to be cached from the flash memory according to the interrupt request; A subset of the image check coefficients is stored in the cache.
  • the flash memory controller is further configured to: receive instruction information sent by the central processing unit; correspondingly, the flash memory controller is specifically configured to: read the subset of image check coefficients currently required to be cached from the flash memory according to the interrupt request and the instruction information .
  • the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time.
  • the total length of the coefficients; among them, the image check coefficient set is composed of all the image check coefficients required in the image processing process, and the image check coefficient subset is a subset of the image check coefficient set.
  • the indication information further includes: a start address of each image check coefficient subset.
  • the flash memory controller is specifically configured to: under the trigger of the interrupt request, determine the start address of the image check coefficient subset that needs to be cached currently and the image check coefficient subset that needs to be cached according to the instruction information.
  • the total length of the image check coefficient; from the flash memory, the data of the total length is read from the start address of the subset of the image check coefficient that currently needs to be cached.
  • the start address of the subset of image check coefficients that currently needs to be cached and the total length of the image check coefficients included in the subset of image check coefficients that currently need to be cached; the subset of image check coefficients is image verification A subset of the coefficient set.
  • the image check coefficient set is composed of all the image check coefficients required in the image processing process.
  • the flash memory controller is specifically used to: from the flash memory, the image check coefficients that are currently buffered.
  • the start address of the set starts to read the total length of data.
  • the flash memory controller is further configured to: determine whether a start address of a subset of image check coefficients currently required to be cached is smaller than an end address of the image check coefficient set in the flash memory; accordingly, the flash memory controller is specifically configured to: If the start address of the image check coefficient subset that needs to be cached is less than the end address of the image check coefficient set in the flash memory, then read from the flash memory starting from the start address of the image check coefficient subset that currently needs to be cached. Take the total length of the data.
  • the flash memory controller is further configured to: if the start address of the subset of image check coefficients currently required to be cached is greater than or equal to the end address of the set of image check coefficients in the flash memory, determine the currently required cached image check
  • the starting address of the coefficient subset is the starting address of the image verification coefficient set in the flash memory.
  • the total length of the image verification coefficient included in the image verification coefficient subset that needs to be cached is the first in the image verification coefficient set.
  • the total length of the image check coefficients included in the image check coefficient subset; from the flash memory, the data of the total length is read from the start address of the image check coefficient subset that currently needs to be buffered.
  • the present application provides an image check coefficient reading system, including a cache, a flash memory, a central processing unit, and an optional flash memory controller for implementing the first aspect or the first aspect.
  • the system further includes: an image sensor and an image signal processor; the image sensor is configured to acquire an image; the image signal processor is configured to acquire an image acquired by the image sensor, and obtain a current subset of image check coefficients to be cached from the cache. , Processing the images acquired by the image sensor according to the current subset of image check coefficients to be buffered.
  • the present application provides a computer storage medium, where the storage medium includes computer instructions, and when the instructions are executed by a computer, the computer implements the first aspect or the method of the first aspect.
  • the present application provides a computer program product, including computer instructions, which, when executed by a computer, cause the computer to implement the first aspect or the method of the first aspect.
  • the application provides a method for reading an image check coefficient, a flash memory controller, a system, and a storage medium, including: the flash memory controller obtains an interrupt request sent by a cache; the flash memory controller reads an image that needs to be cached from the flash memory according to the interrupt request Check coefficient subset; the flash memory controller stores a subset of image check coefficients that currently need to be buffered into the cache. On the one hand, it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU.
  • the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • FIG. 1 is a schematic application scenario diagram of the technical solution of the present application
  • FIG. 2 is a flowchart of a method for reading an image check coefficient provided by an embodiment of the present application
  • FIG. 3 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application.
  • FIG. 4 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application.
  • FIG. 5 is a flowchart of a method for reading an image check coefficient according to another embodiment of the present application.
  • FIG. 6 is a flowchart of a method for reading an image check coefficient according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of an image check coefficient reading system 70 according to an embodiment of the present application.
  • the image check coefficient set is composed of all the image check coefficients required in the image processing process.
  • the image check coefficient subset is composed of at least one image check coefficient to be buffered into the cache each time, and the subset is a subset of the image check coefficient set.
  • FIG. 1 is an application scenario diagram of the technical solution of the present application.
  • the flash memory 11 stores an image check coefficient set corresponding to the frame image, and the flash memory controller 12 may The image check coefficient subset that needs to be cached is read each time.
  • the flash memory controller 12 stores the read image check coefficient subset into the cache 13.
  • the ISP 14 reads the currently cached image correction coefficient in the cache 13. Check the subset of coefficients, and obtain image data through the image sensor 15, and process the image data through the read subset of the image check coefficients, such as noise reduction, verification and other processing.
  • the cache 13 After the current cached image check coefficient subset in the cache 13 is read, the cache 13 generates an interrupt request and sends the interrupt request to the flash controller 12, so that the flash controller 12 reads from the flash 11 the next time it needs Cached image check coefficient subset, and store the read image check coefficient subset into cache 13 so that ISP 14 reads the cached image check coefficient subset cached in cache 13 and acquires the image through image sensor 15 Data, the image data is processed again through the read image check coefficient subset.
  • step S21 The description of step S21:
  • the interrupt request is used to trigger the flash memory controller to read from the flash memory a subset of image check coefficients that currently need to be buffered.
  • the interrupt request includes: a start address of a subset of image check coefficients that currently needs to be buffered and a total length of the image check coefficients included in the subset of image check coefficients that currently need to be buffered.
  • step S22 The description of step S22:
  • the starting address of the subset of the image check coefficients refers to the starting address of the pixels in the first row and the first column in the flash memory.
  • the subset of image check coefficients that currently needs to be buffered includes at least one image check coefficient.
  • the subset of image check coefficients that currently need to be buffered includes one image check coefficient
  • the subset of image check coefficients that currently need to be buffered includes the total length of the included image check coefficient refers to the length of the one image check coefficient.
  • the total length of the image check coefficients included in the subset of image check coefficients that currently need to be cached refers to the multiple image check coefficients Total length. Assume that the image check coefficients corresponding to the pixels in the first line are currently stored in the cache. In this case, the total length of the image check coefficient subset refers to the total length of the image check coefficients corresponding to all pixels in the first line.
  • the flash memory controller also receives instruction information sent by the CPU before step S21, and the instruction information is used to determine a start address of a subset of image check coefficients that currently needs to be buffered. And the total length of image check coefficients included in the subset of image check coefficients that need to be cached.
  • the cache does not need to send an interrupt request to the CPU, but directly sends an interrupt request to the flash memory controller, so that the flash memory controller reads from the flash memory a subset of image check coefficients that currently need to be cached according to the interrupt request, and Store a subset of image check coefficients that currently need to be cached into the cache.
  • it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU.
  • the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • FIG. 3 is a flowchart of a method for reading an image check coefficient provided by another embodiment of the present application. As shown in FIG. 3, the method It includes the following steps:
  • Step S31 The flash memory controller receives instruction information sent by the CPU.
  • Step S32 The flash memory controller obtains an interrupt request sent by the cache.
  • Step S33 The flash memory controller reads from the flash memory a subset of image check coefficients that currently needs to be buffered according to the interrupt request and the instruction information.
  • Step S34 The flash memory controller stores a subset of image check coefficients that currently needs to be buffered into the buffer.
  • step S32 is the same as step S21
  • step S34 is the same as step S23, which is not repeated in the embodiment of the present application.
  • step S31 The following describes step S31:
  • the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check coefficient that needs to be cached each time. The total length of the image check coefficients included in the subset.
  • the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check that needs to be cached each time.
  • the total length of the image check coefficients included in the image check coefficient subsets that need to be cached each time may be the same or different.
  • the termination address of the image check coefficient set in the flash memory refers to the termination address of the last image check coefficient set in the image check coefficient set in the flash memory.
  • step S33 The following describes step S33:
  • FIG. 4 is a flowchart of a method for reading an image verification coefficient according to another embodiment of the present application. As shown in FIG. 4, the above step S33 includes:
  • Step S332 The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the image check coefficient subset that currently needs to be buffered.
  • the flash memory controller directly determines the initial address of the first image check coefficient subset as the image that needs to be cached currently.
  • the initial address of the check coefficient subset and determines the total length of the image check coefficients included in the first image check coefficient subset as the image check coefficients included in the image check coefficient subset that currently needs to be cached. Total length.
  • the flash memory controller first determines the initial address of the image check coefficient subset that was successfully read last time, and the total length of the image check coefficient included in the image check coefficient, and calculates the last successfully read The sum of the initial address of the image check coefficient subset and the total length of the image check coefficient included in the image check coefficient subset, to obtain the initial address of the image check coefficient subset that needs to be buffered.
  • the flash memory controller can directly determine the current image check coefficient subset that needs to be cached in the instruction information. The total length of the image check coefficients included.
  • the second optional manner for the indication information is that the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, The total length of the image check coefficient subset included in the cached image check coefficient subset, and the start address of each of the image check coefficient subsets. Based on this, the flash memory controller can directly determine the current through the instruction information. The initial address of the subset of image check coefficients to be cached and the total length of the image check coefficients it contains.
  • the CPU sends only one instruction message to the flash memory controller, and subsequent flash memory controllers only need to read a subset of image check coefficients that need to be cached from the flash memory according to the interrupt request and the instruction information.
  • it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU.
  • the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • FIG. 5 is a flowchart of a method for reading an image verification coefficient according to another embodiment of the present application. As shown in FIG. 5, the method include:
  • Step S51 The flash memory controller obtains an interrupt request sent by the cache.
  • Step S52 The flash memory controller reads, from the flash memory, the data of the total length of the image check coefficients included in the image check coefficient subset starting from the start address of the image check coefficient subset that currently needs to be buffered.
  • Step S53 The flash memory controller stores a subset of image check coefficients that currently needs to be buffered into the buffer.
  • step S52 is the same as step S21
  • step S53 is the same as step S33, which is not repeated in the embodiment of the present application.
  • step S52 The following describes step S52:
  • the cache does not need to send an interrupt request to the CPU, but directly sends an interrupt request to the flash memory controller, so that the flash memory controller reads from the flash memory a subset of image check coefficients that currently need to be cached according to the interrupt request, and Store a subset of image check coefficients that currently need to be cached into the cache.
  • it can prevent the interrupt request from occupying the CPU time, so that the CPU can process other transactions, which improves the transaction efficiency of the CPU.
  • the embodiment of the present application does not need the CPU to receive an interrupt request every time, the CPU controls the flash memory controller to read the image verification coefficient from the flash memory, but the memory controller can directly read the current cache required according to the interrupt request. A subset of the image check coefficient, thereby improving the reading efficiency of the image check coefficient.
  • the method for reading image verification coefficients further includes: optionally, the flash memory controller determines whether the start address of the subset of image verification coefficients that currently needs to be buffered is smaller than the image verification The termination address of the coefficient set in the flash memory. If the start address of the image check coefficient subset that currently needs to be buffered is smaller than the end address of the image check coefficient set in the flash memory, step S332 or step S52 is performed.
  • the flash memory controller determines the currently needed buffered image check
  • the starting address of the coefficient subset is the starting address of the image verification coefficient set in the flash memory
  • the total length of the image verification coefficient included in the image verification coefficient subset that needs to be buffered is the image calibration.
  • the total length of the image check coefficient included in the first image check coefficient subset in the test coefficient set, and then the flash memory controller reads from the flash memory, starting from the start address of the image check coefficient subset that currently needs to be buffered Take the data of the total length.
  • Step S61 The flash memory controller receives instruction information sent by the CPU.
  • Step S65 The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.
  • Step S66 The flash memory controller determines that the start address of the subset of image check coefficients that needs to be cached is the start address of the set of image check coefficients in the flash memory.
  • the total length of the test coefficients is the total length of the image check coefficients included in the first image check coefficient subset in the image check coefficient set.
  • Step S67 The flash memory controller reads the data of the total length from the flash memory, starting from the start address of the subset of image check coefficients that currently needs to be buffered.
  • Step S68 The flash memory controller stores a subset of image check coefficients that need to be buffered into the buffer.
  • the flash memory controller needs to determine whether the start address of the subset of image check coefficients that currently need to be cached is smaller than the image check coefficient Start address set in flash memory; if the start address of the subset of image check coefficients currently needed to be cached is smaller than the start address of the image check coefficient set in flash, the flash memory controller reads the currently calibrated image Check coefficient subset, otherwise, the flash memory controller reads the first subset of image check coefficients in the image check coefficient set. This ensures that when the image check coefficients required for a frame of image have been transmitted, the flash memory controller can still accurately obtain a subset of the image check coefficients that currently need to be cached, thereby improving the reliability of the flash memory controller.
  • An embodiment of the present application further provides a flash memory controller, where the flash memory controller is configured to: obtain an interrupt request sent by a cache; read a subset of image check coefficients that currently need to be cached from the flash memory according to the interrupt request; A subset of the test coefficients is stored in the cache.
  • the indication information includes: a start address of the image check coefficient set in the flash memory, an end address of the image check coefficient set in the flash memory, and an image check included in the image check coefficient subset that needs to be cached each time.
  • the total length of the coefficients; among them, the image check coefficient set is composed of all the image check coefficients required in the image processing process, and the image check coefficient subset is a subset of the image check coefficient set.
  • the flash memory controller is specifically configured to: under the trigger of the interrupt request, determine the start address of the image check coefficient subset that needs to be cached currently and the image check coefficient subset that needs to be cached according to the instruction information.
  • the total length of the image check coefficient; from the flash memory, the data of the total length is read from the start address of the subset of the image check coefficient that currently needs to be cached.
  • the image check coefficient subset is a subset of the image check coefficient set Set, the image check coefficient set is composed of all the image check coefficients required in the image processing process;
  • the flash memory controller is specifically used to: from the flash memory, from the beginning of the current subset of image check coefficients to be cached The address starts to read the total length of data.
  • the flash memory controller is further configured to: determine whether a start address of a subset of image check coefficients currently required to be cached is smaller than an end address of the image check coefficient set in the flash memory; accordingly, the flash memory controller is specifically configured to: If the start address of the image check coefficient subset that needs to be cached is less than the end address of the image check coefficient set in the flash memory, then read from the flash memory starting from the start address of the image check coefficient subset that currently needs to be cached. Take the total length of the data.
  • the flash memory controller provided in the embodiment of the present application may be used to execute the above-mentioned method for reading the image verification coefficient.
  • the method section which is not limited in the embodiment of the present application.
  • FIG. 7 is a schematic diagram of an image check coefficient reading system 70 according to an embodiment of the present application. As shown in FIG. 7, the system includes: a cache 71, a flash memory 72, a CPU 73, and an image check coefficient. Read method of flash controller 74.
  • the system 70 further includes: an image sensor 75 and an ISP 76.
  • the image sensor 75 is used to collect images; the ISP 76 is used to acquire the images collected by the image sensor 75, and from the cache 71, to obtain a subset of the image check coefficients that need to be cached, and to process according to the subset of the image check coefficients that are currently cached. An image captured by the image sensor 75.
  • the flash memory controller in the image check coefficient reading system provided by the embodiment of the present application can be used to execute the above-mentioned method for reading the image check coefficient.
  • the method part which is not done in the embodiment of the present application. limit.
  • An embodiment of the present application further provides a computer program product, including: computer instructions that, when executed by a computer, cause the computer to implement the method for reading an image check coefficient as described above.
  • a person of ordinary skill in the art may understand that all or part of the steps of implementing the foregoing method embodiments may be implemented by a program instructing related hardware.
  • the aforementioned program may be stored in a computer-readable storage medium.
  • the steps including the foregoing method embodiments are executed; and the foregoing storage medium includes: various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disc.

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Abstract

本申请提供一种图像校验系数的读取方法、闪存控制器、系统及存储介质，包括：闪存控制器获取缓存发送的中断请求；闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集；闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。从而可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。

Description

图像校验系数的读取方法、闪存控制器、系统及存储介质 技术领域
本申请涉及数据处理技术领域，尤其涉及一种图像校验系数的读取方法、闪存控制器、系统及存储介质。
背景技术
在3D或者2D成像系统中，图像信号处理器(Image Signal Processor，ISP)接收来自图像传感器采集的图像，并对该图像进行降噪、校验等处理。而ISP需要通过图像校验系数对图像进行降噪、校验等处理。
在现有技术中，ISP获取图像校验系数的过程包括：通常ISP从缓存(Buffer)中读取图像校验系数，当缓存中图像校验系数被读完时，缓存将生成中断请求。并向中央处理器(Central Processing Unit，CPU)发送该中断请求，CPU接收到该中断请求之后控制闪存控制器(Flash Controller)从闪存(Flash)中读取接下来要用的图像校验系数，并将读取到图像校验系数存放到缓存中。
然而，由于缓存内存有限，其内部的图像校验系数很容易被读完，基于此，缓存生成中断请求的频率非常高。而CPU需要实时处理这些中断请求，以控制闪存控制器从闪存中读取图像校验系数，这将占用CPU的大量时间，影响CPU处理其它事务，即影响了CPU的事务处理效率。
发明内容
本申请提供一种图像校验系数的读取方法、闪存控制器、系统及存储介质。
第一方面，本申请提供一种图像校验系数的读取方法，包括：闪存控制器获取缓存发送的中断请求；闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集；闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。
一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其 它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
可选地，闪存控制器获取缓存发送的中断请求之前，还包括：闪存控制器接收中央处理器发送的指示信息；相应的，闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集，包括：闪存控制器根据中断请求和指示信息从闪存读取当前需要缓存的图像校验系数子集。
即CPU仅向闪存控制器发送一条指示信息，后续闪存控制器只需根据中断请求和该指示信息从闪存读取当前需要缓存的图像校验系数子集即可，一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
可选地，指示信息包括：图像校验系数集在闪存中的起始地址、图像校验系数集在闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
可选地，指示信息还包括：每个图像校验系数子集的起始地址。
可选地，闪存控制器根据中断请求和指示信息从闪存读取当前需要缓存的图像校验系数子集，包括：闪存控制器在中断请求的触发下，根据指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
可选地，中断请求包括：当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；图像校验系数子集为图像校验系数集的子集，图像校验系数集由图像处理过程中所需的所有图像校验系数构成；相应的，闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集，包括：闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据之前，还包括：闪存控制器判断当前需要缓存的图像校验系数子集的起始地址是否小于图像校验系数集在闪存中的终止地址；相应地，闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据，包括：若当前需要缓存的图像校验系数子集的起始地址小于图像校验系数集在闪存中的终止地址，则闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。若当前需要缓存的图像校验系数子集的起始地址大于或等于图像校验系数集在闪存中的终止地址，则闪存控制器确定当前需要缓存的图像校验系数子集的起始地址为图像校验系数集在闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度；闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取当前需要缓存的图像校验系数子集的总长度的数据。从而保证在一帧图像需要的图像校验系数已传输完成时，闪存控制器还是能够精确的获取到当前需要缓存的图像校验系数子集，进而提高了闪存控制器的可靠性。
下面将介绍闪存控制器、系统、存储介质及计算机程序产品，其效果可参考方法部分的效果，下面对此不再赘述。
第二方面，本申请提供一种闪存控制器，包括：闪存控制器用于：获取缓存发送的中断请求；根据中断请求从闪存读取当前需要缓存的图像校验系数子集；将当前需要缓存的图像校验系数子集存储至缓存中。
可选地，闪存控制器还用于：接收中央处理器发送的指示信息；相应的，闪存控制器具体用于：根据中断请求和指示信息从闪存读取当前需要缓存的图像校验系数子集。
可选地，指示信息包括：图像校验系数集在闪存中的起始地址、图像校验系数集在闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度；其中，图像校验系数集由图像处理过程中所需的所有图像校验系数构成，图像校验系数子集为图像校验系数集的子集。
可选地，指示信息还包括：每个图像校验系数子集的起始地址。
可选地，闪存控制器具体用于：在中断请求的触发下，根据指示信息确 定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；图像校验系数子集为图像校验系数集的子集，图像校验系数集由图像处理过程中所需的所有图像校验系数构成；相应的，闪存控制器具体用于：从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，闪存控制器还用于：判断当前需要缓存的图像校验系数子集的起始地址是否小于图像校验系数集在闪存中的终止地址；相应地，闪存控制器具体用于：若当前需要缓存的图像校验系数子集的起始地址小于图像校验系数集在闪存中的终止地址，则从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，闪存控制器还用于：若当前需要缓存的图像校验系数子集的起始地址大于或等于图像校验系数集在闪存中的终止地址，则确定当前需要缓存的图像校验系数子集的起始地址为图像校验系数集在闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度；从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
第三方面，本申请提供一种图像校验系数的读取系统，包括：缓存、闪存、中央处理器和用于实现第一方面或第一方面的可选方式闪存控制器。
可选地，系统还包括：图像传感器和图像信号处理器；图像传感器用于采集图像；图像信号处理器用于获取图像传感器采集的图像，并从缓存中获取当前需要缓存的图像校验系数子集，根据当前需要缓存的图像校验系数子集处理图像传感器采集的图像。
第四方面，本申请提供一种计算机存储介质，存储介质包括计算机指令，当指令被计算机执行时，使得计算机实现第一方面或第一方面的方法。
第五方面，本申请提供一种计算机程序产品，包括计算机指令，当指令被计算机执行时，使得计算机实现第一方面或第一方面的方法。
本申请提供一种图像校验系数的读取方法、闪存控制器、系统及存储介质，包括：闪存控制器获取缓存发送的中断请求；闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集；闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请技术方案的一种示意性应用场景图；
图2为本申请一实施例提供的图像校验系数的读取方法的流程图；
图3为本申请另一实施例提供的图像校验系数的读取方法的流程图；
图4为本申请再一实施例提供的图像校验系数的读取方法的流程图；
图5为本申请又一实施例提供的图像校验系数的读取方法的流程图；
图6为本申请又一实施例提供的图像校验系数的读取方法的流程图；
图7为本申请一实施例提供的一种图像校验系数的读取系统70的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第 三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例，例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
如上所述，一方面由于缓存内存有限，其内部的图像校验系数很容易被读完，基于此，缓存生成中断请求的频率非常高。而CPU需要实时处理这些中断请求，以控制闪存控制器从闪存中读取图像校验系数，这将占用CPU的大量时间，影响CPU处理其它事务，即影响了CPU的事务处理效率。另一方面，由于现有技术中，CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，这势必造成图像校验系数的读取效率较低的问题。为了解决这些技术问题，本申请实施例提供一种图像校验系数的读取方法、闪存控制器、系统及存储介质。
在介绍本发明实施例之前，下面先对相关概念进行介绍：
图像校验系数集是由图像处理过程中，所需要的所有图像校验系数构成。
图像校验系数子集是由每次需要缓存至缓存中的至少一个图像校验系数构成，该子集为所述图像校验系数集的子集。
具体地，图1为本申请技术方案的应用场景图，如图1所示，针对一帧图像，闪存11中存储有该帧图像对应的图像校验系数集，闪存控制器12可以从闪存11中读取每次需要缓存的图像校验系数子集，闪存控制器12将读取到的图像校验系数子集存储至缓存13中，进一步地，ISP14读取缓存13中当前缓存的图像校验系数子集，并通过图像传感器15获取图像数据，通过读取到的图像校验系数子集对图像数据进行处理，如降噪、校验等处理。当缓存13中当前缓存的图像校验系数子集被读取完之后，缓存13生成中断请求，并向闪存控制器12发送中断请求，以使闪存控制器12从闪存11中读取下一次需要缓存的图像校验系数子集，并将读取到的图像校验系数子集存储至缓存13中，以便ISP14读取缓存13中缓存的图像校验系数子集，并通过图像传感器15获取图像数据，通过读取到的图像校验系数子集对图像数据再 次进行处理。
基于上述应用场景，下面对本申请技术方案进行详细介绍：
实施例一
图2为本申请一实施例提供的图像校验系数的读取方法的流程图，如图2所示，该方法包括如下步骤：
步骤S21：闪存控制器获取缓存发送的中断请求。
步骤S22：闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集。
步骤S23：闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。
针对步骤S21进行说明：
一种可选方式：中断请求用于触发闪存控制器从闪存读取当前需要缓存的图像校验系数子集。
另一种可选方式：中断请求包括：当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
在步骤S21中，当缓存13中当前缓存的图像校验系数子集被读取完之后，缓存13生成中断请求，并向闪存控制器12发送中断请求。
针对步骤S22进行说明：
首先，闪存控制器根据中断请求确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。当前需要缓存的图像校验系数子集的起始地址是指图像校验系数子集所包括的第一个图像校验系数的起始地址。通常缓存中存储的是一帧图像中的其中一行像素点对应的图像校验系数，其中每个像素点对应一个图像校验系数。假设缓存中当前存储的是第一行像素点对应的图像校验系数，这时图像校验系数子集的起始地址是指第一行第一列像素点在闪存中的起始地址。进一步地，当前需要缓存的图像校验系数子集包括至少一个图像校验系数，当当前需要缓存的图像校验系数子集包括一个图像校验系数时，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度是指所述一个图像校验系数的长度。当当前需要缓存的图像校验系数子集包括多个图像校验系数 时，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度是指所述多个图像校验系数的总长度。假设缓存中当前存储的是第一行像素点对应的图像校验系数，这时图像校验系数子集的总长度是指第一行所有像素点对应的图像校验系数的总长度。
其次，闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
其中，若中断请求为上述第一种可选方式，则闪存控制器在步骤S21之前还接收CPU发送的指示信息，该指示信息用于确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
若中断请求为上述第二种可选方式，则闪存控制器可以直接根据中断请求确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
可选地，在步骤S23之后，ISP从缓存中读取当前需要缓存的图像校验系数子集，并通过当前需要缓存的图像校验系数子集进行图像处理，具体的，可以是根据当前需要缓存的图像校验系数子集对从图像传感器获得的图像信息进行处理，其中，本申请实施例对如何通过图像校验系数进行图像处理不做限制。
在本申请实施例中，缓存无需向CPU发送中断请求，而是直接向闪存控制器发送中断请求，以使闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集，并将当前需要缓存的图像校验系数子集存储至缓存中。一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
实施例二
结合步骤S21的第一种可选方式对步骤S22进行说明：具体地，图3为本申请另一实施例提供的图像校验系数的读取方法的流程图，如图3所示，该方法包括如下步骤：
步骤S31：闪存控制器接收CPU发送的指示信息。
步骤S32：闪存控制器获取缓存发送的中断请求。
步骤S33：闪存控制器根据中断请求和指示信息从闪存读取当前需要缓存的图像校验系数子集。
步骤S34：闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。
其中，步骤S32与步骤S21相同，步骤S34与步骤S23相同，本申请实施例对此不再赘述。
针对步骤S31进行如下说明：
一种可选方式：指示信息包括：图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
另一种可选方式：指示信息包括：图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度，以及，每个所述图像校验系数子集的起始地址。
可选地，各次需要缓存的图像校验系数子集所包括的图像校验系数的总长度可以相同，也可以不同。
图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址之间的存储区域为连续存储区域。
图像校验系数集在所述闪存中的终止地址是指：图像校验系数集中的最后一个图像校验系数在闪存中的终止地址。
针对步骤S33进行如下说明：
图4为本申请再一实施例提供的图像校验系数的读取方法的流程图，如图4所示，上述步骤S33包括：
步骤S331：闪存控制器在中断请求的触发下，根据指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
步骤S332：闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
具体地，针对指示信息的第一种可选方式，若当前需要缓存的图像校验系数子集为图像校验系数集中的第一个图像校验系数子集，则由于指示信息包括：第一个图像校验系数子集的初始地址以及第一个图像校验系数子集的长度，基于此，闪存控制器直接将第一个图像校验系数子集的初始地址确定为当前需要缓存的图像校验系数子集的初始地址，并将第一个图像校验系数子集所包括的图像校验系数的总长度确定为当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。若当前需要缓存的图像校验系数子集不是图像校验系数集中的第一个图像校验系数子集，则由于指示信息未包括：当前需要缓存的图像校验系数子集的初始地址，基于此，闪存控制器首先确定上一次成功读取到的图像校验系数子集的初始地址，以及，该图像校验系数所包括的图像校验系数的总长度，计算上一次成功读取到的图像校验系数子集的初始地址与该图像校验系数子集所包括的图像校验系数的总长度之和，得到当前需要缓存的图像校验系数子集的初始地址。而由于当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度携带在指示信息中，因此闪存控制器可以直接在该指示信息中确定当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
针对指示信息的第二种可选方式，由于指示信息包括：图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度，以及，每个所述图像校验系数子集的起始地址，基于此，闪存控制器直接通过指示信息即可确定当前需要缓存的图像校验系数子集的初始地址和其所包括的图像校验系数的总长度。
在本申请实施例中，CPU仅向闪存控制器发送一条指示信息，后续闪存控制器只需根据中断请求和该指示信息从所述闪存读取当前需要缓存的图像校验系数子集即可，一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
实施例三
结合步骤S21的第二种可选方式对步骤S22进行说明：具体地，图5为本申请又一实施例提供的图像校验系数的读取方法的流程图，如图5所示，该方法包括：
步骤S51：闪存控制器获取缓存发送的中断请求。
步骤S52：闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取图像校验系数子集所包括的图像校验系数的总长度的数据。
步骤S53：闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。
其中，步骤S52与步骤S21相同，步骤S53与步骤S33相同，本申请实施例对此不再赘述。
针对步骤S52进行如下说明：
由于中断请求包括了当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；所述图像校验系数子集为图像校验系数集的子集，所述图像校验系数集由图像处理过程中所需的所有图像校验系数构成。因此闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
在本申请实施例中，缓存无需向CPU发送中断请求，而是直接向闪存控制器发送中断请求，以使闪存控制器根据中断请求从闪存读取当前需要缓存的图像校验系数子集，并将当前需要缓存的图像校验系数子集存储至缓存中。一方面，可以防止中断请求对CPU的时间占用，以使CPU可以处理其它事务，即提高了CPU的事务处理效率。另一方面，由于本申请实施例无需CPU每接到一次中断请求，CPU就要控制闪存控制器从闪存读取一次图像校验系数，而是内存控制器可以直接根据中断请求读取当前需要缓存的图像校验系数子集，从而提高了图像校验系数的读取效率。
实施例四
针对步骤S332或步骤S52之前，所述图像校验系数的读取方法还包括：可选地，闪存控制器判断当前需要缓存的图像校验系数子集的起始地址是否小于所述图像校验系数集在所述闪存中的终止地址。若所述当前需要缓存的图像校验系数子集的起始地址小于所述图像校验系数集在所述闪存中的终止 地址，则执行步骤S332或步骤S52。若所述当前需要缓存的图像校验系数子集的起始地址大于或等于所述图像校验系数集在所述闪存中的终止地址，则所述闪存控制器确定当前需要缓存的图像校验系数子集的起始地址为所述图像校验系数集在所述闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为所述图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度，接着闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
具体地，结合实施例二对上述内容进行详细说明：
图6为本申请又一实施例提供的图像校验系数的读取方法的流程图，如图6所示，该方法包括如下步骤：
步骤S61：闪存控制器接收CPU发送的指示信息。
步骤S62：闪存控制器获取缓存发送的中断请求。
步骤S63：闪存控制器在中断请求的触发下，根据指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度。
步骤S64：闪存控制器判断当前需要缓存的图像校验系数子集的起始地址是否小于所述图像校验系数集在所述闪存中的终止地址；若小于，则执行步骤S65；否则，则执行步骤S66-步骤S67。
步骤S65：闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
步骤S66：闪存控制器确定当前需要缓存的图像校验系数子集的起始地址为图像校验系数集在闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度。
步骤S67：闪存控制器从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
步骤S68：闪存控制器将当前需要缓存的图像校验系数子集存储至缓存中。
其中，步骤S61与步骤S31相同，步骤S62与步骤S32相同，步骤S63与步骤S331相同，步骤S68与步骤S34相同，本申请实施例对此不再赘述。
结合步骤S64至步骤S67进行说明：
当闪存控制器首次收到中断请求时，闪存控制器将当前需要缓存的图像校验系数子集的起始地址req_address设置为图像校验系数集在内存中的起始地址start_address，从req_address开始读取当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度req_len的数据到缓存中；然后闪存控制器将req_address增加req_len；即req_address＝req_address+req_len。接下来，当闪存控制器每次收到中断请求时，首先判断req_address是否小于图像校验系数集在内存中的终止地址end_address，若是，闪存控制器从req_address开始读取当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度的数据到缓存中；然后闪存控制器将req_address增加req_len；即req_address＝req_address+req_len。如果req_address大于或等于end_address，表示一帧图像需要的图像校验系数已传输完成，闪存控制器将req_address重新设置为start_address。
在本申请实施例中，在闪存控制器读取当前需要缓存的图像校验系数子集之前，闪存控制器需要判断当前需要缓存的图像校验系数子集的起始地址是否小于图像校验系数集在闪存中的起始地址；若当前需要缓存的图像校验系数子集的起始地址小于图像校验系数集在闪存中的起始地址，则闪存控制器读取当前需要缓存的图像校验系数子集，否则，则闪存控制器读取图像校验系数集中的第一个图像校验系数子集。从而保证在一帧图像需要的图像校验系数已传输完成时，闪存控制器还是能够精确的获取到当前需要缓存的图像校验系数子集，进而提高了闪存控制器的可靠性。
实施例五
本申请实施例还提供一种闪存控制器，其中闪存控制器用于：获取缓存发送的中断请求；根据中断请求从闪存读取当前需要缓存的图像校验系数子集；将当前需要缓存的图像校验系数子集存储至缓存中。
可选地，闪存控制器还用于：接收中央处理器发送的指示信息；相应的，闪存控制器具体用于：根据中断请求和指示信息从闪存读取当前需要缓存的图像校验系数子集。
可选地，指示信息包括：图像校验系数集在闪存中的起始地址、图像校验系数集在闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的 图像校验系数的总长度；其中，图像校验系数集由图像处理过程中所需的所有图像校验系数构成，图像校验系数子集为图像校验系数集的子集。
可选地，指示信息还包括：每个图像校验系数子集的起始地址。
可选地，闪存控制器具体用于：在中断请求的触发下，根据指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，
当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；图像校验系数子集为图像校验系数集的子集，图像校验系数集由图像处理过程中所需的所有图像校验系数构成；相应的，闪存控制器具体用于：从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，闪存控制器还用于：判断当前需要缓存的图像校验系数子集的起始地址是否小于图像校验系数集在闪存中的终止地址；相应地，闪存控制器具体用于：若当前需要缓存的图像校验系数子集的起始地址小于图像校验系数集在闪存中的终止地址，则从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
可选地，闪存控制器还用于：若当前需要缓存的图像校验系数子集的起始地址大于或等于图像校验系数集在闪存中的终止地址，则确定当前需要缓存的图像校验系数子集的起始地址为图像校验系数集在闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度；从闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取总长度的数据。
本申请实施例提供的闪存控制器可用于执行上述的图像校验系数的读取方法，其内容和效果可参考方法部分，本申请实施例对此不做限制。
实施例六
图7为本申请一实施例提供的一种图像校验系数的读取系统70的示意图，如图7所示，该系统包括：缓存71、闪存72、CPU73和用于实现图像校验系 数的读取方法的闪存控制器74。
可选地，该系统70还包括：图像传感器75和ISP76。
其中，图像传感器75用于采集图像；ISP76用于获取图像传感器75采集的图像，并从缓存71中获取当前需要缓存的图像校验系数子集，根据当前需要缓存的图像校验系数子集处理图像传感器75采集的图像。
本申请实施例提供的图像校验系数的读取系统中的闪存控制器可用于执行上述的图像校验系数的读取方法，其内容和效果可参考方法部分，本申请实施例对此不做限制。
实施例七
本申请一实施例还提供一种计算机存储介质，存储介质包括计算机指令，当指令被计算机执行时，使得计算机实现如上述的图像校验系数的读取方法。
实施例八
本申请一实施例还提供一种计算机程序产品，包括：计算机指令，当指令被计算机执行时，使得计算机实现如上述的图像校验系数的读取方法。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (19)

  1. 一种图像校验系数的读取方法，其特征在于，包括：
    闪存控制器获取缓存发送的中断请求；
    所述闪存控制器根据所述中断请求从闪存读取当前需要缓存的图像校验系数子集；
    所述闪存控制器将当前需要缓存的图像校验系数子集存储至所述缓存中。
  2. 根据权利要求1所述的方法，其特征在于，所述闪存控制器获取缓存发送的中断请求之前，还包括：
    所述闪存控制器接收中央处理器发送的指示信息；
    相应的，所述闪存控制器根据所述中断请求从闪存读取当前需要缓存的图像校验系数子集，包括：
    所述闪存控制器根据所述中断请求和所述指示信息从所述闪存读取当前需要缓存的图像校验系数子集。
  3. 根据权利要求2所述的方法，其特征在于，所述指示信息包括：图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度；
    其中，所述图像校验系数集由图像处理过程中所需的所有图像校验系数构成，所述图像校验系数子集为所述图像校验系数集的子集。
  4. 根据权利要求3所述的方法，其特征在于，所述指示信息还包括：每个所述图像校验系数子集的起始地址。
  5. 根据权利要求3或4所述的方法，其特征在于，所述闪存控制器根据所述中断请求和所述指示信息从所述闪存读取当前需要缓存的图像校验系数子集，包括：
    所述闪存控制器在所述中断请求的触发下，根据所述指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；
    所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  6. 根据权利要求1所述的方法，其特征在于，所述中断请求包括：当前 需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；所述图像校验系数子集为图像校验系数集的子集，所述图像校验系数集由图像处理过程中所需的所有图像校验系数构成；
    相应的，所述闪存控制器根据所述中断请求从闪存读取当前需要缓存的图像校验系数子集，包括：
    所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  7. 根据权利要求5或6所述的方法，其特征在于，所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据之前，还包括：
    所述闪存控制器判断当前需要缓存的图像校验系数子集的起始地址是否小于所述图像校验系数集在所述闪存中的终止地址；
    相应地，所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据，包括：
    若所述当前需要缓存的图像校验系数子集的起始地址小于所述图像校验系数集在所述闪存中的终止地址，则所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  8. 根据权利要求7所述的方法，其特征在于，还包括：
    若所述当前需要缓存的图像校验系数子集的起始地址大于或等于所述图像校验系数集在所述闪存中的终止地址，则所述闪存控制器确定当前需要缓存的图像校验系数子集的起始地址为所述图像校验系数集在所述闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为所述图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度；
    所述闪存控制器从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  9. 一种闪存控制器，其特征在于，包括：所述闪存控制器用于：
    获取缓存发送的中断请求；
    根据所述中断请求从闪存读取当前需要缓存的图像校验系数子集；
    将当前需要缓存的图像校验系数子集存储至所述缓存中。
  10. 根据权利要求9所述的闪存控制器，其特征在于，所述闪存控制器还用于：
    接收中央处理器发送的指示信息；
    相应的，所述闪存控制器具体用于：
    根据所述中断请求和所述指示信息从所述闪存读取当前需要缓存的图像校验系数子集。
  11. 根据权利要求10所述的闪存控制器，其特征在于，所述指示信息包括：图像校验系数集在所述闪存中的起始地址、所述图像校验系数集在所述闪存中的终止地址、每次需要缓存的图像校验系数子集所包括的图像校验系数的总长度；
    其中，所述图像校验系数集由图像处理过程中所需的所有图像校验系数构成，所述图像校验系数子集为所述图像校验系数集的子集。
  12. 根据权利要求11所述的闪存控制器，其特征在于，所述指示信息还包括：每个所述图像校验系数子集的起始地址。
  13. 根据权利要求11或12所述的闪存控制器，其特征在于，所述闪存控制器具体用于：
    在所述中断请求的触发下，根据所述指示信息确定当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；
    从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  14. 根据权利要求9所述的闪存控制器，其特征在于，当前需要缓存的图像校验系数子集的起始地址和当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度；所述图像校验系数子集为图像校验系数集的子集，所述图像校验系数集由图像处理过程中所需的所有图像校验系数构成；
    相应的，所述闪存控制器具体用于：
    从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  15. 根据权利要求13或14所述的闪存控制器，其特征在于，所述闪存 控制器还用于：
    判断当前需要缓存的图像校验系数子集的起始地址是否小于所述图像校验系数集在所述闪存中的终止地址；
    相应地，所述闪存控制器具体用于：
    若所述当前需要缓存的图像校验系数子集的起始地址小于所述图像校验系数集在所述闪存中的终止地址，则从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  16. 根据权利要求15所述的闪存控制器，其特征在于，所述闪存控制器还用于：
    若所述当前需要缓存的图像校验系数子集的起始地址大于或等于所述图像校验系数集在所述闪存中的终止地址，则确定当前需要缓存的图像校验系数子集的起始地址为所述图像校验系数集在所述闪存中的起始地址，当前需要缓存的图像校验系数子集所包括的图像校验系数的总长度为所述图像校验系数集中第一个图像校验系数子集所包括的图像校验系数的总长度；
    从所述闪存中，自当前需要缓存的图像校验系数子集的起始地址开始读取所述总长度的数据。
  17. 一种图像校验系数的读取系统，其特征在于，包括：缓存、闪存、中央处理器和用于实现权利要求1-8任一项所述方法的闪存控制器。
  18. 根据权利要求17所述的系统，其特征在于，还包括：图像传感器和图像信号处理器；
    所述图像传感器用于采集图像；
    所述图像信号处理器用于获取所述图像传感器采集的图像，并从所述缓存中获取所述当前需要缓存的图像校验系数子集，根据所述当前需要缓存的图像校验系数子集处理所述图像传感器采集的图像。
  19. 一种计算机存储介质，其特征在于，所述存储介质包括计算机指令，当所述指令被计算机执行时，使得所述计算机实现如权利要求1至8中任一项权利要求所述的方法。
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