WO2020056610A1

WO2020056610A1 - Storage apparatus and electronic device

Info

Publication number: WO2020056610A1
Application number: PCT/CN2018/106340
Authority: WO
Inventors: 肖勇军; 孔飞; 耿剑锋; 何彪; 夏邓伟; 张广宇
Original assignee: 华为技术有限公司
Priority date: 2018-09-18
Filing date: 2018-09-18
Publication date: 2020-03-26
Also published as: CN111512294A

Abstract

A storage apparatus and an electronic device, for implementing highly efficient data migration between storage media of different memories. The apparatus comprises: a package (201), a first memory (202), a second memory (203), a third memory (204), and a controller (205). The controller (205) is coupled to the first memory (202), the second memory (203), and the third memory (204), and is used for implementing data migration between at least two memories in the first memory (202), the second memory (203), and the third memory (204); the first memory (202), the second memory (203), and the third memory (204) are memories of different types; the package (201) is used for packaging the first memory (202), the second memory (203), the third memory (204), and the controller (205).

Description

Storage device and electronic equipment

Technical field

The present application relates to the field of information storage technologies, and in particular, to a storage device and an electronic device.

Background technique

The data storage medium may generally include two types of random access memory (Random Access Memory, RAM) and read-only memory (Read-Only Memory, ROM). Among them, RAM has the characteristics of fast access speed, but data loss (volatile) at power-down, such as Double Rate (DDR) Synchronous Dynamic RAM (referred to as DDR SDRAM); ROM has power-down Features that do not lose data (non-volatile), but have slow access speeds, such as NAND flash memory. At present, there is a non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM), which combines the priority of RAM and RAM, has the characteristics of fast access speed and power loss data is not lost, such as resistive RAM (Resistive RAM, ReRAM), Ferromagnetic RAM (FRAM), Magnetic RAM (Magnetic RAM, MRAM), etc.

In practical applications, considering the characteristics, size, and price of storage media with different memories, it is usually necessary to deploy hybrid storage in electronic devices, such as mobile terminals, that is, different types of data storage media are deployed in one hybrid storage. For example, deploying hybrid memory that includes DDR, SDRAM, NAND, and NVRAM in mobile terminals. When a hybrid storage is deployed in a mobile terminal, there will be a need for data migration between different storage media of the hybrid storage. How to perform efficient data migration on different storage media becomes a problem.

Summary of the Invention

Embodiments of the present application provide a storage device and an electronic device, which are used to perform efficient data migration between different memories packaged in the storage device.

To achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

According to a first aspect, a storage device is provided. The device includes: a package, a first storage, a second storage, and a third storage; and the controller is coupled to the first storage, the second storage, and the third storage, and is used for Data is migrated between at least two of the memory, the second memory, and the third memory; the first memory, the second memory, and the third memory are different types of memory; the package is used to encapsulate the first memory, the second memory, Third memory and controller. In the above technical solution, the controller can migrate data between at least two memories of the first memory, the second memory, and the third memory packaged in the same package, and it is not necessary to transfer the data to the outside of the storage device when the data is migrated. The efficiency is improved, and the storage device is small in size and low in cost.

In a possible implementation manner of the first aspect, the first memory is a non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM), and the second memory is a NAND flash memory. Further, the third memory is a double rate (Double Data Rate, DDR) synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), which is referred to as DDR SDRAM for short. The storage device using the technical solution is a hybrid storage, which integrates different types of storage.

In a possible implementation manner of the first aspect, the apparatus further includes: a bus and a processor, the processor, the controller, the first memory, the second memory, and the third memory are coupled to the bus, and the package is also used for packaging A bus and a processor; the controller is further configured to obtain a bus control right from the processor and use the bus to migrate data between the at least two memories; the processor is configured to grant the bus control right to the controller. In the foregoing possible implementation manner, the controller can use the bus to perform efficient data migration between different storage media.

In a possible implementation manner of the first aspect, the controller is further configured to receive an operation on the migration data from at least one of the at least two memories before migrating the data between the at least two memories. request. In the foregoing possible implementation manner, the controller can perform efficient data migration between different storage media based on an operation request of at least one memory.

In a possible implementation manner of the first aspect, the controller is further configured to send a response agreeing to the operation request to the at least one memory. In the foregoing possible implementation manner, the controller can notify the at least one memory after acquiring the bus control authority.

In a possible implementation manner of the first aspect, the processor is further configured to release the bus control authority of the controller after the controller completes the migration data. In the foregoing possible implementation manner, by releasing the bus control authority of the controller in time, the problem that the controller controls the bus for a long time and affects related operations of the processor can be avoided.

In a possible implementation manner of the first aspect, the apparatus further includes: an interface coupled to the controller, configured to couple the first memory, the second memory, and the third memory to an outside of the package of the storage device. Processing equipment. In the foregoing possible implementation manner, a coupling manner of the storage device and a processing device is provided.

In a possible implementation manner of the first aspect, the interface includes at least two interfaces. In the foregoing possible implementation manner, a coupling manner of the storage device and a processing device is provided.

In a possible implementation manner of the first aspect, any one of the at least two interfaces is: a peripheral component interconnect standard PCIe interface, a double-rate synchronous dynamic random access memory DDR SDRAM interface, or a universal flash storage UFS interface . In the foregoing possible implementation manners, several possible at least two interfaces are provided.

In a possible implementation manner of the first aspect, the package includes a chip package. For example, the storage device includes one or more chip particles such that the first memory, the second memory, the third memory, the controller, the bus, and the processor are located on the one or more chip particles. The package encapsulates one or more chip particles to form the storage device, and realizes miniaturization of the storage device.

According to a second aspect, an electronic device is provided. The electronic device includes a storage device and a processing device. The storage device may be the storage device provided by the foregoing first aspect or any possible implementation manner of the first aspect. Optionally, the processing device is a system-on-chip (SoC).

In the above technical solution, the controller in the storage device can migrate data between at least two memories of the first memory, the second memory, and the third memory that are packaged in the same package, thereby achieving the implementation of different memories. Efficient data migration between storage media. At the same time, no external processing equipment is required to participate in the entire data migration process, thereby reducing the power consumption of the electronic device during data migration and improving the performance of the electronic device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 2 is a first schematic structural diagram of a storage device according to an embodiment of the present application; FIG.

FIG. 3 is a schematic flowchart of migrating data according to an embodiment of the present application; FIG.

FIG. 4 is a second schematic structural diagram of a storage device according to an embodiment of the present application; FIG.

FIG. 5 is a third structural schematic diagram of a storage device according to an embodiment of the present application; FIG.

FIG. 6 is a fourth structural schematic diagram of a storage device according to an embodiment of the present application.

detailed description

In the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of related objects, and indicates that there can be three kinds of relationships, for example, A and / or B can represent: the case where A exists alone, A and B exist simultaneously, and B alone exists, where A, B can be singular or plural. "At least one or more of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one (a), a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c may be single or multiple. In addition, in the embodiments of the present application, the words “first”, “second” and the like do not limit the number and execution order.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations, or illustrations. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the words "exemplary" or "for example" is intended to present the relevant concept in a concrete manner. "Coupled" in this application can be understood as a direct connection or an indirect connection. For example, A is coupled to B, which can mean that A and B are directly connected, or A and B are indirectly connected.

FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device may be a mobile phone, a tablet computer, a video camera, a camera, a wearable device, a vehicle-mounted device, or a portable device. For convenience of description, the above-mentioned devices are collectively referred to as electronic devices in this application. The embodiment of the present application uses the electronic device as a mobile phone as an example for description. Referring to FIG. 1, the mobile phone includes a system on chip (SoC) 101 and a hybrid memory 102 coupled to the SoC 101.

Among them, SoC 101 is the control center of the mobile phone. It uses various interfaces and lines to connect various parts of the entire device. It runs or executes software programs and / or software modules stored in the hybrid memory, and calls data stored in the hybrid memory. , Perform various functions of the mobile phone and process data, so as to monitor the mobile phone as a whole. In some feasible embodiments, the SoC 101 may include a central processing unit, other types of general-purpose processors, such as digital signal processors, artificial intelligence processors, microcontrollers, or microprocessors. In addition, the SoC 101 may further include a graphics processor (Graphic Processing Unit, GPU), an image signal processor (Image Signal Processor, ISP), or a voice processor. SoC 101 may further include other hardware circuits or accelerators, such as application specific integrated circuits, field programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

In the embodiment of the present application, the hybrid memory 102 may include different types of memory, and the SoC 101 may be used to access any type of memory or storage medium in the hybrid memory 102. Among them, the hybrid memory 102 in FIG. 1 includes a double-rate (Double Data Rate, DDR) synchronous dynamic random access memory (Synchronous Dynamic RAM (SDRAM) (DDR SDRAM for short), NVRAM and NAND flash memory, and DDR SDRAM, As an example, NVRAM and NAND flash memory are integrated together.

The hybrid memory 102 in FIG. 1 incorporates different types of memory, such as DDR SDRAM, NVRAM, and NAND flash memory, and may further include other types of storage. For details, refer to the description of the following embodiments. At least one of the memories 102 or a storage medium therein may be used to store data, software programs, and modules. For example, any memory may include a storage program area and a storage data area, where the storage program area may store a software program, including instructions formed in code, including but not limited to an operating system, and applications required for at least one function, such as sound Playback function, image playback function, etc .; The storage data area can store data created according to the use of the mobile phone, such as audio data, image data, phonebook, etc.

Further, referring to FIG. 1, the mobile phone may further include a sensor component 103, a multimedia component 104, an input / output interface 105, and the like. Each of the above components will be specifically described below.

Among them, the sensor component 103 includes one or more sensors, which are used to provide various aspects of status assessment for the mobile phone. For example, the sensor component 103 may include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications, that is, to become a component of a camera or a camera. In addition, the sensor component 103 may further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor. The sensor component 103 can detect the acceleration / deceleration, orientation, open / close state of the mobile phone, relative positioning of the component, or Cell phone temperature changes, etc.

The multimedia component 104 provides a screen as an output interface between the mobile phone and the user. The screen can be a display panel or a touch panel. When the screen is a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. . The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensor may not only sense a boundary of a touch or slide action, but also detect duration and pressure related to the touch or slide operation. In addition, the multimedia component 104 further includes at least one camera. For example, the multimedia component 104 includes a front camera and / or a rear camera. When the mobile phone is in an operation mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can sense an external multimedia signal, which is used to form an image frame. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

The input / output interface 105 provides an interface between the SoC 101 and a peripheral interface module. For example, the peripheral interface module may include a keyboard, a mouse, or a USB (Universal Serial Bus) device. In a possible implementation manner, the input \ output interface 105 may have only one input \ output interface, or may have multiple input \ output interfaces.

Although not shown, the mobile phone may further include an audio component and a communication component, for example, the audio component includes a microphone, and the communication component includes a wireless fidelity (WiFi) module, a Bluetooth module, and the like, which are not described in the embodiment of this application. . Those skilled in the art can understand that the structure of the mobile phone shown in FIG. 1 does not constitute a limitation on the mobile phone, and may include more or fewer parts than those shown in the figure, or combine certain parts, or arrange different parts. It can be understood that all the components shown in FIG. 1 may be located on the same circuit board, which is not limited in this embodiment.

In order to specifically describe the hybrid memory 102 in FIG. 1, FIG. 2 is a schematic structural diagram of a storage device provided by an embodiment of the present application. The device corresponds to the hybrid memory 102 and includes a package 201, a first memory 202, a second memory 203, The third memory 204, the controller 205, the processor 206, and the bus 207. The first memory 202, the second memory 203, the third memory 204, the controller 205, and the processor 206 are coupled to the bus 207. It should be noted that the embodiment corresponding to FIG. 2 takes three memories in the storage device as an example. In fact, the storage device may include a larger number of memories. The types of these memories are usually different to form a hybrid memory. This embodiment The introduction includes only the first memory 202, the second memory 203, and the third memory 204 as an example, but it is not limited.

In the embodiment of the present application, the controller 205 is configured to migrate data between at least two memories among the first memory 202, the second memory 203, and the third memory 204. For ease of description, the following only uses at least two memories including the first memory 202 and the second memory 203 as an example for description. The migration data between the first memory 202 and the second memory 203 includes at least one of the following: The memory 202 migrates data to or from the second memory 203. The package 201 is used to package the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206, and the bus 207. Due to the existence of the package 201, the storage device has a small size, low cost, and can achieve better performance. When performing the data migration, the data does not need to be transferred to the outside of the storage device, that is, it is completed within the package, and the efficiency is high. For example, the controller 205 is a direct memory access (DMA) device.

The package 201 mentioned in this embodiment may be a chip package for packaging one or more chip particles. For example, the storage device includes the one or more chips, such that the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206, and the bus 207 are located in the one or more Chips on the chip. The package 201 encapsulates the one or more chip particles to form the storage device, thereby achieving miniaturization of the storage device. The specific technology used for chip packaging may be selected from existing packaging technologies, which is not limited in this embodiment. Since the storage device exists as a whole, the internal data migration does not depend on the outside, and the efficiency is high. The package 201 wraps the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206, and the bus 207, which can well implement dustproof, waterproof, or antistatic, so that the storage device As a separate device located on the circuit board.

The first memory 202, the second memory 203, and the third memory 204 are different types of memories. In a possible implementation manner, the first memory 202 is a non-volatile random access memory (Non-Volatile Random Access Memory, NVRAM), the second memory 203 is a NAND flash memory, and the third memory 204 is a double-rate synchronous dynamic Random access memory DDR SDRAM. Any one of the first memory 202, the second memory 203, and the third memory 204 may include a storage medium, and may further include necessary circuits, such as a control circuit for reading and writing to the storage medium, such as an addressing circuit. Examples do not limit this. Different types of memories have different types of storage media, and may also have different types of control circuits.

In addition, here, the controller 204 is used to migrate data from the first memory 202 to the second memory 203 as an example. The controller 204 is used for at least two memories among the first memory 202, the second memory 203, and the third memory 204. Inter-migration data is exemplified. Specifically, the specific process in which the controller 205 migrates data from the first memory 202 to the second memory 203 may include: 1. The first memory 202 sends an operation request to the controller 205, where the operation request is used to request that the first memory 202 Data is transferred to the second memory 203; 2. When the controller 205 receives the operation request, the controller 205 may obtain the bus control authority from the processor 206, for example, the controller 205 sends the processor 206 to request the bus The bus control request that controls the authority; 3. The processor 206 grants the bus control authority to the controller 205, for example, the processor 206 sends a response to the controller 205 that agrees with the above bus control request; 4. The bus control authority is obtained at the controller 205 After that, the controller 205 may send a response agreeing to the operation request to the first memory 202; 5. The controller 205 uses the bus 207 to migrate the data in the first memory to the second memory, for example, the controller 205 enables the first The read channel of the memory 202 to use the bus to read data from the first memory. After the data is read, the first memory 202 can System 205 transmits a data reading end response. In addition, the controller 205 enables the write channel of the second memory 203 to use the bus to write the read data into the second memory. After the data writing is completed, the second memory 203 can send the data write to the controller 205 End response. Further, after the controller 205 completes the above-mentioned migration data, the processor 206 may also release the bus control authority of the controller 205.

Exemplarily, assuming that the first memory 202 is NVRAM and the second memory 203 is NAND flash memory, the flow chart of the controller 204 migrating data from NVRAM to NAND flash memory can be shown in FIG. 3. SC_REQ in Figure 3 indicates the operation request, SC_RESP indicates the response to the operation request, BH_REQ indicates the bus control request, BH_RESP indicates the response to the bus control request, R_EN indicates the read channel is enabled, and W_EN indicates the write channel is enabled. The memories have corresponding R_EN and W_EN. 5a indicates the operation of enabling the read channel R_EN of the first memory 202 in step 5 above, and 5b indicates the operation of enabling the write channel W_EN of the second memory 203 in step 5 above. FIG. 3 is an example in which the bus 207 includes a data bus and an address bus as shown in FIG. 3, and each of the NVRAM and the NAND flash memory corresponds to one R_EN and W_EN.

It should be noted that the specific process of the controller 205 migrating data from the second memory 203 to the first memory 202 is similar to the specific process of the controller 205 migrating data from the first memory 202 to the second memory 203. For details, refer to the foregoing description. . In addition, the specific process of the controller 204 migrating data between at least two memories of the first memory 202, the second memory 203, and the third memory 204 and the above-mentioned process of migrating data between the first memory 202 and the second memory 203 The specific process is also similar. For details, refer to the foregoing description, which is not repeatedly described in the embodiment of the present application. It can be understood that at least two memories can be transmitted in both directions simultaneously or only in one direction, which is not limited in this embodiment.

In practical applications, as an alternative embodiment, the first storage 202 and the second storage 203 may also use the same type of storage medium, and the controller 205 may also use the same type of storage medium between the two types of storage media. Migrating data between. Generally speaking, the first storage 202 and the second storage 203 use different types of storage media, which is a more common choice. When the first memory 202 and the second memory 203 use the same type of storage medium, the two memories are the same memory. Therefore, the storage device including the two memories is a non-hybrid memory, but still can achieve similar functions. When migrating data between two memories, it is still not necessary to transfer the data to the outside of the storage device, and efficiency can be improved.

Further, the device further includes an interface 208 coupled to the controller 205, for coupling the first memory 202, the second memory 203, and the second memory 204 to a processing device located outside the package 201 of the storage device. The interface 208 may include: at least two interfaces. Optionally, any one of the at least two interfaces is: Peripheral Component Interconnect Standard (PCIe) interface, double-rate synchronous dynamic random access memory DDR SDRAM interface, or universal flash storage (Universal Flash Storage (UFS) interface.

In a possible implementation manner, referring to FIG. 4, the interface 208 includes a UFS interface and a DDR SDRAM interface. The DDR SDRAM interface is used to couple the first memory 202 and the third memory 204 to the outside of the package 201 of the storage device. The UFS interface is used to couple the second memory 203 to a processing device located outside the package 201 of the storage device. For example, the processing device may be the SoC 101 shown in FIG. 1 or a circuit motherboard including the SoC 101. That is, the controller 205 can transmit the data of the first memory 202 or the third memory 204 with the processing device through the DDR SDRAM interface and the data of the second memory 203 with the processing device through the UFS interface. The data can include reading Fetched data and written data. In another possible implementation manner, referring to FIG. 5, the interface 208 includes a PCIe interface, a UFS interface, and a DDR SDRAM interface. The PCIe interface is used to couple the first memory 202 to a processing device outside the package 201, that is, to control. The processor 205 can transmit the data of the first memory 202 to the processing device through the PCIe interface; the UFS interface is used to couple the second memory 203 to the processing device outside the package 201, that is, the controller 205 can communicate with the processing device through the UFS interface The data of the second memory 203 is transmitted; the DDR SDRAM interface is used to couple the third memory 204 to a processing device outside the package 201, that is, the controller 205 can transmit the data of the third memory 204 to the processing device through the DDR SDRAM interface.

It should be noted that the interface 208 includes only a PCIe interface, a UFS interface, and / or a DDR SDRAM interface as an example for description. In practical applications, the interface 208 may also include an embedded multimedia controller (Embedded MultiMedia Card, eMMC). The interface and the like may be used to couple the eMMC memory located in the hybrid memory to the processing device, which is not specifically limited in the embodiment of the present application. The types of interfaces mentioned in this embodiment are also extensible and are not necessarily limited to the types listed in this embodiment.

In the storage device provided in the embodiment of the present application, the controller 205 can migrate data between at least two memories of the first memory 202, the second memory 203, and the third memory 204 packaged in the same package, thereby achieving Efficient data migration between different storage media. For example, the controller 205 is a DMA device, and is configured to implement the data migration instead of the DMA device in the SoC101. The DMA device built in the storage device makes it unnecessary to transfer the data to the outside of the storage device when migrating data, which improves efficiency. At the same time, when the storage device is applied to an electronic device including a processing device, the entire data migration process does not require the participation of the processing device, thereby reducing the power consumption of the electronic device during data migration and improving the performance of the electronic device.

In another embodiment of the present application, a storage device is further provided. As shown in FIG. 6, the storage device includes: a package 301, a first memory 302, a second memory 303, a third memory 304, and a first memory coupled to the first memory. The first controller 305 of the memory 302, the second controller 306 coupled to the second memory 303, the third controller 307 coupled to the third memory 304, the processor 308, and the bus 309. The first memory 302, the second memory 303, the third memory 304, the first controller 305, the second controller 306, the third controller 307, and the processor 308 are coupled to the bus 309.

In the embodiment of the present application, the package 301 is used to package the first memory 302, the second memory 303, the third memory 304, the first controller 305, the second controller 306, the third controller 307, the processor 308, and the bus. 309. The first memory 302, the second memory 303, and the third memory 304 may be different types of memories. In a possible implementation manner, the first memory 302 may be NVRAM, and the second memory 303 may be a NAND flash memory. The third memory 304 is DDR SDRAM, but it is not used for limitation. For example, the storage device may include more other types of memory.

Further, the storage device further includes: a first interface 310 coupled to the first controller 305, for coupling the first memory 302 to a processing device located outside the package 301 of the storage device; and coupled to the second controller A second interface 311 of 306 is used for coupling the second memory 303 to a processing device located outside the package 301 of the storage device; and a third interface 312 of the third controller 307 is used for coupling the third memory 304 To processing equipment located outside the package 301 of the storage device. The first interface 310 may include a PCIe interface, that is, the first controller 305 may transmit data of the first memory 302 to the processing device through the PCIe interface; the second interface 311 may include a UFS interface, that is, the second controller 306 may The data of the second memory 303 is transmitted to the processing device through the UFS interface; the third interface 312 may include a DDR SDRAM interface, that is, the third controller 307 may transmit data of the third memory 304 to the processing device through the DDR SDRAM interface. It should be noted that the PCIe interface, UFS interface, and / or DDR SDRAM interface are used as examples for illustration. In practical applications, the first interface, the second interface, and the third interface may also include other interfaces. Examples do not specifically limit this.

An embodiment of the present application further provides an electronic device. The electronic device may include a storage device and a processing device according to the foregoing embodiments. The storage device may be as shown in the foregoing FIG. 2, FIG. 4, FIG. 5, or FIG. 6. The processing device may be a system-on-chip SoC 101. Specifically, a schematic structural diagram of the electronic device may be shown in FIG. 1.

As a hybrid memory, the storage device of this embodiment includes built-in different types of memories or storage media, and internally transfers data between different memories. For example, different memories may include NVRAM, NAND flash memory, and DDR SDRAM. NVRAM generally has a small storage capacity, while NAND flash memory has a larger capacity, and NVRAM can be used as a data cache for NAND flash memory to achieve good performance. In the hybrid memory structure of this embodiment, for example, in the storage device shown in FIG. 2, the first memory 202, the second memory 203, the third memory 204, the controller 205, the processor 206, and the bus 207 may be located on one chip. To form a whole. Alternatively, these components may be located in different multiple chip particles, but are packaged in a package, and the advantages of miniaturization of the device can still be achieved. For example, since the first memory 202, the second memory 203, and the third memory 204 are different types of memories, they may be located on different chip particles. In addition, the controller 205, the processor 206, and the bus 207 may be located on another independent chip particle to implement a control function. The controller 205 may be a DMA device, which is built into the storage device and becomes a part of the storage device for the data migration. Therefore, data migration does not need to go through external equipment, for example, DMA equipment in SoC 101 is not required to participate.

The above is only a specific implementation of this application, but the scope of protection of this application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application. It should be covered by the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A storage device, characterized in that the device includes: a package, a first memory, a second memory, a third memory, and a controller;

The controller is coupled to the first memory, the second memory, and the third memory, and is used for at least two of the first memory, the second memory, and the third memory Migrating data between storages;

The first memory, the second memory, and the third memory are different types of memories;

The package is used to package the first memory, the second memory, the third memory, and the controller.
The storage device according to claim 1, wherein the first memory is a non-volatile random access memory NVRAM, and the second memory is a NAND flash memory.
The storage device according to claim 2, wherein the third memory is a double-rate synchronous dynamic random access memory (DDRS).
The storage device according to any one of claims 1-3, wherein the device further comprises: a bus and a processor, the processor, the controller, the first memory, and the second A memory and the third memory are coupled to the bus, and the package is further configured to encapsulate the bus and the processor;

The controller is further configured to obtain bus control authority from the processor, and use the bus to migrate data between the at least two memories;

The processor is configured to grant the bus control authority to the controller.
The storage device according to claim 4, wherein the controller is further configured to receive information about all data from at least one of the at least two memories before migrating data between the at least two memories. The operation request for migrating data is described.
The storage device according to claim 5, wherein the controller is further configured to send a response agreeing to the operation request to the at least one memory.
The storage device according to any one of claims 4-6, wherein the processor is further configured to release the bus control authority of the controller after the controller completes the migration data. .
The storage device according to any one of claims 1-7, wherein the device further comprises: an interface coupled to the controller, configured to connect the first memory, the second memory, and all The third memory is coupled to a processing device located outside the package.
The storage device according to claim 8, wherein the interface comprises at least two interfaces.
The storage device according to claim 9, wherein any one of the at least two interfaces is: a peripheral component interconnect standard PCIe interface, a double-rate synchronous dynamic random access memory (DDR) SDRAM interface, or a general-purpose flash memory Store UFS interface.
An electronic device, comprising the storage device according to any one of claims 8 to 10, and the processing device.
The electronic device according to claim 11, wherein the processing device is a system-on-chip (SoC).