WO2020048020A1 - 薄膜晶体管、显示面板及薄膜晶体管的制作方法 - Google Patents

薄膜晶体管、显示面板及薄膜晶体管的制作方法 Download PDF

Info

Publication number
WO2020048020A1
WO2020048020A1 PCT/CN2018/117578 CN2018117578W WO2020048020A1 WO 2020048020 A1 WO2020048020 A1 WO 2020048020A1 CN 2018117578 W CN2018117578 W CN 2018117578W WO 2020048020 A1 WO2020048020 A1 WO 2020048020A1
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric layer
layer
gate dielectric
silicon oxide
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/117578
Other languages
English (en)
French (fr)
Inventor
罗传宝
卢马才
王松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2020048020A1 publication Critical patent/WO2020048020A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a method for manufacturing a thin film transistor, a display panel, and a thin film transistor.
  • Amorphous indium gallium zinc oxide thin film transistor is a representative metal oxide thin film transistor and is widely used in various electronic display devices.
  • IGZO thin film transistors have three typical structures: back channel etching, etch stop layer (ESL) and top gate.
  • the top-gate IGZO thin film transistor structure has a small parasitic capacitance, and the number of masks used in the manufacturing process is relatively small.
  • the gate and the gate dielectric layer can protect the channel region from being affected by the atmospheric environment and the plasma in subsequent processes.
  • the strong electric field in the region of the gate dielectric layer will cause high-energy electrons in the channel to be injected into the gate dielectric layer near the source-drain terminals, which will cause the threshold voltage of the device to drift and destroy the stability of the device.
  • the high electric field will also cause hot carrier effect, which further damages the stability of the device.
  • the present invention provides a thin film transistor, which can effectively reduce the electric field intensity of the channel region and increase the stability of the device.
  • the thin film transistor includes:
  • An active region located above the substrate
  • a gate metal located above the gate dielectric layer
  • the source and drain regions are located on both sides of the active region below the gate dielectric layer;
  • the gate dielectric layer includes a silicon oxide layer over the active region and a second gate dielectric layer over the silicon oxide layer.
  • the length of the silicon oxide layer in the channel direction is shorter than the length of the second gate.
  • the second gate dielectric layer is a silicon nitride layer.
  • the transistor further includes an interlayer dielectric layer.
  • the material of the interlayer dielectric layer is silicon nitride, and the hydrogen element content in the silicon nitride is less than that in the silicon nitride layer. Content of hydrogen.
  • a space on both sides of the silicon oxide layer under the second gate dielectric layer is filled with an interlayer dielectric layer.
  • a length of the silicon oxide layer in a channel direction is not less than a half of a length of the second gate dielectric layer in a channel direction.
  • the present invention also provides a display panel including the thin film transistor described above, and the transistor includes:
  • An active region located above the substrate
  • a gate metal located above the gate dielectric layer
  • the source and drain regions are located in active regions on both sides of the channel region;
  • the gate dielectric layer includes a silicon oxide layer over the active region and a second gate dielectric layer over the silicon oxide layer.
  • the length of the silicon oxide layer in the channel direction is shorter than the length of the second gate.
  • the second gate dielectric layer is a silicon nitride layer.
  • the transistor further includes an interlayer dielectric layer.
  • the material of the interlayer dielectric layer is silicon nitride, and the hydrogen element content in the silicon nitride is less than that in the silicon nitride layer. Content of hydrogen.
  • a space on both sides of the silicon oxide layer under the second gate dielectric layer is filled with an interlayer dielectric layer.
  • a length of the silicon oxide layer in a channel direction is not less than a half of a length of the second gate dielectric layer in a channel direction.
  • the display panel further includes:
  • a color resist layer located above the passivation layer outside the active region
  • An organic light emitting layer located above the pixel electrode
  • the cathode is located above the organic light emitting layer.
  • the present invention also provides a method for manufacturing a thin film transistor, wherein the method includes:
  • the second gate dielectric layer is a silicon nitride layer.
  • the method further includes step h: forming an interlayer dielectric layer covering the thin film transistor, wherein the material forming the interlayer dielectric layer is silicon nitride, and forming The hydrogen element content in the silicon nitride of the interlayer dielectric layer is lower than the hydrogen element content in the second gate dielectric layer.
  • the length of the second gate dielectric layer in step d is greater than the length of the gate dielectric layer required by the thin film transistor.
  • the etching method used for selective etching in step f is dry etching, and the etching gas is C 5 HF 7 .
  • a length of the silicon oxide layer in a channel direction is not less than a half of a length of the second gate dielectric layer in a channel direction.
  • the present invention uses silicon nitride with a larger dielectric constant to replace part of the gate dielectric layer, so that the dielectric constant of the gate dielectric layer
  • the reduction reduces the electric field in the channel region, especially in the regions at both ends of the channel, thereby suppressing the threshold voltage drift and hot carrier effect caused by the high electric field.
  • the performance of the thin film transistor is greatly improved.
  • FIG. 1 is a schematic structural diagram of a thin film transistor in the prior art
  • FIG. 2 is an electric field distribution diagram of a channel region of the thin film transistor in FIG. 1;
  • 3 to 8 are schematic structural diagrams of a thin film transistor in different process steps according to an embodiment of the present invention.
  • FIG. 9 is an electric field distribution diagram of a channel region of the thin film transistor in FIG. 8.
  • FIG. 1 shows a schematic structural diagram of a thin film transistor in the prior art. Specifically, it is a top-gate IGZO thin film transistor.
  • the gate structure in the prior art includes a gate dielectric layer 060 located under the gate metal 070 and is composed of silicon oxide.
  • the formation method is: epitaxial growth is formed over the active region to form silicon oxide, which is used as an insulating material to isolate the gate metal from the active region. Because the interface characteristics between the epitaxially grown silicon dioxide and the active region are excellent, and there are few impurities and defects, silicon dioxide has been used as a mainstream gate dielectric layer material to this day.
  • silicon dioxide also has obvious defects, that is, the dielectric constant is too small.
  • the electric field strength in the channel region is inversely proportional to the dielectric constant of the dielectric layer. Too small a dielectric constant will cause the electric field strength in the channel region to be too large, causing threshold voltage shifts and hot carrier effects. The series of defects seriously affect the performance of the device.
  • FIG. 2 is an electric field distribution diagram of the thin film transistor channel region in FIG. 1. It can be seen that the electric field intensity of the channel region reaches 10 5 V / cm, and the electric field intensity at both ends of the channel is due to the device shape. The impact of the device is further increased, which has seriously affected the device performance.
  • the present invention provides a thin film transistor.
  • the present invention will be described in detail below with reference to FIG. 8.
  • the present invention provides a thin film transistor including: a substrate 130; an active region 140 located above the substrate 130; a gate dielectric layer located above the active region 140; a gate metal 170 Is located above the gate dielectric layer; source and drain regions are located in active regions 140 on both sides of the channel region.
  • the substrate 130 may be a semiconductor substrate of a single material, such as silicon, germanium, gallium arsenide, indium phosphide, or the like, or an SOI semiconductor substrate.
  • the active region 140 is located above the substrate 130 and has a certain doping.
  • the doping concentration is the concentration required by the channel region, and is usually 5 ⁇ 10 14 cm -3 to 5 ⁇ 10 15 cm -3 .
  • the doped elements are usually P-type 15 impurities, such as boron and indium; for P-type semiconductors, P-type impurities, such as arsenic and phosphorus.
  • the gate dielectric layer includes a silicon oxide layer 151 located above the active region and a second gate dielectric layer 160 located above the silicon oxide layer.
  • the silicon oxide layer 151 extends along the channel. The length in the direction is smaller than the length of the second gate dielectric layer 160; wherein the dielectric constant of the silicon oxide layer 151 is greater than the dielectric constant of the second gate dielectric layer 160.
  • the second gate dielectric layer 160 is a silicon nitride layer.
  • the second gate dielectric layer 160 may also be made of other materials with high dielectric constants, such as hafnium oxide, aluminum oxide, and titanium oxide.
  • the above materials all have high dielectric constants, which can further To reduce the electric field intensity in the channel region, in actual applications, a suitable dielectric material can be selected according to needs.
  • the order of forming a gate dielectric layer in the process is: sequentially depositing a gate dielectric layer and a gate metal layer on the active area, and then plasma-etching or other etching methods
  • the gate structure is patterned to form the required gate stack.
  • plasma etching as an example, the width of the structure in the lower layer is generally slightly wider than that in the upper layer due to the cumulative edge effect of the etching. See FIG. 1, where the width of the gate dielectric layer 050 in the lower layer is greater than that of the metal layer 070 in the upper layer. .
  • the length of the silicon oxide layer 151 in the channel direction is shorter than the length of the silicon nitride layer 160
  • the side surface selectively etches the gate dielectric layer along the channel direction.
  • dry etching can be selected. Because the etching gas of dry etching has different speeds for different materials, it can achieve rapid etching of silicon oxide in the lateral direction while silicon nitride etching is slow or even slow. Etching.
  • C 5 HF 7 can be selected as the etching gas.
  • the etching rate of C 5 HF 7 for silicon oxide can reach 400 ⁇ 500nm / min, while the etching rate for silicon nitride is only 100 ⁇ 150nm / min.
  • the etching rate of metal and metal is almost 0. Therefore, the silicon oxide layer 151 and the silicon nitride layer 160 can be perfectly etched into an inverted step structure as shown in FIG. 8.
  • C 5 HF 7 is only an option and should not be construed as a limitation on the present invention.
  • other etching gases can be selected for selective etching, and the etching parameters can be set according to specific process conditions and actual needs.
  • a length of the silicon oxide layer in a channel direction is not less than a half of a length of the second gate dielectric layer in a channel direction. If it is less than this ratio, the silicon oxide above the channel region will be etched away and replaced by silicon nitride, and the interface performance between silicon nitride and the active region is not as good as that of silicon oxide and the active region. In terms of interfacial performance, silicon oxide being over-etched will cause the subthreshold characteristics of the channel region to increase significantly, affecting device performance.
  • the specific etching ratio is based on the effective length of the channel, and can be set as required in practice.
  • the transistor further includes an interlayer dielectric layer 180.
  • the material of the interlayer dielectric layer is silicon nitride, and the hydrogen element content in the silicon nitride is less than the hydrogen element content in the silicon nitride layer 160.
  • the interlayer dielectric layer 180 simultaneously fills the space on both sides of the silicon oxide layer 151 under the silicon nitride layer 160 by diffusion, that is, the original silicon oxide in this area is replaced by silicon nitride. Since the hydrogen element content in the interlayer dielectric layer 180 is smaller than the hydrogen element content in the silicon nitride layer 160 and has a larger dielectric constant, the electric field strength in this region can be further reduced.
  • the present invention uses silicon nitride with a larger dielectric constant to replace part of the gate dielectric layer, so that the dielectric constant of the gate dielectric layer Is reduced, thereby reducing the electric field in the channel region. Further, the present invention also uses a structure in which a cavity is combined with silicon nitride as a gate dielectric layer, so that the dielectric constant of the gate dielectric layer is greatly reduced compared to silicon oxide, which effectively reduces the electric field, thereby curbing The threshold voltage drift and hot carrier effect caused by the high electric field are described. Compared with the prior art, the performance of the thin film transistor is greatly improved.
  • the present invention also provides a display panel including the thin film transistor described above.
  • the display panel further includes a passivation layer 210 above the interlayer dielectric layer, a color resist layer 240 above the passivation layer 210 outside the active region, and the color resist layer A pixel electrode 250 above 240, an organic light emitting layer 260 above the pixel electrode 250, and a cathode 270 above the organic light emitting layer 260.
  • the invention adopts a sandwich structure in which the gate insulating layer is optimized into a silicon oxide layer and a silicon nitride layer, and the dry etching method is used to hollow out both sides of the silicon nitride layer below the silicon nitride layer, thereby reducing the gate insulation.
  • the electric field strength on both sides of the layer avoids threshold voltage drift and hot carrier effects caused by high electric fields. Therefore, the present invention can improve the top-gate IGZO
  • the stability and yield of TFT devices reduce the threshold voltage drift to meet the display's needs for products with high frame rates and high resolution.
  • the method includes the following steps:
  • Source and drain regions are formed on both sides of the active region 140 below the second gate dielectric layer 160.
  • the substrate is a semiconductor material.
  • the substrate may be a single semiconductor such as silicon or germanium, or a Group III or Five compound semiconductor such as gallium arsenide. Common technologies in the field are not repeated here.
  • an active region 140 is formed over the substrate 130.
  • the active region is an amorphous indium gallium zinc oxide film, and the IGZO film has significant advantages such as high resolution, large size, high processing frame rate, and high transmittance in the visible light range, and is more suitable.
  • the IGZO film has significant advantages such as high resolution, large size, high processing frame rate, and high transmittance in the visible light range, and is more suitable. Used in the field of electronic displays, such as TFT arrays in liquid crystal displays.
  • a silicon oxide layer 150 is formed over the active region 140.
  • the silicon oxide layer 150 may be formed by vapor phase epitaxy, and between the silicon oxide layer generated by gas phase epitaxy and the active region Has a good interface state, defects and impurities are better than vapor deposition.
  • a second gate dielectric layer 160 is generated above the silicon oxide layer 150, and the dielectric constant of the silicon oxide layer 150 is greater than the dielectric constant of the second gate dielectric layer 160.
  • the second gate dielectric layer 160 in the present example is a silicon nitride layer.
  • the second gate dielectric layer 160 may also be made of other materials with high dielectric constants, such as hafnium oxide, aluminum oxide, and titanium oxide. The above materials all have high dielectric constants, which can further To reduce the electric field intensity in the channel region, in actual applications, a suitable dielectric material can be selected according to needs.
  • a gate metal 170 is formed over the gate dielectric layer.
  • the material of the gate metal layer may be one of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTa, or a combination thereof, and the thickness is between 5 nm and 20 nm.
  • the gate metal can be formed by chemical vapor deposition, high-density plasma chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, pulsed laser deposition, or other suitable methods.
  • the silicon oxide layer 150, the second gate dielectric layer 160, and the gate metal 170 are patterned to expose a part of the active region 140 to form a gate structure.
  • the silicon oxide layer 150, the second gate dielectric layer 160, and the gate metal 170 are selectively etched along the channel direction, so that the length of the etched silicon oxide layer 151 along the channel direction is less than Second gate dielectric layer 160.
  • a step of selective etching is required after the gate pattern is patterned, and the side edge The gate dielectric layer is selectively etched in the channel direction.
  • dry etching can be selected. Because the etching gas of dry etching has different speeds for different materials, it can achieve rapid etching of silicon oxide in the lateral direction while silicon nitride etching is slow or even slow. Etching.
  • C 5 HF 7 can be selected as the etching gas.
  • the etching rate of C 5 HF 7 for silicon oxide can reach 400 ⁇ 500nm / min, while the etching rate for silicon nitride is only 100 ⁇ 150nm / min.
  • the etching rate of metal and metal is almost 0. Therefore, the silicon oxide layer 151 and the silicon nitride layer 160 can be perfectly etched into an inverted step structure as shown in FIG. 8.
  • C 5 HF 7 is only an option and should not be construed as a limitation on the present invention.
  • other etching gases can be selected for selective etching, and the etching parameters can be set according to specific process conditions and actual needs.
  • a length of the silicon oxide layer in a channel direction is not less than a half of a length of the second gate dielectric layer in a channel direction. If it is less than this ratio, the silicon oxide above the channel region will be etched away and replaced by silicon nitride, and the interface performance between silicon nitride and the active region is not as good as that of silicon oxide and the active region. In terms of interfacial performance, silicon oxide being over-etched will cause the subthreshold characteristics of the channel region to increase significantly, affecting device performance.
  • the specific etching ratio is based on the effective length of the channel, and can be set as required in practice.
  • step g a source-drain region is formed under the gate dielectric layer.
  • the source-drain region may be formed by implanting a P-type or N-type dopant or impurity into the active region.
  • the source-drain region may be P-type doped.
  • the source and drain regions are formed.
  • the drain region may be N-type doped.
  • the source / drain regions may be formed by a method including photolithography, ion implantation, diffusion, and / or other suitable processes.
  • the source / drain region may be a raised source-drain structure formed by selective epitaxial growth, and the top of the epitaxial portion is higher than the bottom of the gate stack. The high temperature treatment is then used to activate the impurities, such as an annealing process.
  • the source-drain region after the source-drain region is formed, it further includes a step h: forming an interlayer dielectric layer 180 covering the thin film transistor, wherein a material forming the interlayer dielectric layer 180 is nitrogen. Silicon, and the hydrogen element content in the silicon nitride forming the interlayer dielectric layer 180 is lower than the hydrogen element content in the silicon nitride layer 160.
  • the interlayer dielectric layer may be formed on the substrate by chemical vapor deposition, high-density plasma, spin coating, or other suitable methods.
  • the material of the interlayer dielectric layer may include SiO 2 , carbon-doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, low-k material, or a combination thereof.
  • the thickness of the interlayer dielectric layer can range from 40 nm to 150 nm, such as 80 nm, 100 nm, or 120 nm.
  • the method further includes: forming a passivation layer 210 above the interlayer dielectric layer, and forming a color resist layer above the passivation layer 210 outside the active region. 240.
  • a pixel electrode 250 is formed over the color resist layer 240, an organic light emitting layer 260 is formed over the pixel electrode 250, and a cathode 270 is formed over the organic light emitting 260 layer, thereby forming a display panel having the aforementioned thin film transistor.
  • the gate dielectric layer in the present invention adopts an inverted stepped stacked structure, which not only increases the dielectric constant of the gate dielectric layer by stacking silicon nitride and silicon oxide, but also selectively etches and interlayers.
  • the method of dielectric layer deposition replaces the silicon oxide under the silicon nitride at the two ends of the channel with silicon nitride, which further reduces the electric field intensity at both ends of the channel. See FIG. 9, which is a thin film transistor channel in the present invention
  • the electric field strength in the region can be seen that the electric field in the channel region has been significantly reduced, especially in the regions at both ends of the channel, the electric field intensity has decreased by an order of magnitude.
  • the present invention uses silicon nitride with a larger dielectric constant to replace part of the gate dielectric layer, so that the dielectric constant of the gate dielectric layer The reduction reduces the electric field in the channel region and suppresses the threshold voltage drift and hot carrier effect caused by the high electric field. Compared with the prior art, the performance of the thin film transistor is greatly improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管，所述晶体管包括：衬底（130）；有源区（140），位于所述衬底（130）上方；栅极介质层，位于所述有源区（140）上方；栅极金属（170），位于所述栅极介质层上方；源漏区，位于沟道区两侧的有源区（140）中；其中，所述栅极介质层包括位于所述有源区（140）上方的氧化硅层（151）和位于所述氧化硅层（151）上方的第二栅介质层（160），所述氧化硅层（151）沿沟道方向的长度小于所述第二栅介质层（160）的长度；其中，所述第二栅介质层（160）的介电常数大于氧化硅层（151）的介电常数。

Description

薄膜晶体管、显示面板及薄膜晶体管的制作方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种薄膜晶体管、显示面板及薄膜晶体管的制作方法。
 背景技术
近年来，金属氧化物薄膜晶体管被普遍应用于液晶显示器和有机自发光显示器中，使用该晶体管的显示器具有分辨率高、尺寸大、处理帧率高和可见光范围内穿透率高等显著优点，在电子显示领域具有广阔的应用前景。非晶铟镓锌氧化物薄膜晶体管是一种代表性的金属氧化物薄膜晶体管，被广泛应用在各种电子显示设备中。
 技术问题
目前，IGZO薄膜晶体管有背沟道刻蚀, 蚀刻终止层(ESL)和顶栅三种典型结构。顶栅型IGZO薄膜晶体管结构的寄生电容小，制作工艺中使用的掩膜数量也相对较少。同时，栅极和栅极介质层能够保护沟道区，使其不被大气环境和后续制程中的电浆所影响。但是，栅极介质层区域的较强电场将使沟道中的高能电子在源漏端附近注入栅极介质层，导致器件的阈值电压漂移，破坏了器件的稳定性。此外，高电场还会引发热载流子效应，进一步破坏了器件的稳定性。
因此，急需开发一种稳定性更高的顶栅型IGZO薄膜晶体管结构解决上述问题。
 技术解决方案
为解决上述问题，本发明提供了一种薄膜晶体管，能够有效的减小沟道区域的电场强度，增加器件的稳定性。具体的，所述薄膜晶体管包括：
衬底；
有源区，位于所述衬底上方；
栅极介质层，位于所述有源区上方；
栅极金属，位于所述栅极介质层上方；
源漏区，位于所述栅极介质层下方的有源区两侧；其中，
所述栅极介质层包括位于所述有源区上方的氧化硅层和位于所述氧化硅层上方的第二栅介质层，所述氧化硅层沿沟道方向的长度小于所述第二栅介质层的长度；其中，所述第二栅介质层的介电常数大于氧化硅层的介电常数。
根据本发明的其中一个实施例，其中，所述第二栅介质层为氮化硅层。
根据本发明的其中一个实施例，其中，所述晶体管还包括层间介质层，所述层间介质层的材料为氮化硅，所述氮化硅中的氢元素含量小于氮化硅层中的氢元素含量。
根据本发明的其中一个实施例，其中，所述第二栅介质层下方的氧化硅层两侧的空间被层间介质层填充。
根据本发明的其中一个实施例，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
相应的，本发明还提供了一种显示面板，包括如前所述的薄膜晶体管，所述晶体管包括：
衬底；
有源区，位于所述衬底上方；
栅极介质层，位于所述有源区上方；
栅极金属，位于所述栅极介质层上方；
源漏区，位于所述沟道区两侧的有源区中；其中，
所述栅极介质层包括位于所述有源区上方的氧化硅层和位于所述氧化硅层上方的第二栅介质层，所述氧化硅层沿沟道方向的长度小于所述第二栅介质层的长度；其中，所述第二栅介质层的介电常数大于氧化硅层的介电常数。
根据本发明的其中一个实施例，其中，所述第二栅介质层为氮化硅层。
根据本发明的其中一个实施例，其中，所述晶体管还包括层间介质层，所述层间介质层的材料为氮化硅，所述氮化硅中的氢元素含量小于氮化硅层中的氢元素含量。
根据本发明的其中一个实施例，其中，所述第二栅介质层下方的氧化硅层两侧的空间被层间介质层填充。
根据本发明的其中一个实施例，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
根据本发明的其中一个实施例，其中，所述显示面板还包括：
钝化层，位于所述层间介质层上方；
色阻层，位于所述有源区外侧的钝化层上方；
像素电极，位于所述色阻层上方；
有机发光层，位于所述像素电极上方；
阴极，位于所述有机发光层上方。
相应的，本发明还提供了一种薄膜晶体管的制作方法，其中，该方法包括：
a. 提供衬底；
b. 在所述衬底上方形成有源区；
c. 在所述有源区上方形成氧化硅层；
d. 在所述有氧化硅层上方形成第二栅介质层；
e. 在所述栅极介质层上方形成栅极金属；
f. 沿沟道方向进对氧化硅层和第二栅介质层进行选择性刻蚀，使刻蚀后的氧化硅层沿沟道方向的长度小于第二栅介质层；
g. 在所述第二栅介质层两侧的有源区中形成源漏区。
根据本发明的其中一个实施例，其中，所述第二栅介质层为氮化硅层。
根据本发明的其中一个实施例，其中，在步骤g之后还包括步骤h：形成覆盖所述薄膜晶体管的层间介质层，其中，形成所述层间介质层的材料为氮化硅，且形成所述层间介质层的氮化硅中的氢元素含量低于第二栅介质层中的氢元素含量。
根据本发明的其中一个实施例，其中，步骤d中的第二栅介质层的长度大于所述薄膜晶体管所需要的栅极介质层的长度。
根据本发明的其中一个实施例，其中，在步骤f中选择性刻蚀所用的刻蚀方法为干法刻蚀，刻蚀气体为C 5HF 7。
根据本发明的其中一个实施例，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
 有益效果
相比于现有技术中采用氧化硅材料作为栅极介质层的薄膜晶体管，本发明采用了介电常数较大的氮化硅替换了部分栅极介质层，使得栅极介质层的介电常数减小，从而减小沟道区的电场，特别是位于沟道两端区域的电场，从而遏制了由于高电场引起阈值电压漂移和热载流子效应。相比于现有技术，极大地改善了薄膜晶体管的性能。
 附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1为现有技术中的薄膜晶体管的结构示意图；
图2为图1中的薄膜晶体管沟道区域的电场分布图；
图3至图8为本发明一个实施例中的薄膜晶体管在不同工艺步骤中的结构示意图；
图9为图8中的薄膜晶体管沟道区域的电场分布图；
附图中相同或相似的附图标记代表相同或相似的部件。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
首先对现有技术进行简要说明。参见图1，图1示出了现有技术中的薄膜晶体管的结构示意图，具体的，是一种顶栅型IGZO薄膜晶体管。如图所示，现有技术中的栅极结构由栅极介质层060位于栅极金属070下方，由氧化硅组成。其形成方法为：在有源区上方外延生长形成氧化硅，作为绝缘材料隔离栅极金属和有源区。由于外延生长的二氧化硅与有源区之间的界面特性优良，少有杂质和缺陷，因此二氧化硅作为主流的栅极介质层材料被沿用至今。但二氧化硅也存在明显的缺陷，即介电常数过小。对于薄膜晶体管，沟道区域的电场强度与介质层的介电常数成反比，过小的介电常数会导致沟道区的电场强度过大，引发阈值电压偏移、热载流子效应等一系列缺陷，严重影响器件的性能。
参见图2，图2为图1中的薄膜晶体管沟道区域的电场分布图，可以看出，沟道区域的电场强度达到了10 5V/cm，而沟道两端的电场强度则由于器件形状的影响进一步增大，已经严重影响了器件性能。
为了改善上述缺陷，本发明提供了一种薄膜晶体管。下面将结,图8对本发明进行详细说明。
参见图8，本发明提供了一种薄膜晶体管，包括：衬底130；有源区140，位于所述衬底130上方；栅极介质层，位于所述有源区140上方；栅极金属170，位于所述栅极介质层上方；源漏区，位于所述沟道区两侧的有源区140中。
具体的，所述衬底130可以是单一材料的半导体衬底，例如硅、锗、砷化镓、磷化铟等，也可以是SOI半导体衬底。所述有源区140位于衬底130上方，具有一定的掺杂，掺杂浓度为沟道区所需要的浓度，通常为5×10 14cm -3~5×10 15cm -3，对于N型半导体，掺杂的元素通常为P型15杂质，例如硼和铟，对于P型半导体，P型杂质，例如砷和磷。
在本实施例中，所述栅极介质层包括位于所述有源区上方的氧化硅层151和位于所述氧化硅层上方的第二栅介质层160，所述氧化硅层151沿沟道方向的长度小于所述第二栅介质层160的长度；其中，所述氧化硅层151的介电常数大于第二栅介质层160的介电常数。具体的，由于在氧化硅层上生长或淀积氮化硅层的工艺在本领域中相对成熟，且氮化硅的相对介电常数约为7，大于氧化硅的相对介电常数4，因此，本实施例中所述第二栅介质层160为氮化硅层。在其他实施例中，所述第二栅极介质层160也可以采用其他介电常数高的材料，例如氧化铪、氧化铝、氧化钛等，上述材料都拥有很高的介电常数，能够进一步减小沟道区域的电场强度，在实际应用中可以根据需要挑选合适的介电材料。
通常，对于顶栅型薄膜晶体管，在工艺中形成栅极介质层的顺序为：在有源区上依次淀积栅极介质层、栅极金属层，之后通过等离子刻蚀或其他刻蚀方法将栅极结构图形化，形成需要的栅极叠层。以等离子刻蚀为例，由于刻蚀的边缘累积效应，通常位于下层的结构的宽度略宽于上层结构，参见图1，其中位于下层的栅极介质层050的宽度大于位于上层的金属层070。
在本发明中，为了实现所述氧化硅层151沿沟道方向的长度小于所述氮化硅层160的长度这一技术特征，需要在栅极图形化之后增益一步选择性刻蚀工艺，从侧面沿着沟道方向对栅极介质层进行选择性刻蚀。具体的，可以选择干法刻蚀，由于干法刻蚀的刻蚀气体对不同的材料的可是速度差异很大，因此可以实现在横向快速刻蚀氧化硅的同时氮化硅刻蚀很慢甚至刻蚀。
例如，可以选择C 5HF 7作为刻蚀气体，C 5HF 7对于氧化硅的刻蚀速率可以达到400~500nm/min，同时对于氮化硅的刻蚀速率只有100~150nm/min，对多晶硅和金属的刻蚀速率几乎为0，因此，可以完美的将氧化硅层151和氮化硅层160刻蚀为图8所示的倒台阶型结构。当然，在实际应用中，C 5HF 7只是一种选择，不应理解为对本发明的限制。也可以选择其他刻蚀气体执行选择性刻蚀，刻蚀参数可根据具体工艺条件和实际需求进行设定。
根据本发明的其中一个实施例，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。如小于这一比值，则所述沟道区域上方的氧化硅会被刻蚀掉而被氮化硅取代，而氮化硅与有源区之间的界面性能是不如氧化硅与有源区之间的界面性能的，氧化硅被过度刻蚀会导致沟道区域的亚阈值特性显著增加，影响器件性能。具体的刻蚀比例以沟道的有效长度为参考，在实际中可根据需要进行设置。
优选的，所述晶体管还包括层间介质层180，所述层间介质层的材料为氮化硅，所述氮化硅中的氢元素含量小于氮化硅层160中的氢元素含量。层间介质层180在淀积时通过扩散同时填充所述氮化硅层160下方的氧化硅层151两侧的空间，即该区域原有的氧化硅被氮化硅取代。由于层间介质层180中的氢元素含量小于氮化硅层160中的氢元素含量，具有更大的介电常数，因此，可以进一步减小该区域的电场强度。
相比于现有技术中采用氧化硅材料作为栅极介质层的薄膜晶体管，本发明采用了介电常数较大的氮化硅替换了部分栅极介质层，使得栅极介质层的介电常数减小，从而减小沟道区的电场。进一步的，本发明还采用空腔和氮化硅结合的结构作为栅极介质层，使得栅极介质层的介电常数相比于氧化硅大幅度减小，有效的减小了电场，从而遏制了由于高电场引起阈值电压漂移和热载流子效应。相比于现有技术，极大地改善了薄膜晶体管的性能。
相应的，本发明还提供了一种显示面板，包括如前所述的薄膜晶体管。参考图8，所述显示面板还包括：位于所述层间介质层上方的钝化层210，位于所述有源区外侧的钝化层210上方的色阻层240，位于所述色阻层240上方的像素电极250，位于所述像素电极250上方的有机发光层260，以及位于所述有机发光层260上方的阴极270。
本发明采用将栅极绝缘层优化成氧化硅层和氮化硅层的夹层结构，采用干法刻蚀的方法将氮化硅层下方的氮化硅层两侧挖空，降低了栅极绝缘层两侧的电场强度，避免了由高电场引发的阈值电压漂移和热载流子效应。因此，本发明能够提升顶栅型IGZO TFT器件的稳定性和良率，减少阈值电压的漂移，以满足显示屏对高帧率和高解析度等产品的需求。
下面，将结合附图3至图8对本发明提供的一种薄膜晶体管的制作方法进行详细说明。该方法包括以下步骤：
a. 提供衬底130；
b. 在所述衬底130上方形成有源区140；
c. 在所述有源区140上方形成氧化硅层150；
d. 在所述有氧化硅层150上方形成第二栅介质层160；
e. 在所述栅极介质层上方形成栅极金属170；
f. 沿沟道方向进对氧化硅层150和第二栅介质层160进行选择性刻蚀，使刻蚀后的氧化硅层151沿沟道方向的长度小于第二栅介质层160；
g. 在所述第二栅介质层160下方的有源区140两侧形成源漏区。
具体的，在步骤a中，所述衬底为半导体材料，优选的，可以是硅、锗等单只半导体，也可以是三五族化合物半导体，例如砷化镓等，衬底的选择是本领域的常用技术，在此不再赘述。
接下来，参见图3，在步骤b中，在所述衬底130上方形成有源区140。在本实施例中，所述有源区为非晶铟镓锌氧化物薄膜，所述IGZO薄膜具有分辨率高、尺寸大、处理帧率高和可见光范围内穿透率高等显著优点，更适合应用于电子显示领域，例如液晶显示器中的TFT阵列。
接下来，参见图4，在步骤c中，在有源区140上方形成氧化硅层150，具体的，可以采用气相外延生成氧化硅层150，气相外延生成的氧化硅层与有源区之间具有良好的界面态，缺陷和杂质相比于气相淀积更好。
之后，在步骤d中，参见图4，在所述氧化硅层150上方生成第二栅介质层160，所述氧化硅层150的介电常数大于第二栅介质层160的介电常数。具体的，由于在氧化硅层上生长或淀积氮化硅层的工艺在本领域中相对成熟，且氮化硅的相对介电常数约为7，大于氧化硅的相对介电常数4，因此，本事实例中所述第二栅介质层160为氮化硅层。在其他实施例中，所述第二栅极介质层160也可以采用其他介电常数高的材料，例如氧化铪、氧化铝、氧化钛等，上述材料都拥有很高的介电常数，能够进一步减小沟道区域的电场强度，在实际应用中可以根据需要挑选合适的介电材料。
之后，参见图4，在步骤e中，在所述栅极介质层上方形成栅极金属170。具体的，栅极金属层的材料可以选用TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTa中的一种或其组合，其厚度在5nm~20nm之间。栅极金属可以通过化学气相沉积、高密度等离子体化学气相沉积、原子层淀积、等离子体增强原子层淀积、脉冲激光沉积或其他合适的方法形成。
之后，参见图5，对氧化硅层150、第二栅介质层160和栅极金属170进行图形化，暴露出部分有源区140，形成栅极结构。
之后，参加图6，沿沟道方向进对氧化硅层150、第二栅介质层160和栅极金属170进行选择性刻蚀，使刻蚀后的氧化硅层151沿沟道方向的长度小于第二栅介质层160。具体的，为了实现所述氧化硅层151沿沟道方向的长度小于所述氮化硅层160的长度这一技术特征，需要在栅极图形化之后增益一步选择性刻蚀工艺，从侧面沿着沟道方向对栅极介质层进行选择性刻蚀。具体的，可以选择干法刻蚀，由于干法刻蚀的刻蚀气体对不同的材料的可是速度差异很大，因此可以实现在横向快速刻蚀氧化硅的同时氮化硅刻蚀很慢甚至刻蚀。
例如，可以选择C 5HF 7作为刻蚀气体，C 5HF 7对于氧化硅的刻蚀速率可以达到400~500nm/min，同时对于氮化硅的刻蚀速率只有100~150nm/min，对多晶硅和金属的刻蚀速率几乎为0，因此，可以完美的将氧化硅层151和氮化硅层160刻蚀为图8所示的倒台阶型结构。当然，在实际应用中，C 5HF 7只是一种选择，不应理解为对本发明的限制。也可以选择其他刻蚀气体执行选择性刻蚀，刻蚀参数可根据具体工艺条件和实际需求进行设定。
根据本发明的其中一个实施例，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。如小于这一比值，则所述沟道区域上方的氧化硅会被刻蚀掉而被氮化硅取代，而氮化硅与有源区之间的界面性能是不如氧化硅与有源区之间的界面性能的，氧化硅被过度刻蚀会导致沟道区域的亚阈值特性显著增加，影响器件性能。具体的刻蚀比例以沟道的有效长度为参考，在实际中可根据需要进行设置。
之后，在步骤g中，在所述栅极介质层下方形成源漏区。
具体的，源漏区可以通过向有源区中注入P型或N型掺杂物或杂质而形成，例如，对于PMOS来说，源漏区可以是P型掺杂，对于NMOS来说，源漏区可以是N型掺杂。源/漏区可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成。在其他一些实施例中，源/漏区可以是通过选择性外延生长所形成的提升的源漏极结构，其外延部分的顶部高于栅极堆叠底部。之后采用高温处理激活杂质，例如退火工艺。
根据本发明的其中一个实施例，其中，在源漏区形成之后，还包括步骤h：形成覆盖所述薄膜晶体管的层间介质层180，其中，形成所述层间介质层180的材料为氮化硅，且形成所述层间介质层180的氮化硅中的氢元素含量低于氮化硅层160中的氢元素含量。参加图7，具体的，层间介质层可以通过化学气相沉积、高密度等离子体、旋涂或其他合适的方法形成在衬底上。层间介质层的材料可以包括SiO 2、碳掺杂SiO 2、BPSG、PSG、UGS、氮氧化硅、低k材料或其组合。层间介质层的厚度范围可以是40nm~150nm，如80nm、100nm 或120nm。
优选的，参见图8，在层间介质层180形成之后，还包括：在所述层间介质层上方形成钝化层210，在所述有源区外侧的钝化层210上方形成色阻层240，在所述色阻层240上方形成像素电极250，在所述像素电极250上方形成有机发光层260，以及在所述有机发光260层上方形成阴极270，从而形成具有前述薄膜晶体管的显示面板，可应用于OLED显示屏中。
本发明中的栅极介质层采用倒台阶型的叠层结构，不仅仅是通过氮化硅和氧化硅的叠层增大栅极介质层的介电常数，更通过选择性刻蚀和层间介质层淀积的方法把氮化硅下方位于沟道两端的氧化硅替换为氮化硅，进一步减小了沟道两端的电场强度，参见图9，图9为本发明中的薄膜晶体管沟道区域的电场强度，可以看出，沟道区域的电场得到了显著的减小，特别是沟道两端的区域，电场强度下降了一个数量级。
相比于现有技术中采用氧化硅材料作为栅极介质层的薄膜晶体管，本发明采用了介电常数较大的氮化硅替换了部分栅极介质层，使得栅极介质层的介电常数减小，从而减小沟道区的电场，遏制了由于高电场引起阈值电压漂移和热载流子效应。相比于现有技术，极大地改善了薄膜晶体管的性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种薄膜晶体管，其中，所述晶体管包括：
    衬底；
    有源区，位于所述衬底上方；
    栅极介质层，位于所述有源区上方；
    栅极金属，位于所述栅极介质层上方；
    源漏区，位于所述沟道区两侧的有源区中；其中，
    所述栅极介质层包括位于所述有源区上方的氧化硅层和位于所述氧化硅层上方的第二栅介质层，所述氧化硅层沿沟道方向的长度小于所述第二栅介质层的长度；其中，所述第二栅介质层的介电常数大于氧化硅层的介电常数。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第二栅介质层为氮化硅层。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述晶体管还包括层间介质层，所述层间介质层的材料为氮化硅，所述氮化硅中的氢元素含量小于氮化硅层中的氢元素含量。
  4. 根据权利要求3所述的薄膜晶体管，其中，所述第二栅介质层下方的氧化硅层两侧的空间被层间介质层填充。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
  6. 一种显示面板，其中，包括薄膜晶体管，
    所述晶体管包括：
    衬底；
    有源区，位于所述衬底上方；
    栅极介质层，位于所述有源区上方；
    栅极金属，位于所述栅极介质层上方；
    源漏区，位于所述沟道区两侧的有源区中；其中，
    所述栅极介质层包括位于所述有源区上方的氧化硅层和位于所述氧化硅层上方的第二栅介质层，所述氧化硅层沿沟道方向的长度小于所述第二栅介质层的长度；其中，所述第二栅介质层的介电常数大于氧化硅层的介电常数。
  7. 根据权利要求6所述的显示面板，其中，所述第二栅介质层为氮化硅层。
  8. 根据权利要求6所述的显示面板，其中，所述晶体管还包括层间介质层，所述层间介质层的材料为氮化硅，所述氮化硅中的氢元素含量小于氮化硅层中的氢元素含量。
  9. 根据权利要求8所述的显示面板，其中，所述第二栅介质层下方的氧化硅层两侧的空间被层间介质层填充。
  10. 根据权利要求9所述的显示面板，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
  11. 根据权利要求10所述的显示面板，其中，还包括：
    钝化层，位于所述层间介质层上方；
    色阻层，位于所述有源区外侧的钝化层上方；
    像素电极，位于所述色阻层上方；
    有机发光层，位于所述像素电极上方；
    阴极，位于所述有机发光层上方。
  12. 一种薄膜晶体管的制作方法，其中，该方法包括：
    a. 提供衬底；
    b. 在所述衬底上方形成有源区；
    c. 在所述沟道区上方形成氧化硅层；
    d. 在所述有氧化硅层上方形成第二栅介质层；
    e. 在所述栅极介质层上方形成栅极金属；
    f. 沿沟道方向进对氧化硅层和第二栅介质层进行选择性刻蚀，使刻蚀后的氧化硅层沿沟道方向的长度小于第二栅介质层；
    g. 在所述第二栅介质层两侧的有源区中形成源漏区。
  13. 根据权利要求12所述的薄膜晶体管的制作方法，其中，所述第二栅介质层为氮化硅层。
  14. 根据权利要求13所述的薄膜晶体管的制作方法，其中，在步骤g之后还包括步骤h：
    形成覆盖所述薄膜晶体管的层间介质层，其中，形成所述层间介质层的材料为氮化硅，且形成所述层间介质层的氮化硅中的氢元素含量低于第二栅介质层中的氢元素含量。
  15. 根据权利要求14所述的薄膜晶体管的制作方法，其中，步骤d中的第二栅介质层的长度大于所述薄膜晶体管所需要的栅极介质层的长度。
  16. 根据权利要求15所述的薄膜晶体管的制作方法，其中，在步骤f中选择性刻蚀所用的刻蚀方法为干法刻蚀，刻蚀气体为C 5HF 7。
  17. 根据权利要求16所述的薄膜晶体管的制作方法，其中，所述氧化硅层沿沟道方向的长度不小于所述第二栅介质层沿沟道方向长度的二分之一。
PCT/CN2018/117578 2018-09-03 2018-11-27 薄膜晶体管、显示面板及薄膜晶体管的制作方法 Ceased WO2020048020A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811019288.1 2018-09-03
CN201811019288.1A CN109192784A (zh) 2018-09-03 2018-09-03 薄膜晶体管、显示面板及所述薄膜晶体管的制作方法

Publications (1)

Publication Number Publication Date
WO2020048020A1 true WO2020048020A1 (zh) 2020-03-12

Family

ID=64917855

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/117578 Ceased WO2020048020A1 (zh) 2018-09-03 2018-11-27 薄膜晶体管、显示面板及薄膜晶体管的制作方法

Country Status (2)

Country Link
CN (1) CN109192784A (zh)
WO (1) WO2020048020A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114122023A (zh) * 2021-11-19 2022-03-01 武汉华星光电技术有限公司 一种显示面板及其制造方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110085678A (zh) * 2019-04-18 2019-08-02 深圳市华星光电半导体显示技术有限公司 显示面板和薄膜晶体管的制作方法
WO2023184236A1 (zh) * 2022-03-30 2023-10-05 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100119A (en) * 1995-08-31 2000-08-08 Lg Electronics Inc. Thin film transistor and method for fabricating the same
CN1591903A (zh) * 2003-09-04 2005-03-09 株式会社东芝 半导体器件
US20070018238A1 (en) * 2005-07-06 2007-01-25 Kabushiki Kaisha Toshiba Semiconductor device
CN101317272A (zh) * 2005-11-28 2008-12-03 日本电气株式会社 半导体器件及其制造方法
CN108336147A (zh) * 2018-02-12 2018-07-27 崔金益 一种二硫化钼场效应晶体管的制备方法及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100119A (en) * 1995-08-31 2000-08-08 Lg Electronics Inc. Thin film transistor and method for fabricating the same
CN1591903A (zh) * 2003-09-04 2005-03-09 株式会社东芝 半导体器件
US20070018238A1 (en) * 2005-07-06 2007-01-25 Kabushiki Kaisha Toshiba Semiconductor device
CN101317272A (zh) * 2005-11-28 2008-12-03 日本电气株式会社 半导体器件及其制造方法
CN108336147A (zh) * 2018-02-12 2018-07-27 崔金益 一种二硫化钼场效应晶体管的制备方法及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114122023A (zh) * 2021-11-19 2022-03-01 武汉华星光电技术有限公司 一种显示面板及其制造方法

Also Published As

Publication number Publication date
CN109192784A (zh) 2019-01-11

Similar Documents

Publication Publication Date Title
KR100845175B1 (ko) 반도체 디바이스 및 그 제조 방법
US9583590B2 (en) Integrated circuit devices including FinFETs and methods of forming the same
US10312155B2 (en) FinFET device and fabrication method thereof
US9997601B2 (en) Metal-oxide-semiconductor field-effect transistor with extended gate dielectric layer
US9679962B2 (en) FinFET and method of manufacturing the same
CN105097841B (zh) Tft基板的制作方法及tft基板
US20160079400A1 (en) A junction-modulated tunneling field effect transistor and a fabrication method thereof
WO2017020358A1 (zh) 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
US9640660B2 (en) Asymmetrical FinFET structure and method of manufacturing same
WO2020048020A1 (zh) 薄膜晶体管、显示面板及薄膜晶体管的制作方法
US20210057579A1 (en) Transistor with strained superlattice as source/drain region
US20150060843A1 (en) Display substrate and method of manufacturing a display substrate
CN103855022B (zh) 鳍式场效应晶体管的形成方法
WO2020006945A1 (zh) 背沟道蚀刻型tft基板的制作方法及背沟道蚀刻型tft基板
CN109637932B (zh) 薄膜晶体管及其制备方法
US11374116B2 (en) Semiconductor devices
US10516058B2 (en) Low temperature polysilicon thin film transistor and preparation method thereof
US10269972B2 (en) Fin-FET devices and fabrication methods thereof
US10205026B2 (en) Thin film transistor having a composite metal gate layer
US20190221671A1 (en) Array substrate and manufacturing method thereof
WO2019028934A1 (zh) 低温多晶硅薄膜晶体管及其制备方法
JPH04245480A (ja) Ｍｏｓ型半導体装置およびその製造方法
US7968889B2 (en) Semiconductor device with thinned gate insulating film and polycrystal semiconductor layer and production method thereof
US10510899B2 (en) Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel
US8390042B2 (en) Gate etch optimization through silicon dopant profile change

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18932686

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18932686

Country of ref document: EP

Kind code of ref document: A1