WO2020040370A1 - Support handle and method for manufacturing compound semiconductor solar battery using same - Google Patents

Support handle and method for manufacturing compound semiconductor solar battery using same Download PDF

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Publication number
WO2020040370A1
WO2020040370A1 PCT/KR2019/000300 KR2019000300W WO2020040370A1 WO 2020040370 A1 WO2020040370 A1 WO 2020040370A1 KR 2019000300 W KR2019000300 W KR 2019000300W WO 2020040370 A1 WO2020040370 A1 WO 2020040370A1
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WO
WIPO (PCT)
Prior art keywords
layer
compound semiconductor
film
adhesive
support handle
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PCT/KR2019/000300
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French (fr)
Korean (ko)
Inventor
신용일
허윤호
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엘지전자 주식회사
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Publication of WO2020040370A1 publication Critical patent/WO2020040370A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03926—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a support handle and a method for manufacturing a compound semiconductor solar cell using the same. )to be.
  • the present invention relates to a support handle capable of stably separating a compound semiconductor layer from a mother substrate without damage after an epitaxial lift off (ELO) process, and a method of manufacturing a compound semiconductor solar cell using the same.
  • ELO epitaxial lift off
  • a compound semiconductor solar cell is a method of manufacturing a compound semiconductor solar cell by using a mother substrate (GaAs wafer or Ge wafer) for forming the compound semiconductor layer together as a component of the solar cell without separating from the compound semiconductor layer, or ELO
  • the mother substrate (GaAs wafer or Ge wafer) is separated from the compound semiconductor layer by removing the sacrificial layer using an epitaxial lift off process, and only the compound semiconductor layer is used as a component of the solar cell. It can manufacture by the method of manufacturing.
  • an Epitaxial Lift Off (ELO) process prevents damage to the compound semiconductor layer and uses a support handle for supporting the compound semiconductor layer in a subsequent step.
  • ELO Epitaxial Lift Off
  • the support handles used in the related art can be used only once because of shrinkage of the support handle material generated in the ELO process and deformation of the adhesive layer for bonding the support handle to the compound semiconductor layer, thereby increasing the manufacturing cost of the compound semiconductor solar cell. There is a problem.
  • the present invention can be reused to reduce the manufacturing cost of the compound semiconductor solar cell, and a support handle that can stably separate the compound semiconductor layer from the mother substrate after the Epitaxial Lift Off (ELO) process and the compound semiconductor using the same It is an object to provide a method of manufacturing a solar cell.
  • ELO Epitaxial Lift Off
  • a support handle includes: a flexible substrate; An adhesive layer located on one side of the flexible substrate; And a foam type self-adhesive film adhered to the flexible substrate by the adhesive layer and having a self-adhesive surface on a surface opposite to the surface bonded to the adhesive layer.
  • the foam type self-adhesive film may be formed of any one material selected from acrylic, polyurethane, and polyethylene, and may be peeled at a temperature of 30 ° C. to 60 ° C.
  • a plurality of pores are formed on the self-adhesive surface, and the plurality of pores may be further formed inside the foam type self-adhesive film.
  • the plurality of pores formed on the self-adhesive surface and the plurality of pores further formed inside the self-adhesive film may be formed in non-uniform size, and may be distributed non-uniformly.
  • the flexible substrate may be formed of any one selected from glass, polypropylene, polyethylene, polycarbonate, polyurethane, and has a thickness of 100 ⁇ m or more. It may have acid resistance and solvent resistance.
  • Method for producing a compound semiconductor solar cell using the support handle of this configuration forming a sacrificial layer on one side of the mother substrate; Forming a compound semiconductor layer on the sacrificial layer; Attaching an epitaxial lift off (ELO) film on the compound semiconductor layer; Performing an ELO process; Attaching a support handle to the ELO film; And separating the compound semiconductor layer from the mother substrate by using the support handle.
  • ELO epitaxial lift off
  • the adhesive layer of the support handle can be prevented from being damaged by the hydrofluoric acid used in the ELO process. No shrinkage deformation of the flexible substrate of the support handle occurs.
  • the support handle has a foam-type self-adhesive film having a plurality of pores formed on the self-adhesive surface
  • the support handle when the support handle is attached to the ELO film, bubbles placed between the self-adhesive surface and the ELO film are self-adhesive surfaces. Since it is trapped by the pores formed in the film, the bubbles between the ELO film and the self-adhesive film can be suppressed from decreasing the adhesive force between the support handle and the ELO film.
  • the self-adhesive film firmly adhered to the ELO film can be easily peeled from the ELO film due to thermal expansion of air trapped in pores of the self-adhesive surface under constant temperature conditions (30 ° C. to 60 ° C.). It is possible to suppress the self-adhesive film from being peeled from the ELO film due to carelessness of the operator while handling the support handle, and can effectively peel off the self-adhesive film without damaging the compound semiconductor layer.
  • the support handle After peeling the support handle from the ELO film, the support handle can be reused after cleaning the self-adhesive surface.
  • the manufacturing cost of the compound semiconductor solar cell can be reduced, and the compound semiconductor layer can be stably separated from the mother substrate after the ELO process without damage.
  • FIG. 1 is a perspective view of a compound semiconductor solar cell.
  • FIG. 2 is a cross-sectional view of a support handle according to an embodiment of the present invention.
  • FIG. 3 is a photograph of the self-adhesive surface shown in FIG. 2.
  • FIG. 4 is a process chart showing a method for manufacturing a compound semiconductor solar cell using the support handle shown in FIG. 2.
  • Figure 5 is a photograph comparing the embodiment of the present invention using a conventional foam type self-adhesive tape with a conventional adhesive tape.
  • first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
  • the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
  • the term "and / or” may include a combination of a plurality of related items or any of a plurality of related items.
  • a component When a component is said to be “connected” or “coupled” to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
  • FIG. 3 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to the present invention
  • FIG. 4 is a process diagram illustrating the manufacturing method of FIG. 3 in detail.
  • FIG. 5 is a cross-sectional view illustrating various embodiments of the first protective layer and the second protective layer illustrated in FIG. 4, and FIG. 6 is a perspective view of the compound semiconductor solar cell manufactured by the manufacturing method of FIG. 4.
  • the compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a front electrode 20 positioned on the front surface of the window layer 10, and a window layer ( 10) the front contact layer 30 positioned between the front electrode 20, the antireflection film 40 positioned on the window layer 10, the rear contact layer 50 positioned on the rear surface of the light absorbing layer PV, and
  • the rear electrode 60 may include a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
  • At least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted, but as shown in FIG. It demonstrates as an example.
  • the light absorbing layer PV may include a III-VI semiconductor compound, a p-type semiconductor layer PV-p doped with impurities of a first conductivity type (eg, p-type impurities), and a second conductivity It may include an n-type semiconductor layer (PV-n) doped with a type of impurities (for example, n-type impurities).
  • the light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a group III-VI semiconductor compound with impurities of a second conductivity type.
  • the window layer 10 may not include n-type or p-type impurities, and functions to passivate the front surface of the light absorbing layer PV.
  • the anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
  • the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
  • the compound semiconductor solar cell may further include a busbar electrode for physically connecting the plurality of front electrodes 20, and the busbar electrode is not covered by the anti-reflection film 40 and exposed to the outside. Can be.
  • the antireflection film 40 having such a configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
  • the front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
  • the front electrode 20 having such a configuration may be formed by including an electrically conductive material.
  • the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
  • the front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
  • the front contact layer 30 forms an ohmic contact between the window layer 10 and the front electrode 20.
  • the rear contact layer 50 located on the rear of the rear electric field layer may be a light absorbing layer ( It is located on the back of the PV) as a whole, and may be formed by doping the III-VI semiconductor compound with a doping concentration higher than that of the p-type semiconductor layer PV-p.
  • the back contact layer 50 may form an ohmic contact with the back electrode 160.
  • the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor located entirely on the rear surface of the rear contact layer 50. That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
  • the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
  • FIG. 1 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention
  • FIG. 2 is a process diagram illustrating the manufacturing method of FIG. 1 in detail.
  • FIG. 3 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a second embodiment of the present invention
  • FIG. 4 is a process diagram illustrating the manufacturing method of FIG. 3 in detail
  • FIG. 1 is a cross-sectional view showing various embodiments of the protective layer and the second protective layer.
  • FIGS. 1 and 2 a manufacturing method according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
  • the manufacturing method of the first embodiment is large, forming a sacrificial layer on one side of the mother substrate (S110); Forming a compound semiconductor layer on the sacrificial layer (S120); Attaching a first lamination film on the first surface of the compound semiconductor layer (S130); Separating the compound semiconductor layer and the first lamination film from the mother substrate by performing an ELO process to remove the sacrificial layer (S140); Forming a rear electrode on the second surface of the compound semiconductor layer (S150); Attaching a second lamination film on the back electrode (S160); Removing the first lamination film (S170); And forming a front electrode on the first surface of the compound semiconductor layer (S180).
  • a sacrificial layer 120 is formed on one side of a mother substrate 110 serving as a base for providing an appropriate lattice structure in which a light absorbing layer PV is formed (S110).
  • a compound semiconductor layer CS is formed on the sacrificial layer 120.
  • the compound semiconductor layer CS sequentially forms the back contact layer 50, the light absorbing layer PV, the window layer 10, and the front contact layer 30 on the sacrificial layer 120 using the regular growth method. It can form by laminating
  • the first lamination film 130 is attached onto the compound semiconductor layer CS (S130).
  • the first lamination film 130 may be formed of a base film 130B serving as a support substrate and an adhesive 130A positioned on one side of the base film 130B.
  • the base film 130B may be formed of polyethylene terephthalate, polyvinyl chloride, ethylene vinyl acetate, or the like, or a polyolefin-based resin or a copolymer thereof, and may have a thickness of 2 to 200 ⁇ m.
  • the base film 130B since the first lamination film 130 is directly adhered to the first surface of the compound semiconductor layer CS, the base film 130B must support the compound semiconductor layer CS.
  • the base film 130B of the first lamination film 130 used in the manufacturing method of the present embodiment is preferably formed to a thickness of 150 to 200 ⁇ m to effectively support the compound semiconductor layer (CS).
  • the pressure-sensitive adhesive for adhering the base film 130B to the first surface of the compound semiconductor layer CS may include an acrylic resin as a composition, and in addition to the acrylic resin, a heat curing agent, a light curing agent, a foaming agent formed of microspheres, and the like may be selected. It may further include as.
  • acrylic resin silicone acrylate, polyether acrylate or polyester acrylate may be used.
  • the pressure-sensitive adhesive may be formed of a silicone acrylate, polyether acrylate or polyester acrylate-based resin.
  • the pressure-sensitive adhesive may be formed by mixing an acrylic resin (silicone acrylate, polyether acrylate or polyester acrylate) with a thermosetting agent (isocyanate-based crosslinking agent or methylol-based crosslinking agent). It may be formed by mixing a blowing agent formed of microspheres that are foamed by heating. At this time, it is preferable to form solid content in the composition which forms an adhesive so that it may become 10 to 60 weight% with respect to the total weight of the said adhesive.
  • the pressure-sensitive adhesive is one of an acrylic resin (silicone acrylate, polyether acrylate or polyester acrylate) and a light curing agent (benzoin ether, amine, diazonium salt, iodonium salt, sulfonium salt or metal nocene compound). Or a mixture of two or more materials) and a blowing agent formed of microspheres foamed by light.
  • an acrylic resin silicone acrylate, polyether acrylate or polyester acrylate
  • a light curing agent benzoin ether, amine, diazonium salt, iodonium salt, sulfonium salt or metal nocene compound.
  • a blowing agent formed of microspheres foamed by light.
  • the pressure-sensitive adhesive includes a foaming agent that is foamed by heat or light
  • the foaming agent is foamed to lower the adhesive force, thereby easily peeling off the base film 130B.
  • the first lamination film 130 is composed of a base film 130B and an adhesive applied to one side of the film.
  • the first lamination film is a pressure-sensitive adhesive on the first surface of the compound semiconductor layer.
  • the composition of the base film may be formed by applying a composition such as spin coating, bar coating or screen printing onto the pressure-sensitive adhesive.
  • the sacrificial layer 120 is removed by performing an ELO process (S140).
  • hydrofluoric acid HF
  • etching solution hydrofluoric acid
  • the sacrificial layer 120 is removed by the hydrofluoric acid (HF), and thus the compound semiconductor layer CS and the first lamination film 130 are used. ) May be separated from the mother substrate 110.
  • the first support handle 150 is attached to the rear surface of the first lamination film 130, and the compound semiconductor layer ( A rear electrode 60 is formed on the CS (S150).
  • the rear electrode 60 includes gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), nickel (Ni), magnesium (Mg), palladium (Pd), and copper (Cu) It may be formed as a single film or multiple films containing at least one material selected from, and germanium (Ge).
  • the second lamination film 160 is attached onto the rear electrode 60 (S160).
  • the second lamination film 160 may be formed in the same structure as the first lamination film 130 and may be attached in the same manner as the first lamination film 130.
  • the second lamination film 160 may have a different structure from the first lamination film 130.
  • the first support handle 150 is disposed upward, and then, the first support handle 150 and the first support handle 150 are disposed upward.
  • the lamination film 130 is removed (S170).
  • the first lamination film 130 may be removed by any one of the following four methods.
  • the first lamination film was peeled off after heating at a temperature of 60 to 200 ° C. for 5 seconds to 20 minutes.
  • the pressure-sensitive adhesive of the first lamination film includes an acrylic resin such as silicone acrylate, polyether acrylate or polyester acrylate as a composition.
  • the adhesive force of the adhesive 130A containing an acrylic composition is generally 0.2-5 N / 25mm.
  • the first lamination film may be physically peeled off using a force of 0.2 to 5 N / 25 mm.
  • the pressure-sensitive adhesive (130A) further comprises a foaming agent formed of a microsphere foamed by heating, the foaming agent by heating for 5 seconds to 20 minutes at a temperature of 60 to 200 °C according to the method described in item (2) By foaming, the first lamination film can be peeled off.
  • the pressure-sensitive adhesive (130A) further comprises a foaming agent formed of microspheres foamed by light, the intensity of 20 to 600mJ / cm2 for light having a wavelength of 200 to 400nm according to the method described in item (3)
  • the first lamination film can be peeled off by irradiating with a foaming agent.
  • the acrylic pressure-sensitive adhesive has a physical property that is dissolved in at least one solvent of Acetone (2-propanone), Isopropyl alcohol (Isopropanol), NMP (1-Methyl-2-pyrrolidon), DMSO (dimethyl sulfoxide), the solvent
  • the first lamination film may be peeled off by dissolving the pressure-sensitive adhesive 130A using one of them.
  • the front electrode 20 is formed on the first surface of the compound semiconductor layer CS (S180).
  • the front electrode 20 may be formed by depositing a metal only on a region where the front electrode is to be formed, or by patterning after depositing a front electrode material on the front contact layer 30.
  • the second support handle 170 and the second support pattern 170 are patterned.
  • the lamination film 160 is removed to manufacture the compound semiconductor solar cell shown in FIG. 6.
  • the compound semiconductor solar cell is provided with one light absorbing layer as an example, but a plurality of light absorbing layers may be formed.
  • the lower light absorbing layer may include a GaAs compound that absorbs light in a long wavelength band and photoelectrically converts the upper light absorbing layer may include a GaInP compound that absorbs light in a short wavelength band and photoelectrically converts the upper light absorbing layer.
  • the tunnel junction layer may be positioned between the lower light absorbing layer and the lower light absorbing layer.
  • An intrinsic semiconductor layer may be further formed between the p-type semiconductor layer and the n-type semiconductor layer of the light absorbing layer.
  • the manufacturing method of the present invention largely, forming a sacrificial layer on one side of the mother substrate (S210); Forming a compound semiconductor layer on the sacrificial layer (S220); Forming a first passivation layer formed of a compound semiconductor on the first surface of the compound semiconductor layer (S230); Depositing a second protective layer formed of a metal on the first protective layer (S240); Attaching a first lamination film on the second protective layer (S250); Separating the compound semiconductor layer, the first and second protective layers, and the first lamination film from the mother substrate by performing an ELO process to remove the sacrificial layer (S260); Forming a rear electrode on the compound semiconductor layer (S270); Attaching a second lamination film on the back electrode (S280); Removing the first lamination film (S290); Removing the second protective layer (S300); Removing the first protective layer (S310); And forming a front electrode on the compound semiconductor layer (S320).
  • one of the compound semiconductor layers directly contacting the first protective layer is formed of GaAs, and the first protective layer is formed of another compound semiconductor except for the GaAs.
  • the sacrificial layer 120 is formed on one surface of the mother substrate 110 (S210), and the compound semiconductor layer CS is formed on the sacrificial layer 120 (S220).
  • the compound semiconductor layer CS is formed by the regular growth method as in the first embodiment described above.
  • the front contact layer 30 may be formed entirely on the window layer 10, and may be formed of GaAs having excellent electrical conductivity for ohmic contact.
  • a first protective layer 140A formed of a compound semiconductor is formed on the compound semiconductor layer CS (S230), and a second protective layer 140B formed of metal is formed on the first protective layer 140A. (S240). Therefore, the protective layer 140 including the first protective layer 140A and the second protective layer 140B is formed.
  • the first protective layer 140A is formed of any compound semiconductor except GaAs, preferably any one compound semiconductor selected from GaInP, AlInP, and AlGaInP.
  • the compound semiconductor layer CS and the passivation layer 140A are formed of different compound semiconductors, the compound semiconductor layer CS and the passivation layer 140A, It is possible to effectively prevent the peeling of the 140B, and to effectively prevent the etching of a portion of the compound semiconductor layer CS during the process of removing the protective layers 140A and 140B.
  • the sacrificial layer 120 and the compound semiconductor layer CS and the first protective layer 140A may be a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy method, or any other suitable method for forming an epitaxial layer. It can form by a method and can be formed by a regular growth method.
  • MOCVD metal organic chemical vapor deposition
  • a molecular beam epitaxy method or any other suitable method for forming an epitaxial layer. It can form by a method and can be formed by a regular growth method.
  • the second protective layer 140B may be formed of the first metal layer 140B-1 formed of copper having excellent etching resistance, and the first metal layer 140B-1 may be formed of the second metal layer 140B-2 formed of another metal. Can be.
  • the second metal layer 140B-2 may be a metal that can prevent the surface of the first metal layer 140B-1 from being oxidized, or an etching solution used to remove the first metal layer 140B-1. It is preferable to form at least one selected from a material having corrosion resistance, for example, silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni) and molybdenum (Mo). Do.
  • the second metal layer 140B-2 includes the first passivation layer 140A.
  • the first metal layer 140B-1 and between the first metal layer 140B-1 and the first lamination film 130, and the first metal layer 140B-1 may be formed.
  • the second metal layer 140B-2 may be further formed between the two first metal layers 140B-1.
  • an etching process and an ELO process for removing the second metal layer 140B-2 may be performed. Since the first protective layer 140A can be protected during the first protective layer 140A, the first protective layer 140A and the second protective layer 140B, in particular, between the first protective layer 140A and the first metal layer 140B-1. The peeling phenomenon which arises can be prevented.
  • the second metal layer 140B-2 is formed between the first metal layer 140B-1 and the first lamination film 130, the second metal layer 140B-2 is formed on the surface of the first metal layer 140B-1. Since the oxide film can be prevented from being formed, the peeling phenomenon occurring between the first lamination film 130 and the second protective layer 140B can be prevented during the etching process, especially the ELO process.
  • the second protective layer 140B may be formed to a thickness of 1 ⁇ m to 10 ⁇ m, and the thickness of the first metal layer 140B-1 may be used to support the compound semiconductor layer CS during the manufacturing process of the compound semiconductor solar cell. It may be formed to 80% or more of the thickness of the second protective layer (140B).
  • the first lamination film 130 is attached onto the second protective layer 140B (S250).
  • the first lamination film 130 is not directly adhered to the compound semiconductor layer CS, but directly adhered to the protective layer 140 for supporting the compound semiconductor layer CS.
  • the base film of the 1st lamination film 130 used for the manufacturing method of this embodiment with a thin thickness compared with the base film of 1st Example mentioned above.
  • the base film may be formed to a thickness of 100 ⁇ m or less
  • FIG. 4 illustrates a case in which the first lamination film is formed to have a thickness thinner than that of the first lamination film of the first embodiment.
  • the sacrificial layer 120 is removed by performing an ELO process (S260).
  • the first lamination film 130 is the second protective layer. It does not peel off from 140B.
  • FIG. 7 is a photograph showing that peeling between the first lamination film 140 and the second protective layer 130B is suppressed after performing the ELO process according to the manufacturing method of the second embodiment.
  • FIG. 7 shows the interface between the first lamination film and the protective metal layer in the conventional example in which the ELO process is performed in a state in which a single-layered protective metal layer is deposited on the first surface of the compound semiconductor layer and the first lamination film is attached thereto. It is a photograph showing that peeling occurred.
  • the first support handle 150 is attached on the rear surface of the first lamination film 130, and the compound semiconductor layer
  • the back electrode 60 is formed on the CS (S270).
  • the second lamination film 160 is attached to the rear electrode 60 (S280), and the first support handle 150 is attached to the second support handle 170 on the second lamination film 160. Place it face up.
  • first support handle 150 and the first lamination film 130 are removed (S290), and the second protective layer 140B is removed (S300).
  • the first metal layer 140B-1 is removed using an etching solution in which ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) are mixed, and the second metal layer 140B-2 is removed from the first metal layer ( 140B-1) is removed with an etching solution other than the etching solution used for removing 140B-1), for example, an etching solution containing at least one of potassium iodide (KI) and potassium cyanide (H 2 O 2 ).
  • the first metal layer 140B-1 has excellent etching resistance to the etching solution used to remove the second metal layer 140B-2, while the second metal layer 140B-2 is removed.
  • the first metal layer 140B-1 is not removed.
  • the second metal layer 140B-2 is formed between the first metal layer 140B-1 and the first lamination film 130, an oxide film is formed on the surface of the first metal layer 140B-1. Since it is suppressed by the 2 metal layer 140B-2, the peeling phenomenon which arises between the 2nd protective layer 140B and the 1st lamination film 130 during an etching process, especially an ELO process is prevented.
  • the first protective layer 140A is removed (S310).
  • the first passivation layer 140A may be removed using an etching solution including hydrochloric acid (HCL) in which the front contact layer formed of GaAs has etching resistance.
  • HCL hydrochloric acid
  • the front electrode 20 is formed on the first surface of the compound semiconductor layer CS (S320).
  • first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
  • the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
  • the term "and / or” may include a combination of a plurality of related items or any of a plurality of related items.
  • a component When a component is said to be “connected” or “coupled” to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
  • FIG. 1 is a perspective view of a compound semiconductor solar cell
  • FIG. 2 is a cross-sectional view of a support handle according to an embodiment of the present invention
  • FIG. 3 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the support handle shown in FIG. 2. .
  • the compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a front electrode 20 positioned on the front surface of the window layer 10, and a window layer ( 10) the front contact layer 30 positioned between the front electrode 20, the antireflection film 40 positioned on the window layer 10, the rear contact layer 50 positioned on the rear surface of the light absorbing layer PV, and
  • the rear electrode 60 may include a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
  • At least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted, but as shown in FIG. It demonstrates as an example.
  • the light absorbing layer PV may be formed including a III-VI semiconductor compound.
  • a III-VI semiconductor compound For example, GaInP compounds containing gallium (Ga), indium (In) and phosphorus (P) or GaAs compounds containing gallium (Ga) and arsenic (As) may be formed.
  • the light absorbing layer (PV) will be described with an example containing a GaAs compound.
  • the light absorption layer PV is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity.
  • Layer (PV-n) is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity.
  • the light absorbing layer PV may further include a rear electric field layer disposed at the rear of the p-type semiconductor layer PV-p.
  • the p-type semiconductor layer PV-p is formed by doping the compound semiconductor described above with a first conductivity type, that is, a p-type impurity, and the n-type semiconductor layer PV-n is formed by the second compound semiconductor in the aforementioned compound semiconductor. That is, n-type impurities may be formed by doping.
  • the p-type impurity may be selected from carbon, magnesium, zinc or a combination thereof
  • the n-type impurity may be selected from silicon, selenium, tellurium or a combination thereof.
  • the n-type semiconductor layer PV-n may be located in an area adjacent to the front electrode 20, and the p-type semiconductor layer PV-p may be disposed directly below the n-type semiconductor layer PV-n. It may be located in an area adjacent to).
  • the distance between the n-type semiconductor layer PV-n and the front electrode 20 is smaller than the distance between the p-type semiconductor layer PV-p and the front electrode, and the n-type semiconductor layer PV-n
  • the spacing between the back electrodes 60 is greater than the spacing between the p-type semiconductor layer PV-p and the back electrodes.
  • a pn junction in which the p-type semiconductor layer PV-p and the n-type semiconductor layer PV-n are bonded to each other is formed in the light absorbing layer PV.
  • the generated electron-hole pair is separated into electrons and holes by the internal potential difference formed by the pn junction of the light absorbing layer PV so that the electrons move toward the n-type and the holes move toward the p-type.
  • holes generated in the light absorbing layer PV move to the back electrode 60 through the back contact layer 50, and electrons generated in the light absorbing layer PV are transferred to the window layer 10 and the front contact layer 30. It moves to the front electrode 20 through).
  • the p-type semiconductor layer PV-p is positioned in the region adjacent to the front electrode 20 and the n-type semiconductor layer PV-n is directly below the p-type semiconductor layer PV-p.
  • the electrons generated in the light absorbing layer (PV) is the back contact layer 50 It moves to the rear electrode 60 through).
  • the rear electric field layer is of the same conductive type as the upper layer in direct contact, that is, the n-type semiconductor layer PV-n or the p-type semiconductor layer PV-p. It may be formed of the same material as the window layer 10.
  • the rear electric field layer is an upper layer in direct contact, that is, an n-type semiconductor layer (PV-n) or in order to effectively block the movement of charges (holes or electrons) to be moved toward the front electrode toward the rear electrode.
  • PV-n n-type semiconductor layer
  • the back surface of the p-type semiconductor layer PV-p is entirely formed.
  • the rear field layer when the rear field layer is formed on the rear side of the p-type semiconductor layer PV-p, the rear field layer serves to block electrons from moving toward the rear electrode.
  • the rear electric field layer is located on the entire rear surface of the p-type semiconductor layer PV-p.
  • the light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the p-type semiconductor layer PV-p and the n-type semiconductor layer PV-n may be made of the same material having the same bandgap (homogeneous junction), and different materials having different bandgaps may be different. It may consist of (heterojunction).
  • the window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a III-VI group semiconductor compound with a second conductivity type, that is, an n-type impurity.
  • the window layer 10 is formed. It may include one conductivity type, that is, p-type impurities.
  • the window layer 10 may not include n-type or p-type impurities.
  • the window layer 10 functions to passivate the front surface of the light absorbing layer PV. Therefore, when the carrier (electrons or holes) move to the surface of the light absorbing layer PV, the window layer 10 can prevent the carrier from recombining at the surface of the light absorbing layer PV.
  • the window layer 10 since the window layer 10 is disposed on the entire surface of the light absorbing layer PV, that is, on the light incident surface, the window layer 10 may be disposed in an amount greater than that of the energy band gap of the light absorbing layer PV so as to hardly absorb light incident on the light absorbing layer PV. It can have a high energy bandgap.
  • the window layer 10 may further contain aluminum (Al).
  • the anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
  • the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
  • the compound semiconductor solar cell may further include a bus bar electrode that physically connects the plurality of front electrodes 20, and the bus bar electrode may be exposed to the outside without being covered by the anti-reflection film 40. .
  • the anti-reflection film 40 may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
  • the front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
  • the front electrode 20 having such a configuration may be formed by including an electrically conductive material.
  • the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
  • the front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
  • the front contact layer 30 forms an ohmic contact between the window layer 10 and the front electrode 20. That is, when the front electrode 20 directly contacts the window layer 10, the ohmic contact between the front electrode 20 and the light absorbing layer PV may not be well formed due to the low impurity doping concentration of the window layer 10. Do not. Therefore, the carrier moved to the window layer 10 may disappear easily without moving to the front electrode 20.
  • the carrier is smoothly moved by the front contact layer 30 forming the ohmic contact with the front electrode 20.
  • the short-circuit current density (Jsc) of the compound semiconductor solar cell increases. Accordingly, the efficiency of the solar cell can be further improved.
  • the doping concentration of the second impurity doped in the front contact layer 30 may be higher than the doping concentration of the second impurity doped in the window layer 10.
  • the front contact layer 30 may be formed in the same shape as the front electrode 20.
  • the rear contact layer 50 located on the rear of the rear electric field layer may be a light absorbing layer ( PV) or the backside of the backside electric field layer as a whole, and may be formed by doping the III-VI semiconductor compound with a higher doping concentration than the p-type semiconductor layer (PV-p).
  • the back contact layer 50 may form an ohmic contact with the back electrode 160, thereby further improving the short circuit current density Jsc of the compound semiconductor solar cell. Accordingly, the efficiency of the solar cell can be further improved.
  • the thickness of the front contact layer 30 and the thickness of the back contact layer 50 may be formed to a thickness of 100nm to 300nm, respectively.
  • the front contact layer 30 is formed to a thickness of 100nm and the back contact layer ( 50) may be formed to a thickness of 300 nm.
  • the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor positioned entirely on the rear surface of the rear contact layer 50. . That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
  • the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
  • the back electrode 60 is made of gold (Au), platinum (Pt) / titanium (Ti), tungsten-silicon alloy (WSi), and silicon (Si) / It may be formed of any one selected from nickel (Ni) / magnesium (Mg) / nickel (Ni), and preferably, may be formed of gold (Au) having low contact resistance with a p-type back contact layer.
  • the back electrode 60 may include palladium (Pd) / gold (Au), copper (Cu) / germanium (Ge), and nickel (Ni) / germanium- It may be formed of any one selected from alloys of gold (GeAu) / nickel (Ni) and gold (Au) / titanium (Ti), and preferably palladium (Pd) / with low contact resistance with a p-type back contact layer. It may be formed of gold (Au).
  • the material forming the back electrode may be appropriately selected from the above materials, and particularly, may be appropriately selected from materials having low contact resistance with the back contact layer.
  • the compound semiconductor solar cell is provided with one light absorbing layer as an example, but a plurality of light absorbing layers may be formed.
  • the lower light absorbing layer (light absorbing layer of the middle cell and / or the bottom cell) may include a GaAs compound that absorbs light of the long wavelength band and photoelectrically converts the light absorbing layer (light absorbing layer of the top cell). It may include a GaInP compound that absorbs light of the photoelectric conversion, the tunnel junction layer may be located between the upper light absorbing layer and the lower light absorbing layer.
  • An intrinsic semiconductor layer may be further formed between the p-type semiconductor layer and the n-type semiconductor layer of the light absorbing layer.
  • a method of manufacturing a compound semiconductor solar cell is largely provided by forming a sacrificial layer on one side of a mother substrate, forming a compound semiconductor layer on the sacrificial layer, and attaching an epitaxial lift off (ELO) film on the compound compound semiconductor layer.
  • the method may include performing an ELO process, attaching a support handle to the ELO film, and separating the compound semiconductor layer from the mother substrate using the support handle.
  • a sacrificial layer (1) on one side of a mother substrate ie, a GaAs wafer or a Ge wafer serving as a base for providing a suitable lattice structure in which a light absorbing layer (PV) is formed is described.
  • a mother substrate ie, a GaAs wafer or a Ge wafer
  • PV light absorbing layer
  • the compound semiconductor layer CS may include a back contact layer 50, a light absorbing layer PV, a window layer 10, and a front contact layer 30.
  • the front contact layer 30 may be formed entirely on the window layer 10, and may be formed of GaAs having excellent electrical conductivity for ohmic contact. have.
  • the ELO film 130 supports the compound semiconductor layer CS and the compound semiconductor layer CS when the sacrificial layer 120 is removed using hydrofluoric acid (HF) in the ELO process.
  • HF hydrofluoric acid
  • the compound semiconductor layer CS is formed using an inverse growth method
  • a front electrode is formed on one side (lower surface in FIG. 4) of the compound semiconductor layer CS
  • the compound semiconductor solar cell shown in FIG. 1 can be manufactured by forming a back electrode on the other side (upper surface in FIG. 4) of the compound semiconductor layer CS.
  • the inverse growth method is a method of laminating in order from a layer (for example, a front contact layer) located on the front electrode side to a layer (for example, a back contact layer) located on the rear electrode side.
  • the compound semiconductor layer CS is formed using the regular growth method, after the ELO process is performed, a rear electrode is formed on one side (lower surface in FIG. 4) of the compound semiconductor layer CS.
  • the compound semiconductor solar cell shown in FIG. 1 can be manufactured by forming and forming a front electrode on the other surface (upper surface in FIG. 4) of the compound semiconductor layer CS.
  • the regular growth method refers to a method of laminating in order from a layer (for example, a rear contact layer) located on the rear electrode side to a layer (for example, a front contact layer) located on the front electrode side.
  • the support handle 200 of the present embodiment is bonded to the flexible substrate 210 by the flexible substrate 210, the adhesive layer 220 positioned on one side of the flexible substrate 210, and the adhesive layer 220. It may include a foam type self-adhesive film 230 having a self-adhesive surface 230A on a surface opposite to the surface adhered to the adhesive layer 220.
  • a plurality of pores 230A-1 are formed on the self-adhesive surface 230A of the self-adhesive film, and a separate pressure-sensitive adhesive for adhesion with the ELO film 220 is not applied.
  • the plurality of pores 230A-1 formed on the self-adhesive surface 230A may be formed to have a non-uniform size as shown in FIG. 3, and may be distributed non-uniformly.
  • a plurality of pores may be further formed in the self-adhesive film 230, and the plurality of pores formed in the self-adhesive film 230 may be formed in a non-uniform size, and are distributed unevenly. Can be.
  • the cross section of the self-adhesive film may have the same cross section as shown in FIG. 3.
  • Foam-type self-adhesive film 230 may be formed of any one material selected from acrylic (acrylic), polyurethane (polyurethane), polyethylene (polyethylene).
  • the self-adhesive film 230 having such a configuration has a self-adhesive surface 230A when the support handle 200 is adhered to the ELO film 130 with the self-adhesive surface 230A facing the ELO film 130. Bubbles between the ELO film 130 and the ELO film 130 are trapped in the plurality of pores 230A-1 formed on the self-adhesive surface 230A, and thus, due to the air bubbles between the ELO film 130 and the self-adhesive film 230. The adhesive force between the support handle 200 and the ELO film 130 may be suppressed from being lowered, and the adhesion state between the support handle 200 and the ELO film 130 may be maintained firmly.
  • the self-adhesive film 230 firmly adhered to the ELO film 130 is a thermal expansion of air trapped in the pores 230A-1 of the self-adhesive surface 230A under a constant temperature condition (30 ° C. to 60 ° C.). Due to this, it can be easily peeled from the ELO film.
  • the reason for limiting the temperature condition to 30 ° C to 60 ° C is that thermal expansion of air is not well performed at a temperature of less than 30 ° C, so that the self-adhesive film 230 and the ELO film 130 are not effectively peeled off. This is because thermal damage may be applied to the compound semiconductor layer at a temperature of 60 ° C or higher.
  • the self-adhesive film 230 is preferably peeled from the ELO film 220 at a temperature of 30 °C to 60 °C.
  • the flexible substrate 210 may be formed of any one material selected from glass, polypropylene, polyethylene, polycarbonate, and polyurethane, and has a thickness of 100 ⁇ m or more. It may be formed of (T1), and may have acid resistance and solvent resistance.
  • the flexible substrate 210 and the mother substrate 110 may be in a vacuum fixed state by a chuck, respectively.
  • the support handle 200 may be attached to the ELO film 220 while the self-adhesive surface 230A faces the ELO film 220.
  • the support handle 200 may be lined with the ELO film 130 by a roll method.
  • the foam type self-adhesive film 230 is separated from the ELO film 220 at a temperature of 30 ° C. to 60 ° C., and the foam type self adhesive film 230 is included.
  • the support handle 200 is reused after cleaning the self-adhesive surface (230A).
  • FIG. 5 is a photograph comparing a conventional embodiment using a general adhesive tape with an embodiment of the present invention using a foam type self-adhesive tape. It can be seen that poor adhesion occurs, and lifting and wrinkles occur in some areas.

Abstract

The present invention relates to a support handle and a method for manufacturing a compound semiconductor solar battery using same. A support handle according to an aspect of the present invention may comprise: a flexible substrate; an adhesive layer located on one surface of the flexible substrate; and a foam-type self-adhesive film adhered to the flexible substrate by the adhesive layer, and having a self-adhesive surface opposite to the surface of the film adhered to the adhesive layer.

Description

지지 핸들 및 이를 이용한 화합물 반도체 태양전지의 제조 방법Support handle and manufacturing method of compound semiconductor solar cell using same
본 발명은 지지 핸들 및 이를 이용한 화합물 반도체 태양전지의 제조 방법에 관한 것으로, 2018년도 정부(과학기술정보통신부)의 재원으로 한국연구재단-우주핵심기술개발사업 지원을 받아 수행된 연구(NRF-2017M1A3A3A03016626)이다.The present invention relates to a support handle and a method for manufacturing a compound semiconductor solar cell using the same. )to be.
그리고 보다 상세하게는 ELO (Epitaxial Lift Off) 공정 후에 화합물 반도체층을 모기판으로부터 손상 없이 안정적으로 분리할 수 있는 지지 핸들 및 이를 이용한 화합물 반도체 태양전지의 제조 방법에 관한 것이다.In more detail, the present invention relates to a support handle capable of stably separating a compound semiconductor layer from a mother substrate without damage after an epitaxial lift off (ELO) process, and a method of manufacturing a compound semiconductor solar cell using the same.
화합물 반도체 태양전지는 상기 화합물 반도체층을 형성하기 위한 모기판(GaAs 웨이퍼 또는 Ge 웨이퍼)을 화합물 반도체층과 분리하지 않고 태양전지의 구성 요소로 함께 사용하여 화합물 반도체 태양전지를 제조하는 방법, 또는 ELO (Epitaxial Lift Off) 공정을 이용하여 희생층을 제거함으로써 상기 모기판(GaAs 웨이퍼 또는 Ge 웨이퍼)을 상기 화합물 반도체층과 분리한 후 상기 화합물 반도체층만 태양전지의 구성 요소로 사용하여 화합물 반도체 태양전지를 제조하는 방법에 의해 제조할 수 있다.A compound semiconductor solar cell is a method of manufacturing a compound semiconductor solar cell by using a mother substrate (GaAs wafer or Ge wafer) for forming the compound semiconductor layer together as a component of the solar cell without separating from the compound semiconductor layer, or ELO The mother substrate (GaAs wafer or Ge wafer) is separated from the compound semiconductor layer by removing the sacrificial layer using an epitaxial lift off process, and only the compound semiconductor layer is used as a component of the solar cell. It can manufacture by the method of manufacturing.
그리고 후자의 경우, ELO (Epitaxial Lift Off) 공정에서는 화합물 반도체층의 손상을 방지함과 아울러, 후속 공정에서 상기 화합물 반도체층을 지지하는 지지 핸들을 사용한다.In the latter case, an Epitaxial Lift Off (ELO) process prevents damage to the compound semiconductor layer and uses a support handle for supporting the compound semiconductor layer in a subsequent step.
그런데, 종래에 사용되는 지지 핸들은 ELO 공정에서 발생하는 지지 핸들 재료의 수축 및 지지 핸들을 화합물 반도체층에 접착하기 위한 접착층의 변형으로 인해 1회만 사용할 수 있으므로, 화합물 반도체 태양전지의 제조 원가가 상승하는 문제점이 있다.However, the support handles used in the related art can be used only once because of shrinkage of the support handle material generated in the ELO process and deformation of the adhesive layer for bonding the support handle to the compound semiconductor layer, thereby increasing the manufacturing cost of the compound semiconductor solar cell. There is a problem.
본 발명은 재사용이 가능하여 화합물 반도체 태양전지의 제조 원가를 절감할 수 있으며, ELO (Epitaxial Lift Off) 공정 후에 화합물 반도체층을 모기판으로부터 손상 없이 안정적으로 분리할 수 있는 지지 핸들 및 이를 이용한 화합물 반도체 태양전지의 제조 방법을 제공하는데 목적이 있다.The present invention can be reused to reduce the manufacturing cost of the compound semiconductor solar cell, and a support handle that can stably separate the compound semiconductor layer from the mother substrate after the Epitaxial Lift Off (ELO) process and the compound semiconductor using the same It is an object to provide a method of manufacturing a solar cell.
본 발명의 한 측면에 따른 지지 핸들은, 가요성 기판; 상기 가요성 기판의 한쪽 면에 위치하는 접착층; 및 상기 접착층에 의해 상기 가요성 기판에 접착되며, 상기 접착층에 접착되는 면의 반대쪽 면에 자가 점착면을 구비하는 폼(foam) 타입 자가 점착 필름을 포함할 수 있다.According to one aspect of the invention, a support handle includes: a flexible substrate; An adhesive layer located on one side of the flexible substrate; And a foam type self-adhesive film adhered to the flexible substrate by the adhesive layer and having a self-adhesive surface on a surface opposite to the surface bonded to the adhesive layer.
상기 폼 타입 자가 점착 필름은 아크릴(acrylic), 폴리우레탄(polyurethane), 폴리에틸렌(polyethylene) 중에서 선택된 어느 하나의 재질로 형성될 수 있고, 30℃ 내지 60℃의 온도에서 박리될 수 있다.The foam type self-adhesive film may be formed of any one material selected from acrylic, polyurethane, and polyethylene, and may be peeled at a temperature of 30 ° C. to 60 ° C.
상기 자가 점착면에는 복수의 기공(pore)이 형성되어 있고, 복수의 기공은 폼 타입 자가 점착 필름의 내부에 더 형성되어 있을 수 있다.A plurality of pores are formed on the self-adhesive surface, and the plurality of pores may be further formed inside the foam type self-adhesive film.
자가 점착면에 형성된 복수의 기공 및 자가 점착 필름의 내부에 더 형성된 복수의 기공은 불균일한 크기로 형성될 수 있으며, 불균일하게 분포될 수 있다.The plurality of pores formed on the self-adhesive surface and the plurality of pores further formed inside the self-adhesive film may be formed in non-uniform size, and may be distributed non-uniformly.
상기 가요성 기판은 유리(glass), 폴리프로필렌(polypropylene), 폴리에틸렌(polyethylene), 폴리카보네이트(polycarbonate), 폴리우레탄(polyurethane) 중에서 선택된 어느 하나의 재질로 형성될 수 있고, 100㎛ 이상의 두께로 형성될 수 있으며, 내산성 및 내용제성을 가질 수 있다.The flexible substrate may be formed of any one selected from glass, polypropylene, polyethylene, polycarbonate, polyurethane, and has a thickness of 100 μm or more. It may have acid resistance and solvent resistance.
이러한 구성의 지지 핸들을 이용한 화합물 반도체 태양전지의 제조 방법은, 모기판의 한쪽 면 위에 희생층을 형성하는 단계; 상기 희생층 위에 화합물 반도체층을 형성하는 단계; 상기 화합물 반도체층 위에 ELO(Epitaxial Lift Off) 필름을 부착하는 단계; ELO 공정을 실시하는 단계; 상기 ELO 필름에 지지 핸들을 부착하는 단계; 및 상기 지지 핸들을 이용하여 상기 화합물 반도체층을 상기 모기판과 분리하는 단계를 포함할 수 있다.Method for producing a compound semiconductor solar cell using the support handle of this configuration, forming a sacrificial layer on one side of the mother substrate; Forming a compound semiconductor layer on the sacrificial layer; Attaching an epitaxial lift off (ELO) film on the compound semiconductor layer; Performing an ELO process; Attaching a support handle to the ELO film; And separating the compound semiconductor layer from the mother substrate by using the support handle.
본 발명에 따른 화합물 반도체 태양전지의 제조 방법에 따르면, 지지 핸들은은 ELO 공정 후에 ELO 필름 위에 부착되므로, ELO 공정에서 사용되는 불산에 의해 지지 핸들의 점착층이 손상되는 것을 방지할 수 있음과 아울러, 지지 핸들의 가요성 기판의 수축 변형이 발생하지 않는다.According to the method for manufacturing a compound semiconductor solar cell according to the present invention, since the support handle is attached onto the ELO film after the ELO process, the adhesive layer of the support handle can be prevented from being damaged by the hydrofluoric acid used in the ELO process. No shrinkage deformation of the flexible substrate of the support handle occurs.
그리고 지지 핸들은 자가 점착면에 복수의 기공(pore)이 형성된 폼 타입의 자가 점착 필름을 구비하므로, 지지 핸들을 ELO 필름에 부착할 때 자가 점착면과 ELO 필름 사이에 위치하는 기포가 자가 점착면에 형성된 기공에 포획되므로, ELO 필름과 자가 점착 필름 사이에 있는 기포로 인해 지지 핸들과 ELO 필름 간의 점착력이 저하하는 것을 억제할 수 있다.And since the support handle has a foam-type self-adhesive film having a plurality of pores formed on the self-adhesive surface, when the support handle is attached to the ELO film, bubbles placed between the self-adhesive surface and the ELO film are self-adhesive surfaces. Since it is trapped by the pores formed in the film, the bubbles between the ELO film and the self-adhesive film can be suppressed from decreasing the adhesive force between the support handle and the ELO film.
그리고, ELO 필름에 견고하게 점착되어 있는 자가 점착 필름은 일정한 온도 조건(30℃ 내지 60℃)에서 자가 점착면의 기공에 포획된 공기의 열팽창으로 인해 ELO 필름으로부터 쉽게 박리할 수 있으므로, 후속 공정에서 지지 핸들을 취급하는 중에 작업자의 부주의로 인해 자가 점착 필름이 ELO 필름으로부터 박리되는 것을 억제할 수 있고, 화합물 반도체층의 손상 없이 자가 점착 필름을 효과적으로 박리할 수 있다.In addition, the self-adhesive film firmly adhered to the ELO film can be easily peeled from the ELO film due to thermal expansion of air trapped in pores of the self-adhesive surface under constant temperature conditions (30 ° C. to 60 ° C.). It is possible to suppress the self-adhesive film from being peeled from the ELO film due to carelessness of the operator while handling the support handle, and can effectively peel off the self-adhesive film without damaging the compound semiconductor layer.
그리고 지지 핸들을 ELO 필름으로부터 박리한 후에는 자가 점착면을 세정한 후 지지 핸들을 재사용할 수 있다.After peeling the support handle from the ELO film, the support handle can be reused after cleaning the self-adhesive surface.
따라서, 화합물 반도체 태양전지의 제조 원가를 절감할 수 있으며, ELO 공정 후에 화합물 반도체층을 모기판으로부터 손상 없이 안정적으로 분리할 수 있다.Therefore, the manufacturing cost of the compound semiconductor solar cell can be reduced, and the compound semiconductor layer can be stably separated from the mother substrate after the ELO process without damage.
도 1은 화합물 반도체 태양전지의 사시도이다.1 is a perspective view of a compound semiconductor solar cell.
도 2는 본 발명의 실시예에 따른 지지 핸들의 단면도이다.2 is a cross-sectional view of a support handle according to an embodiment of the present invention.
도 3은 도 2에 도시한 자가 점착면을 촬영한 사진이다.3 is a photograph of the self-adhesive surface shown in FIG. 2.
도 4는 도 2에 도시한 지지 핸들을 이용한 화합물 반도체 태양전지의 제조 방법을 나타내는 공정도이다.FIG. 4 is a process chart showing a method for manufacturing a compound semiconductor solar cell using the support handle shown in FIG. 2.
도 5는 일반적인 점착 테이프를 사용한 종래와 폼 타입 자가 점착 테이프를 사용한 본 발명의 실시예를 비교하는 사진이다.Figure 5 is a photograph comparing the embodiment of the present invention using a conventional foam type self-adhesive tape with a conventional adhesive tape.
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해될 수 있다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It is not intended to limit the invention to the specific embodiments, it can be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.
본 발명을 설명함에 있어서 제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되지 않을 수 있다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. In describing the present invention, terms such as first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다.For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
"및/또는" 이라는 용어는 복수의 관련된 기재된 항목들의 조합 또는 복수의 관련된 기재된 항목들 중의 어느 항목을 포함할 수 있다.The term "and / or" may include a combination of a plurality of related items or any of a plurality of related items.
어떤 구성요소가 다른 구성요소에 "연결되어" 있다거나 "결합되어" 있다고 언급되는 경우는, 그 다른 구성요소에 직접적으로 연결되어 있거나 또는 결합되어 있을 수도 있지만, 중간에 다른 구성요소가 존재할 수도 있다고 이해될 수 있다.When a component is said to be "connected" or "coupled" to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
반면에, 어떤 구성요소가 다른 구성요소에 "직접 연결되어" 있다거나 "직접 결합되어" 있다고 언급된 때에는, 중간에 다른 구성요소가 존재하지 않는 것으로 이해될 수 있다.On the other hand, when a component is referred to as being "directly connected" or "directly coupled" to another component, it may be understood that there is no other component in between.
본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함할 수 있다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions may include plural expressions unless the context clearly indicates otherwise.
본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것으로서, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해될 수 있다.In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It may be understood that the present invention does not exclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or a combination thereof.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 층, 막, 영역, 판 등의 부분이 다른 부분 "위에" 있다고 할 때, 이는 다른 부분 "바로 위에" 있는 경우뿐 아니라 그 중간에 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 "바로 위에" 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가질 수 있다. Unless defined otherwise, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art.
일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 가지는 것으로 해석될 수 있으며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않을 수 있다.Terms such as those defined in the commonly used dictionaries may be interpreted as having meanings consistent with the meanings in the context of the related art, and shall be interpreted in ideal or excessively formal meanings unless expressly defined in the present application. It may not be.
아울러, 이하의 실시예는 당 업계에서 평균적인 지식을 가진 자에게 보다 완전하게 설명하기 위해서 제공되는 것으로서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있다.In addition, the following embodiments are provided to more fully describe those skilled in the art, and the shape and size of the elements in the drawings may be exaggerated for clarity.
이하, 첨부도면을 참조하여 본 발명에 따른 화합물 반도체 태양전지의 제조 방법을 설명한다.Hereinafter, a method of manufacturing a compound semiconductor solar cell according to the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명에 따른 화합물 반도체 태양전지의 제조 방법을 나타내는 블록도이고, 도 4는 도 3의 제조 방법을 구체적으로 나타내는 공정도이다.3 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to the present invention, and FIG. 4 is a process diagram illustrating the manufacturing method of FIG. 3 in detail.
그리고 도 5는 도 4에 도시한 제1 보호층과 제2 보호층의 다양한 실시예를 나타내는 단면도이며, 도 6은 도 4의 제조 방법에 의해 제조한 화합물 반도체 태양전지의 사시도이다.5 is a cross-sectional view illustrating various embodiments of the first protective layer and the second protective layer illustrated in FIG. 4, and FIG. 6 is a perspective view of the compound semiconductor solar cell manufactured by the manufacturing method of FIG. 4.
먼저, 본 발명의 제조 방법에 의해 제조한 화합물 반도체 태양전지에 대해 도 6을 참조하여 설명한다.First, the compound semiconductor solar cell manufactured by the manufacturing method of this invention is demonstrated with reference to FIG.
화합물 반도체 태양전지는 광 흡수층(PV), 광 흡수층(PV)의 전면(front surface) 위에 위치하는 윈도우층(10), 윈도우층(10)의 전면 위에 위치하는 전면 전극(20), 윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30), 윈도우층(10) 위에 위치하는 반사 방지막(40), 광 흡수층(PV)의 후면 위에 위치하는 후면 콘택층(50) 및 후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)을 포함할 수 있다. The compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a front electrode 20 positioned on the front surface of the window layer 10, and a window layer ( 10) the front contact layer 30 positioned between the front electrode 20, the antireflection film 40 positioned on the window layer 10, the rear contact layer 50 positioned on the rear surface of the light absorbing layer PV, and The rear electrode 60 may include a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
여기서, 반사 방지막(40), 윈도우층(10), 전면 콘택층(30) 및 후면 콘택층(50) 중 적어도 하나는 생략될 수도 있지만, 도 6에 도시된 바와 같이 상기 층들이 구비된 경우를 일례로 설명한다.Here, at least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted, but as shown in FIG. It demonstrates as an example.
광 흡수층(PV)은 III-VI족 반도체 화합물을 포함하여 형성될 수 있고, 제1 도전성 타입의 불순물(예, p형 불순물)이 도핑되는 p형 반도체층(PV-p)과, 제2 도전성 타입의 불순물(예, n형 불순물)이 도핑되는 n형 반도체층(PV-n)을 포함할 수 있다.The light absorbing layer PV may include a III-VI semiconductor compound, a p-type semiconductor layer PV-p doped with impurities of a first conductivity type (eg, p-type impurities), and a second conductivity It may include an n-type semiconductor layer (PV-n) doped with a type of impurities (for example, n-type impurities).
이러한 구성의 광 흡수층(PV)은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 모기판(mother substrate)으로부터 제조할 수 있다.The light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
윈도우층(10)은 광 흡수층(PV)과 전면 전극(20) 사이에 형성될 수 있으며, III-VI족 반도체 화합물에 제2 도전성 타입의 불순물을 도핑하여 형성할 수 있다.The window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a group III-VI semiconductor compound with impurities of a second conductivity type.
하지만 윈도우층(10)은 n형 또는 p형의 불순물을 포함하지 않을 수도 있으며, 광 흡수층(PV)의 전면(front surface)을 패시베이션(passivation)하는 기능을 한다. However, the window layer 10 may not include n-type or p-type impurities, and functions to passivate the front surface of the light absorbing layer PV.
반사 방지막(40)은 윈도우층(10)의 전면 위 중에서 전면 전극(20) 및/또는 전면 콘택층(30)이 위치하는 영역을 제외한 나머지 영역에 위치할 수 있다.The anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
이와 달리, 반사 방지막(40)은 노출된 윈도우층(10) 뿐만 아니라, 전면 콘택층(30) 및 전면 전극(20) 위에 배치될 수도 있다.Alternatively, the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
이 경우, 도시하지는 않았지만 화합물 반도체 태양전지는 복수의 전면 전극(20)을 물리적으로 연결하는 버스바 전극을 더 구비할 수 있으며, 버스바 전극은 반사 방지막(40)에 의해 덮여지지 않고 외부로 노출될 수 있다.In this case, although not shown, the compound semiconductor solar cell may further include a busbar electrode for physically connecting the plurality of front electrodes 20, and the busbar electrode is not covered by the anti-reflection film 40 and exposed to the outside. Can be.
이러한 구성의 반사 방지막(40)은 불화마그네슘, 황화아연, 티타늄 옥사이드, 실리콘 옥사이드, 이들의 유도체 또는 이들의 조합을 포함할 수 있다.The antireflection film 40 having such a configuration may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
전면 전극(20)은 제1 방향(X-X')으로 길게 연장되어 형성될 수 있으며, 제1 방향과 직교하는 제2 방향(Y-Y')을 따라 복수개가 일정한 간격으로 이격될 수 있다.The front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
이러한 구성의 전면 전극(20)은 전기 전도성 물질을 포함하여 형성될 수 있으며, 일례로 금속인 금(Au), 게르마늄(Ge), 니켈(Ni) 중 적어도 하나를 포함하여 형성될 수 있다.The front electrode 20 having such a configuration may be formed by including an electrically conductive material. For example, the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30)은 III-VI족 반도체 화합물에 윈도우층(10)의 불순물 도핑농도보다 높은 도핑농도로 제2 불순물을 도핑하여 형성할 수 있다.The front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
전면 콘택층(30)은 윈도우층(10)과 전면 전극(20) 간에 오믹 콘택(ohmic contact)을 형성한다.The front contact layer 30 forms an ohmic contact between the window layer 10 and the front electrode 20.
광 흡수층(PV)의 p형 반도체층(PV-p)의 후면, 광 흡수층(PV)이 후면 전계층을 구비하는 경우에는 후면 전계층의 후면 위에 위치하는 후면 콘택층(50)은 광 흡수층(PV)의 후면에 전체적으로 위치하며, III-VI족 반도체 화합물에 제1 도전성 타입의 불순물을 p형 반도체층(PV-p)보다 높은 도핑농도로 도핑하여 형성할 수 있다.When the back of the p-type semiconductor layer PV-p of the light absorbing layer PV and the light absorbing layer PV have a rear electric field layer, the rear contact layer 50 located on the rear of the rear electric field layer may be a light absorbing layer ( It is located on the back of the PV) as a whole, and may be formed by doping the III-VI semiconductor compound with a doping concentration higher than that of the p-type semiconductor layer PV-p.
이러한 후면 콘택층(50)은 후면 전극(160)과 오믹 콘택을 형성할 수 있다.The back contact layer 50 may form an ohmic contact with the back electrode 160.
후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)은 전면 전극(20)과는 다르게 후면 콘택층(50)의 후면에 전체적으로 위치하는 시트(Sheet) 형상의 도전체로 형성될 수 있다. 즉, 후면 전극(60)은 후면 콘택층(50)의 후면 전체에 위치하는 면 전극(sheet electrode)이라고도 말할 수 있다.Unlike the front electrode 20, the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor located entirely on the rear surface of the rear contact layer 50. That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
이때, 후면 전극(60)은 광 흡수층(PV)과 동일한 평면적으로 형성될 수 있으며, 금(Au), 백금(Pt), 티타늄(Ti), 텅스텐(W), 규소(Si), 니켈(Ni), 마그네슘(Mg), 팔라듐(Pd), 구리(Cu), 및 게르마늄(Ge) 중에서 선택된 적어도 어느 한 물질을 포함하는 단일막 또는 다중막으로 형성될 수 있고, 후면 전극을 형성하는 물질은 후면 콘택층의 도전성 타입에 따라 적절하게 선택될 수 있다.In this case, the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
이하, 상기한 화합물 반도체 태양전지의 제조 방법에 대해 설명한다.Hereinafter, the manufacturing method of said compound semiconductor solar cell is demonstrated.
도 1은 본 발명의 제1 실시예에 따른 화합물 반도체 태양전지의 제조 방법을 나타내는 블록도이고, 도 2는 도 1의 제조 방법을 구체적으로 나타내는 공정도이다.1 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a first embodiment of the present invention, and FIG. 2 is a process diagram illustrating the manufacturing method of FIG. 1 in detail.
그리고 도 3은 본 발명의 제2 실시예에 따른 화합물 반도체 태양전지의 제조 방법을 나타내는 블록도이고, 도 4는 도 3의 제조 방법을 구체적으로 나타내는 공정도이며, 도 5는 도 4에 도시한 제1 보호층과 제2 보호층의 다양한 실시예를 나타내는 단면도이다.3 is a block diagram illustrating a method of manufacturing a compound semiconductor solar cell according to a second embodiment of the present invention, FIG. 4 is a process diagram illustrating the manufacturing method of FIG. 3 in detail, and FIG. 1 is a cross-sectional view showing various embodiments of the protective layer and the second protective layer.
이하, 상기 도 1 및 도 2를 참조하여 본 발명의 제1 실시예에 따른 제조 방법에 대해 먼저 설명한다.Hereinafter, a manufacturing method according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.
제1 실시예의 제조 방법은 크게, 모기판의 한쪽 면 위에 희생층을 형성하는 단계(S110); 상기 희생층 위에 화합물 반도체층을 형성하는 단계(S120); 상기 화합물 반도체층의 제1 면 위에 제1 라미네이션 필름을 부착하는 단계(S130); ELO 공정을 실시하여 상기 희생층을 제거함으로써, 상기 화합물 반도체층 및 상기 제1 라미네이션 필름을 상기 모기판으로부터 분리하는 단계(S140); 상기 화합물 반도체층의 제2 면 위에 후면 전극을 형성하는 단계(S150); 상기 후면 전극 위에 제2 라미네이션 필름을 부착하는 단계(S160); 상기 제1 라미네이션 필름을 제거하는 단계(S170); 및 상기 화합물 반도체층의 제1 면 위에 전면 전극을 형성하는 단계(S180)를 포함한다.The manufacturing method of the first embodiment is large, forming a sacrificial layer on one side of the mother substrate (S110); Forming a compound semiconductor layer on the sacrificial layer (S120); Attaching a first lamination film on the first surface of the compound semiconductor layer (S130); Separating the compound semiconductor layer and the first lamination film from the mother substrate by performing an ELO process to remove the sacrificial layer (S140); Forming a rear electrode on the second surface of the compound semiconductor layer (S150); Attaching a second lamination film on the back electrode (S160); Removing the first lamination film (S170); And forming a front electrode on the first surface of the compound semiconductor layer (S180).
이에 대해 보다 상세히 설명하면, 먼저, 광 흡수층(PV)이 형성되는 적절한 격자 구조를 제공하기 위한 베이스로 작용하는 모기판(110, mother substrate)의 한쪽 면에 희생층(120)을 형성하고(S110), 희생층(120) 위에 화합물 반도체층(CS)을 형성한다(S120).In more detail, first, a sacrificial layer 120 is formed on one side of a mother substrate 110 serving as a base for providing an appropriate lattice structure in which a light absorbing layer PV is formed (S110). In operation S120, a compound semiconductor layer CS is formed on the sacrificial layer 120.
여기에서, 화합물 반도체층(CS)은 레귤러 성장법을 이용하여 희생층(120) 위에 후면 콘택층(50), 광 흡수층(PV), 윈도우층(10) 및 전면 콘택층(30)을 순차적으로 적층하는 것에 의해 형성할 수 있다In this case, the compound semiconductor layer CS sequentially forms the back contact layer 50, the light absorbing layer PV, the window layer 10, and the front contact layer 30 on the sacrificial layer 120 using the regular growth method. It can form by laminating
이어서, 상기 화합물 반도체층(CS) 위에 제1 라미네이션 필름(130)을 부착한다(S130).Subsequently, the first lamination film 130 is attached onto the compound semiconductor layer CS (S130).
제1 라미네이션 필름(130)은 지지 기판으로 작용하는 기재 필름(130B) 및 상기 기재 필름(130B)의 한쪽 면에 위치하는 점착제(130A)로 형성할 수 있다.The first lamination film 130 may be formed of a base film 130B serving as a support substrate and an adhesive 130A positioned on one side of the base film 130B.
기재 필름(130B)은 폴리에틸렌테레프탈레이트, 폴리비닐클로라이드, 에틸렌비닐아세테이트 등과 폴리올레핀 계열의 수지 또는 이의 공중합체로 형성될 수 있으며, 2 내지 200㎛의 두께로 형성될 수 있다.The base film 130B may be formed of polyethylene terephthalate, polyvinyl chloride, ethylene vinyl acetate, or the like, or a polyolefin-based resin or a copolymer thereof, and may have a thickness of 2 to 200 μm.
그런데, 본 실시예의 제조 방법에서는 제1 라미네이션 필름(130)을 화합물 반도체층(CS)의 제1 면에 직접 점착하고 있으므로, 기재 필름(130B)이 화합물 반도체층(CS)을 지지해야 한다.However, in the manufacturing method of the present embodiment, since the first lamination film 130 is directly adhered to the first surface of the compound semiconductor layer CS, the base film 130B must support the compound semiconductor layer CS.
따라서, 본 실시예의 제조 방법에 사용되는 제1 라미네이션 필름(130)의 기재 필름(130B)은 화합물 반도체층(CS)을 효과적으로 지지할 수 있도록 150 내지 200㎛의 두께로 형성되는 것이 바람직하다.Therefore, the base film 130B of the first lamination film 130 used in the manufacturing method of the present embodiment is preferably formed to a thickness of 150 to 200㎛ to effectively support the compound semiconductor layer (CS).
기재 필름(130B)을 화합물 반도체층(CS)의 제1 면에 점착하기 위한 점착제는 아크릴계 수지를 조성물로 포함할 수 있고, 상기 아크릴계 수지 외에 열 경화제, 광 경화제, 미세구체로 형성된 발포제 등을 선택적으로 더 포함할 수 있다.The pressure-sensitive adhesive for adhering the base film 130B to the first surface of the compound semiconductor layer CS may include an acrylic resin as a composition, and in addition to the acrylic resin, a heat curing agent, a light curing agent, a foaming agent formed of microspheres, and the like may be selected. It may further include as.
상기 아크릴계 수지로는 실리콘 아크릴레이트, 폴리에테르 아크릴레이트 또는 폴리에스테르 아크릴레이트를 사용할 수 있다.As the acrylic resin, silicone acrylate, polyether acrylate or polyester acrylate may be used.
한 예로, 상기 점착제는 실리콘 아크릴레이트, 폴리에테르 아크릴레이트 또는 폴리에스테르 아크릴레이트 계열의 수지로 형성될 수 있다.As one example, the pressure-sensitive adhesive may be formed of a silicone acrylate, polyether acrylate or polyester acrylate-based resin.
다른 예로, 상기 점착제는 아크릴계 수지(실리콘 아크릴레이트, 폴리에테르 아크릴레이트 또는 폴리에스테르 아크릴레이트)와, 열 경화제(이소시아네이트계 가교제 또는 메틸롤계 가교제 중 1종 또는 2종 물질을 혼합하여 형성함), 및 가열에 의해 발포되는 미세구체로 형성된 발포제를 혼합하여 형성할 수 있다. 이때, 점착제를 형성하는 조성물 중에서 고형분은 상기 점착제의 전체 중량에 대해 10~60중량%가 되도록 형성하는 것이 바람직하다.As another example, the pressure-sensitive adhesive may be formed by mixing an acrylic resin (silicone acrylate, polyether acrylate or polyester acrylate) with a thermosetting agent (isocyanate-based crosslinking agent or methylol-based crosslinking agent). It may be formed by mixing a blowing agent formed of microspheres that are foamed by heating. At this time, it is preferable to form solid content in the composition which forms an adhesive so that it may become 10 to 60 weight% with respect to the total weight of the said adhesive.
다른 예로, 상기 점착제는 아크릴계 수지(실리콘 아크릴레이트, 폴리에테르 아크릴레이트 또는 폴리에스테르 아크릴레이트)와, 광 경화제(벤조인에테르, 아민, 디아조늄염, 요오드늄염, 술포늄염 또는 메탈노센화합물 중 1종 또는 2종 이상의 물질을 혼합하여 형성함) 및 광에 의해 발포되는 미세구체로 형성된 발포제를 혼합하여 형성할 수 있다. 이때, 점착제를 형성하는 조성물 중에서 고형분은 상기 점착제의 전체 중량에 대해 10~60중량%가 되도록 형성하는 것이 바람직하다.In another example, the pressure-sensitive adhesive is one of an acrylic resin (silicone acrylate, polyether acrylate or polyester acrylate) and a light curing agent (benzoin ether, amine, diazonium salt, iodonium salt, sulfonium salt or metal nocene compound). Or a mixture of two or more materials) and a blowing agent formed of microspheres foamed by light. At this time, it is preferable to form solid content in the composition which forms an adhesive so that it may become 10 to 60 weight% with respect to the total weight of the said adhesive.
점착제가 열 또는 광에 의해 발포되는 발포제를 포함하는 경우, 제1 라미네이션 필름에 열을 가하거나 광을 조사하면 발포제가 발포되어 점착력이 저하되므로 기재 필름(130B)의 박리가 쉽게 이루어진다.When the pressure-sensitive adhesive includes a foaming agent that is foamed by heat or light, when the heat is applied to the first lamination film or irradiated with light, the foaming agent is foamed to lower the adhesive force, thereby easily peeling off the base film 130B.
본 실시예에서는 제1 라미네이션 필름(130)이 기재 필름(130B) 및 이 필름의 한쪽 면에 도포된 점착제로 구성되는 것을 예로 들어 설명하였지만, 제1 라미네이션 필름은 화합물 반도체층의 제1 면에 점착제를 도포한 후 점착제 위에 기재 필름의 조성물을 스핀 코팅, 바 코팅, 스크린 인쇄 등의 방법으로 도포하는 것에 의해 형성할 수도 있다.In the present exemplary embodiment, the first lamination film 130 is composed of a base film 130B and an adhesive applied to one side of the film. However, the first lamination film is a pressure-sensitive adhesive on the first surface of the compound semiconductor layer. After coating, the composition of the base film may be formed by applying a composition such as spin coating, bar coating or screen printing onto the pressure-sensitive adhesive.
다음으로, ELO 공정을 실시하여 희생층(120)을 제거한다(S140).Next, the sacrificial layer 120 is removed by performing an ELO process (S140).
ELO 공정에서는 불산(HF)을 식각 용액으로 사용할 수 있으며, ELO 공정을 실시하면, 상기 불산(HF)에 의해 희생층(120)이 제거되므로, 화합물 반도체층(CS) 및 제1 라미네이션 필름(130)을 모기판(110)과 분리할 수 있다.In the ELO process, hydrofluoric acid (HF) may be used as an etching solution. When the ELO process is performed, the sacrificial layer 120 is removed by the hydrofluoric acid (HF), and thus the compound semiconductor layer CS and the first lamination film 130 are used. ) May be separated from the mother substrate 110.
이어서, 제1 라미네이션 필름(130)이 화합물 반도체층(CS)의 하부에 위치하도록 배치한 상태에서 제1 라미네이션 필름(130)의 후면 위에 제1 지지 핸들(150)을 부착하고, 화합물 반도체층(CS) 위에 후면 전극(60)을 형성한다(S150).Subsequently, in a state where the first lamination film 130 is disposed below the compound semiconductor layer CS, the first support handle 150 is attached to the rear surface of the first lamination film 130, and the compound semiconductor layer ( A rear electrode 60 is formed on the CS (S150).
후면 전극(60)은 금(Au), 백금(Pt), 티타늄(Ti), 텅스텐(W), 규소(Si), 니켈(Ni), 마그네슘(Mg), 팔라듐(Pd), 구리(Cu), 및 게르마늄(Ge) 중에서 선택된 적어도 어느 한 물질을 포함하는 단일막 또는 다중막으로 형성할 수 있다.The rear electrode 60 includes gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), nickel (Ni), magnesium (Mg), palladium (Pd), and copper (Cu) It may be formed as a single film or multiple films containing at least one material selected from, and germanium (Ge).
이어서, 후면 전극(60) 위에 제2 라미네이션 필름(160)을 부착한다(S160).Subsequently, the second lamination film 160 is attached onto the rear electrode 60 (S160).
제2 라미네이션 필름(160)은 제1 라미네이션 필름(130)과 동일한 구조로 형성할 수 있으며, 제1 라미네이션 필름(130)과 동일한 방법으로 부착할 수 있다.The second lamination film 160 may be formed in the same structure as the first lamination film 130 and may be attached in the same manner as the first lamination film 130.
하지만, 제2 라미네이션 필름(160)이 제1 라미네이션 필름(130)과 서로 다른 구조로 형성되는 것도 가능하다.However, it is also possible for the second lamination film 160 to have a different structure from the first lamination film 130.
계속하여, 제2 라미네이션 필름(160) 위에 제2 지지 핸들(170)을 부착한 상태에서 제1 지지 핸들(150)이 상부를 향하도록 배치하고, 이후, 제1 지지 핸들(150)과 제1 라미네이션 필름(130)을 제거한다(S170).Subsequently, in a state where the second support handle 170 is attached on the second lamination film 160, the first support handle 150 is disposed upward, and then, the first support handle 150 and the first support handle 150 are disposed upward. The lamination film 130 is removed (S170).
이때, 제1 라미네이션 필름(130)은 아래의 4가지 방법 중 어느 한 방법으로 제거할 수 있다.In this case, the first lamination film 130 may be removed by any one of the following four methods.
(1) 0.2 내지 5N/25mm의 힘을 이용하여 상기 제1 라미네이션 필름을 박리함.(1) Peeling the said 1st lamination film using the force of 0.2-5N / 25mm.
(2) 60 내지 200℃의 온도로 5초 내지 20분동안 가열한 후 상기 제1 라미네이션 필름을 박리함.(2) The first lamination film was peeled off after heating at a temperature of 60 to 200 ° C. for 5 seconds to 20 minutes.
(3) 200 내지 400nm의 파장을 갖는 빛을 20 내지 600mJ/㎠의 강도로 조사하여 상기 제1 라미네이션 필름을 박리함.(3) peeling the first lamination film by irradiating light having a wavelength of 200 to 400 nm with an intensity of 20 to 600 mJ / cm 2.
(4) Acetone(2-propanone), Isopropyl alcohol(Isopropanol), NMP(1-Methyl-2-pyrrolidon), DMSO(Dimethyl sulfoxide) 중 하나 이상의 용매를 이용하여 상기 제1 라미네이션 필름을 박리함.(4) Peeling the first lamination film using at least one solvent of Acetone (2-propanone), Isopropyl alcohol (Isopropanol), NMP (1-Methyl-2-pyrrolidon), DMSO (dimethyl sulfoxide).
위에서 말한 바와 같이, 제1 라미네이션 필름의 점착제는 실리콘 아크릴레이트, 폴리에테르 아크릴레이트 또는 폴리에스테르 아크릴레이트와 같은 아크릴계 수지를 조성물로 포함한다.As mentioned above, the pressure-sensitive adhesive of the first lamination film includes an acrylic resin such as silicone acrylate, polyether acrylate or polyester acrylate as a composition.
그런데, 아크릴계 조성물을 포함하는 점착제(130A)의 점착력은 일반적으로 0.2 내지 5N/25mm이다.By the way, the adhesive force of the adhesive 130A containing an acrylic composition is generally 0.2-5 N / 25mm.
따라서, 상기 (1)번 항목에 기재한 방법에 따라 0.2 내지 5N/25mm의 힘을 이용하여 제1 라미네이션 필름을 물리적으로 박리할 수 있다.Therefore, according to the method described in item (1), the first lamination film may be physically peeled off using a force of 0.2 to 5 N / 25 mm.
그리고 점착제(130A)가 가열에 의해 발포되는 미소구체로 형성된 발포제를 더 포함하는 경우에는 상기 (2)번 항목에 기재한 방법에 따라 60 내지 200℃의 온도로 5초 내지 20분동안 가열하여 발포제를 발포시키는 것에 의해 제1 라미네이션 필름을 박리할 수 있다.And if the pressure-sensitive adhesive (130A) further comprises a foaming agent formed of a microsphere foamed by heating, the foaming agent by heating for 5 seconds to 20 minutes at a temperature of 60 to 200 ℃ according to the method described in item (2) By foaming, the first lamination film can be peeled off.
그리고 점착제(130A)가 광에 의해 발포되는 미소구체로 형성된 발포제를 더 포함하는 경우에는 상기 (3)번 항목에 기재한 방법에 따라 200 내지 400nm의 파장을 갖는 빛을 20 내지 600mJ/㎠의 강도로 조사하여 발포제를 발포시키는 것에 의해 제1 라미네이션 필름을 박리할 수 있다.And when the pressure-sensitive adhesive (130A) further comprises a foaming agent formed of microspheres foamed by light, the intensity of 20 to 600mJ / ㎠ for light having a wavelength of 200 to 400nm according to the method described in item (3) The first lamination film can be peeled off by irradiating with a foaming agent.
이와 달리, 상기 아크릴계 점착제는 Acetone(2-propanone), Isopropyl alcohol(Isopropanol), NMP(1-Methyl-2-pyrrolidon), DMSO(Dimethyl sulfoxide) 중 하나 이상의 용매에 용해되는 물성을 가지므로, 상기 용매 중 하나를 이용하여 상기 점착제(130A)를 용해시키는 것에 의해 제1 라미네이션 필름을 박리할 수 있다.In contrast, the acrylic pressure-sensitive adhesive has a physical property that is dissolved in at least one solvent of Acetone (2-propanone), Isopropyl alcohol (Isopropanol), NMP (1-Methyl-2-pyrrolidon), DMSO (dimethyl sulfoxide), the solvent The first lamination film may be peeled off by dissolving the pressure-sensitive adhesive 130A using one of them.
이어서, 화합물 반도체층(CS)의 제1 면 위에 전면 전극(20)을 형성한다(S180).Subsequently, the front electrode 20 is formed on the first surface of the compound semiconductor layer CS (S180).
전면 전극(20)은 전면 전극을 형성하고자 하는 영역에만 금속을 증착하여 형성하거나, 전면 콘택층(30) 위에 전면 전극 물질을 증착한 후 패터닝하여 형성할 수 있다.The front electrode 20 may be formed by depositing a metal only on a region where the front electrode is to be formed, or by patterning after depositing a front electrode material on the front contact layer 30.
계속하여, 전면 전극(20)을 마스크(mask)로 사용하여 상기 전면 전극(20)에에 의해 커버되지 않은 영역의 전면 콘택층(30)을 패터닝한 후, 제2 지지 핸들(170)과 제2 라미네이션 필름(160)을 제거하여 도 6에 도시한 화합물 반도체 태양전지를 제조한다.Subsequently, after patterning the front contact layer 30 in the region not covered by the front electrode 20 using the front electrode 20 as a mask, the second support handle 170 and the second support pattern 170 are patterned. The lamination film 160 is removed to manufacture the compound semiconductor solar cell shown in FIG. 6.
이상에서는 화합물 반도체 태양전지가 1개의 광 흡수층을 구비한 것을 예로 들어 설명하였지만, 광 흡수층은 복수 개로 형성될 수도 있다.In the above description, the compound semiconductor solar cell is provided with one light absorbing layer as an example, but a plurality of light absorbing layers may be formed.
이 경우, 하부 광 흡수층은 장파장 대역의 빛을 흡수하여 광전 변환하는 GaAs 화합물을 포함할 수 있고, 상부 광 흡수층은 단파장 대역의 빛을 흡수하여 광전 변환하는 GaInP 화합물을 포함할 수 있으며, 상부 광 흡수층과 하부 광 흡수층 사이에는 터널 정션층이 위치할 수 있다. In this case, the lower light absorbing layer may include a GaAs compound that absorbs light in a long wavelength band and photoelectrically converts the upper light absorbing layer may include a GaInP compound that absorbs light in a short wavelength band and photoelectrically converts the upper light absorbing layer. The tunnel junction layer may be positioned between the lower light absorbing layer and the lower light absorbing layer.
그리고 광 흡수층의 p형 반도체층과 n형 반도체층 사이에는 진성 반도체층이 더 형성될 수도 있다.An intrinsic semiconductor layer may be further formed between the p-type semiconductor layer and the n-type semiconductor layer of the light absorbing layer.
이하, 도 3 및 도 5를 참조하여 본 발명의 제2 실시예에 따른 제조 방법을 설명한다.Hereinafter, a manufacturing method according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 3 and 5.
제2 실시예를 설명함에 있어서, 전술한 제1 실시예와 동일한 구성요소에 대해서는 상세한 설명을 생략한다.In describing the second embodiment, detailed descriptions of the same components as those of the first embodiment will be omitted.
본 발명의 제조 방법은 크게, 모기판의 한쪽 면 위에 희생층을 형성하는 단계(S210); 상기 희생층 위에 화합물 반도체층을 형성하는 단계(S220); 상기 화합물 반도체층의 제1 면 위에, 화합물 반도체로 형성된 제1 보호층을 형성하는 단계(S230); 상기 제1 보호층 위에, 금속으로 형성된 제2 보호층을 증착하는 단계(S240); 상기 제2 보호층 위에 제1 라미네이션 필름을 부착하는 단계(S250); ELO 공정을 실시하여 상기 희생층을 제거함으로써, 상기 화합물 반도체층, 상기 제1 및 제2 보호층, 및 상기 제1 라미네이션 필름을 상기 모기판으로부터 분리하는 단계(S260); 상기 화합물 반도체층 위에 후면 전극을 형성하는 단계(S270); 상기 후면 전극 위에 제2 라미네이션 필름을 부착하는 단계(S280); 상기 제1 라미네이션 필름을 제거하는 단계(S290); 상기 제2 보호층을 제거하는 단계(S300); 상기 제1 보호층을 제거하는 단계(S310); 및 상기 화합물 반도체층 위에 전면 전극을 형성하는 단계(S320)를 포함한다.The manufacturing method of the present invention, largely, forming a sacrificial layer on one side of the mother substrate (S210); Forming a compound semiconductor layer on the sacrificial layer (S220); Forming a first passivation layer formed of a compound semiconductor on the first surface of the compound semiconductor layer (S230); Depositing a second protective layer formed of a metal on the first protective layer (S240); Attaching a first lamination film on the second protective layer (S250); Separating the compound semiconductor layer, the first and second protective layers, and the first lamination film from the mother substrate by performing an ELO process to remove the sacrificial layer (S260); Forming a rear electrode on the compound semiconductor layer (S270); Attaching a second lamination film on the back electrode (S280); Removing the first lamination film (S290); Removing the second protective layer (S300); Removing the first protective layer (S310); And forming a front electrode on the compound semiconductor layer (S320).
이때, 상기 화합물 반도체층 중에서 상기 제1 보호층과 직접 접촉하는 층은 GaAs로 형성하고, 상기 제1 보호층은 상기 GaAs를 제외한 다른 화합물 반도체로 형성한다.In this case, one of the compound semiconductor layers directly contacting the first protective layer is formed of GaAs, and the first protective layer is formed of another compound semiconductor except for the GaAs.
이에 대해 보다 상세히 설명하면, 모기판(110, mother substrate)의 한쪽 면에 희생층(120)을 형성하고(S210), 희생층(120) 위에 화합물 반도체층(CS)을 형성한다(S220).In more detail, the sacrificial layer 120 is formed on one surface of the mother substrate 110 (S210), and the compound semiconductor layer CS is formed on the sacrificial layer 120 (S220).
여기에서, 화합물 반도체층(CS)은 전술한 제1 실시예와 동일하게 레귤러 성장법에 의해 형성한다.Here, the compound semiconductor layer CS is formed by the regular growth method as in the first embodiment described above.
화합물 반도체층(CS)이 전면 콘택층(30)을 포함하는 경우, 전면 콘택층(30)은 윈도우층(10) 위에 전체적으로 형성될 수 있고, 오믹 콘택을 위해 전기 전도도가 우수한 GaAs로 형성된다.When the compound semiconductor layer CS includes the front contact layer 30, the front contact layer 30 may be formed entirely on the window layer 10, and may be formed of GaAs having excellent electrical conductivity for ohmic contact.
이어서, 상기 화합물 반도체층(CS) 위에, 화합물 반도체로 형성된 제1 보호층(140A)을 형성하고(S230), 제1 보호층(140A) 위에 금속으로 형성된 제2 보호층(140B)을 형성한다(S240). 따라서, 제1 보호층(140A)과 제2 보호층(140B)을 포함하는 보호층(140)이 형성된다.Subsequently, a first protective layer 140A formed of a compound semiconductor is formed on the compound semiconductor layer CS (S230), and a second protective layer 140B formed of metal is formed on the first protective layer 140A. (S240). Therefore, the protective layer 140 including the first protective layer 140A and the second protective layer 140B is formed.
제1 보호층(140A)은 GaAs를 제외한 다른 화합물 반도체, 바람직하게는 GaInP, AlInP, AlGaInP 중에서 선택된 어느 하나의 화합물 반도체로 형성한다.The first protective layer 140A is formed of any compound semiconductor except GaAs, preferably any one compound semiconductor selected from GaInP, AlInP, and AlGaInP.
이와 같이, 제1 보호층(140A)과 전면 콘택층(30)을 서로 다른 화합물 반도체로 형성하면, 복수 회의 식각 공정, 특히 ELO 공정을 실시하는 동안 화합물 반도체층(CS)과 보호층(140A, 140B)이 박리되는 현상을 효과적으로 방지할 수 있으며, 보호층(140A, 140B)을 제거하는 공정을 실시하는 동안 화합물 반도체층(CS)의 일부분이 식각되는 현상을 효과적으로 방지할 수 있다.As such, when the first passivation layer 140A and the front contact layer 30 are formed of different compound semiconductors, the compound semiconductor layer CS and the passivation layer 140A, It is possible to effectively prevent the peeling of the 140B, and to effectively prevent the etching of a portion of the compound semiconductor layer CS during the process of removing the protective layers 140A and 140B.
희생층(120)과 화합물 반도체층(CS) 및 제1 보호층(140A)은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 형성할 수 있으며, 레귤러 성장법에 의해 형성할 수 있다.The sacrificial layer 120 and the compound semiconductor layer CS and the first protective layer 140A may be a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy method, or any other suitable method for forming an epitaxial layer. It can form by a method and can be formed by a regular growth method.
제2 보호층(140B)은 내식각성이 우수한 구리로 형성된 제1 금속층(140B-1)과, 제1 금속층과(140B-1)는 다른 금속으로 형성된 제2 금속층(140B-2)으로 형성할 수 있다.The second protective layer 140B may be formed of the first metal layer 140B-1 formed of copper having excellent etching resistance, and the first metal layer 140B-1 may be formed of the second metal layer 140B-2 formed of another metal. Can be.
이때, 제2 금속층(140B-2)은 제1 금속층(140B-1)의 표면이 산화되는 것을 방지할 수 있는 금속, 또는 제1 금속층(140B-1)을 제거하기 위해 사용하는 식각 용액에 대한 내식각성을 갖는 물질, 예를 들면 은(Ag), 금(Au), 백금(Pt), 팔라듐(Pd), 니켈(Ni), 몰리브덴(Mo) 중에서 선택된 적어도 하나 또는 이의 합금으로 형성하는 것이 바람직하다.In this case, the second metal layer 140B-2 may be a metal that can prevent the surface of the first metal layer 140B-1 from being oxidized, or an etching solution used to remove the first metal layer 140B-1. It is preferable to form at least one selected from a material having corrosion resistance, for example, silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni) and molybdenum (Mo). Do.
도 5는 제1 보호층(140A)과 제2 보호층(140B)의 다양한 실시예를 나타내는 단면도를 도시한 것으로, 도시한 바와 같이, 제2 금속층(140B-2)은 제1 보호층(140A)과 제1 금속층(140B-1) 사이, 및 제1 금속층(140B-1)과 제1 라미네이션 필름(130) 사이 중 적어도 어느 한 위치에 형성할 수 있으며, 제1 금속층(140B-1)이 적어도 2개인 경우 2개의 제1 금속층(140B-1) 사이에 제2 금속층(140B-2)을 더 형성할 수 있다.5 is a cross-sectional view illustrating various embodiments of the first passivation layer 140A and the second passivation layer 140B, and as shown, the second metal layer 140B-2 includes the first passivation layer 140A. ) And the first metal layer 140B-1 and between the first metal layer 140B-1 and the first lamination film 130, and the first metal layer 140B-1 may be formed. In the case of at least two, the second metal layer 140B-2 may be further formed between the two first metal layers 140B-1.
제2 금속층(140B-2)을 제1 보호층(140A)과 제1 금속층(140B-1) 사이에 형성하면, 제2 금속층(140B-2)을 제거하기 위한 식각 공정 및 ELO 공정을 실시하는 동안 제1 보호층(140A)을 보호할 수 있으므로, 제1 보호층(140A)과 제2 보호층(140B), 특히, 제1 보호층(140A)과 제1 금속층(140B-1) 사이에 발생하는 박리 현상을 방지할 수 있다.When the second metal layer 140B-2 is formed between the first protective layer 140A and the first metal layer 140B-1, an etching process and an ELO process for removing the second metal layer 140B-2 may be performed. Since the first protective layer 140A can be protected during the first protective layer 140A, the first protective layer 140A and the second protective layer 140B, in particular, between the first protective layer 140A and the first metal layer 140B-1. The peeling phenomenon which arises can be prevented.
그리고 제2 금속층(140B-2)을 제1 금속층(140B-1)과 제1 라미네이션 필름(130) 사이에 형성하면, 제2 금속층(140B-2)은 제1 금속층(140B-1)의 표면에 산화막이 형성되는 것을 억제할 수 있으므로, 식각 공정, 특히 ELO 공정을 실시하는 동안 제1 라미네이션 필름(130)과 제2 보호층(140B) 사이에 발생하는 박리 현상을 방지할 수 있다.When the second metal layer 140B-2 is formed between the first metal layer 140B-1 and the first lamination film 130, the second metal layer 140B-2 is formed on the surface of the first metal layer 140B-1. Since the oxide film can be prevented from being formed, the peeling phenomenon occurring between the first lamination film 130 and the second protective layer 140B can be prevented during the etching process, especially the ELO process.
제2 보호층(140B)은 1㎛ 내지 10㎛의 두께로 형성할 수 있으며, 화합물 반도체 태양전지의 제조 공정 중에 화합물 반도체층(CS)을 지지하기 위해 제1 금속층(140B-1)의 두께를 제2 보호층(140B)의 두께의 80% 이상으로 형성할 수 있다.The second protective layer 140B may be formed to a thickness of 1 μm to 10 μm, and the thickness of the first metal layer 140B-1 may be used to support the compound semiconductor layer CS during the manufacturing process of the compound semiconductor solar cell. It may be formed to 80% or more of the thickness of the second protective layer (140B).
계속하여, 제2 보호층(140B) 위에 제1 라미네이션 필름(130)을 부착한다(S250).Subsequently, the first lamination film 130 is attached onto the second protective layer 140B (S250).
본 실시예의 제조 방법에 따르면, 제1 라미네이션 필름(130)은 화합물 반도체층(CS)에 직접 점착되지 않고, 화합물 반도체층(CS)을 지지하기 위한 보호층(140)에 직접 점착된다.According to the manufacturing method of the present embodiment, the first lamination film 130 is not directly adhered to the compound semiconductor layer CS, but directly adhered to the protective layer 140 for supporting the compound semiconductor layer CS.
따라서, 본 실시예의 제조 방법에 사용되는 제1 라미네이션 필름(130)의 기재 필름은 전술한 제1 실시예의 기재 필름에 비해 얇은 두께로 형성하는 것도 가능하다.Therefore, it is also possible to form the base film of the 1st lamination film 130 used for the manufacturing method of this embodiment with a thin thickness compared with the base film of 1st Example mentioned above.
이 경우, 기재 필름은 100㎛ 이하의 두께로 형성될 수 있으며, 도 4에서는 제1 라미네이션 필름이 전술한 제1 실시예의 제1 라미네이션 필름보다 얇은 두께로 형성된 경우를 도시하였다.In this case, the base film may be formed to a thickness of 100 μm or less, and FIG. 4 illustrates a case in which the first lamination film is formed to have a thickness thinner than that of the first lamination film of the first embodiment.
다음으로, ELO 공정을 실시하여 희생층(120)을 제거한다(S260).Next, the sacrificial layer 120 is removed by performing an ELO process (S260).
ELO 공정을 실시할 때, 제1 라미네이션 필름(130)과 제2 보호층(140B)간의 접착력이 제2 금속층(140B-2)에 의해 유지되므로, 제1 라미네이션 필름(130)은 제2 보호층(140B)으로부터 박리되지 않는다.When performing the ELO process, since the adhesive force between the first lamination film 130 and the second protective layer 140B is maintained by the second metal layer 140B-2, the first lamination film 130 is the second protective layer. It does not peel off from 140B.
도 7의 우측 사진은 제2 실시예의 제조 방법에 따라 ELO 공정을 실시한 후 제1 라미네이션 필름(140)과 제2 보호층(130B) 사이의 박리가 억제된 것을 보여주는 사진이다.7 is a photograph showing that peeling between the first lamination film 140 and the second protective layer 130B is suppressed after performing the ELO process according to the manufacturing method of the second embodiment.
그리고 도 7의 좌측 사진은 화합물 반도체층의 제1 면 위에 단일막 구조의 보호 금속층을 증착한 후 제1 라미네이션 필름을 부착한 상태에서 ELO 공정을 실시한 종래 예의 경우 제1 라미네이션 필름과 보호 금속층의 계면에서 박리가 발생된 것을 보여주는 사진이다.7 shows the interface between the first lamination film and the protective metal layer in the conventional example in which the ELO process is performed in a state in which a single-layered protective metal layer is deposited on the first surface of the compound semiconductor layer and the first lamination film is attached thereto. It is a photograph showing that peeling occurred.
이어서, 제1 라미네이션 필름(130)이 제2 보호층(140B)의 하부에 위치하도록 배치한 상태에서 제1 라미네이션 필름(130)의 후면 위에 제1 지지 핸들(150)을 부착하고, 화합물 반도체층(CS) 위에 후면 전극(60)을 형성한다(S270).Subsequently, in a state in which the first lamination film 130 is disposed below the second protective layer 140B, the first support handle 150 is attached on the rear surface of the first lamination film 130, and the compound semiconductor layer The back electrode 60 is formed on the CS (S270).
이어서, 후면 전극(60) 위에 제2 라미네이션 필름(160)을 부착하고(S280), 제2 라미네이션 필름(160) 위에 제2 지지 핸들(170)을 부착한 상태에서 제1 지지 핸들(150)이 상부를 향하도록 배치한다.Subsequently, the second lamination film 160 is attached to the rear electrode 60 (S280), and the first support handle 150 is attached to the second support handle 170 on the second lamination film 160. Place it face up.
이후, 제1 지지 핸들(150)과 제1 라미네이션 필름(130)을 제거하고(S290), 제2 보호층(140B)을 제거한다(S300).Thereafter, the first support handle 150 and the first lamination film 130 are removed (S290), and the second protective layer 140B is removed (S300).
이때, 제1 금속층(140B-1)은 수산화암모늄(NH 4OH)과 과산화수소(H 2O 2)을 혼합한 식각 용액을 사용하여 제거하고, 제2 금속층(140B-2)은 제1 금속층(140B-1)을 제거할 때 사용하는 식각 용액과는 다른 식각 용액, 예를 들어 요오드화칼륨(KI) 및 시안화칼륨(H 2O 2) 중 적어도 하나를 포함하는 식각 용액으로 제거한다.At this time, the first metal layer 140B-1 is removed using an etching solution in which ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) are mixed, and the second metal layer 140B-2 is removed from the first metal layer ( 140B-1) is removed with an etching solution other than the etching solution used for removing 140B-1), for example, an etching solution containing at least one of potassium iodide (KI) and potassium cyanide (H 2 O 2 ).
이러한 공정에 따르면, 제1 금속층(140B-1)은 제2 금속층(140B-2)을 제거하기 위해 사용되는 식각 용액에 대한 내식각성이 우수하므로, 제2 금속층(140B-2)을 제거하는 동안 제1 금속층(140B-1)은 제거되지 않는다.According to this process, since the first metal layer 140B-1 has excellent etching resistance to the etching solution used to remove the second metal layer 140B-2, while the second metal layer 140B-2 is removed. The first metal layer 140B-1 is not removed.
이때, 제2 금속층(140B-2)을 제1 보호층(140A)과 제1 금속층(140B-1) 사이에 형성한 경우에는 제1 금속층(140B-1)을 제거하기 위한 식각 공정 및 ELO 공정을 실시하는 동안 제1 보호층(140A)이 제2 금속층(140B-2)에 의해 보호되므로, 제1 보호층(140A)과 제2 보호층(140B) 사이에 발생하는 박리 현상이 방지된다.In this case, when the second metal layer 140B-2 is formed between the first protective layer 140A and the first metal layer 140B-1, an etching process and an ELO process for removing the first metal layer 140B-1 are performed. Since the first protective layer 140A is protected by the second metal layer 140B-2, the peeling phenomenon occurring between the first protective layer 140A and the second protective layer 140B is prevented.
또한, 제2 금속층(140B-2)을 제1 금속층(140B-1)과 제1 라미네이션 필름(130) 사이에 형성한 경우에는 제1 금속층(140B-1)의 표면에 산화막이 형성되는 것이 제2 금속층(140B-2)에 의해 억제되므로, 식각 공정, 특히 ELO 공정을 실시하는 동안 제2 보호층(140B)과 제1 라미네이션 필름(130) 사이에 발생하는 박리 현상이 방지된다.In addition, when the second metal layer 140B-2 is formed between the first metal layer 140B-1 and the first lamination film 130, an oxide film is formed on the surface of the first metal layer 140B-1. Since it is suppressed by the 2 metal layer 140B-2, the peeling phenomenon which arises between the 2nd protective layer 140B and the 1st lamination film 130 during an etching process, especially an ELO process is prevented.
계속하여, 제1 보호층(140A)을 제거한다(S310).Subsequently, the first protective layer 140A is removed (S310).
제1 보호층(140A)은 GaAs로 형성된 전면 콘택층이 내식각성을 갖는 염산(HCL)을 포함하는 식각 용액으로 제거할 수 있다.The first passivation layer 140A may be removed using an etching solution including hydrochloric acid (HCL) in which the front contact layer formed of GaAs has etching resistance.
이어서, 화합물 반도체층(CS)의 제1 면 위에 전면 전극(20)을 형성한다(S320).Next, the front electrode 20 is formed on the first surface of the compound semiconductor layer CS (S320).
본 발명은 다양한 변경을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변경, 균등물 내지 대체물을 포함하는 것으로 이해될 수 있다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. It is not intended to limit the invention to the specific embodiments, it can be understood to include all changes, equivalents, and substitutes included in the spirit and scope of the present invention.
본 발명을 설명함에 있어서 제1, 제2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되지 않을 수 있다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. In describing the present invention, terms such as first and second may be used to describe various components, but the components may not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component.
예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소도 제1 구성요소로 명명될 수 있다.For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.
"및/또는" 이라는 용어는 복수의 관련된 기재된 항목들의 조합 또는 복수의 관련된 기재된 항목들 중의 어느 항목을 포함할 수 있다.The term "and / or" may include a combination of a plurality of related items or any of a plurality of related items.
어떤 구성요소가 다른 구성요소에 "연결되어" 있다거나 "결합되어" 있다고 언급되는 경우는, 그 다른 구성요소에 직접적으로 연결되어 있거나 또는 결합되어 있을 수도 있지만, 중간에 다른 구성요소가 존재할 수도 있다고 이해될 수 있다.When a component is said to be "connected" or "coupled" to another component, it may be directly connected to or coupled to the other component, but other components may be present in the middle. Can be understood.
반면에, 어떤 구성요소가 다른 구성요소에 "직접 연결되어" 있다거나 "직접 결합되어" 있다고 언급된 때에는, 중간에 다른 구성요소가 존재하지 않는 것으로 이해될 수 있다.On the other hand, when a component is referred to as being "directly connected" or "directly coupled" to another component, it may be understood that there is no other component in between.
본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함할 수 있다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions may include plural expressions unless the context clearly indicates otherwise.
본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것으로서, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해될 수 있다.In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It may be understood that the present invention does not exclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or a combination thereof.
도면에서 여러 층 및 영역을 명확하게 표현하기 위하여 두께를 확대하여 나타내었다. 층, 막, 영역, 판 등의 부분이 다른 부분 "위에" 있다고 할 때, 이는 다른 부분 "바로 위에" 있는 경우뿐 아니라 그 중간에 다른 부분이 있는 경우도 포함한다. 반대로 어떤 부분이 다른 부분 "바로 위에" 있다고 할 때에는 중간에 다른 부분이 없는 것을 뜻한다.In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가질 수 있다. Unless defined otherwise, all terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art.
일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 가지는 것으로 해석될 수 있으며, 본 출원에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않을 수 있다.Terms such as those defined in the commonly used dictionaries may be interpreted as having meanings consistent with the meanings in the context of the related art, and shall be interpreted in ideal or excessively formal meanings unless expressly defined in the present application. It may not be.
아울러, 이하의 실시예는 당 업계에서 평균적인 지식을 가진 자에게 보다 완전하게 설명하기 위해서 제공되는 것으로서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있다.In addition, the following embodiments are provided to more fully describe those skilled in the art, and the shape and size of the elements in the drawings may be exaggerated for clarity.
이하, 첨부도면을 참조하여 본 발명의 실시예에 따른 지지 핸들 및 이를 이용한 화합물 반도체 태양전지의 제조 방법을 설명한다.Hereinafter, a support handle and a method of manufacturing a compound semiconductor solar cell using the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.
도 1은 화합물 반도체 태양전지의 사시도이고, 도 2는 본 발명의 실시예에 따른 지지 핸들의 단면도이며, 도 3은 도 2에 도시한 지지 핸들을 이용한 화합물 반도체 태양전지의 제조 방법을 나타내는 공정도이다.1 is a perspective view of a compound semiconductor solar cell, FIG. 2 is a cross-sectional view of a support handle according to an embodiment of the present invention, and FIG. 3 is a process diagram showing a method of manufacturing a compound semiconductor solar cell using the support handle shown in FIG. 2. .
먼저, 화합물 반도체 태양전지에 대해 도 1을 참조하여 설명한다.First, a compound semiconductor solar cell will be described with reference to FIG. 1.
화합물 반도체 태양전지는 광 흡수층(PV), 광 흡수층(PV)의 전면(front surface) 위에 위치하는 윈도우층(10), 윈도우층(10)의 전면 위에 위치하는 전면 전극(20), 윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30), 윈도우층(10) 위에 위치하는 반사 방지막(40), 광 흡수층(PV)의 후면 위에 위치하는 후면 콘택층(50) 및 후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)을 포함할 수 있다. The compound semiconductor solar cell includes a light absorbing layer PV, a window layer 10 positioned on the front surface of the light absorbing layer PV, a front electrode 20 positioned on the front surface of the window layer 10, and a window layer ( 10) the front contact layer 30 positioned between the front electrode 20, the antireflection film 40 positioned on the window layer 10, the rear contact layer 50 positioned on the rear surface of the light absorbing layer PV, and The rear electrode 60 may include a rear electrode 60 positioned on the rear surface of the rear contact layer 50.
여기서, 반사 방지막(40), 윈도우층(10), 전면 콘택층(30) 및 후면 콘택층(50) 중 적어도 하나는 생략될 수도 있지만, 도 1에 도시된 바와 같이 상기 층들이 구비된 경우를 일례로 설명한다.Here, at least one of the anti-reflection film 40, the window layer 10, the front contact layer 30, and the rear contact layer 50 may be omitted, but as shown in FIG. It demonstrates as an example.
광 흡수층(PV)은 III-VI족 반도체 화합물을 포함하여 형성될 수 있다. 일례로, 갈륨(Ga), 인듐(In) 및 인(P)이 함유된 GaInP 화합물 또는 갈륨(Ga)과 비소(As)가 함유된 GaAs 화합물을 포함하여 형성될 수 있다.The light absorbing layer PV may be formed including a III-VI semiconductor compound. For example, GaInP compounds containing gallium (Ga), indium (In) and phosphorus (P) or GaAs compounds containing gallium (Ga) and arsenic (As) may be formed.
이하에서는 광 흡수층(PV)이 GaAs 화합물을 포함하는 것을 예로 들어 설명한다.Hereinafter, the light absorbing layer (PV) will be described with an example containing a GaAs compound.
광 흡수층(PV)은 제1 도전성 타입의 불순물, 한 예로 p형 불순물이 도핑되는 p형 반도체층(PV-p)과, 제2 도전성 타입의 불순물, 한 예로 n형 불순물이 도핑되는 n형 반도체층(PV-n)을 포함할 수 있다.The light absorption layer PV is a p-type semiconductor layer PV-p doped with an impurity of a first conductivity type, for example, a p-type impurity, and an n-type semiconductor doped with an impurity of a second conductivity type, for example, an n-type impurity. Layer (PV-n).
그리고 도시하지는 않았지만, 광 흡수층(PV)은 p형 반도체층(PV-p)의 후면에 위치하는 후면 전계층을 더 포함할 수 있다.Although not shown, the light absorbing layer PV may further include a rear electric field layer disposed at the rear of the p-type semiconductor layer PV-p.
p형 반도체층(PV-p)은 전술한 화합물 반도체에 제1 도전성 타입, 즉 p형의 불순물이 도핑되어 형성되고, n형 반도체층(PV-n)은 전술한 화합물 반도체에 제2 도전성 타입, 즉 n형의 불순물이 도핑되어 형성될 수 있다.The p-type semiconductor layer PV-p is formed by doping the compound semiconductor described above with a first conductivity type, that is, a p-type impurity, and the n-type semiconductor layer PV-n is formed by the second compound semiconductor in the aforementioned compound semiconductor. That is, n-type impurities may be formed by doping.
여기에서, p형 불순물은 탄소, 마그네슘, 아연 또는 이들의 조합으로부터 선택될 수 있고, n형 불순물은 실리콘, 셀레늄, 텔루륨 또는 이들의 조합으로부터 선택될 수 있다.Here, the p-type impurity may be selected from carbon, magnesium, zinc or a combination thereof, and the n-type impurity may be selected from silicon, selenium, tellurium or a combination thereof.
n형 반도체층(PV-n)은 전면 전극(20)에 인접한 영역에 위치할 수 있으며, p형 반도체층(PV-p)은 n형 반도체층(PV-n) 바로 아래에서 후면 전극(60)에 인접한 영역에 위치할 수 있다.The n-type semiconductor layer PV-n may be located in an area adjacent to the front electrode 20, and the p-type semiconductor layer PV-p may be disposed directly below the n-type semiconductor layer PV-n. It may be located in an area adjacent to).
즉, n형 반도체층(PV-n)과 전면 전극(20) 사이의 간격은 p형 반도체층(PV-p)과 전면 전극 사이의 간격보다 작으며, n형 반도체층(PV-n)과 후면 전극(60) 사이의 간격은 p형 반도체층(PV-p)과 후면 전극 사이의 간격보다 크다.That is, the distance between the n-type semiconductor layer PV-n and the front electrode 20 is smaller than the distance between the p-type semiconductor layer PV-p and the front electrode, and the n-type semiconductor layer PV-n The spacing between the back electrodes 60 is greater than the spacing between the p-type semiconductor layer PV-p and the back electrodes.
이에 따라, 광 흡수층(PV)의 내부에는 p형 반도체층(PV-p)과 n형 반도체층(PV-n)이 접합된 p-n 접합이 형성되므로, 광 흡수층(PV)에 입사된 빛에 의해 생성된 전자-정공 쌍은 광 흡수층(PV)의 p-n 접합에 의해 형성된 내부 전위차에 의해 전자와 정공으로 분리되어 전자는 n형 쪽으로 이동하고, 정공은 p형 쪽으로 이동한다.As a result, a pn junction in which the p-type semiconductor layer PV-p and the n-type semiconductor layer PV-n are bonded to each other is formed in the light absorbing layer PV. The generated electron-hole pair is separated into electrons and holes by the internal potential difference formed by the pn junction of the light absorbing layer PV so that the electrons move toward the n-type and the holes move toward the p-type.
따라서, 광 흡수층(PV)에서 생성된 정공은 후면 콘택층(50)을 통하여 후면 전극(60)으로 이동하고, 광 흡수층(PV)에서 생성된 전자는 윈도우층(10)과 전면 콘택층(30)을 통해 전면 전극(20)으로 이동한다.Accordingly, holes generated in the light absorbing layer PV move to the back electrode 60 through the back contact layer 50, and electrons generated in the light absorbing layer PV are transferred to the window layer 10 and the front contact layer 30. It moves to the front electrode 20 through).
이와 달리, p형 반도체층(PV-p)이 전면 전극(20)에 인접한 영역에 위치하고 n형 반도체층(PV-n)이 p형 반도체층(PV-p) 바로 아래에서 후면 전극(60)에 인접한 영역에 위치하는 경우, 광 흡수층(PV)에서 생성된 정공은 전면 콘택층(30)을 통하여 전면 전극(20)으로 이동하고, 광 흡수층(PV)에서 생성된 전자는 후면 콘택층(50)을 통하여 후면 전극(60)으로 이동한다.In contrast, the p-type semiconductor layer PV-p is positioned in the region adjacent to the front electrode 20 and the n-type semiconductor layer PV-n is directly below the p-type semiconductor layer PV-p. When located in the region adjacent to the hole generated in the light absorbing layer (PV) is moved to the front electrode 20 through the front contact layer 30, the electrons generated in the light absorbing layer (PV) is the back contact layer 50 It moves to the rear electrode 60 through).
광 흡수층(PV)이 후면 전계층을 더 포함하는 경우, 후면 전계층은 직접 접촉하는 상부의 층, 즉 n형 반도체층(PV-n) 또는 p형 반도체층(PV-p)과 동일한 도전성 타입을 가지며, 윈도우층(10)과 동일한 물질로 형성될 수 있다.In the case where the light absorbing layer PV further includes a rear electric field layer, the rear electric field layer is of the same conductive type as the upper layer in direct contact, that is, the n-type semiconductor layer PV-n or the p-type semiconductor layer PV-p. It may be formed of the same material as the window layer 10.
그리고 후면 전계층은 전면 전극 쪽으로 이동해야 할 전하(정공 또는 전자)가 후면 전극 쪽으로 이동하는 것을 효과적으로 차단(blocking)하기 위해, 직접 접촉하는 상부의 층, 즉 n형 반도체층(PV-n) 또는 p형 반도체층(PV-p)의 후면에 전체적으로(entirely) 형성된다.And the rear electric field layer is an upper layer in direct contact, that is, an n-type semiconductor layer (PV-n) or in order to effectively block the movement of charges (holes or electrons) to be moved toward the front electrode toward the rear electrode. The back surface of the p-type semiconductor layer PV-p is entirely formed.
즉, 도 1에 도시한 화합물 반도체 태양전지에 있어서, p형 반도체층(PV-p)의 후면에 후면 전계층이 형성된 경우, 후면 전계층은 전자가 후면 전극 쪽으로 이동하는 것을 차단하는 작용을 하며, 후면 전극 쪽으로 전자가 이동하는 것을 효과적으로 차단하기 위해, 후면 전계층은 p형 반도체층(PV-p)의 후면 전체에 위치한다.That is, in the compound semiconductor solar cell illustrated in FIG. 1, when the rear field layer is formed on the rear side of the p-type semiconductor layer PV-p, the rear field layer serves to block electrons from moving toward the rear electrode. In order to effectively block electrons from moving toward the rear electrode, the rear electric field layer is located on the entire rear surface of the p-type semiconductor layer PV-p.
이러한 구성의 광 흡수층(PV)은 MOCVD(Metal Organic Chemical Vapor Deposition) 방법, MBE(Molecular Beam Epitaxy) 방법 또는 에피택셜층을 형성하기 위한 임의의 다른 적절한 방법에 의해 모기판(mother substrate)으로부터 제조할 수 있다.The light absorbing layer (PV) of this configuration can be prepared from a mother substrate by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method or any other suitable method for forming an epitaxial layer. Can be.
p형 반도체층(PV-p)과 n형 반도체층(PV-n)은 서로 동일한 밴드갭을 갖는 서로 동일한 물질로 이루어질 수 있고(동종 접합), 이와 달리, 서로 다른 밴드갭을 갖는 서로 다른 물질로 이루어질 수 있다(이종 접합).The p-type semiconductor layer PV-p and the n-type semiconductor layer PV-n may be made of the same material having the same bandgap (homogeneous junction), and different materials having different bandgaps may be different. It may consist of (heterojunction).
윈도우층(10)은 광 흡수층(PV)과 전면 전극(20) 사이에 형성될 수 있으며, III-VI족 반도체 화합물에 제2 도전성 타입, 즉 n형의 불순물을 도핑하여 형성할 수 있다.The window layer 10 may be formed between the light absorbing layer PV and the front electrode 20, and may be formed by doping a III-VI group semiconductor compound with a second conductivity type, that is, an n-type impurity.
그러나, p형 반도체층(PV-p)이 n형 반도체층(PV-n) 위에 위치하고 윈도우층(10)이 p형 반도체층(PV-p) 위에 위치하는 경우, 윈도우층(10)은 제1 도전성 타입, 즉 p형의 불순물을 포함할 수 있다.However, when the p-type semiconductor layer PV-p is positioned on the n-type semiconductor layer PV-n and the window layer 10 is positioned on the p-type semiconductor layer PV-p, the window layer 10 is formed. It may include one conductivity type, that is, p-type impurities.
하지만 윈도우층(10)은 n형 또는 p형의 불순물을 포함하지 않을 수도 있다.However, the window layer 10 may not include n-type or p-type impurities.
윈도우층(10)은 광 흡수층(PV)의 전면(front surface)을 패시베이션(passivation)하는 기능을 한다. 따라서, 광 흡수층(PV)의 표면으로 캐리어(전자나 정공)가 이동할 경우, 윈도우층(10)은 캐리어가 광 흡수층(PV)의 표면에서 재결합하는 것을 방지할 수 있다.The window layer 10 functions to passivate the front surface of the light absorbing layer PV. Therefore, when the carrier (electrons or holes) move to the surface of the light absorbing layer PV, the window layer 10 can prevent the carrier from recombining at the surface of the light absorbing layer PV.
아울러, 윈도우층(10)은 광 흡수층(PV)의 전면, 즉 광 입사면에 배치되므로, 광 흡수층(PV)으로 입사되는 빛을 거의 흡수하지 않도록 하기 위하여 광 흡수층(PV)의 에너지 밴드갭보다 높은 에너지 밴드갭을 가질 수 있다.In addition, since the window layer 10 is disposed on the entire surface of the light absorbing layer PV, that is, on the light incident surface, the window layer 10 may be disposed in an amount greater than that of the energy band gap of the light absorbing layer PV so as to hardly absorb light incident on the light absorbing layer PV. It can have a high energy bandgap.
윈도우층(10)의 에너지 밴드갭을 광 흡수층의 에너지 밴드갭보다 높게 형성하기 위해, 윈도우층(10)은 알루미늄(Al)을 더 함유할 수 있다.In order to form an energy band gap of the window layer 10 higher than that of the light absorbing layer, the window layer 10 may further contain aluminum (Al).
반사 방지막(40)은 윈도우층(10)의 전면 위 중에서 전면 전극(20) 및/또는 전면 콘택층(30)이 위치하는 영역을 제외한 나머지 영역에 위치할 수 있다.The anti-reflection film 40 may be located on the remaining area of the window layer 10 except for the area where the front electrode 20 and / or the front contact layer 30 is located.
이와 달리, 반사 방지막(40)은 노출된 윈도우층(10) 뿐만 아니라, 전면 콘택층(30) 및 전면 전극(20) 위에 배치될 수도 있다.Alternatively, the anti-reflection film 40 may be disposed on the front contact layer 30 and the front electrode 20 as well as the exposed window layer 10.
이 경우, 화합물 반도체 태양전지는 복수의 전면 전극(20)을 물리적으로 연결하는 버스바 전극을 더 구비할 수 있으며, 버스바 전극은 반사 방지막(40)에 의해 덮여지지 않고 외부로 노출될 수 있다.In this case, the compound semiconductor solar cell may further include a bus bar electrode that physically connects the plurality of front electrodes 20, and the bus bar electrode may be exposed to the outside without being covered by the anti-reflection film 40. .
반사 방지막(40)은 불화마그네슘, 황화아연, 티타늄 옥사이드, 실리콘 옥사이드, 이들의 유도체 또는 이들의 조합을 포함할 수 있다.The anti-reflection film 40 may include magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or a combination thereof.
전면 전극(20)은 제1 방향(X-X')으로 길게 연장되어 형성될 수 있으며, 제1 방향과 직교하는 제2 방향(Y-Y')을 따라 복수개가 일정한 간격으로 이격될 수 있다.The front electrode 20 may be formed to extend in the first direction X-X ', and the plurality of front electrodes 20 may be spaced apart at regular intervals along the second direction Y-Y' perpendicular to the first direction. .
이러한 구성의 전면 전극(20)은 전기 전도성 물질을 포함하여 형성될 수 있으며, 일례로 금속인 금(Au), 게르마늄(Ge), 니켈(Ni) 중 적어도 하나를 포함하여 형성될 수 있다.The front electrode 20 having such a configuration may be formed by including an electrically conductive material. For example, the front electrode 20 may include at least one of gold (Au), germanium (Ge), and nickel (Ni).
윈도우층(10)과 전면 전극(20) 사이에 위치하는 전면 콘택층(30)은 III-VI족 반도체 화합물에 윈도우층(10)의 불순물 도핑농도보다 높은 도핑농도로 제2 불순물을 도핑하여 형성할 수 있다.The front contact layer 30 positioned between the window layer 10 and the front electrode 20 is formed by doping the group III-VI semiconductor compound with a second impurity at a doping concentration higher than the impurity doping concentration of the window layer 10. can do.
전면 콘택층(30)은 윈도우층(10)과 전면 전극(20) 간에 오믹 콘택(ohmic contact)을 형성한다. 즉, 전면 전극(20)이 윈도우층(10)에 바로 접촉하는 경우, 윈도우층(10)의 불순물 도핑농도가 낮음으로 인해 전면 전극(20)과 광 흡수층(PV) 간의 오믹 콘택이 잘 형성되지 않는다. 따라서, 윈도우층(10)으로 이동한 캐리어가 전면 전극(20)으로 쉽게 이동하지 못하고 소멸될 수 있다.The front contact layer 30 forms an ohmic contact between the window layer 10 and the front electrode 20. That is, when the front electrode 20 directly contacts the window layer 10, the ohmic contact between the front electrode 20 and the light absorbing layer PV may not be well formed due to the low impurity doping concentration of the window layer 10. Do not. Therefore, the carrier moved to the window layer 10 may disappear easily without moving to the front electrode 20.
그러나, 전면 전극(20)과 윈도우층(10) 사이에 전면 콘택층(30)이 형성된 경우, 전면 전극(20)과 오믹 콘택을 형성하는 전면 콘택층(30)에 의해 캐리어의 이동이 원활하게 이루어져 화합물 반도체 태양전지의 단락전류밀도(Jsc)가 증가한다. 이에 따라 태양전지의 효율을 보다 향상시킬 수 있다.However, when the front contact layer 30 is formed between the front electrode 20 and the window layer 10, the carrier is smoothly moved by the front contact layer 30 forming the ohmic contact with the front electrode 20. As a result, the short-circuit current density (Jsc) of the compound semiconductor solar cell increases. Accordingly, the efficiency of the solar cell can be further improved.
전면 전극(20)과 오믹 콘택을 형성하기 위하여, 전면 콘택층(30)에 도핑된 제2 불순물의 도핑농도는 윈도우층(10)에 도핑된 제2 불순물의 도핑농도보다 더 높을 수 있다.In order to form an ohmic contact with the front electrode 20, the doping concentration of the second impurity doped in the front contact layer 30 may be higher than the doping concentration of the second impurity doped in the window layer 10.
전면 콘택층(30)은 전면 전극(20)과 동일한 형상으로 형성될 수 있다.The front contact layer 30 may be formed in the same shape as the front electrode 20.
광 흡수층(PV)의 p형 반도체층(PV-p)의 후면, 광 흡수층(PV)이 후면 전계층을 구비하는 경우에는 후면 전계층의 후면 위에 위치하는 후면 콘택층(50)은 광 흡수층(PV) 또는 후면 전계층의 후면에 전체적으로 위치하며, III-VI족 반도체 화합물에 제1 도전성 타입의 불순물을 p형 반도체층(PV-p)보다 높은 도핑농도로 도핑하여 형성할 수 있다.When the back of the p-type semiconductor layer PV-p of the light absorbing layer PV and the light absorbing layer PV have a rear electric field layer, the rear contact layer 50 located on the rear of the rear electric field layer may be a light absorbing layer ( PV) or the backside of the backside electric field layer as a whole, and may be formed by doping the III-VI semiconductor compound with a higher doping concentration than the p-type semiconductor layer (PV-p).
이러한 후면 콘택층(50)은 후면 전극(160)과 오믹 콘택을 형성할 수 있어, 화합물 반도체 태양전지의 단락전류밀도(Jsc)를 보다 향상시킬 수 있다. 이에 따라 태양전지의 효율을 보다 향상시킬 수 있다.The back contact layer 50 may form an ohmic contact with the back electrode 160, thereby further improving the short circuit current density Jsc of the compound semiconductor solar cell. Accordingly, the efficiency of the solar cell can be further improved.
전면 콘택층(30)의 두께와 후면 콘택층(50)의 두께는 각각 100nm 내지 300nm의 두께로 형성될 수 있으며, 일례로, 전면 콘택층(30)은 100nm의 두께로 형성되고 후면 콘택층(50)은 300nm의 두께로 형성될 수 있다.The thickness of the front contact layer 30 and the thickness of the back contact layer 50 may be formed to a thickness of 100nm to 300nm, respectively. For example, the front contact layer 30 is formed to a thickness of 100nm and the back contact layer ( 50) may be formed to a thickness of 300 nm.
그리고 후면 콘택층(50)의 후면 위에 위치하는 후면 전극(60)은 전면 전극(20)과는 다르게 후면 콘택층(50)의 후면에 전체적으로 위치하는 시트(Sheet) 형상의 도전체로 형성될 수 있다. 즉, 후면 전극(60)은 후면 콘택층(50)의 후면 전체에 위치하는 면 전극(sheet electrode)이라고도 말할 수 있다.In addition, unlike the front electrode 20, the rear electrode 60 positioned on the rear surface of the rear contact layer 50 may be formed of a sheet-shaped conductor positioned entirely on the rear surface of the rear contact layer 50. . That is, the rear electrode 60 may also be referred to as a sheet electrode positioned on the entire rear surface of the rear contact layer 50.
이때, 후면 전극(60)은 광 흡수층(PV)과 동일한 평면적으로 형성될 수 있으며, 금(Au), 백금(Pt), 티타늄(Ti), 텅스텐(W), 규소(Si), 니켈(Ni), 마그네슘(Mg), 팔라듐(Pd), 구리(Cu), 및 게르마늄(Ge) 중에서 선택된 적어도 어느 한 물질을 포함하는 단일막 또는 다중막으로 형성될 수 있고, 후면 전극을 형성하는 물질은 후면 콘택층의 도전성 타입에 따라 적절하게 선택될 수 있다.In this case, the rear electrode 60 may be formed in the same plane as the light absorbing layer PV, and may include gold (Au), platinum (Pt), titanium (Ti), tungsten (W), silicon (Si), and nickel (Ni). ), Magnesium (Mg), palladium (Pd), copper (Cu), and germanium (Ge) may be formed as a single film or a multi-layer including at least one material selected from, and the material forming the rear electrode is It may be appropriately selected depending on the conductivity type of the contact layer.
한 예로, 후면 콘택층이 p형 불순물을 함유하는 경우, 후면 전극(60)은 금(Au), 백금(Pt)/티타늄(Ti), 텅스텐-규소 합금(WSi), 및 규소(Si)/니켈(Ni)/마그네슘(Mg)/니켈(Ni) 중에서 선택된 어느 하나로 형성될 수 있으며, 바람직하게는 p형 후면 콘택층과의 접촉 저항이 낮은 금(Au)으로 형성될 수 있다.For example, when the back contact layer contains a p-type impurity, the back electrode 60 is made of gold (Au), platinum (Pt) / titanium (Ti), tungsten-silicon alloy (WSi), and silicon (Si) / It may be formed of any one selected from nickel (Ni) / magnesium (Mg) / nickel (Ni), and preferably, may be formed of gold (Au) having low contact resistance with a p-type back contact layer.
그리고, 후면 콘택층(50)이 n형 불순물을 함유하는 경우, 후면 전극(60)은 팔라듐(Pd)/금(Au), 구리(Cu)/게르마늄(Ge), 니켈(Ni)/게르마늄-금의 합금(GeAu)/니켈(Ni), 및 금(Au)/티타늄(Ti) 중에서 선택된 어느 하나로 형성될 수 있으며, 바람직하게는 p형 후면 콘택층과의 접촉 저항이 낮은 팔라듐(Pd)/금(Au)으로 형성될 수 있다.In addition, when the back contact layer 50 contains n-type impurities, the back electrode 60 may include palladium (Pd) / gold (Au), copper (Cu) / germanium (Ge), and nickel (Ni) / germanium- It may be formed of any one selected from alloys of gold (GeAu) / nickel (Ni) and gold (Au) / titanium (Ti), and preferably palladium (Pd) / with low contact resistance with a p-type back contact layer. It may be formed of gold (Au).
하지만, 상기 후면 전극을 형성하는 물질은 상기 물질들 중에서 적절하게 선택될 수 있으며, 특히, 후면 콘택층과의 접촉 저항이 낮은 물질들 중에서 적절하게 선택될 수 있다.However, the material forming the back electrode may be appropriately selected from the above materials, and particularly, may be appropriately selected from materials having low contact resistance with the back contact layer.
이상에서는 화합물 반도체 태양전지가 1개의 광 흡수층을 구비한 것을 예로 들어 설명하였지만, 광 흡수층은 복수 개로 형성될 수도 있다.In the above description, the compound semiconductor solar cell is provided with one light absorbing layer as an example, but a plurality of light absorbing layers may be formed.
이 경우, 하부 광 흡수층(미들 셀 및/또는 바텀 셀의 광 흡수층)은 장파장 대역의 빛을 흡수하여 광전 변환하는 GaAs 화합물을 포함할 수 있고, 상부 광 흡수층(탑 셀의 광 흡수층)은 단파장 대역의 빛을 흡수하여 광전 변환하는 GaInP 화합물을 포함할 수 있으며, 상부 광 흡수층과 하부 광 흡수층 사이에는 터널 정션층이 위치할 수 있다. In this case, the lower light absorbing layer (light absorbing layer of the middle cell and / or the bottom cell) may include a GaAs compound that absorbs light of the long wavelength band and photoelectrically converts the light absorbing layer (light absorbing layer of the top cell). It may include a GaInP compound that absorbs light of the photoelectric conversion, the tunnel junction layer may be located between the upper light absorbing layer and the lower light absorbing layer.
그리고 광 흡수층의 p형 반도체층과 n형 반도체층 사이에는 진성 반도체층이 더 형성될 수도 있다.An intrinsic semiconductor layer may be further formed between the p-type semiconductor layer and the n-type semiconductor layer of the light absorbing layer.
이하, 상기한 구성의 화합물 반도체 태양전지를 제조하는 방법 및 이 방법에 사용되는 지지 핸들에 대해 설명한다.Hereinafter, the method of manufacturing the compound semiconductor solar cell of the above-mentioned structure, and the support handle used for this method are demonstrated.
화합물 반도체 태양전지의 제조 방법은 크게, 모기판의 한쪽 면 위에 희생층을 형성하는 단계, 상기 희생층 위에 화합물 반도체층을 형성하는 단계, 화합물 화합물 반도체층 위에 ELO(Epitaxial Lift Off) 필름을 부착하는 단계, ELO 공정을 실시하는 단계, ELO 필름에 지지 핸들을 부착하는 단계, 및 지지 핸들을 이용하여 화합물 반도체층을 모기판과 분리하는 단계를 포함할 수 있다.A method of manufacturing a compound semiconductor solar cell is largely provided by forming a sacrificial layer on one side of a mother substrate, forming a compound semiconductor layer on the sacrificial layer, and attaching an epitaxial lift off (ELO) film on the compound compound semiconductor layer. The method may include performing an ELO process, attaching a support handle to the ELO film, and separating the compound semiconductor layer from the mother substrate using the support handle.
이에 대해 구체적으로 설명하면, 먼저, 광 흡수층(PV)이 형성되는 적절한 격자 구조를 제공하기 위한 베이스로 작용하는 모기판(110, mother substrate), 즉 GaAs 웨이퍼 또는 Ge 웨이퍼의 한쪽 면에 희생층(120)을 형성하고, 희생층(120) 위에 화합물 반도체층(CS)을 형성하며, 화합물 반도체층(CS) 위에 ELO 필름(130)을 부착한다.Specifically, first, a sacrificial layer (1) on one side of a mother substrate (ie, a GaAs wafer or a Ge wafer) serving as a base for providing a suitable lattice structure in which a light absorbing layer (PV) is formed is described. 120, a compound semiconductor layer CS is formed on the sacrificial layer 120, and the ELO film 130 is attached to the compound semiconductor layer CS.
여기에서, 화합물 반도체층(CS)은 후면 콘택층(50), 광 흡수층(PV), 윈도우층(10) 및 전면 콘택층(30)을 포함할 수 있다.The compound semiconductor layer CS may include a back contact layer 50, a light absorbing layer PV, a window layer 10, and a front contact layer 30.
화합물 반도체층(CS)이 전면 콘택층(30)을 포함하는 경우, 전면 콘택층(30)은 윈도우층(10) 위에 전체적으로 형성될 수 있고, 오믹 콘택을 위해 전기 전도도가 우수한 GaAs로 형성될 수 있다.When the compound semiconductor layer CS includes the front contact layer 30, the front contact layer 30 may be formed entirely on the window layer 10, and may be formed of GaAs having excellent electrical conductivity for ohmic contact. have.
ELO 필름(130)은 ELO 공정에서 불산(HF)을 이용하여 희생층(120)을 제거할 때, 화합물 반도체층(CS)을 지지함과 아울러 화합물 반도체층(CS)을 지지한다.The ELO film 130 supports the compound semiconductor layer CS and the compound semiconductor layer CS when the sacrificial layer 120 is removed using hydrofluoric acid (HF) in the ELO process.
화합물 반도체층(CS) 위에 ELO 필름(130)을 부착한 후, ELO 공정을 실시한다.After attaching the ELO film 130 on the compound semiconductor layer CS, an ELO process is performed.
인버스(inverse) 성장법을 이용하여 화합물 반도체층(CS)을 형성한 경우, ELO 공정을 실시한 후에는 화합물 반도체층(CS)의 한쪽 면(도 4의 경우 하부면)에 전면 전극을 형성하고, 화합물 반도체층(CS)의 다른 쪽 면(도 4의 경우 상부면)에 후면 전극을 형성하는 것에 의해 도 1에 도시한 화합물 반도체 태양전지를 제조할 수 있다.In the case where the compound semiconductor layer CS is formed using an inverse growth method, after the ELO process is performed, a front electrode is formed on one side (lower surface in FIG. 4) of the compound semiconductor layer CS, The compound semiconductor solar cell shown in FIG. 1 can be manufactured by forming a back electrode on the other side (upper surface in FIG. 4) of the compound semiconductor layer CS.
여기에서, 인버스 성장법은 전면 전극 쪽에 위치하는 층(예를 들면, 전면 콘택층)부터 후면 전극 쪽에 위치하는 층(예를 들면, 후면 콘택층)의 순서대로 적층하는 법을 말한다.Here, the inverse growth method is a method of laminating in order from a layer (for example, a front contact layer) located on the front electrode side to a layer (for example, a back contact layer) located on the rear electrode side.
이와 달리, 레귤러(regular) 성장법을 이용하여 화합물 반도체층(CS)을 형성한 경우, ELO 공정을 실시한 후에는 화합물 반도체층(CS)의 한쪽 면(도 4의 경우 하부면)에 후면 전극을 형성하고, 화합물 반도체층(CS)의 다른 쪽 면(도 4의 경우 상부면)에 전면 전극을 형성하는 것에 의해 도 1에 도시한 화합물 반도체 태양전지를 제조할 수 있다.On the other hand, when the compound semiconductor layer CS is formed using the regular growth method, after the ELO process is performed, a rear electrode is formed on one side (lower surface in FIG. 4) of the compound semiconductor layer CS. The compound semiconductor solar cell shown in FIG. 1 can be manufactured by forming and forming a front electrode on the other surface (upper surface in FIG. 4) of the compound semiconductor layer CS.
여기에서, 레귤러 성장법은 후면 전극 쪽에 위치하는 층(예를 들면, 후면 콘택층)부터 전면 전극 쪽에 위치하는 층(예를 들면, 전면 콘택층)의 순서대로 적층하는 법을 말한다.Here, the regular growth method refers to a method of laminating in order from a layer (for example, a rear contact layer) located on the rear electrode side to a layer (for example, a front contact layer) located on the front electrode side.
이와 같이, 화합물 반도체층(CS)의 양쪽 면에 전면 전극과 후면 전극을 형성하기 위해서는 모기판(110)과 분리된 화합물 반도체층(CS)을 뒤집을 필요가 있다.As such, in order to form the front electrode and the rear electrode on both surfaces of the compound semiconductor layer CS, it is necessary to invert the compound semiconductor layer CS separated from the mother substrate 110.
이때, 도 2 및 도 3에 도시한 본 발명의 실시예에 따른 지지 핸들을 사용할 수 있다.At this time, the support handle according to the embodiment of the present invention shown in Figures 2 and 3 can be used.
본 실시예의 지지 핸들(200)은 가요성 기판(210), 가요성 기판(210)의 한쪽 면에 위치하는 접착층(220), 및 접착층(220)에 의해 가요성 기판(210)에 접착되며 상기 접착층(220)에 접착되는 면의 반대쪽 면에 자가 점착면(230A)을 구비하는 폼(foam) 타입 자가 점착 필름(230)을 포함할 수 있다.The support handle 200 of the present embodiment is bonded to the flexible substrate 210 by the flexible substrate 210, the adhesive layer 220 positioned on one side of the flexible substrate 210, and the adhesive layer 220. It may include a foam type self-adhesive film 230 having a self-adhesive surface 230A on a surface opposite to the surface adhered to the adhesive layer 220.
자가 점착 필름의 자가 점착면(230A)에는 복수의 기공(230A-1)이 형성되어 있으며, ELO 필름(220)과의 점착을 위한 별도의 점착제가 도포되어 있지 않다.A plurality of pores 230A-1 are formed on the self-adhesive surface 230A of the self-adhesive film, and a separate pressure-sensitive adhesive for adhesion with the ELO film 220 is not applied.
자가 점착면(230A)에 형성되어 있는 복수의 기공(230A-1)은 도 3에 도시한 바와 같이 불균일한 크기로 형성될 수 있으며, 불균일하게 분포될 수 있다.The plurality of pores 230A-1 formed on the self-adhesive surface 230A may be formed to have a non-uniform size as shown in FIG. 3, and may be distributed non-uniformly.
그리고 도시하지는 않았지만, 자가 점착 필름(230)의 내부에도 복수의 기공이 더 형성될 수 있으며, 자가 점착 필름(230)의 내부에 형성된 복수의 기공도 불균일한 크기로 형성될 수 있으며, 불균일하게 분포될 수 있다.Although not shown, a plurality of pores may be further formed in the self-adhesive film 230, and the plurality of pores formed in the self-adhesive film 230 may be formed in a non-uniform size, and are distributed unevenly. Can be.
자가 점착 필름(230)의 내부에도 복수의 기공이 형성될 경우, 자가 점착 필름의 단면은 도 3에 도시한 것과 동일한 단면을 가질 수 있다.When a plurality of pores are formed inside the self-adhesive film 230, the cross section of the self-adhesive film may have the same cross section as shown in FIG. 3.
폼 타입 자가 점착 필름(230)은 아크릴(acrylic), 폴리우레탄(polyurethane), 폴리에틸렌(polyethylene) 중에서 선택된 어느 하나의 재질로 형성될 수 있다.Foam-type self-adhesive film 230 may be formed of any one material selected from acrylic (acrylic), polyurethane (polyurethane), polyethylene (polyethylene).
이러한 구성의 자가 점착 필름(230)은 자가 점착면(230A)이 ELO 필름(130)을 향하도록 한 상태에서 지지 핸들(200)을 ELO 필름(130)에 점착할 때, 자가 점착면(230A)과 ELO 필름 사이(130)에 위치하는 기포가 자가 점착면(230A)에 형성된 복수의 기공(230A-1)에 포획되므로, ELO 필름(130)과 자가 점착 필름(230) 사이에 있는 기포로 인해 지지 핸들(200)과 ELO 필름(130) 간의 점착력이 저하하는 것을 억제할 수 있으며, 지지 핸들(200)과 ELO 필름(130)의 점착 상태가 견고하게 유지될 수 있다. The self-adhesive film 230 having such a configuration has a self-adhesive surface 230A when the support handle 200 is adhered to the ELO film 130 with the self-adhesive surface 230A facing the ELO film 130. Bubbles between the ELO film 130 and the ELO film 130 are trapped in the plurality of pores 230A-1 formed on the self-adhesive surface 230A, and thus, due to the air bubbles between the ELO film 130 and the self-adhesive film 230. The adhesive force between the support handle 200 and the ELO film 130 may be suppressed from being lowered, and the adhesion state between the support handle 200 and the ELO film 130 may be maintained firmly.
그리고 ELO 필름(130)에 견고하게 점착되어 있는 자가 점착 필름(230)은 일정한 온도 조건(30℃ 내지 60℃)에서 자가 점착면(230A)의 기공(230A-1)에 포획된 공기의 열팽창으로 인해 ELO 필름으로부터 쉽게 박리할 수 있다.The self-adhesive film 230 firmly adhered to the ELO film 130 is a thermal expansion of air trapped in the pores 230A-1 of the self-adhesive surface 230A under a constant temperature condition (30 ° C. to 60 ° C.). Due to this, it can be easily peeled from the ELO film.
여기에서, 온도 조건을 30℃ 내지 60℃로 제한하는 이유는 30℃ 미만의 온도에서는 공기의 열팽창이 잘 이루어지지 않아 자가 점착 필름(230)과 ELO 필름(130)의 박리가 효과적으로 이루어지지 않기 때문이고, 60℃ 이상의 온도에서는 화합물 반도체층에 열적 손상이 가해질 가능성이 있기 때문이다.The reason for limiting the temperature condition to 30 ° C to 60 ° C is that thermal expansion of air is not well performed at a temperature of less than 30 ° C, so that the self-adhesive film 230 and the ELO film 130 are not effectively peeled off. This is because thermal damage may be applied to the compound semiconductor layer at a temperature of 60 ° C or higher.
따라서, 자가 점착 필름(230)은 30℃ 내지 60℃의 온도에서 ELO 필름(220)으로부터 박리하는 것이 바람직하다.Therefore, the self-adhesive film 230 is preferably peeled from the ELO film 220 at a temperature of 30 ℃ to 60 ℃.
가요성 기판(210)은 유리(glass), 폴리프로필렌(polypropylene), 폴리에틸렌(polyethylene), 폴리카보네이트(polycarbonate), 폴리우레탄(polyurethane) 중에서 선택된 어느 하나의 재질로 형성될 수 있고, 100㎛ 이상의 두께(T1)로 형성될 수 있으며, 내산성 및 내용제성을 가질 수 있다.The flexible substrate 210 may be formed of any one material selected from glass, polypropylene, polyethylene, polycarbonate, and polyurethane, and has a thickness of 100 μm or more. It may be formed of (T1), and may have acid resistance and solvent resistance.
이러한 구성의 지지 핸들(200)을 이용하여 화합물 반도체층을 취급할 때, 가요성 기판(210)과 모기판(110)은 각각 척(chuck)에 의해 진공 고정된 상태일 수 있다.When the compound semiconductor layer is handled using the support handle 200 having such a configuration, the flexible substrate 210 and the mother substrate 110 may be in a vacuum fixed state by a chuck, respectively.
이 경우, 상기 자가 점착면(230A)이 ELO 필름(220)을 향하도록 한 상태에서 지지 핸들(200)을 ELO 필름(220)에 점착할 수 있다.In this case, the support handle 200 may be attached to the ELO film 220 while the self-adhesive surface 230A faces the ELO film 220.
이와 달리, 롤(roll) 방법에 의해 지지 핸들(200)을 ELO 필름(130)에 라이네이션하는 것도 가능하다.Alternatively, the support handle 200 may be lined with the ELO film 130 by a roll method.
이후, 지지 핸들(200)을 제거하는 공정에서는 30℃ 내지 60℃의 온도에서 상기 폼 타입 자가 점착 필름(230)을 상기 ELO 필름(220)과 박리하며, 폼 타입 자가 점착 필름(230)을 포함하는 지지 핸들(200)은 자가 점착면(230A)을 세정한 후 재사용한다.Subsequently, in the process of removing the support handle 200, the foam type self-adhesive film 230 is separated from the ELO film 220 at a temperature of 30 ° C. to 60 ° C., and the foam type self adhesive film 230 is included. The support handle 200 is reused after cleaning the self-adhesive surface (230A).
도 5는 일반적인 점착 테이프를 사용한 종래와 폼 타입 자가 점착 테이프를 사용한 본 발명의 실시예를 비교하는 사진으로서, 일반적인 점착 테이프를 사용한 종래의 지지 핸들을 사용한 경우에는 미세 기포의 제거가 불가함과 아울러 점착 불량이 발생하고, 일부 영역에서 들뜸 및 주름이 발생하는 것을 알 수 있다.FIG. 5 is a photograph comparing a conventional embodiment using a general adhesive tape with an embodiment of the present invention using a foam type self-adhesive tape. It can be seen that poor adhesion occurs, and lifting and wrinkles occur in some areas.
하지만, 폼 타입 자가 점착 테이프를 사용한 본 발명의 실시예에서는 종래 기술에 따른 상기한 문제점을 억제할 수 있음을 알 수 있다.However, in the embodiment of the present invention using a foam type self-adhesive tape it can be seen that the above problems according to the prior art can be suppressed.
이상에서 본 발명의 바람직한 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (14)

  1. 가요성 기판;Flexible substrates;
    상기 가요성 기판의 한쪽 면에 위치하는 접착층; 및An adhesive layer located on one side of the flexible substrate; And
    상기 접착층에 의해 상기 가요성 기판에 접착되며, 상기 접착층에 접착되는 면의 반대쪽 면에 자가 점착면을 구비하는 폼(foam) 타입 자가 점착 필름A foam type self-adhesive film bonded to the flexible substrate by the adhesive layer and having a self-adhesive surface on a surface opposite to the surface bonded to the adhesive layer.
    을 포함하는 지지 핸들.Support handle comprising a.
  2. 제1항에서,In claim 1,
    상기 폼 타입 자가 점착 필름은 아크릴(acrylic), 폴리우레탄(polyurethane), 폴리에틸렌(polyethylene) 중에서 선택된 어느 하나의 재질로 형성되는 지지 핸들.The foam type self-adhesive film is a support handle formed of any one material selected from acrylic (acrylic), polyurethane (polyurethane), polyethylene (polyethylene).
  3. 제2항에서,In claim 2,
    상기 자가 점착면에는 복수의 기공(pore)이 형성되어 있는 지지 핸들.And a plurality of pores formed in the self-adhesive surface.
  4. 제3항에서,In claim 3,
    상기 복수의 기공은 불균일한 크기로 불균일하게 분포되어 있는 지지 핸들.And the plurality of pores are unevenly distributed in non-uniform size.
  5. 제3항에서,In claim 3,
    상기 폼 타입 자가 점착 필름의 내부에는 복수의 기공(pore)이 더 형성되어 있는 지지 핸들.And a plurality of pores are further formed inside the foam type self-adhesive film.
  6. 제5항에서,In claim 5,
    상기 폼 타입 자가 점착 필름의 내부에 형성되어 있는 복수의 기공은 불균일한 크기로 불균일하게 분포되어 있는 지지 핸들.And a plurality of pores formed inside the foam type self-adhesive film, which are unevenly distributed in a non-uniform size.
  7. 제2항에서, In claim 2,
    상기 폼 타입 자가 점착 필름은 30℃ 내지 60℃의 온도에서 박리되는 지지 핸들.The foam type self-adhesive film is peeled at a temperature of 30 ℃ to 60 ℃ support handle.
  8. 제1항 내지 제7항 중 어느 한 항에서,The method according to any one of claims 1 to 7,
    상기 가요성 기판은 유리(glass), 폴리프로필렌(polypropylene), 폴리에틸렌(polyethylene), 폴리카보네이트(polycarbonate), 폴리우레탄(polyurethane) 중에서 선택된 어느 하나의 재질로 형성되는 지지 핸들.The flexible substrate is a support handle formed of any one material selected from glass, polypropylene, polyethylene, polycarbonate, polyurethane.
  9. 제8항에서,In claim 8,
    상기 가요성 기판은 100㎛ 이상의 두께로 형성되며, 내산성 및 내용제성을 갖는 지지 핸들.The flexible substrate is formed to a thickness of 100㎛ or more, the support handle having acid resistance and solvent resistance.
  10. 모기판의 한쪽 면 위에 희생층을 형성하는 단계;Forming a sacrificial layer on one side of the mother substrate;
    상기 희생층 위에 화합물 반도체층을 형성하는 단계;Forming a compound semiconductor layer on the sacrificial layer;
    상기 화합물 반도체층 위에 ELO(Epitaxial Lift Off) 필름을 부착하는 단계;Attaching an epitaxial lift off (ELO) film on the compound semiconductor layer;
    ELO 공정을 실시하는 단계;Performing an ELO process;
    상기 ELO 필름에 지지 핸들을 부착하는 단계; 및Attaching a support handle to the ELO film; And
    상기 지지 핸들을 이용하여 상기 화합물 반도체층을 상기 모기판과 분리하는 단계Separating the compound semiconductor layer from the mother substrate by using the support handle.
    를 포함하며,Including;
    상기 지지 핸들은,The support handle,
    가요성 기판;Flexible substrates;
    상기 가요성 기판의 한쪽 면에 위치하는 접착층; 및An adhesive layer located on one side of the flexible substrate; And
    상기 접착층에 의해 상기 가요성 기판에 접착되며, 상기 접착층에 접착되는 면의 반대쪽 면에 자가 점착면을 구비하는 폼(foam) 타입 자가 점착 필름A foam type self-adhesive film bonded to the flexible substrate by the adhesive layer and having a self-adhesive surface on a surface opposite to the surface bonded to the adhesive layer.
    을 포함하고,Including,
    상기 자가 점착면에는 복수의 기공(pore)이 형성되어 있고,A plurality of pores are formed on the self-adhesive surface,
    상기 자가 점착면이 상기 ELO 필름을 향하도록 한 상태에서 상기 지지 핸들을 상기 ELO 필름에 부착하는 화합물 반도체 태양전지의 제조 방법.A method for producing a compound semiconductor solar cell, wherein the support handle is attached to the ELO film in a state in which the self-adhesive side faces the ELO film.
  11. 제10항에서,In claim 10,
    아크릴(acrylic), 폴리우레탄(polyurethane), 폴리에틸렌(polyethylene) 중에서 선택된 어느 하나의 재질로 상기 폼 타입 자가 점착 필름을 형성하는 화합물 반도체 태양전지의 제조 방법.Method of manufacturing a compound semiconductor solar cell to form the foam type self-adhesive film of any one material selected from acrylic (acrylic), polyurethane (polyurethane), polyethylene (polyethylene).
  12. 제11항에서,In claim 11,
    30℃ 내지 60℃의 온도에서 상기 폼 타입 자가 점착 필름을 상기 ELO 필름과 박리하는 화합물 반도체 태양전지의 제조 방법.A method of manufacturing a compound semiconductor solar cell, wherein the foam type self-adhesive film is peeled off from the ELO film at a temperature of 30 ° C to 60 ° C.
  13. 제10항 내지 제12항 중 어느 한 항에서,The method according to any one of claims 10 to 12,
    유리, 폴리프로필렌, 폴리에틸렌, 폴리카보네이트, 폴리우레튼 중에서 선택된 어느 하나의 재질로 상기 가요성 기판을 형성하는 화합물 반도체 태양전지의 제조 방법.A method for producing a compound semiconductor solar cell, wherein the flexible substrate is formed of any one selected from glass, polypropylene, polyethylene, polycarbonate, and polyurethane.
  14. 제13항에서,In claim 13,
    상기 가요성 기판을 100㎛ 이상의 두께로 형성하는 화합물 반도체 태양전지의 제조 방법.A method of manufacturing a compound semiconductor solar cell, wherein the flexible substrate is formed to a thickness of 100 μm or more.
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