WO2020034447A1 - 一种超低损耗双路电源切换防倒灌电路 - Google Patents

一种超低损耗双路电源切换防倒灌电路 Download PDF

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WO2020034447A1
WO2020034447A1 PCT/CN2018/114014 CN2018114014W WO2020034447A1 WO 2020034447 A1 WO2020034447 A1 WO 2020034447A1 CN 2018114014 W CN2018114014 W CN 2018114014W WO 2020034447 A1 WO2020034447 A1 WO 2020034447A1
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pmos transistor
resistor
pmos
pmos tube
tube
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PCT/CN2018/114014
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English (en)
French (fr)
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陈石平
陈顺清
郑彩霞
彭进双
谈书才
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广州奥格智能科技有限公司
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Priority claimed from CN201810920908.2A external-priority patent/CN108808845B/zh
Priority claimed from CN201821304874.6U external-priority patent/CN208571700U/zh
Application filed by 广州奥格智能科技有限公司 filed Critical 广州奥格智能科技有限公司
Publication of WO2020034447A1 publication Critical patent/WO2020034447A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems

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  • the invention relates to the technical field of anti-backflow protection of a dual-circuit power supply switching circuit, in particular to an ultra-low-loss dual-channel power supply switching anti-backflow circuit.
  • auxiliary power sources such as power bank, wall adapter, etc.
  • the load will automatically disconnect from the battery when the auxiliary power source is connected. Therefore, there is a need for a power switching circuit that selects between input power sources to maximize power efficiency, reduce power consumption, and extend battery operating time.
  • an ultra-low-power power switching circuit with anti-backflow, Protect the front circuit This enables an efficient OR operation of the two power supplies, designed to extend battery life and reduce self-heating.
  • Two-diode solution two diodes are connected in series to the power supply, the circuit is simple, and the logical OR function is implemented. You can choose between the battery and the adapter.
  • the disadvantage is that the diode has a voltage drop of about 0.6V, and the voltage drop will be proportional to the power loss of the input current. As the current increases, the voltage drop will also increase.
  • Schottky diodes can reduce the power, but the power loss is still relatively large: Take the Schottky diode SS54 as an example. The currents correspond to 0.1A, 1A, 10A, and 20A.
  • the voltage drops are 0.3V, 0.4V, 0.85V, 1.4V, and the corresponding losses are 0.03W, 0.4W, 8.5W, and 28W, which means that the larger the passing current, the greater the loss.
  • the disadvantage of Schottky diodes is that there is reverse current when the reverse voltage exceeds the threshold, which is generally in the milliamp range, and it does not have anti-backflow protection when the reverse overvoltage occurs, so the quiescent current is generally in the milliamp class.
  • Diode + PMOS tube solution As an invention patent (a multi-input power switching circuit, application number: CN201410700845.1), Schottky diodes are connected in series to Vbus, and the battery Vbat uses a PMOS tube to control the power supply. The loss is large; the PMOS tube uses irfb7440pbf as an example.
  • Triode + MOS tube solution For example, the invention patent (device and method for power switching and compensation, application number: CN200410039550.0), both power sources use triodes to control the MOS tube to supply power to the device, and one of them needs to add an additional third
  • the high-voltage power source controls the MOS tube.
  • the bias resistance of the triode is in the kilo-ohm level, and its static working current is in the milliampere level.
  • the static working current of the transistor is milliamp level, the current loss is very large, and a third high-voltage power supply is needed.
  • Ideal diode solution Use chip LTC4412 to control an external P-channel MOSFET for power switching near-ideal diode function.
  • the gate driver includes an internal voltage clamp for MOSFET protection.
  • the STAT pin can be used to enable an auxiliary P-channel MOSFET power switch. This pin can also be used to signal the microcontroller when an auxiliary power source is connected.
  • the control (CTL) input enables the user to forcibly turn off the main MOSFET and set the STAT pin low.
  • the typical value of quiescent current is 11 ⁇ A, which has nothing to do with the load current.
  • the circuit is very simple. There are few peripheral devices. It has anti-backflow function.
  • the disadvantage is that the chip price is more expensive.
  • the current price is 5-10 yuan per piece.
  • the purpose of the present invention is to overcome the shortcomings in the prior art and provide an ultra-low-loss dual-circuit power switching anti-backflow circuit.
  • An ultra-low-loss dual power switching anti-backflow circuit includes a first PMOS tube (V1), a second PMOS tube (V2), a third PMOS tube (V3), a fourth PMOS tube (V4), and a first NMOS tube.
  • the drain of the first PMOS tube is connected to the source of the third PMOS tube
  • the source of the first PMOS tube is connected to the source of the second PMOS tube
  • the gate of the first PMOS tube is connected to the drain of the fourth PMOS tube
  • the drain of the second PMOS tube is connected to the battery
  • the gate of the second PMOS tube is connected to the drain of the third PMOS tube
  • the first The gates of the three PMOS transistors are connected to the drain of the first NMOS transistor through a third resistor (R3)
  • the gates of the fourth PMOS tube are connected to the drain of the second NMOS transistor through a fourth resistor (R4).
  • the gate of the second PMOS tube is grounded through a fifth resistor (R5), and the gate of the first PMOS tube is grounded through a sixth resistor (R6).
  • the gate of the first NMOS tube is connected to one end of a seventh resistor (R7), and the source of the first NMOS tube is grounded and connected to one end of the ninth resistor (R9), respectively.
  • the gate of the third PMOS transistor is connected to the other ends of the seventh resistor and the ninth resistor through the first resistor (R1), respectively.
  • the gate of the second NMOS tube is connected to one end of the eighth resistor (R8), and the source of the second NMOS tube is grounded and connected to one end of the tenth resistor (R10), respectively.
  • the gate of the third PMOS transistor is connected to the other ends of the eighth resistor and the tenth resistor through a second resistor (R2), respectively.
  • the invention has the beneficial effects that the invention has the function of preventing backflow and can protect the front-stage circuit; it has very low loss, the static loss is microampere level, and the combination switch circuit is used, the circuit is simple, the cost is low, and the practicability is strong.
  • FIG. 1 is a schematic diagram of the present invention.
  • an ultra-low-loss dual power switching anti-backflow circuit As shown in Figure 1, an ultra-low-loss dual power switching anti-backflow circuit.
  • the circuit consists of 4 PMOS tubes (V1 to V4), 2 NMOS tubes (V5, V6), and 10 resistors (R1 to R10). .
  • the dual power switching circuit is a symmetrical circuit.
  • One NMOS + PMOS combination switch (V3, V5) is used to control the other PMOS tube (V2) of the power path; the other NMOS + PMOS combination switch (V4, V6) is used to control
  • the PMOS tube (V1) of one power path, the dual power switch has priority, the power supply with high voltage is preferentially used, and the two power sources have anti-backflow function to protect the power supply front stage circuit.
  • the size of the bias resistance ((R1 and R9) or (R2 and R10)) between the N-pole, G-pole, and S-pole of the combined switch circuit is adjusted according to different loss requirements to meet power consumption requirements.
  • the two power sources of the circuit are DC power sources, and the power supply difference is greater than the absolute value of the on-threshold voltage
  • the static power consumption of the circuit is very low, and the current loss is microampere level, and the combination switch is composed of NMOS, PMOS and resistor.
  • first PMOS tube (V1) and the second PMOS tube (V2) can use the same type of P-channel MOS tube, and the magnitude of the on-current is determined according to the circuit requirements.
  • the combined logic control circuit has the functions of seamless switching of dual power sources and preventing back-flow.
  • PMOS can select a power tube device with on-resistance between D and S poles of several milliohms. It consists of two identical control circuits. Each control circuit consists of MOS tubes and resistors. One combination switch circuit controls the other. The PMOS tube (gate) of the power supply (such as a 12V battery) path, and another combination switch controls the PMOS tube (gate) of the power supply (such as a 15V charger) path. After selecting and comparing the voltages of the two power sources, the output of different levels is used to control one of the two PMOS transistors (V1, V2) to be turned on and the other to be turned off. Since the MOS tube is a voltage device, the MOS tube is turned on and off.
  • the current is very small and can be ignored, and only a small current is dissipated when it is on (microampere level).
  • Selecting PMOS tubes (V1, V2) with on-resistance between D and S poles of several milliohms can pass a large current (several amps), then the voltage drop through the PMOS tubes (V1, V2) is small and can be Approximately an ideal power diode.

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  • Emergency Management (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

一种超低损耗双路电源切换防倒灌电路，包括第一PMOS管（V1）、第二PMOS管（V2）、第三PMOS管（V3）、第四PMOS管（V4）、第一NMOS管（V5）和第二NMOS管（V6），所述第一PMOS管（V1）的漏极连接第三PMOS管（V3）的源极，第一PMOS管（V1）的源极连接第二PMOS管（V2）的源极，第一PMOS管（V1）的栅极连接第四PMOS管（V4）的漏极，第二PMOS管（V2）的漏极接电池，第二PMOS管（V2）的栅极连接第三PMOS管（V3）的漏极，第三PMOS管（V3）的栅极通过第三电阻（R3）连接第一NMOS管（V5）的漏极，第四PMOS管（V4）的栅极通过第四电阻（R4）连接第二NMOS管（V6）的漏极。该电路具有双路电源无缝切换、防止倒灌功能，可以保护前级电路；具有非常低的损耗，静态电流损耗为微安级，使用NMOS+PMOS组合开关电路，电路简单，成本很低，实用性强。

Description

一种超低损耗双路电源切换防倒灌电路 技术领域
本发明涉及双路电源切换电路防倒灌技术领域，尤其是一种超低损耗双路电源切换防倒灌电路。
背景技术
用其他辅助电源如充电宝、墙上适配器等。对于那些采用了一个墙上适配器或其他辅助电源的应用，当辅助电源接入时，负载将自动地与电池断接。因此需要一种电源切换电路，在输入电源之间进行选择，使功率效率达到最佳，减少功耗，延长电池工作时间，特别是一种超低功耗的电源切换电路，并具有防倒灌，保护前级电路。这实现了两个电源的高效“或”操作，旨在延长电池的使用寿命和减少自发热。
双二极管方案：使用两种二极管分别串接在电源上，电路简单，实现逻辑“或”功能，可以在电池和适配器之间进行选择，当电压通过二极管时有压降，电源高的优先被使用，其缺陷是二极管大约有0.6V的压降，电压降会随着输入电流成比例的功率损耗。随着电流增大，压降也会变大，如用肖特基二极管取代可以降低功率，但是功率损耗仍旧比较大：以肖特基二极管SS54为例，电流0.1A、1A、10A、20A对应的压降分别为0.3V、0.4V、0.85V、1.4V，对应的损耗分别为0.03W、0.4W、8.5W、28W，意味着通过电流越大，损耗也越大。肖特基二极管缺点是反向电压超过阈值时存在反向电流，一般为毫安级，反向过压时不具有防倒灌功能，因此静态电流一般为毫安级。
二极管+PMOS管方案：如发明专利(一种多输入电源切换电路，申请号：CN201410700845.1)，肖特基二极管串接在Vbus上，电池Vbat使用PMOS管进行控制供电，由上述知二极管压降损耗大；PMOS管以irfb7440pbf为例，典型值RDS(ON)为2mΩ，取RDS(ON)＝2mΩ，电流0.1A、1A、10A、20A对应的压降分别为0.2mV、2mV、20mV、40mV，对应的损耗分别为0.02mW、2mW、 0.2W、0.8W，显而易见，使用MOS管方案损耗下降非常大，约为肖特基二极管损耗的几十分之一。
三极管+MOS管方案：如发明专利(电源切换及补偿的装置和方法，申请号：CN200410039550.0)，两路电源均使用三极管控制MOS管对设备供电，其中一路还需要增加额外的第三种高压电源控制MOS管，显然三极管的偏置电阻为千欧姆级，其静态工作电流毫安级。不足之处三极管的静态工作电流毫安级，电流损耗很大，且需要使用的第三种高压电源。
理想二极管方案：使用芯片LTC4412，控制一个外部P沟道MOSFET，用于电源切换近理想型二极管功能。当导通时，MOSFET两端的压降通常为20mV。栅极驱动器包括一个用于MOSFET保护的内部电压箝位。当检测到一个辅助电源时，可采用STAT引脚来使能一个辅助P沟道MOSFET电源开关。该引脚还可被用于在接入了一个辅助电源时向微控制器发出指示信号。控制(CTL)输入使得用户能够强制关断主MOSFET，并将STAT引脚置于低电平。静态电流典型值为11μA与负载电流无关，电路很简单，外围器件很少，具有防倒灌功能，不足之处，其芯片价格较贵，目前价格为每片5～10元。根据芯片手册第9页图2原理图制作PCB板，使用PMOS管AO3401A，电阻阻值500k欧姆，贴片焊接后进行测试，只有锂电池3.78V供电时(无负载)静态电流13.6μA，且存在输入输出压差17mV；单独外电4.2V供电时(无负载)静态电流19.8μA，若接有电池测量发现辅助PMOS管(V GS＝-0.09V>V GS(th)＝-0.7V，处于正准备进入导通状态，严格意义上应该为0V)有0.1μA倒灌电流流向锂电池；有负载时(负载电流1A)还是存在0.1μA倒灌电流流向锂电池，辅助PMOS管(V GS＝-0.0959V)，说明LTC4412内部控制器不能外部PMOS管进行绝对的关闭(截止)，还是存在微弱的倒灌电流。
因此，对于上述问题有必要提出一种超低损耗双路电源切换防倒灌电路。
发明内容
本发明目的是克服了现有技术中的不足，提供了一种超低损耗双路电源切换防倒灌电路。
为了解决上述技术问题，本发明是通过以下技术方案实现：
一种超低损耗双路电源切换防倒灌电路，包括第一PMOS管(V1)、第二PMOS管(V2)、第三PMOS管(V3)、第四PMOS管(V4)、第一NMOS管(V5)和第二NMOS管(V6)，所述第一PMOS管的漏极连接第三PMOS管的源极，所述第一PMOS管的源极连接第二PMOS管的源极，所述第一PMOS管的栅极连接第四PMOS管的漏极，所述第二PMOS管的漏极的接电池，所述第二PMOS管的栅极连接第三PMOS管的漏极，所述第三PMOS管的栅极通过第三电阻(R3)连接第一NMOS管的漏极，所述第四PMOS管的栅极通过第四电阻(R4)连接第二NMOS管的漏极。
优选地，所述第二PMOS管的栅极通过第五电阻(R5)接地，所述第一PMOS管的栅极通过第六电阻(R6)接地。
优选地，所述第一NMOS管的栅极连接第七电阻(R7)的一端，所述第一NMOS管的源极分别接地和连接第九电阻(R9)的一端。
优选地，所述第三PMOS管的栅极通过第一电阻(R1)分别连接第七电阻和第九电阻的另一端。
优选地，所述第二NMOS管的栅极连接第八电阻(R8)的一端，所述第二NMOS管的源极分别接地和连接第十电阻(R10)的一端。
优选地，所述第三PMOS管的栅极通过第二电阻(R2)分别连接第八电阻和第十电阻的另一端。
本发明有益效果：本发明具有防止倒灌功能，可以保护前级电路；具有非常低的损耗，静态损耗为微安级，使用组合开关电路，电路简单，成本很低，实用性强。
以下将结合附图对本发明的构思、具体结构及产生的技术效果作进一步说明，以充分地了解本发明的目的、特征和效果。
附图说明
图1是本发明的原理图。
具体实施方式
以下结合附图对本发明的实施例进行详细说明，但是本发明可以由权利要求限定和覆盖的多种不同方式实施。
如图1所示，一种超低损耗双路电源切换防倒灌电路，电路由4个PMOS管(V1～V4)、2个NMOS管(V5、V6)、10个电阻(R1～R10)组成。双路电源切换电路属于对称电路，采用一路NMOS+PMOS组合开关管(V3、V5)去控制另外一路电源通路的PMOS管(V2)；另一路NMOS+PMOS组合开关管(V4、V6)去控制一路电源通路的PMOS管(V1)，双路电源切换具有优先级，优先使用电压高的电源，且对两路电源均具有防倒灌功能，保护电源前级电路。
进一步的，所述根据不同损耗需求调整组合开关电路NMOS、PMOS管G极、S极之间的偏置电阻((R1和R9)或(R2和R10))大小，满足功耗需求。所述电路两种电源均为直流电源，电源差要大于PMOS管(V1、V2)导通阈值电压绝对值|VGS(th)|、优先选择低阈值导通电压的PMOS管。
进一步的，所述电路静态功耗很低，电流损耗为微安级，所述组合开关由NMOS、PMOS和电阻组成。
进一步的，所述第一PMOS管(V1)和第二PMOS管(V2)可以使用同种型号的P沟道MOS管，导通电流大小根据电路要求来定。所述组合逻辑控制电路具有双路电源无缝切换、防止倒灌功能。
PMOS可以选择D极与S极之间的导通电阻为数毫欧的功率管器件，由两路相同的控制电路组成，每一路控制电路均由MOS管、电阻组成，一路组合开关电路控制另外一路电源(如12V电池)通路的PMOS管(栅极)，另外一路组合开关控制一路电源(如15V充电器)通路的PMOS管(栅极)。通过对双路电源的电压选择、比较后，输出不同的电平控制两路PMOS管(V1、V2)的一路导通另一路截止，由于MOS管属于电压器件，MOS管导通和截止时其 电流非常小，可以忽略不计，导通时只损耗很小的电流(微安级)。选用D极与S极之间的导通电阻为数毫欧的PMOS管(V1、V2)，可以通过很大电流(数安培)，那么通过PMOS管(V1、V2)的压降很小，可以近似为一个理想功率二极管。
本发明贴片焊接后进行测试(元器件型号如图1所示)：本方案只有3.7V锂电池供电时，静态功耗电流功耗为1.1μA；只有墙上适配器4.2V电源供电时，静态功耗电流功耗为1.26μA，PMOS管V2的V GS＝2.9mV，处于截止状态，V2无倒灌电流存在；同时接上两种电源时，静态功耗电流功耗为两者之和为2.36μA，PMOS管V2的V GS＝-1.3mV，处于截止状态，V2无倒灌电流存在。NMOS、PMOS管G极、S极之间的偏置电阻((R1和R9)或(R2和R10))若焊接更大的阻值，其损耗电流将更小。
以上详细描述了本发明的较佳具体实施例。应当理解，本领域的普通技术人员无需创造性劳动就可以根据本发明的构思做出诸多修改和变化。因此，凡本技术领域中技术人员依本发明的构思在现有技术的基础上通过逻辑分析、推理或者有限的实验可以得到的技术方案，皆应在由权利要求书所确定的保护范围内。

Claims (4)

  1. 一种超低损耗双路电源切换防倒灌电路，其特征在于：包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NMOS管和第二NMOS管，所述第一PMOS管的漏极连接第三PMOS管的源极，所述第一PMOS管的源极连接第二PMOS管的源极，所述第一PMOS管的栅极连接第四PMOS管的漏极，所述第二PMOS管的漏极的接电池，所述第二PMOS管的栅极连接第三PMOS管的漏极，所述第三PMOS管的栅极通过第三电阻连接第一NMOS管的漏极，所述第四PMOS管的栅极通过第四电阻连接第二NMOS管的漏极；所述第二PMOS管的栅极通过第五电阻接地，所述第一PMOS管的栅极通过第六电阻接地；所述第一NMOS管的栅极连接第七电阻的一端，所述第一NMOS管的源极分别接地和连接第九电阻的一端。
  2. 如权利要求1所述的一种超低损耗双路电源切换防倒灌电路，其特征在于：所述第三PMOS管的栅极通过第一电阻分别连接第七电阻和第九电阻的另一端。
  3. 如权利要求2所述的一种超低损耗双路电源切换防倒灌电路，其特征在于：所述第二NMOS管的栅极连接第八电阻的一端，所述第二NMOS管的源极分别接地和连接第十电阻的一端。
  4. 如权利要求3所述的一种超低损耗双路电源切换防倒灌电路，其特征在于：所述第三PMOS管的栅极通过第二电阻分别连接第八电阻和第十电阻的另一端。
PCT/CN2018/114014 2018-08-14 2018-11-05 一种超低损耗双路电源切换防倒灌电路 WO2020034447A1 (zh)

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CN201821304874.6 2018-08-14
CN201821304874.6U CN208571700U (zh) 2018-08-14 2018-08-14 一种超低损耗双路电源切换防倒灌电路

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CN102130492A (zh) * 2010-07-31 2011-07-20 华为技术有限公司 电源选择装置和方法
CN104022647A (zh) * 2014-06-25 2014-09-03 上海协霖电子有限公司 一种电源自切换的稳压电路
CN104377812A (zh) * 2014-11-28 2015-02-25 青岛歌尔声学科技有限公司 一种多输入电源切换电路
CN106208358A (zh) * 2016-08-31 2016-12-07 合肥联宝信息技术有限公司 一种双电源切换供电的控制电路
CN207612119U (zh) * 2017-10-31 2018-07-13 中国航空无线电电子研究所 隔离器电路及电源备份网路

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US20100109440A1 (en) * 2008-10-31 2010-05-06 Honeywell International Inc. Single fault tolerant isolated dual bus power input circuits and systems
CN102130492A (zh) * 2010-07-31 2011-07-20 华为技术有限公司 电源选择装置和方法
CN104022647A (zh) * 2014-06-25 2014-09-03 上海协霖电子有限公司 一种电源自切换的稳压电路
CN104377812A (zh) * 2014-11-28 2015-02-25 青岛歌尔声学科技有限公司 一种多输入电源切换电路
CN106208358A (zh) * 2016-08-31 2016-12-07 合肥联宝信息技术有限公司 一种双电源切换供电的控制电路
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