WO2020031265A1

WO2020031265A1 - Semiconductor memory device

Info

Publication number: WO2020031265A1
Application number: PCT/JP2018/029627
Authority: WO
Inventors: 東　和幸; 一道津村; 勝又　竜太; 史隆荒井
Original assignee: キオクシア株式会社
Priority date: 2018-08-07
Filing date: 2018-08-07
Publication date: 2020-02-13
Also published as: CN112262474A; SG11202013103YA

Abstract

The semiconductor memory device according to an embodiment of the present invention includes a plurality of memory cell array layers each of which has a first surface and a second surface opposite the first surface and does not include a substrate, said memory cell array layers each including a plurality of memory cells three-dimensionally arranged in a memory cell array region and a surface wiring layer that is embedded in the first surface and/or the second surface. The surface wiring layers of the memory cell array layers are provided so as to overlap one another when viewed in a direction perpendicular to the first surface, and the plurality of memory cell array layers are stacked by the surface wiring layers being connected to each other.

Description

Semiconductor storage device

Embodiments of the present invention relate to a semiconductor memory device.

A semiconductor having a three-dimensional structure in which a memory hole is formed in a stacked body in which a plurality of electrode layers are stacked on a substrate via an insulating layer, and a silicon body serving as a channel is provided in the memory hole via a charge storage film. Storage devices have been proposed. In addition, a technique has been proposed in which a control circuit for a memory cell array having the three-dimensional structure is provided immediately below or directly above the memory cell array.

However, in this example, the memory density per area cannot be sufficiently improved.

JP 2011-204829 A JP 2016-62901 A

提供 Provide small and high performance semiconductor memory devices.

According to the embodiment, a memory cell array layer having a first surface and a second surface opposite to the first surface and not including a substrate, and a plurality of memory cells three-dimensionally arranged in a memory cell array region; A plurality of memory cell array layers including a surface wiring layer embedded in the first surface and / or the second surface;
The surface wiring layers of the respective memory cell array layers are provided so as to overlap when viewed from a direction perpendicular to the first surface, and the plurality of memory cell array layers are formed by joining the surface wiring layers to each other. A semiconductor memory device characterized by being stacked is provided.

1 is a schematic cross-sectional view illustrating a semiconductor memory device according to a first embodiment. 1 is a schematic perspective view illustrating a semiconductor memory device according to a first embodiment. 1 is a schematic cross-sectional view illustrating a semiconductor memory device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing an enlarged part of the semiconductor memory device according to the first embodiment. 1 is a schematic perspective view illustrating a semiconductor memory device according to a first embodiment. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. FIG. 4 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. Schematic sectional view of a semiconductor memory device according to a first modification of the first embodiment. Schematic sectional view of a semiconductor memory device according to a second modification of the first embodiment. Schematic sectional view showing a semiconductor memory device according to a second embodiment. Circuit diagram of a semiconductor memory device according to a second embodiment FIG. 2 is a block diagram illustrating a configuration of a system of a semiconductor memory device according to a second embodiment.

Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are given to the same elements in each drawing.

(First embodiment)
FIG. 1 is a schematic sectional view of the semiconductor memory device according to the first embodiment. The semiconductor memory device according to the first embodiment includes a peripheral circuit layer 100 including a control circuit for controlling writing, erasing, and reading of data to and from a memory cell, and a first circuit including a plurality of three-dimensionally arranged first memory cells. And the memory cell array layer 200 are laminated so as to face each other, and are laminated and bonded. Further, a structure in which the first memory cell array layer 200 and the second memory cell array layer 300 including a plurality of two-dimensionally arranged second memory cells are joined so as to face each other, stacked, and bonded to each other. Have.

First, the first memory cell array layer 200 will be described. The first memory cell array layer 200 has a first surface (lower surface) Sa1 in FIG. 1 and a second surface (upper surface) Sa2 opposite to the first surface, and has a first memory cell array 10a having a three-dimensional structure. FIG. 2 is a schematic perspective view of the semiconductor memory device according to the first embodiment, and is a schematic perspective view of the first memory cell array 10a. In FIG. 2, illustration of some insulating layers such as an inter-electrode insulating layer is omitted. FIG. 2 is upside down with respect to FIG. 1. The upper side in FIG. 2 is the first surface side, and the lower side is the second surface side.

In FIG. 2, two directions orthogonal to each other are defined as an X direction and a Y direction, and a direction in which a plurality of electrode layers WL are stacked is orthogonal to the X direction and the Y direction (XY plane). Direction).

The first memory cell array 10a has a first stacked body 12a in which a plurality of electrode layers WL and insulating layers 11 are alternately stacked one by one. A plurality of first columnar portions 13a extending in the Z direction are provided in the first stacked body 12a. The first columnar portion 13a is provided, for example, in a columnar or elliptical columnar shape. The plurality of first columnar portions 13a are arranged in, for example, a staggered lattice or a square lattice on the XY plane. The electrode layer WL is divided into a plurality of blocks in the Y direction and extends in the X direction.

(4) The electrode layer WL is, for example, a layer containing silicon as a main component. Further, the electrode layer WL contains boron as an impurity for giving conductivity to the silicon layer. Further, the electrode layer WL may include metal silicide.

The insulating layer 11 mainly contains, for example, silicon and oxygen, and is, for example, a silicon oxide film (SiO), a silicon oxynitride film (SiON), or a carbon-containing silicon oxide film (SiOC).

(4) A drain-side selection gate SGD is provided in the upper portion on the first surface Sa1 side of the first columnar portion 13a, and a source-side selection gate SGS is provided in a lower portion on the second surface Sa2 side. The drain-side selection gate SGD is provided on the uppermost electrode layer WL via the insulating layer 11. The source-side selection gate SGS is provided below the lowermost electrode layer WL via an insulating layer 11. Here, for example, the drain-side selection gate SGD and the source-side selection gate SGS can be formed thicker than the single electrode layer WL.

上端 A first bit line 16a is connected to an upper end of the first columnar portion 13a on the first surface Sa1 side. A plurality of first bit lines 16a are provided and metal is used. The plurality of first bit lines 16a are separated in the X direction and extend in the Y direction. The first bit line 16a is provided on the drain-side selection gate SGD via the insulating layer 11 and the interlayer insulating layer 14.

１A first source line 17a is connected to the lower end of the first columnar portion 13a on the second surface Sa2 side. The first source line 17a is provided below the source-side selection gate SGS via the interlayer insulating layer 15. Further, a first source side wiring layer 19a is provided in the interlayer insulating layer 18 at the lower end of the first columnar portion 13a and further below the first source line 17a. The interlayer insulating layer 18 may be a laminated layer.

FIG. 3 is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment, and is a schematic cross-sectional view near the first columnar portion. FIG. 4 is an enlarged schematic cross-sectional view of a portion A, which is a part near the first columnar portion in FIG. 3 and 4 show cross sections parallel to the YZ plane in FIG.

As shown in FIG. 3, the first columnar portion 13a is formed in an I-shaped memory hole formed in a first stacked body 12a including a plurality of electrode layers WL and a plurality of insulating layers 11. . A channel body 20 as a semiconductor channel is provided in the memory hole. The channel body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than the impurity concentration of the electrode layer WL.

(4) As shown in FIG. 4, the memory film MC is provided between the inner wall of the memory hole and the channel body 20 in the memory cell MC. The memory film 21 includes, for example, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24. Between the electrode layer WL and the channel body 20, a block insulating film 22, a charge storage film 23, and a tunnel insulating film 24 are provided in this order from the electrode layer WL side.

The channel body 20 is provided in a cylindrical shape extending in the stacking direction of the stacked body. The electrode layer WL surrounds the periphery of the channel body 20 via the memory film 21. The core insulating film 25 is provided inside the channel body 20. The core insulating film 25 is, for example, a silicon oxide film.

The block insulating film 22 is in contact with the electrode layer WL, the tunnel insulating film 24 is in contact with the channel body 20, and the charge storage film 23 is provided between the block insulating film 22 and the tunnel insulating film 24.

The channel body 20 functions as a channel in the memory cell MC, and the electrode layer WL functions as a control gate of the memory cell. The charge storage film 23 functions as a data storage layer for storing charges injected from the channel body 20. That is, a memory cell MC having a structure in which the control gate surrounds the periphery of the channel is formed at the intersection of the channel body 20 and each electrode layer WL.

The semiconductor memory device according to the first embodiment is a non-volatile semiconductor memory device that can electrically perform data erasing and writing freely and can retain stored contents even when the power is turned off.

The memory cell MC is, for example, a charge trap type memory cell. The charge storage film 23 has a large number of trap sites for capturing charges, and is, for example, a silicon nitride film. It may be a floating gate type memory cell.

(4) The tunnel insulating film 24 becomes a potential barrier when charges are injected into the charge storage film 23 from the channel body 20 or when charges stored in the charge storage film 23 diffuse into the channel body 20. The tunnel insulating film 24 is, for example, a silicon oxide film.

Alternatively, a laminated film (ONO film) having a structure in which a silicon nitride film is sandwiched between a pair of silicon oxide films may be used as the tunnel insulating film. When an ONO film is used as a tunnel insulating film, an erasing operation can be performed with a lower electric field than a single layer of a silicon oxide film.

(4) The block insulating film 22 prevents the charge stored in the charge storage film 23 from diffusing into the electrode layer WL. The block insulating film 22 includes, for example, a silicon nitride film 221 provided in contact with the electrode layer WL, and a silicon oxide film 222 provided between the silicon nitride film 221 and the charge storage film 23.

(4) By providing the silicon nitride film 221 having a higher dielectric constant than the silicon oxide film 222 in contact with the electrode layer WL, back tunnel electrons injected from the electrode layer WL during erasing can be suppressed. That is, by using a stacked film of the silicon oxide film and the silicon nitride film as the block insulating film 35, the charge blocking property can be improved.

(2) As shown in FIGS. 2 and 3, a drain-side selection transistor STD is provided above the first columnar portion 13a, and a source-side selection transistor STS is provided below the other.

The memory cell MC, the drain-side selection transistor STD, and the source-side selection transistor STS are vertical transistors in which current flows in the stacking direction (Z direction) of the stacked body.

(4) The drain-side selection gate SGD functions as a gate electrode (control gate) of the drain-side selection transistor STD. An insulating film 26 (FIG. 3) functioning as a gate insulating film of the drain-side selection transistor STD is provided between the drain-side selection gate SGD and the channel body 20. The channel body 20 of the drain-side selection transistor STD provided in the first columnar portion 13a is connected to the bit line BL above the drain-side selection gate SGD.

(4) The source-side selection gate SGS functions as a gate electrode (control gate) of the source-side selection transistor STS. An insulating film 27 (FIG. 3) functioning as a gate insulating film of the source-side selection transistor STS is provided between the source-side selection gate SGS and the channel body 20. The channel body 20 of the source-side selection transistor STS provided in the first columnar portion 13a is connected to the source line SL below the source-side selection gate SGS.

Below the source line SL, a first source side wiring layer 19a is provided in the interlayer insulating layer 18.

The memory cells MC, the drain-side selection transistor STD, and the source-side selection transistor STS are connected in series through the channel body 20 to form one I-shaped memory string MS. Since the plurality of memory strings MS are arranged in the X direction and the Y direction, the plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

FIG. 1 shows an end area in the X direction of the first memory cell array 10a. At the end of the first memory cell array region 28a where the plurality of memory cells MC are arranged, a step structure 29 of the electrode layer WL extending in the X direction is formed. In the staircase structure section 29, the end in the X direction of the electrode layer WL of each layer is formed in a staircase shape. The staircase structure portion 29 is provided with a plurality of contact plugs 30 connected to the electrode layers WL of each layer formed in a staircase shape. The contact plug 30 penetrates through the interlayer insulating layer 31 and is connected to the electrode layer WL of each step-like layer.

In the staircase structure 29, the selection gate SG (the drain-side selection gate SGD and the source-side selection gate SGS) is connected to the contact plug 32.

The contact plug 30 connected to the electrode layer WL is connected to the word wiring layer 33. The contact plug 32 connected to the selection gate SG is connected to the selection gate wiring layer 34. The word wiring layer 33 and the selection gate wiring layer 34 are provided on the same layer.

The first memory cell array layer 200 does not include a substrate. Further, a first source side wiring layer 19a is further provided on the second surface side of the first source line SL.
At least a part of the word wiring layer 33 and the select gate wiring layer 34 is formed by another wiring layer or plug outside the first memory cell array region 28a when viewed from a direction perpendicular to the first surface. And a selection gate line drawing section 36. The word line lead portion 35 and the select gate line lead portion 36 drawn out of the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided outside the first memory cell array region 28a. Have been.

{The channel body 20 of the first columnar portion 13a is electrically connected to the first bit line BL and the first source line SL. Further, similarly, at least a part of the first bit line BL and the first source line SL is also outside the first memory cell array region 28a when viewed from a direction perpendicular to the first surface by another wiring layer or plug. Are drawn out as a first bit line lead-out part and a first source line lead-out part (not shown). The first bit line lead-out portion and the first source line lead-out portion drawn out of the first memory cell array region 28a are the first signal line lead-out electrodes provided outside the first memory cell array region 28a. 37a.

{Circle around (1)} On the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, a first surface wiring layer 38a and a second surface wiring layer 39a are provided. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and the surfaces are exposed from an interlayer insulating layer (not shown). Here, for example, the first signal line lead-out electrode 37a is formed of the first surface wiring layer 38a and the second surface wiring layer provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. 39a is electrically connected. The first signal line lead-out electrode 37a, the first surface wiring layer 38a, and the second surface wiring layer 39a penetrate the first memory cell array layer 200.

{Circle around (1)}, a first external connection electrode 40a is provided outside the first memory cell array region 28a. That is, the first external connection electrode 40a is provided in a region further outside the staircase structure in the memory cell array. The first external connection electrode 40a is electrically connected to the first surface wiring layer 38a and the second surface wiring layer 39a provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively. It is connected. The first surface wiring layer 38a and the second surface wiring layer 39a are embedded in the first surface Sa1 and the second surface Sa2, respectively, and the surfaces are exposed from an interlayer insulating layer (not shown). The first external connection electrode 40a, the first surface wiring layer 38a, and the second surface wiring layer 39a penetrate the first memory cell array layer 200.

The peripheral circuit layer 100 includes the circuit board 1. The circuit substrate 1 of the peripheral circuit layer 100 is, for example, a silicon substrate. A control circuit is formed on the circuit forming surface of the circuit board 1 in the peripheral circuit layer. The control circuit is formed as an integrated circuit including a transistor. The transistor has a MOSFET structure having a gate electrode, source / drain regions, and the like. The source / drain region of the MOSFET is connected to the circuit-side connection electrode 41 by another wiring layer or a plug. The circuit-side connection electrode 41 is electrically connected to a circuit-side wiring layer 42 provided on a circuit formation surface of the peripheral circuit layer 100. The circuit-side wiring layer 42 is embedded in the circuit formation surface, and the surface is exposed from an interlayer insulating layer (not shown).

The second memory cell array layer 300 has the same configuration as the first memory cell array layer 200 shown in FIGS. That is, the second memory cell array layer 300 has a third surface (lower surface) Sb1 and a fourth surface (upper surface) Sb2 opposite to the third surface in FIG. 1 and has a three-dimensional structure of the second memory cell array 10b. Have. Descriptions of other similar configurations are omitted.

The second memory cell array layer 300 does not include a substrate. Further, a second source side wiring layer 19b is further provided on the fourth surface side of the second source line SL.
Similarly to the first memory cell array layer 200, at least a part of the word wiring layer 33 and the select gate wiring layer 34 is formed by another wiring layer or plug by a second memory cell array area as viewed from a direction perpendicular to the third surface. The word line lead-out part 35 and the select gate line lead-out part 36 are drawn out of the area 28b. The word line lead portion 35 and the select gate line lead portion 36 drawn outside the second memory cell array region 28b are connected to the second signal line lead electrode 37b provided outside the second memory cell array region 28b. Have been.

{The channel body 20 of the second columnar portion 13b is electrically connected to the second bit line BL and the second source line SL. Further, at least a part of the second bit line BL and the second source line SL is formed outside the second memory cell array region 28b as viewed from a direction perpendicular to the third surface by another wiring layer or plug. It is led out as a second bit line lead-out part and a second source line lead-out part. The second bit line lead-out portion and the second source line lead-out portion drawn out of the first memory cell array region 28b are connected to a second signal line lead-out electrode provided outside the second memory cell array region 28b. 37b. Note that the configuration in the second memory cell array region 28b is the same as that of the first memory cell array layer 200, and therefore the description of the reference numerals is omitted.

A third surface wiring layer 38b and a fourth surface wiring layer 39b are provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and the surfaces are exposed from an interlayer insulating layer (not shown). Here, for example, the second signal line extraction electrode 37b is connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third and fourth surfaces of the second memory cell array layer 300, respectively. It is electrically connected. The second signal line lead-out electrode and the third and fourth surface wiring layers penetrate the second memory cell array layer 300.

{Circle around (2)}, a second external connection electrode 40b is provided outside the second memory cell array region 28b. That is, the second external connection electrode 40b is provided in a region further outside the staircase structure in the memory cell array. The second external connection electrode 40b is electrically connected to the third surface wiring layer 38b and the fourth surface wiring layer 39b provided on the third surface Sb1 and the fourth surface Sb2 of the second memory cell array layer 300, respectively. It is connected. The third surface wiring layer 38b and the fourth surface wiring layer 39b are embedded in the third surface Sb1 and the fourth surface Sb2, respectively, and the surfaces are exposed from an interlayer insulating layer (not shown). The second external connection electrode 40b, the third surface wiring layer 38b, and the fourth surface wiring layer 39b penetrate the second memory cell array layer 300. The external connection pad 52 is provided on the surface wiring layer of the fourth surface wiring layer 39b that is electrically connected to the second external connection electrode 40b.

(1) As shown in FIG. 1, the first surface wiring layer 38a provided on the first surface Sa1 is bonded and joined to the circuit-side wiring layer 42 provided on the circuit forming surface. The first surface wiring layer 38a and the circuit-side wiring layer 42 are, for example, copper or a copper alloy containing copper as a main component. An insulating film (not shown) is provided around the first surface wiring layer 38a and the circuit-side wiring layer 42. The insulating film is, for example, an inorganic film, a resin film, or the like. The first memory cell array layer 200 and the peripheral circuit layer 100 are electrically connected via the first surface wiring layer 38a and the circuit-side wiring layer 42.

Further, as shown in FIG. 1, the second surface wiring layer 39a provided on the second surface Sa2 is bonded to and bonded to the third surface wiring layer 38b provided on the third surface Sb1. . The second surface wiring layer 39a and the third surface wiring layer 38b are, for example, copper or a copper alloy containing copper as a main component. An insulating film (not shown) is provided around the second surface wiring layer 39a provided on the second surface and the third surface wiring layer 38b provided on the third surface Sb1. The insulating film is, for example, an inorganic film and includes a silicon nitride film. The first memory cell array layer and the second memory cell array layer are electrically connected via a second surface wiring layer 39a and a third surface wiring layer 38b.

In the case where the insulating film around the wiring layer is an inorganic film, the bonding between the wiring layers can be performed at the bonding surface, and the bonding using hydrogen bonding between the inorganic films can be performed. Therefore, it is preferable to use an inorganic film as the insulating film since a gap between bonding surfaces is less likely to occur, and it is not necessary to perform underfill using a resin film.

FIG. 5 is a schematic perspective view of the semiconductor memory device according to the first embodiment, and is a schematic perspective view relating to the electrical connection state of the peripheral circuit layer, the first memory cell array layer, and the second memory cell array layer. .

As shown in FIG. 5, the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 include a first signal line lead electrode, a second signal line lead electrode, a first external connection electrode, They are electrically connected by a second external connection electrode (not shown). Signal line extraction electrodes are provided outside the memory

cell array regions

28a and 28b, and external connection electrodes are provided outside the memory cell array region and further outside the staircase structure portion in the memory cell array. The signal line lead-out electrodes and the external connection electrodes of the memory cell array layer are respectively provided in overlapping regions when viewed from a direction perpendicular to the first surface Sa1. The signal line lead-out electrodes are electrically connected to the surface wiring layers 39a and 39b, and the external connection electrodes of the uppermost second memory cell array layer 300 are electrically connected to the external connection pads 52. Note that FIG. 5 shows only a part of the electrical connection states of the first signal line lead electrode, the second signal line lead electrode, the first external connection electrode, the second external connection electrode, and the like. Illustration is omitted.

方法 A method of manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 6 to 9 are cross-sectional views of the semiconductor memory device according to the method for manufacturing the semiconductor memory device according to the first embodiment.

(6) As shown in FIG. 6, a control circuit including a transistor and the like is formed on the circuit substrate 1, and a peripheral circuit layer 100 having a circuit-side wiring layer 42 whose surface is exposed from an insulating film (not shown) is formed. A first insulating layer 50, for example, a silicon oxide film is formed as a buffer layer under the other substrate 2, and a first source line side wiring layer 19a and a first source line are formed under the first insulating layer 50. 17a are formed, and a first select gate SG, a plurality of electrode layers WL, and the like are formed below the first source line 17a. Next, the memory string MS, the staircase structure 29, and the like are formed. Further, a first external connection electrode 40a, a first signal line extraction electrode 37a, and a first surface wiring layer 38a whose surface is exposed from an insulating film (not shown) are formed, and a first memory cell array layer 200 is formed. Is done. Subsequently, the circuit-side wiring layer 42 of the peripheral circuit layer 100 and the first surface wiring layer 38a of the first memory cell array layer 200 are stacked so as to face each other.

Next, as shown in FIG. 7, the peripheral circuit layer 100 and the first memory cell array layer 200 are stacked. At this time, the circuit-side wiring layer 42 and the first surface wiring layer 38a are joined. As a joining method, for example, joining is performed by applying a mechanical pressure, and diffusion joining is performed. Alternatively, the bonding is performed by using an inert plasma treatment on the bonding surface and forming a OH group on the bonding surface to generate hydrogen bonds. Alternatively, they are joined using an organic adhesive or the like. Thereafter, the substrate 2 is removed with a chemical such as KOH. At this time, the insulating films around each wiring layer can also be joined.

ため Since the memory cell array layer does not have a substrate, it is likely that the memory cell array layer is easily deformed by stress applied to the memory cell array layer, and the stacked semiconductor memory devices may warp. Therefore, a second insulating layer 51 is formed. The second insulating layer 51 is a layer having a stress in a direction opposite to a warp generated after the substrate is removed, and is formed as a stress adjusting film. As the second insulating layer 51, for example, a silicon nitride film is formed. By doing so, the stress generated in the semiconductor memory device can be reduced, and the warpage of the semiconductor memory device can be suppressed.

Next, the first insulating layer 50 and the second insulating layer 51 are removed so that the upper surfaces of the first external connection electrode 40a and the first signal line extraction electrode 37a are exposed, and a groove is formed. As shown in FIG. 8, a second surface wiring layer 39a serving as a bonding metal is formed in the groove, and the upper surface of the second surface wiring layer 39a is exposed.

Next, following FIG. 8, a first memory cell array layer 200 is used instead of the peripheral circuit layer 100 shown in FIG. 6, and a second memory cell array layer 300 is used instead of the first memory cell array layer 200 shown in FIG. 6 to FIG. 8 are repeated. As shown in FIG. 9, the external connection pad 52 is formed on the surface wiring layer electrically connected to the second external connection electrode 40b among the fourth surface wiring layer 39b exposed on the upper surface. Thus, a semiconductor memory device in which the peripheral circuit layer 100, the first memory cell array layer 200, and the second memory cell array layer 300 are stacked can be formed.

In the first embodiment, the second memory cell array layer 300 is stacked on the first memory cell array layer 200. However, one or more other memory cell array layers are stacked on the second memory cell array layer 300. May be. At this time, at least a part of one or more other memory cell array layers may include the substrate. In that case, warpage of the stacked semiconductor memory devices can be reduced.

{Circle around (4)} The peripheral circuit layer 100 may not be laminated, and only a laminate of the memory cell array layers may be formed.

(First Modification)
FIG. 10 is a schematic cross-sectional view of a semiconductor memory device according to a first modification of the first embodiment. A wiring layer 61 that connects the memory string MS1 of the first memory cell array layer 200 and the memory string MS2 of the second memory cell array layer 300 is provided. The wiring layer 61 is provided inside the memory cell array region, and is connected to the first source side wiring layer 19a of the first memory cell array layer 200 and the second bit line 16b of the second memory cell array layer 300. The first memory cell array layer and the second memory cell array layer are connected without interposing a signal line extraction electrode provided outside the memory cell array region.

In the first modified example, the first memory cell array layer and the second memory cell array layer are connected to a signal line extraction electrode provided outside the memory cell array region and a wiring provided inside the memory cell array region. They are connected using layers.

形成 By forming in this manner, the electrode area required for connecting the memory cell array layer can be reduced, and the chip area can be reduced.

(Second Modification)
FIG. 11 is a schematic cross-sectional view of a semiconductor memory device according to a second modification of the first embodiment. The description of the external connection electrode is omitted.

At least a part of the word wiring layer and the select gate wiring layer of the first memory cell array layer 200 is drawn as a word line lead portion 35 and a select gate line lead portion 36 by another wiring layer or plug, and the first surface Sa1 is provided. Is folded inside the first memory cell array region 28a when viewed from the direction perpendicular to the first direction. The word line lead portion 35 and the select gate line lead portion 36 drawn inside the first memory cell array region 28a are connected to the first signal line lead electrode 37a provided inside the first memory cell array region 28a. Have been.

Similarly, at least a part of the first bit line BL and the first source line SL is also drawn out as a first bit line lead-out part and a first source line lead-out part by another wiring layer or plug. It is folded back inside the first memory cell array region 28a when viewed from a direction perpendicular to the first surface Sa1 (not shown). The first bit line lead-out portion and the first source line lead-out portion drawn out inside the first memory cell array region 28a are the first signal line lead-out electrodes provided inside the first memory cell array region 28a. 37a.

{Circle around (2)} The first source-side wiring layer 19a on the second surface Sa2 side is connected to a first signal line extraction electrode 37a provided inside the first memory cell array region 28a. Here, a part of the first signal line extraction electrode 37a may be provided outside the first memory cell array region 28a.

には A first surface wiring layer 38a and a second surface wiring layer 39a are provided on the first surface Sa1 and the second surface Sa2 of the first memory cell array layer 200, respectively, inside the memory cell array region. The first surface wiring layer 38a and the second surface wiring layer 39a provided inside the memory cell array region are electrically connected to the first signal line extraction electrode 37a.

In the second memory cell array layer 300, as in the first memory cell array layer 200, at least a part of the word wiring layer and the selection gate wiring layer is formed by another wiring layer or plug by using the word line lead-out portion 35 and the selection gate line. It is pulled out as the lead-out portion 36 and is folded back inside the second memory cell array region 28b when viewed from the direction perpendicular to the third surface Sb1. The word line lead portion 35 and the select gate line lead portion 36 drawn inside the second memory cell array region 28b are connected to the second signal line lead electrode 37b provided inside the second memory cell array region 28b. Have been.

Further, at least a part of the second bit line BL and the second source line SL is led out as a second bit line lead-out part and a second source line lead-out part by another wiring layer or plug, and It is folded back inside the second memory cell array region 28b when viewed from a direction perpendicular to the plane (not shown). The second bit line lead-out portion and the second source line lead-out portion drawn out inside the second memory cell array region 28b are the second signal line lead-out electrodes provided inside the second memory cell array region 28b. 37b. Here, a part of the second signal line extraction electrode 37b may be provided outside the second memory cell array region 28b.

A third surface wiring layer 38b is provided on the third surface Sb1 of the second memory cell array layer 300 inside the memory cell array region. The third surface wiring layer 38 provided inside the memory cell array region is electrically connected to the second signal line extraction electrode 37b. Here, on the fourth surface Sb2 of the second memory cell array layer 300, a fourth surface wiring layer (not shown) may be provided inside the memory cell array region. In this case, the fourth surface wiring layer provided inside the memory cell array region is electrically connected to the second signal line extraction electrode 37b.

Therefore, the signal line extraction electrode of each memory cell array layer is connected to a surface wiring layer provided inside the memory cell array region, and the surface wiring layer of each memory array layer is viewed from a direction perpendicular to the first surface. Each can be provided in an overlapping area. Therefore, when a plurality of memory cell array layers are stacked, the chip area can be further reduced, the wiring length can be reduced, and operation delay can be suppressed.

According to the second modification, at least a part of the bit lines and the word lines are folded inside the memory cell array region. A signal line lead electrode connected via a bit line lead portion and a word line lead portion is provided inside the memory cell array region. The signal line extraction electrode of each memory cell array layer is connected to a surface wiring layer provided inside the memory cell array region, and the surface wiring layer of each memory array layer is viewed from a direction perpendicular to the first surface. Each can be provided in an overlapping area. Therefore, when a plurality of memory cell array layers are stacked, the chip area can be further reduced, the wiring length can be reduced, and operation delay can be suppressed.

According to the first embodiment, the first memory cell array layer 200 and the second memory cell array layer 300 do not have a substrate (for example, a silicon substrate). Therefore, in stacking the first memory cell array layer 200 and the second memory cell array layer 300 and electrically connecting them, it is possible to connect them without forming a through silicon via (TSV). Accordingly, there is no need to perform a substrate etching step which requires cost and processing time, or to form an insulating film for preventing a short circuit between the substrate and the via, thereby reducing costs and improving throughput.

Further, since the memory cell array layer and the peripheral circuit layer are formed by different wafer processes, even when a high-temperature heat treatment is required when forming the memory cell array layer, the impurity diffusion of the transistor in the peripheral circuit layer or the metallization may be performed. Adverse effects such as deterioration of the wiring layer can be suppressed.

{Circle around (1)} The memory cell array layer is stacked so that the first surface faces the peripheral circuit layer. A bit line or a word line is drawn out to the first surface side of the memory cell array layer, and the bit line or the word line is connected to a signal line drawing electrode. Since the memory cell array layer is stacked so that the first surface faces the peripheral circuit layer, the wiring distance of the electrode layer can be reduced, and the adverse effect on the operation speed can be suppressed.

According to the first embodiment, a plurality of memory cell array layers are stacked on the peripheral circuit layer. Therefore, when the stacked body of one memory cell array layer is 48 layers, for example, by stacking two memory cell array layers, a memory cell array of 96 layers, which is twice the 48 layers, is realized by using a 48-layer process technology. can do. Therefore, it is possible to easily improve the memory density.

Further, at least a part of the bit lines and the word lines are led out of the memory cell array region, and a signal line lead electrode connected via a bit line lead portion and a word line lead portion is provided outside the memory cell array region. ing. The external connection electrode is provided in a region outside the memory cell array region and further outside the staircase structure portion in the memory cell array. The signal line lead-out electrodes and the external connection electrodes of each memory cell array layer are provided in respective overlapping regions when viewed from a direction perpendicular to the first surface. Therefore, when a plurality of memory cell array layers are stacked, the wiring length can be reduced, and operation delay can be suppressed.

{Alternatively, at least some of the bit lines and word lines are folded back inside the memory cell array area. A signal line lead electrode connected via a bit line lead portion and a word line lead portion is provided inside the memory cell array region. The signal line extraction electrode of each memory cell array layer is connected to a surface wiring layer provided inside the memory cell array region, and the surface wiring layer of each memory array layer is viewed from a direction perpendicular to the first surface. Each is provided in an overlapping area. Therefore, when a plurality of memory cell array layers are stacked, the chip area can be further reduced, the wiring length can be reduced, and operation delay can be suppressed.

In addition, the external connection electrode and the surface wiring layer connected to the external connection electrode at least penetrate a layer (here, the first memory cell array layer) sandwiched between the upper and lower sides by the memory cell array layer and / or the peripheral circuit layer. It is provided in. Further, the signal line extraction electrode and the surface wiring layer connected to the signal line extraction electrode at least penetrate a layer (here, the first memory cell array layer) sandwiched between upper and lower sides by the memory cell array layer and / or the peripheral circuit layer. It is provided to be. Therefore, when a plurality of memory cell array layers are stacked, the wiring length can be further reduced, the operation delay can be further reduced, and the reliability can be improved.

(4) Further, the layout of the external connection electrodes can be made so as not to be connected to the memory cells, and external signals can be input from the external connection pads to the peripheral circuit layer without passing through the memory cells. By doing so, adverse effects such as operation delay can be further suppressed. In addition, since the signal line lead-out electrode is electrically connected to each memory cell array layer even in a route not connected to the memory cell, the signal lines of each layer are connected without passing through the memory cell. By doing so, adverse effects such as operation delay can be further suppressed.

(4) Further, the memory cell array layer does not have a substrate, and there is no need to form a through silicon via such as a TSV. On the second surface side (fourth surface side) of the memory cell array layer, a source side wiring layer is provided instead of providing a substrate. Therefore, the stacked memory cell array layers can be arbitrarily connected, and the wiring area can be increased without increasing the chip area.

Further, a first source side wiring layer can be used as a first source lead portion of the first source line SL. A second source-side wiring layer can be used as a second source line lead portion of the second source line SL. As described above, in a memory cell array having a memory cell string having an I-shaped columnar portion, by providing a source side wiring layer on the second surface side (fourth surface side) of a source line, a signal from a source line is provided. The wiring length up to the line extraction electrode can be efficiently reduced.
Further, the signal line lead-out electrode and the surface wiring layer of the second memory cell array layer may be formed so as to penetrate the second memory cell array layer, similarly to the first memory cell array layer. This is preferable in that the first memory cell array layer and the second memory cell array layer can have a common device structure, and characteristics such as stress generated in the memory cell array layer can be uniformed. In addition, it is preferable in that the processes in the first memory cell array layer and the second memory cell array layer can be shared, and the memory cell array layer can be manufactured efficiently.

In the first memory cell array layer or the second memory cell array layer, a bit line or a word line is drawn out to the first surface side or the third surface side, and the bit line or the word line is connected to a signal line drawing electrode. I have. The first memory cell array layer is stacked with the first surface facing the peripheral circuit layer, and the second memory cell array layer is stacked with the third surface facing the first memory cell array layer. That is, the first memory cell array layer and the second memory cell array layer are stacked so that the signal lines are drawn out in the same direction and the orientations of the first memory cell array layer and the second memory cell array layer are aligned. As described above, since the bit lines and the word lines are drawn out on the side where the peripheral circuit layer is provided (the lower side in FIG. 1) and are stacked on the peripheral circuit layer, the wiring distance of the electrode layer can be reduced. Therefore, it is possible to suppress an adverse effect on the operation speed.

Further, if the first memory cell array layer and the second memory cell array layer are stacked face-to-face without being aligned, one of the memory cell array layers is placed on, for example, a tape, and the substrate is placed on the tape. After removal, it is necessary to stack the substrate so that the surface from which the substrate has been removed faces the peripheral circuit or the other memory cell array layer. When the first memory cell array layer and the second memory cell array layer are stacked in the same orientation, it is not necessary to use a tape or the like. In other words, the memory cell array layer formed on the substrate can be formed by stacking the memory cell array layer on the peripheral circuit layer so that the substrate surface faces upward and removing the substrate. Therefore, stacking the memory cell array layer and the second memory cell array layer in the same orientation is preferable in that it can be easily formed without using a tape or the like.

(Second embodiment)
Next, a semiconductor memory device according to a second embodiment will be described. Note that the basic configuration is the same as that of the first embodiment, and a description of the items described in the first embodiment will be omitted.

FIG. 12 is a schematic cross-sectional view of the semiconductor memory device according to the second embodiment. In FIG. 12, another memory cell array layer is stacked on the semiconductor memory device of FIG. 1, and a peripheral circuit layer 100, a first memory cell array layer 200, and a second memory cell array layer 300 are sequentially arranged from the bottom. , A third memory cell array layer 400.

Here, as shown in FIG. 12, the stacked second memory cell array layer 300 includes a third surface wiring layer 38b provided on the third surface Sb1 and a fourth surface wiring layer 38b provided on the fourth surface Sb2. A wiring layer 71 connected to the memory string MS3 is provided between the wiring layer 71 and the surface wiring layer 39b. That is, the second memory cell array layer 300 is connected to the upper and lower memory cell array layers by the wiring layer 71 via the memory string MS3.

FIG. 13 is a circuit diagram of the semiconductor memory device according to the second embodiment. FIG. 13 shows a part of the circuit of the memory string MS3 connected to the wiring layer 71. A plurality of memory cells are provided, and some of them are not shown. The plurality of memory cells are provided with a drain-side selection transistor STD and a source-side selection transistor STS, and store an array layer ID provided for each memory cell array layer. The circuit of the memory string MS3 functions as a part of an array layer select circuit for selecting an array layer.

FIG. 14 is a block diagram showing the configuration of the system of the semiconductor memory device according to the second embodiment. FIG. 14 shows a system configuration of a semiconductor memory device including an array layer select circuit provided in the memory string MS3 connected to the wiring layer 71.

(4) Address lines and array layer select signal lines are input to each memory cell array layer as signal lines. In the memory cell array layer, it is determined whether the memory cell array layer is selected based on the array layer select signal line and the stored array layer ID, and an address line is input to the memory cell array.

By forming in this manner, the memory cell array layer can be selected using the transistors and the memory cells in the memory string MS3 without individually selecting the memory cell array using each signal line. Even in a semiconductor memory device having a plurality of stacked memory cell array layers, the number of wirings can be significantly reduced.

In this case, each of the memory areas or memory blocks of the second memory cell array layer may be connected to the upper and lower memory cell array layers using the wiring layer 71. By forming in this manner, a memory area or a memory block can be selected using each transistor and each memory cell in each memory string MS, and a semiconductor memory having a plurality of stacked memory cell array layers Even in a device, the number of wirings can be significantly reduced.

The embodiments have been described above with reference to the drawings. However, the present invention is not limited to these.

In the present invention, the example including the circuit board is described, but the case where only the memory cell array layer is laminated is also included in the scope of the present invention.

っても Even if a person skilled in the art makes various design changes regarding the configuration of the memory cell array constituting the present invention, etc., it is included in the scope of the present invention unless departing from the gist of the present invention.

According to still another aspect, there is provided a semiconductor memory device provided with a three-dimensional memory cell array having another configuration.

Although some embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

A memory cell array layer having a first surface and a second surface opposite to the first surface and not including a substrate, the plurality of memory cells being three-dimensionally arranged in the memory cell array region; and the first surface and / or A plurality of memory cell array layers including a surface wiring layer embedded in the second surface;
The surface wiring layers of the respective memory cell array layers are provided so as to overlap when viewed from a direction perpendicular to the first surface, and the plurality of memory cell array layers are formed by joining the surface wiring layers to each other. A semiconductor memory device characterized by being stacked.
A circuit substrate, a control circuit provided on a circuit formation surface of the circuit substrate, and a circuit-side wiring layer provided on the circuit formation surface of the circuit substrate and electrically connected to the control circuit. A peripheral circuit layer having
A first memory cell array layer having a first surface and a second surface opposite to the first surface and not including a first substrate,
A plurality of first memory cells three-dimensionally arranged in the memory cell array region, a first signal line lead electrode, and a first memory cell provided outside the memory cell array region when viewed from a direction perpendicular to the first surface. And a first surface wiring layer and a second surface connected to the first signal line lead-out electrode and the first external connection electrode, and provided on the first surface and the second surface, respectively. A first memory cell array layer having the first surface facing the peripheral circuit layer, wherein the circuit-side wiring layer and the first surface wiring layer are joined. ,
A second memory cell array layer having a third surface and a fourth surface opposite to the third surface and not including the second substrate,
A plurality of second memory cells three-dimensionally arranged in the memory cell array region, a second signal line lead electrode, and a second memory cell provided outside the memory cell array region when viewed from a direction perpendicular to the third surface. A second external connection electrode, a third surface wiring layer connected to the second signal line lead-out electrode and the second external connection electrode, and provided on the third and fourth surfaces, respectively. And a fourth surface wiring layer, wherein the third surface is stacked so that the third surface faces the first memory cell array layer, and the second surface wiring layer and the third surface wiring layer are joined. And a memory cell array layer.
3. The semiconductor according to claim 2, wherein the circuit-side wiring layer and the first surface wiring layer, and the second surface wiring layer and the third surface wiring layer are directly bonded. 4. Storage device.
The plurality of first memory cells include a first stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked, and a first columnar portion extending in a stacking direction of the first stacked body. Then, a first bit line is electrically connected to the first surface side of the first columnar portion, and a first source line is electrically connected to the second surface side of the first columnar portion. 3. The semiconductor memory device according to claim 2, wherein a first source-side wiring layer is provided on the second surface side of the first source line.
The plurality of second memory cells include a second stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked, and a second columnar portion extending in a stacking direction of the second stacked body. Then, a second bit line is electrically connected to the third surface side of the second columnar portion, and a second source line is electrically connected to the fourth surface side of the second columnar portion. 3. The semiconductor memory device according to claim 2, wherein a second source side wiring layer is provided on the fourth surface side of the second source line.
The plurality of first memory cells include a first stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked, and a first columnar portion extending in a stacking direction of the first stacked body. Then, a first bit line is electrically connected to the first surface side of the first columnar portion, and a first source line is electrically connected to the second surface side of the first columnar portion. And a first source-side wiring layer is provided on the second surface side of the first source line,
The plurality of second memory cells include a second stacked body in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked, and a second columnar portion extending in a stacking direction of the second stacked body. Then, a second bit line is electrically connected to the third surface side of the second columnar portion, and a second source line is electrically connected to the fourth surface side of the second columnar portion. A second source-side wiring layer is provided on the fourth surface side of the second source line,
The first source-side wiring layer of the first memory cell array layer is provided between the second bit line of the second memory cell array layer and the memory cell array region when viewed from a direction perpendicular to the first surface. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is connected inside.
The second surface wiring layer and the third surface wiring layer respectively connected to the first signal line lead electrode and the second signal line lead electrode are provided inside the memory cell array region. 3. The semiconductor memory device according to claim 2, wherein:
3. The semiconductor device according to claim 2, further comprising at least one other memory cell array layer stacked so as to face the second memory cell array layer, and having three or more memory cell array layers. 13. The semiconductor memory device according to claim 1.
The first memory cell array layer or the second memory cell array layer includes a transistor and an array layer ID for selecting the first memory cell array layer or the second memory cell array layer as part of an array layer select circuit. A memory string having a memory cell to be stored is provided, and the memory string is provided with the first signal line extraction electrode of the first memory cell array layer or the second signal line of the second memory cell array layer. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is electrically connected to an extraction electrode.
At least one of the plurality of memory cell array layers is provided with a memory string having a transistor for selecting a memory cell array layer and a memory cell for storing an array layer ID as a part of an array layer select circuit. 9. The semiconductor memory device according to claim 1, wherein:
The plurality of memory cell array layers are at least three memory cell array layers, and a part of the array layer select circuit is sandwiched between other memory cell array layers above and below the plurality of memory cell array layers. 11. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is provided in one memory cell array layer.
11. The semiconductor memory device according to claim 10, wherein a part of said array layer select circuit is provided for each memory area or memory block of said at least one memory cell array layer.