WO2020029602A1 - Procédé et appareil de détection de retard temporel, et système - Google Patents

Procédé et appareil de détection de retard temporel, et système Download PDF

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Publication number
WO2020029602A1
WO2020029602A1 PCT/CN2019/082363 CN2019082363W WO2020029602A1 WO 2020029602 A1 WO2020029602 A1 WO 2020029602A1 CN 2019082363 W CN2019082363 W CN 2019082363W WO 2020029602 A1 WO2020029602 A1 WO 2020029602A1
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Prior art keywords
time
storage device
response message
storage
message
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PCT/CN2019/082363
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English (en)
Chinese (zh)
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杨俊涛
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0852—Delays
    • H04L43/0864—Round trip delays

Definitions

  • the present application relates to the field of storage technology, and in particular, to a method, a device, and a system for detecting a delay.
  • the storage array used for data storage is composed of a large number of storage units, and each storage unit can store 1-bit binary data (that is, 0 or 1).
  • a storage array works as a single disk by combining multiple disks into an array. When accessing data, the related disks in the storage array are operated together, which greatly reduces the data access time and improves the disk space utilization.
  • Storage area network is a Fibre Channel (FC) technology that connects storage arrays and hosts through FC switches to establish an area network dedicated to data storage.
  • FC Fibre Channel
  • data storage systems can be deployed in the data centers in the two locations, which are called mainframe systems and standby systems.
  • the host system and the standby system run online at the same time and back up each other to ensure data consistency.
  • This kind of data backup method is called Dual-Live Disaster Tolerance (DLDT) technology.
  • DLDT Dual-Live Disaster Tolerance
  • the transmission delay of the transmission link can be used to determine the priority path of data transmission, which will directly affect the performance of the storage system and the customer experience.
  • the storage device A and the storage device B in the two data storage systems detect the link delay between the two data storage systems by testing the write IO service; specific operations include:
  • Step 1 The business application logic on storage device A sends an IO write request to storage device B via the protocol stack and chip of storage device A; the above IO write request is sent to the storage via the chip and protocol stack on storage device B Business application logic on device B;
  • Step 2 The storage device B sends an XFER_RDY command to the storage device A, and notifies the storage device A that a buffer (ie, a buffer) for receiving data on the storage device B is ready;
  • Step 3 The chip of the storage device A starts a Direct Memory Access (DMA) operation after receiving the XFER_RDY command, and sends data to be transmitted to the storage device B through a transmission link;
  • DMA Direct Memory Access
  • Step 4 After the business application logic of storage device B receives the data, it sends an IO completion response to the business application logic of storage device A.
  • Storage device A calculates the time it takes for the application logic on storage device A to send an IO write request to receiving the IO completion response as the link transmission delay between storage device A and storage device B.
  • An embodiment of the present application provides a method for detecting a delay, which is used to improve overall system performance.
  • the method includes:
  • the first storage device and the second storage device are connected through a storage area network, and the method includes:
  • the first storage device calculates a link transmission delay of one bidirectional transmission between the first storage device and the second storage device according to the first time and the fourth time.
  • An embodiment of the present application further provides a device for detecting a delay.
  • the device is a storage device and is connected to a second storage device through a storage area network.
  • the device includes:
  • An obtaining unit configured to obtain a first time when a chip on the device sends a test message and a fourth time when a response message is received; wherein the response message is the second storage device responding to the test message Sent by text;
  • a calculation unit is configured to calculate a link transmission delay in one bidirectional transmission between the apparatus and the second storage device according to the first time and the fourth time.
  • an embodiment of the present application further provides a storage system.
  • the storage system includes at least a first storage device and a second storage device. The first storage device and the second storage device are connected through a storage area network. ;
  • the first storage device is configured to obtain a first time when a chip on the first storage device sends a test message and a fourth time when a response message is received; wherein the response message is the second storage device Sent in response to the test message;
  • the first storage device is further configured to calculate a link transmission delay in one bidirectional transmission between the first storage device and the second storage device according to the first time and the fourth time.
  • the apparatus for detecting time delay provided in another embodiment of the present application includes at least one processor and at least one memory, the at least one memory is configured to store a computer program, and the at least one processor is configured to call the computer program to execute the embodiment. The method described.
  • An embodiment of the present application further provides a computer storage medium, where computer software instructions are stored on the computer storage medium, and after the computer software instructions run, the computer executes the method described in the embodiment.
  • the time when a chip on a storage device sends or receives a message can accurately obtain the link transmission delay of a two-way transmission between the storage devices without being affected by the data processing overhead of the application program. And the impact of the processing delay of the protocol stack.
  • FIG. 1 is a system architecture diagram according to an embodiment of the present application
  • FIG. 2 is a simplified schematic diagram of a system architecture according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a first embodiment of the present application.
  • FIG. 4 is a schematic diagram of a payload of an Echo message in the first embodiment of the present application.
  • FIG. 5 is a schematic diagram of a payload of an Echo message in a second embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a device for detecting delay according to an embodiment of the present application.
  • the “multiple” referred to in the embodiments of the present application means two or more than two; the terms “first”, “second”, “third”, “fourth” and the like in this application , For the purpose of distinguishing descriptions only, and should not be interpreted as indicating or implying relative importance, nor as indicating or implying order.
  • FIG. 1 The embodiment of the present application relates to a system architecture as shown in FIG. 1, which includes a storage system A and a storage system B.
  • the storage system A and the storage system B are connected through a backbone network.
  • Storage system A includes storage device A and storage area network SAN-A;
  • storage system B includes storage device B and storage area network SAN-B.
  • Storage device A and storage device B can be composed of storage arrays; storage area networks SAN-A and SAN-B can use mesh channel technology and connect storage devices and server hosts through FC switches.
  • the foregoing storage system A and storage system B may be data centers deployed in two different cities, and perform data synchronization operations through a SAN network to implement application scenarios such as active-active disaster recovery.
  • the technical solutions in the embodiments of the present application can also be applied to other network deployment scenarios with severe transmission delay requirements.
  • Both storage device A and storage device B in FIG. 2 may include two components, which are a protocol stack and a chip, respectively.
  • the protocol stack may specifically include a small computer system interface (SCSI) protocol stack and an FC protocol stack, which are important components of a storage system. Both the SCSI protocol stack and the FC protocol stack can be implemented by software.
  • SCSI small computer system interface
  • FC protocol stack which are important components of a storage system. Both the SCSI protocol stack and the FC protocol stack can be implemented by software.
  • the SCSI protocol stack is responsible for the assembly and analysis of SCSI commands, including the processing of SCSI CDB / LBA information and other SCSI information.
  • the FC protocol stack is responsible for the processing of FC2 and FC4 related information, including assembling the payload and address resolution conversion in the FCP command; the FC protocol stack is also responsible for converting the FCP command into an IOB command recognized by the FC chip, and reporting the IOB to the FC chip The commands are converted into FCP commands and submitted to the SCSI protocol stack.
  • the FC chip is a Fibre Channel controller chip capable of handling FC protocols (including the FC0, FC1, FC2, FC3 and FC4 layers).
  • FC protocols including the FC0, FC1, FC2, FC3 and FC4 layers.
  • the FC chip can handle the signal transmission and signal reception of the FC link, can organize and analyze the FC frame structure, and can also perform the operations of FC frame transmission and FC frame reception.
  • This embodiment of the present application only uses an FC chip supporting the FC protocol as an example.
  • the technical solution of the embodiment of the present application is also applicable to a chip supporting a network offload protocol such as IOE (ISCSI Offload Engine) or TOE (TCP Offload Engine).
  • IOE ISCSI Offload Engine
  • TOE TCP Offload Engine
  • network offloading uses an off-chip chip to independently implement the Ethernet communication protocol that originally required storage resources and computing resources; the network offloading protocol is an Ethernet communication protocol implemented on the independent chip, such as The FC protocol, IOE protocol or TOE protocol described above.
  • the network offload protocol is a transport layer protocol and can be applied to storage application scenarios.
  • the network offloading protocol message corresponding to the network offloading protocol may encapsulate the SCSI protocol message.
  • FC network may further include one or more storage area networks, and may further include a backbone network.
  • FIG. 3 it is a schematic diagram of a detailed scheme for detecting a link transmission delay according to the first embodiment of the present application.
  • the protocol stack on the storage device A generates an ECHO command, and sets a tag at a specific position of the payload information of the ECHO command to instruct the ECHO command to detect a link transmission delay;
  • the ECHO command is a non-IO command, and is a FC-ELS (Fibre Channel Extended Link Services) format defined using the FC protocol.
  • FC-ELS Fibre Channel Extended Link Services
  • the content of the payload in the ECHO command can be defined by the user.
  • the protocol stack on the storage device A constructs an input / output block (Input / Output Block, referred to as IOB) recognized by the chip on the storage device A, and sends the IOB to the chip's first-in-first-out FIFO) queue.
  • IOB input / output block
  • the IOB is a data block structure used for interaction between the protocol stack software and the chip; the IOB carries a piece of data with a fixed format and a customizable content.
  • the chip on the storage device A fetches the IOB from the FIFO queue, and obtains the payload information of the ECHO command.
  • the tag of the payload information determines that the ECHO command is a command for detecting a link transmission delay.
  • the chip on the storage device A organizes frame header and frame tail information of the ECHO command message according to the ECHO command, and writes the current timing information T1 into the payload. After performing a Cyclic Redundancy Check (CRC) operation, a chip on the storage device A sends the ECHO command message to the storage device B.
  • CRC Cyclic Redundancy Check
  • the protocol stack of the storage device A generates an ECHO command, and the ECHO command is transmitted to the chip of the storage device A using an IOB to generate a corresponding ECHO command message and sent to the storage device B.
  • the ECHO command message can be regarded as a data message that the chip encapsulates the ECHO command generated by the protocol stack using the FC-ELS format and can be transmitted on the SAN network.
  • the ECHO response message can be regarded as a data message encapsulated by the chip to the protocol stack using the FC-ELS format and can be transmitted on the SAN network.
  • the ECHO command message and ECHO response message here are both ECHO messages.
  • the chip on the storage device B receives the ECHO command message, and after it determines that it is a command message for detecting a link transmission delay through the tag of the payload, writes the current timing information T2 to the ECHO command message. Payload.
  • the chip on the storage device B processes the ECHO command message, assembles the IOB, and sends the corresponding ECHO command to the protocol stack of the storage device B.
  • the protocol stack on the storage device B generates and delivers an ECHO response in response to the above-mentioned ECHO command. Specifically, the protocol stack on the storage device B organizes an ECHO response, and the payload of the ECHO response is the same as the payload of the ECHO command received by the storage device B.
  • the protocol stack on the storage device B constructs an IOB recognizable by the chip on the storage device B, and sends the IOB to the chip's FIFO queue.
  • the chip on the storage device B After the chip on the storage device B removes the IOB from the FIFO queue, and obtains the payload information of the ECHO response, the tag of the payload information determines that it is the response to the command for detecting the link transmission delay, and writes the current timing information T3 Into the payload. After performing CRC processing, the chip on storage device B sends the generated ECHO response packet to storage device A.
  • the current timing information T4 is written to the ECHO response. The payload of the message.
  • the chip on the storage device A assembles the IOB and sends the ECHO response to the protocol stack of the storage device A.
  • the protocol stack on storage device A After receiving the ECHO response, the protocol stack on storage device A obtains T, T2, T3, and T4 from its payload, and is used to calculate the link transmission delay of a two-way transmission between storage device A and storage device B. DT.
  • storage device A can calculate DT by the following formula or its algorithm:
  • FIG. 4 it is a schematic diagram of a payload in an ECHO message according to the first embodiment of the present application. Different fields are defined in the position areas corresponding to different offsets of the payload of the ECHO message.
  • the payload of the ECHO message may specifically include the following:
  • Offset0 represents the field local magic version tag, which is used to identify that the format of the payload message is a custom format.
  • the sender of the ECHO command message needs to fill in the timing information required in the echo cmd send time and echo response time fields;
  • Offset stands for the field remote magic version tag, used to identify whether the remote end supports the command; the initial value of this field can be set to the remote end does not support the command, if the remote end supports, the remote end after receiving the command Fill in the corresponding identification as agreed; if the remote end supports the command, the sender of the ECHO response message needs to fill in the timing information required in the echo cmd received time and echo response time fields;
  • Offset + 1 represents the echo cmd time field, which indicates the time when the sender of the ECHO command message sends the ECHO command message, that is, corresponding to T1 in the first embodiment 304 of the application;
  • Offset + 2 represents the echo cmd time field, which indicates the time when the receiver of the ECHO command message received the ECHO command message, that is, corresponding to T2 in the first embodiment 305 of the application;
  • Offset + 3 represents the echo response time field, which indicates the time at which the sender of the ECHO response message sends the ECHO response message, which corresponds to T3 in the first embodiment 309 of this application;
  • Offset + 4 represents the echo response time field, which indicates the time when the receiver of the ECHO response message receives the ECHO response message, that is, corresponding to T4 in the first embodiment 310 of this application;
  • Offset + 5 to 255 Used to indicate other unformatted content in the payload.
  • T1 and 310 in the first embodiment 304 of the above application.
  • Storage device A sends the above T1 and T4 to the protocol stack through the IOB between the chip and the protocol stack, and is used to calculate the link transmission delay DT of a two-way transmission between storage device A and storage device B.
  • FIG. 5 it is a schematic diagram of a payload of an ECHO message according to a second embodiment of the present application.
  • the third embodiment of the present application provides a method for detecting a delay.
  • the method is applied to a storage system connected between a first storage device and a second storage device through a storage area network.
  • the method includes:
  • the first storage device acquires a fourth time when a chip on the first storage device receives a response message, and the response message is sent by the second storage device in response to the test message;
  • the first storage device calculates a link transmission delay of a bidirectional transmission between the first storage device and the second storage device according to the first time and the fourth time.
  • the response message may further include a second time and a third time, where:
  • the second time is the time when the chip of the second storage device receives the test message;
  • the third time is the time when the chip of the second storage device sends a response message;
  • the first storage device may calculate a link transmission delay of one bidirectional transmission between the first storage device and the second storage device according to the first time, the second time, the third time, and the fourth time.
  • the test message in this application may be an ECHO command message, and the response message may be an ECHO response message.
  • the ECHO command message and ECHO response message are both ECHO messages using the FC-ELS protocol. The first to fourth times involved in the embodiments of the present application are further described below.
  • the first time of this application is the time when the chip of the first storage device sends the ECHO command message to the link, that is, corresponding to T1 in the first embodiment 304 of the application, which can be carried in the echo cmd send time field of the ECHO message. in;
  • the second time of the present application is the time when the chip of the second storage device receives the ECHO command message, that is, corresponding to T2 in the first embodiment 305 of the present application, and can be carried in the echo cmd received time field of the ECHO message;
  • the third time of the present application is the time when the chip of the second storage device sends the ECHO response message, that is, corresponding to T3 in the first embodiment 309 of the present application, and can be carried in the echo response time field of the ECHO message;
  • the fourth time of this application is the time when the chip of the first storage device receives the ECHO response message, that is, corresponding to T4 in the above-mentioned first embodiment 310 of the application, and can be carried in the echo response time field of the ECHO message.
  • the first time can be transmitted to the second storage device through the ECHO command message sent by the first storage device, and then the second storage device sends the first time back to the first storage device through the ECHO response message; the second After the storage device obtains the second time and the third time, it writes the second time and the third time into the ECHO response message and sends it to the first storage device; after receiving the ECHO response message, the chip of the first storage device sends Write the ECHO response message at the fourth time and send it to the protocol stack.
  • the time between sending and receiving a message by using a chip on a storage device can accurately obtain the link transmission delay of a two-way transmission between the storage devices without being processed by the application program data.
  • the embodiment of the present application can obtain the time for transmitting messages between the chips on the storage device through a two-way ECHO interaction at one time, without adding an interface, which is simple to implement and has low overhead.
  • the technical solution of the present application can be used to more accurately determine the priority path of data transmission, thereby improving the integrity of the system.
  • the technical solution provided in the embodiments of the present application can also be used in combination with the existing IO model-based delay statistics technology to quickly determine the performance bottleneck of the storage system to determine the load balancing strategy.
  • the technical solutions provided in the embodiments of the present application can also be used to locate the network configuration and link congestion, and the transmission distance of the actual link can be evaluated by detecting the transmission delay.
  • the apparatus 600 is a storage device and is connected to the second storage device through a storage area network.
  • the apparatus 600 may include an obtaining unit 601 and a computing unit 602.
  • the obtaining unit 601 is configured to obtain a first time when a chip on the device sends a test message and a fourth time when a response message is received; wherein the response message is sent by the second storage device in response to the test message;
  • the calculating unit 602 is configured to calculate a link transmission delay in one bidirectional transmission between the device and the second storage device according to the first time and the fourth time.
  • the response message may include a second time and a third time, where the second time is the time when the chip of the second storage device receives the test message, and the third time is the second storage device The time that the chip sends the response message.
  • the calculation unit 602 calculates a link transmission delay of a two-way transmission between the device and the second storage device according to the first time, the second time, the third time, and the fourth time.
  • the second time and the third time may be written into the response message by the second storage device, and the obtaining unit 601 obtains the second time and the third time from the response message.
  • the first time may be that the device writes into the test message, and is written by the second storage device into the response message after receiving the test message;
  • the fourth time may be The chip writes the response message after receiving the response message. Accordingly, the acquiring unit may acquire the first time and the fourth time from the response message.
  • the present application also discloses a storage system.
  • the storage system includes at least a first storage device and a second storage device according to the foregoing embodiments of the present application.
  • the first storage device and the second storage device are connected through a storage area network.
  • Computer-readable media includes computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
  • a storage media may be any available media that can be accessed by a computer.
  • computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), read-only memory (EEPROM), compact disc-read-only memory (CD-ROM) ROM) or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer. Also. Any connection is properly a computer-readable medium.
  • disks and discs include compact discs (CDs), laser discs, optical discs, digital video discs (DVDs), floppy discs, and Blu-ray discs, among which Discs usually reproduce data magnetically, while discs use lasers to reproduce data optically.
  • CDs compact discs
  • DVDs digital video discs
  • floppy discs floppy discs
  • Blu-ray discs among which Discs usually reproduce data magnetically, while discs use lasers to reproduce data optically. The above combination should also be included in the protection scope of the computer-readable medium.

Abstract

Les modes de réalisation de la présente invention concernent un procédé de détection de retard temporel, dans lequel un premier dispositif de stockage est connecté à un second dispositif de stockage au moyen d'un réseau de zones de stockage. Le procédé comprend les étapes suivantes : le premier dispositif de stockage obtient un premier instant auquel une puce se situant sur le premier dispositif de stockage envoie un message de test ; le premier dispositif de stockage obtient un quatrième instant auquel la puce du premier dispositif de stockage reçoit un message de réponse, le message de réponse étant envoyé par le second dispositif de stockage en réponse au message de test ; et le premier dispositif de stockage calcule un retard temporel de transmission de liaison d'une transmission bidirectionnelle entre le premier dispositif de stockage et le second dispositif de stockage selon le premier instant et le quatrième instant. Le procédé dans les modes de réalisation de la présente invention permet d'obtenir avec précision le retard temporel de transmission de liaison de la transmission bidirectionnelle entre les dispositifs de stockage, sans être affecté par le surdébit de traitement de données d'un programme d'application et le retard temporel de traitement d'une pile de protocoles. La présente invention concerne également un appareil de détection de retard temporel et un système de stockage.
PCT/CN2019/082363 2018-08-09 2019-04-12 Procédé et appareil de détection de retard temporel, et système WO2020029602A1 (fr)

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